A preparation method of TOPCon solar cell for reducing back parasitic absorption

Abstract

The present invention provides a method for preparing a TOPCon solar cell with reduced backside parasitic absorption, which relates to the technical field of solar cells. The method for preparing a TOPCon solar cell with reduced backside parasitic absorption comprises the following steps: forming a first tunneling oxide layer on the backside of an N-type crystalline silicon substrate; depositing an intrinsic polysilicon layer and a second tunneling oxide layer on the first tunneling oxide layer; depositing a phosphorus-doped polysilicon layer and a third tunneling oxide layer on the second tunneling oxide layer; and forming a transparent conductive thin film on the third tunneling oxide layer. The preparation method of the present invention can significantly reduce parasitic absorption and fully increase the light utilization rate, thereby further improving the efficiency of the solar cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a TOPCon cell for reducing backside parasitic absorption. Background Art

[0002] TOPCon cell (Tunnel Oxide Passivating Contacts) is a tunneling oxide passivating contact solar cell technology based on the principle of selective carriers. Its cell structure is an N-type silicon substrate cell. Compared with a P-type PERC cell (passivated emitter and rear cell structure), the boron content in phosphorus-doped N-type crystalline silicon is relatively low, and it has a better passivation effect.

[0003] The existing backside passivation structure of Topcon cells uses PECVD or LPCVD methods to prepare a tunneling oxide layer and a doped silicon thin layer. First, an ultra-thin tunneling layer with a thickness of 0.5 - 2.5 nm is prepared on the backside of the cell, and then a doped silicon thin layer with a thickness of 110 - 130 nm is deposited. Finally, silicon nitride is deposited on the doped polysilicon layer to form a passivating contact structure. The ultra-thin oxide layer allows electrons to tunnel into the polysilicon layer while blocking the transport of holes, reducing the recombination current; the lateral transport characteristics of the doped polysilicon layer reduce the series resistance, providing more room for further improvement of the cell conversion efficiency. However, in order to reduce the recombination current density, a sufficient thickness of doped polysilicon is usually required, and its thickness is in the range of 110 - 130 nm. This Poly-Si layer is relatively thick. A too large thickness of polysilicon will have free carrier absorption (FCA) for long-wavelength light, resulting in a loss of short-circuit current of the TOPCon cell, and a too thick Poly-Si layer will also lead to high optical parasitic absorption and low light utilization efficiency, affecting the efficiency of the cell.

[0004] In view of this, the present invention is specifically proposed. Summary of the Invention

[0005] One of the purposes of the present invention is to provide a method for preparing a TOPCon cell for reducing backside parasitic absorption. The preparation method can effectively reduce the thickness of the backside Poly-Si layer, reduce parasitic absorption, increase light utilization efficiency, and improve the efficiency of the cell.

[0006] In order to achieve the above object of the present invention, the following technical solutions are specifically adopted:

[0007] In the first aspect, the present invention provides a method for preparing a TOPCon cell for reducing backside parasitic absorption, and the preparation method includes the following steps:

[0008] Form a first tunneling oxide layer on the backside of the N-type crystalline silicon substrate;

[0009] Deposit an intrinsic polysilicon layer and a second tunneling oxide layer on the first tunneling oxide layer;

[0010] Deposit a phosphorus-doped polysilicon layer and a third tunneling oxide layer on the second tunneling oxide layer;

[0011] Form a transparent conductive thin film on the third tunneling oxide layer.

[0012] In the present invention, the preparation method can effectively reduce the total thickness of the back Poly-Si layer, reduce parasitic absorption, increase light utilization rate, and improve the efficiency of the cell; and the prepared TOPCon cell has a specific laminated structure, which can block the inward diffusion of the phosphorus source and reduce the corrosion damage of the silver paste to the Poly-Si layer and the tunneling layer, reduce recombination, and improve the efficiency of the cell.

[0013] Preferably, the thickness of the first tunneling oxide layer is 1 - 1.6 nm, for example, it can be 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, etc.

[0014] Preferably, the first tunneling oxide layer is deposited by PECVD process.

[0015] Preferably, the process parameters of the PECVD process for depositing the first tunneling oxide layer are: the temperature is 500 - 600 °C, for example, it can be 500 °C, 520 °C, 540 °C, 560 °C, 580 °C, 600 °C, etc.; the process chamber pressure is 150 - 200 Pa, for example, it can be 150 Pa, 160 Pa, 170 Pa, 180 Pa, 190 Pa, 200 Pa, etc.; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:(8 - 10), for example, it can be 1:8, 1:8.2, 1:8.4, 1:8.6, 1:8.8, 1:9, 1:9.2, 1:9.4, 1:9.6, 1:9.8, 1:10, etc.

[0016] Preferably, the thickness of the intrinsic polysilicon layer is 5 - 20 nm, for example, it can be 5 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, etc.

[0017] Preferably, the thickness of the second tunneling oxide layer is 0.8 - 1.5 nm, for example, it can be 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc.

[0018] In the present invention, an intrinsic polysilicon layer and a second tunneling oxide layer with a specific thickness are deposited on the first tunneling oxide layer, and the combination of the two forms a composite layer, the purpose of which is to prevent the inward diffusion of the phosphorus source into the silicon substrate and reduce recombination.

[0019] Preferably, both the intrinsic polysilicon layer and the second tunneling oxide layer are deposited by PECVD process.

[0020] Preferably, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are: the temperature is 350 - 450 °C, for example, it can be 350 °C, 360 °C, 370 °C, 380 °C, 390 °C, 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, etc.; the pressure condition is 1300 - 1800 mTorr, for example, it can be 1300 mTorr, 1400 mTorr, 1500 mTorr, 1600 mTorr, 1700 mTorr, 1800 mTorr, etc.; the process gas is a mixed gas of SiH 4 and H 2 The volume ratio of SiH 4 and H 2 is 1:(3 - 5), for example, it can be 1:3, 1:3.5, 1:4, 1:4.5, 1:5, etc.

[0021] Preferably, the process parameters of the PECVD process for depositing the second tunneling oxide layer are: the temperature is 400 - 480 °C, for example, it can be 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, 460 °C, 470 °C, 480 °C, etc.; the process chamber pressure is 100 - 150 Pa, for example, it can be 100 Pa, 110 Pa, 120 Pa, 130 Pa, 140 Pa, 150 Pa, etc.; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O and Ar is 1:(6 - 8), for example, it can be 1:6, 1:6.5, 1:7, 1:7.5, 1:8, etc.

[0022] Preferably, the thickness of the phosphorus - doped polysilicon layer is 20 - 50 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc., and the purpose is to thin the Poly - Si layer and reduce parasitic absorption.

[0023] Preferably, in the phosphorus - doped polysilicon layer, the doping concentration of phosphorus is 1×10 19 ~1×10 21 cm -3 , for example, it can be 1×10 19 cm -3 、5×10 19cm -3 、 1×10 20 cm -3 、 5×10 20 cm -3 、 1×10 21 cm -3 etc.

[0024] Preferably, the thickness of the third tunneling oxide layer is 0.8 - 1.5 nm, such as 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc., and its purpose is to enhance the electron transport effect.

[0025] Preferably, both the phosphorus-doped polysilicon layer and the third tunneling oxide layer are deposited by PECVD process.

[0026] Preferably, the process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are: the temperature is 350 - 400 °C, such as 350 °C, 360 °C, 370 °C, 380 °C, 390 °C, 400 °C, etc.; the pressure condition is 1300 - 1800 mTorr, such as 1300 mTorr, 1400 mTorr, 1500 mTorr, 1600 mTorr, 1700 mTorr, 1800 mTorr, etc.; the process gas is a mixed gas of PH 3 , SiH 4 and H 2 , and the volume ratio of PH 3 , SiH 4 and H 2 is 1:(1 - 3):(3 - 5), such as 1:1:3, 1:2:3, 1:3:3, 1:1:4, 1:2:4, 1:3:4, 1:1:5, 1:2:5, 1:3:5, etc.

[0027] Preferably, the process parameters of the PECVD process for depositing the third tunneling oxide layer are: the temperature is 400 - 480 °C, such as 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, 460 °C, 470 °C, 480 °C, etc.; the process chamber pressure is 100 - 150 Pa, such as 100 Pa, 110 Pa, 120 Pa, 130 Pa, 140 Pa, 150 Pa, etc.; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O and Ar is 1:(6 - 8), such as 1:6, 1:6.5, 1:7, 1:7.5, 1:8, etc.

[0028] Preferably, the material of the transparent conductive film is selected from any one or a combination of at least two of indium tin oxide, zinc aluminum oxide, or indium zinc oxide.

[0029] In the present invention, a transparent conductive film is prepared by PVD sputtering method. The conductive film can be made of indium tin oxide (ITO), zinc aluminum oxide (AZO), or indium zinc oxide (IZO) materials, and the film thickness is 15 - 70 nm, aiming to reduce the corrosion of the silver paste to the Poly-Si layer and the tunneling layer.

[0030] Preferably, the thickness of the transparent conductive film is 15 - 70 nm, for example, it can be 15 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, etc.

[0031] Preferably, the transparent conductive film is prepared by PVD sputtering method.

[0032] Preferably, the process parameters of the PVD for preparing the transparent conductive film are: the deposition pressure is 0.1 - 1.0 Pa, for example, it can be 0.1 Pa, 0.2 Pa, 0.3 Pa, 0.4 Pa, 0.5 Pa, 0.6 Pa, 0.7 Pa, 0.8 Pa, 0.9 Pa, 1.0 Pa, etc., the deposition temperature is 200 - 300 °C, for example, it can be 200 °C, 220 °C, 240 °C, 260 °C, 280 °C, 300 °C, etc., and the power density is 1 - 5 W / cm 2 For example, it can be 1 W / cm 2 、1.5 W / cm 2 、2 W / cm 2 、2.5 W / cm 2 、3 W / cm 2 、3.5 W / cm 2 、4 W / cm 2 、4.5 W / cm 2 、5 W / cm 2 etc.

[0033] Preferably, before preparing the first tunneling oxide layer, the silicon substrate needs to be pretreated. The pretreatment specifically includes: texturing, primary boron diffusion, selective heavy doping, secondary boron diffusion, removing BSG, and alkali polishing treatment.

[0034] Preferably, after the formation of the transparent conductive film, surface passivation treatment and metallization treatment are successively included.

[0035] Preferably, the surface passivation treatment specifically includes the following steps: preparing a silicon nitride layer on the transparent conductive film; successively preparing an aluminum oxide layer and a silicon nitride layer on the front surface of the silicon substrate; and simultaneously performing curing and repair treatment.

[0036] In the present invention, the silicon nitride layer is coated while curing and repairing the conductive thin film. The curing treatment and H passivation repair are carried out during the coating of the silicon nitride layer, aiming to repair the defects of the conductive film layer caused by PVD sputtering.

[0037] Preferably, the thickness of the silicon nitride layer is 30 - 40 μm, such as 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc.

[0038] Preferably, the thickness of the alumina layer is 1 - 10 μm, such as 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0039] Preferably, the temperature of the curing and repair treatment is 350 - 500 °C, such as 350 °C, 360 °C, 380 °C, 400 °C, 420 °C, 440 °C, 460 °C, 480 °C, 500 °C, etc.

[0040] Preferably, the metallization treatment is: forming an N-region electrode on the back surface of the cell through metallization treatment.

[0041] As an optional technical solution of the present invention, the preparation method of the TOPCon cell with reduced backside parasitic absorption specifically includes the following steps:

[0042] S1. Form a first tunneling oxide layer on the back surface of the N-type crystalline silicon substrate;

[0043] S2. Deposit an intrinsic polysilicon layer and a second tunneling oxide layer on the first tunneling oxide layer;

[0044] S3. Deposit a phosphorus-doped polysilicon layer and a third tunneling oxide layer on the second tunneling oxide layer;

[0045] S4. Form a transparent conductive thin film on the third tunneling oxide layer;

[0046] S5. Prepare a silicon nitride layer on the transparent conductive thin film; sequentially prepare an alumina layer and a silicon nitride layer on the front surface of the silicon substrate; and simultaneously carry out the curing and repair treatment;

[0047] S6. Form an N-region electrode on the back surface of the cell through metallization treatment to obtain the TOPCon cell with reduced backside parasitic absorption.

[0048] As an optional technical solution of the present invention, the pretreatment of the silicon substrate specifically includes the following steps:

[0049] (a) Texturing: Place the N-type crystalline silicon substrate in an alkaline solution for cleaning and texturing to form a pyramidal texture on the front surface of the N-type crystalline silicon substrate;

[0050] (b) First boron diffusion: Place the silicon substrate with a textured front surface in a diffusion furnace, introduce N 2 , O 2 and a boron source to perform the first boron diffusion deposition;

[0051] (c) Selective heavy doping: Utilize the high-temperature effect of SE laser for selective heavy doping;

[0052] (d) Second boron diffusion: Place the silicon substrate after selective heavy doping in a diffusion furnace, introduce N 2 , O 2 and a boron source to perform the second boron diffusion deposition;

[0053] (e) Removal of BSG: Place the silicon substrate after the second boron diffusion in an HF reagent for pickling to remove the BSG overcoat layer;

[0054] (f) Alkaline polishing treatment: Place the silicon substrate after removing the BSG layer in an alkaline polishing solution for alkaline polishing and cleaning to obtain the pre-treated N-type crystalline silicon substrate.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] (1) The method of the present invention reduces the thickness of the back Poly-Si layer, reduces parasitic absorption, increases light utilization rate, and improves the efficiency of the solar cell;

[0057] (2) In the method of the present invention, the Poly-Si layer adopts a laminated structure, which blocks the inward diffusion of the phosphorus source and reduces the corrosion damage of the silver paste to the Poly-Si layer and the tunneling layer, reduces recombination, and improves the efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0059] Figure 1 It is a schematic structural diagram of the TOPCon solar cell for reducing the back parasitic absorption described in the present invention.

[0060] Among them, 1 is an N-type crystalline silicon substrate, 2 is a first tunneling oxide layer, 3 is an intrinsic polysilicon layer, 4 is a second tunneling oxide layer, 5 is a phosphorus-doped polysilicon layer, 6 is a third tunneling oxide layer, 7 is a transparent conductive film, 8 is a backside silicon nitride layer, 9 is an N-region electrode, 10 is a B emitter, 11 is a front-side aluminum oxide layer, and 12 is a front-side silicon nitride layer. Detailed implementation manners

[0061] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meanings and scopes of the terms should be clear. However, in any case of potential ambiguity, the definitions provided herein shall prevail over any dictionary or extrinsic definition. In this application, unless otherwise specified, the use of "or" means "and / or". In addition, the use of the term "comprising" and other forms is non-restrictive.

[0062] It should be noted that specific details are set forth in the following description to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific implementation manners disclosed below.

[0063] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0064] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0065] The present invention will be further described below through embodiments. Unless otherwise specified, the materials in the embodiments are prepared according to existing methods or directly purchased from the market.

[0066] Such as Figure 1As shown, the present invention provides a TOPCon solar cell with reduced back parasitic absorption. The TOPCon solar cell includes an N-type crystalline silicon substrate 1. Among them, a first tunneling oxide layer 2, an intrinsic polysilicon layer 3, a second tunneling oxide layer 4, a phosphorus-doped polysilicon layer 5, a third tunneling oxide layer 6, a transparent conductive thin film 7, and a back silicon nitride layer 8 are sequentially covered on the back of the N-type crystalline silicon substrate 1. And an N-region electrode 9 is also provided on the back of the N-type crystalline silicon substrate 1. Among them, the front of the N-type crystalline silicon substrate 1 has a pyramid texture, and a B emitter 10, a front aluminum oxide layer 11, and a front silicon nitride layer 12 are sequentially covered on the front of the N-type crystalline silicon substrate 1.

[0067] Preparation Example 1

[0068] This preparation example provides a pretreatment method for an N-type crystalline silicon substrate. The pretreatment specifically includes the following steps:

[0069] (a) Texturing: Place the N-type crystalline silicon substrate in an alkaline solution and clean and texture it at 70 °C for 200 s to form a pyramid texture on the front of the N-type crystalline silicon substrate.

[0070] Among them, the alkaline solution includes the following components by mass percentage: sodium hydroxide 2%, sodium metasilicate 0.2%, isopropyl alcohol 3%, and the balance is water.

[0071] (b) First boron diffusion: Place the silicon substrate with a textured front in a diffusion furnace, and introduce N 2 , O 2 and a boron source to perform the first boron diffusion deposition.

[0072] Among them, in the first boron diffusion: the flow rate of N 2 is 15000 sccm, the flow rate of O 2 is 150 sccm, and the flow rate of boron tribromide is 400 sccm; the temperature of the first boron diffusion deposition is 1000 °C, the heating rate of the first boron diffusion deposition is 5 °C / min, and the time of the first boron diffusion deposition is 20 min.

[0073] (c) Selective heavy doping: Use the high-temperature effect of SE laser to perform selective heavy doping.

[0074] Among them, the emitter power of the SE laser is 100 W, the engraving speed is 450000 mm / s, and the temperature is 1000 °C.

[0075] (d) Second boron diffusion: Place the silicon substrate after selective heavy doping in a diffusion furnace, and introduce N 2 , O 2 and a boron source to perform the second boron diffusion deposition.

[0076] Among them, in the secondary boron diffusion: the N 2 flow rate is 30,000 sccm, the O 2 flow rate is 200 sccm, and the flow rate of boron tribromide is 100 sccm; the temperature of the second boron diffusion deposition is 900 °C, the heating rate of the second boron diffusion deposition is 5 °C / min, and the time of the second boron diffusion deposition is 60 min.

[0077] (e) Removing BSG: Placing the silicon substrate after secondary boron diffusion in an aqueous solution of 5 wt% HF for pickling to remove the BSG bypass coating;

[0078] Among them, the temperature of the pickling is 50 °C, and the time of the pickling is 400 s.

[0079] (d) Alkaline polishing treatment: Placing the silicon substrate after removing the BSG layer in an alkaline polishing solution for alkaline polishing and cleaning to obtain a pre-treated N-type crystalline silicon substrate;

[0080] Among them, the alkaline polishing solution comprises the following components by mass percentage: 3% sodium hydroxide, 1% hydrogen peroxide, and the balance is water; the temperature of the alkaline polishing is 60 °C, and the time is 120 s.

[0081] Example 1

[0082] This example provides a method for preparing a TOPCon solar cell with reduced backside parasitic absorption, and the preparation method specifically includes the following steps:

[0083] S1. Forming a 1-nm first tunneling oxide layer on the back surface of the pre-treated N-type crystalline silicon substrate provided in Preparation Example 1 by using the PECVD process;

[0084] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are: the temperature is 500 °C; the process chamber pressure is 150 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:8.

[0085] S2. Depositing a 5-nm intrinsic polysilicon layer and a 0.8-nm second tunneling oxide layer on the first tunneling oxide layer by using the PECVD process;

[0086] Among them, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are: the temperature is 350 °C; the pressure condition is 1300 mTorr; the process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of SiH 4 to H 2 is 1:3;

[0087] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are as follows: the temperature is 400 °C; the process chamber pressure is 100 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:6.

[0088] S3. Deposit a 50-nm phosphorus-doped polysilicon layer (the doping concentration of phosphorus is 1×10 19 cm -3 ) and a 1.5-nm third tunneling oxide layer on the second tunneling oxide layer by using the PECVD process;

[0089] Among them, the process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are as follows: the temperature is 350 °C; the pressure condition is 1300 mTorr; the process gas is PH 3 , SiH 4 and H 2 mixed gas, and the volume ratio of PH 3 , SiH 4 and H 2 is 1:1:3;

[0090] Among them, the process parameters of the PECVD process for depositing the third tunneling oxide layer are as follows: the temperature is 400 °C; the process chamber pressure is 100 Pa; the process gas is N 2 O and Ar mixed gas, and the volume ratio of N 2 O to Ar is 1:6.

[0091] S4. Form a 15-nm indium tin oxide transparent conductive film on the third tunneling oxide layer;

[0092] Among them, the process parameters of the PVD for preparing the transparent conductive film are as follows: the deposition pressure is 0.1 Pa, the deposition temperature is 200 °C, and the power density is 1 W / cm 2 .

[0093] S5. Prepare a 30-μm silicon nitride layer on the transparent conductive film; sequentially prepare a 2-μm aluminum oxide layer and a 30-μm silicon nitride layer on the front surface of the silicon substrate; and simultaneously perform a curing and repairing treatment at 350 °C;

[0094] S6. Form an N-region electrode on the back surface of the cell by metallization treatment to obtain the TOPCon cell with reduced backside parasitic absorption.

[0095] Example 2

[0096] This example provides a method for preparing a TOPCon cell with reduced backside parasitic absorption. The preparation method specifically includes the following steps:

[0097] S1. Form a 1.3 - nm first tunneling oxide layer on the back surface of the pretreated N - type crystalline silicon substrate provided in Preparation Example 1 by using the PECVD process;

[0098] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are: the temperature is 550 °C; the process chamber pressure is 180 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:9.

[0099] S2. Deposit a 10 - nm intrinsic polysilicon layer and a 1.2 - nm second tunneling oxide layer on the first tunneling oxide layer by using the PECVD process;

[0100] Among them, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are: the temperature is 400 °C; the pressure condition is 1500 mTorr; the process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of SiH 4 to H 2 is 1:4;

[0101] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are: the temperature is 440 °C; the process chamber pressure is 120 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:7.

[0102] S3. Deposit a 35 - nm phosphorus - doped polysilicon layer (the doping concentration of phosphorus is 1×10 20 cm -3 ) and a 1.0 - nm third tunneling oxide layer on the second tunneling oxide layer by using the PECVD process;

[0103] Among them, the process parameters of the PECVD process for depositing the phosphorus - doped polysilicon layer are: the temperature is 380 °C; the pressure condition is 1600 mTorr; the process gas is PH 3 , SiH 4 and H 2 , and the volume ratio of PH 3 , SiH 4 to H 2 is 1:2:4;

[0104] Among them, the process parameters of the PECVD process for depositing the third tunneling oxide layer are: the temperature is 450 °C; the process chamber pressure is 110 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2The volume ratio of O and Ar is 1:7.

[0105] S4. Form a 30-nm zinc aluminum oxide transparent conductive film on the third tunneling oxide layer;

[0106] Among them, the process parameters of the PVD for preparing the transparent conductive film are: the deposition pressure is 0.2 Pa, the deposition temperature is 250 °C, and the power density is 2 W / cm 2 .

[0107] S5. Prepare a 35-μm silicon nitride layer on the transparent conductive film; sequentially prepare a 5-μm aluminum oxide layer and a 35-μm silicon nitride layer on the front surface of the silicon substrate; and simultaneously perform a curing and repairing treatment at 420 °C;

[0108] S6. Form an N-region electrode on the back surface of the cell by metallization treatment to obtain the TOPCon cell with reduced backside parasitic absorption.

[0109] Example 3

[0110] This example provides a method for preparing a TOPCon cell with reduced backside parasitic absorption, and the preparation method specifically includes the following steps:

[0111] S1. Use the PECVD process to form a 1.6-nm first tunneling oxide layer on the back surface of the pretreated N-type crystalline silicon substrate provided in Preparation Example 1;

[0112] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are: the temperature is 600 °C; the process chamber pressure is 200 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of the N 2 O and Ar is 1:10.

[0113] S2. Use the PECVD process to deposit a 20-nm intrinsic polysilicon layer and a 1.5-nm second tunneling oxide layer on the first tunneling oxide layer;

[0114] Among them, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are: the temperature is 450 °C; the pressure condition is 1800 mTorr; the process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of the SiH 4 and H 2 is 1:5;

[0115] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are: the temperature is 480 °C; the process chamber pressure is 150 Pa; the process gas is a mixed gas of N 2 O and Ar, and the N2 The volume ratio of O to Ar is 1:8.

[0116] S3. Deposit a 20-nm phosphorus-doped polysilicon layer (the doping concentration of phosphorus is 1×10 21 cm -3 ) and a 0.8-nm third tunneling oxide layer on the second tunneling oxide layer by using the PECVD process;

[0117] Among them, the process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are: the temperature is 400 °C; the pressure condition is 1800 mTorr; the process gas is PH 3 , SiH 4 and H 2 mixed gas, and the volume ratio of the PH 3 , SiH 4 and H 2 is 1:3:5;

[0118] Among them, the process parameters of the PECVD process for depositing the third tunneling oxide layer are: the temperature is 480 °C; the process chamber pressure is 150 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of the N 2 O to Ar is 1:8.

[0119] S4. Form a 50-nm indium zinc oxide transparent conductive film on the third tunneling oxide layer;

[0120] Among them, the process parameters of the PVD for preparing the transparent conductive film are: the deposition pressure is 0.5 Pa, the deposition temperature is 300 °C, and the power density is 3 W / cm 2 .

[0121] S5. Prepare a 40-μm silicon nitride layer on the transparent conductive film; sequentially prepare a 2-μm aluminum oxide layer and a 40-μm silicon nitride layer on the front surface of the silicon substrate; and simultaneously perform a curing and repair treatment at 420 °C;

[0122] S6. Form an N-region electrode on the back surface of the cell by metallization treatment to obtain the TOPCon cell with reduced backside parasitic absorption.

[0123] Example 4

[0124] This example provides a method for preparing a TOPCon cell with reduced backside parasitic absorption. The difference from Example 1 is only that in S2, a 50-nm intrinsic polysilicon layer is deposited on the first tunneling oxide layer by using the PECVD process; in S3, a 5-nm phosphorus-doped polysilicon layer is deposited on the second tunneling oxide layer by using the PECVD process; and the other steps are exactly the same as those in Example 1.

[0125] Example 5

[0126] This example provides a method for preparing a TOPCon solar cell with reduced backside parasitic absorption. The difference from Example 1 is only that in S2, a 2-nm intrinsic polysilicon layer is deposited on the first tunneling oxide layer by PECVD process; in S3, a 53-nm phosphorus-doped polysilicon layer is deposited on the second tunneling oxide layer by PECVD process; other steps are exactly the same as those in Example 1.

[0127] Comparative Example 1

[0128] This comparative example provides a method for preparing a TOPCon solar cell, and the preparation method specifically includes the following steps:

[0129] S1. Form a 1-nm first tunneling oxide layer on the backside of the pretreated N-type crystalline silicon substrate provided in Preparation Example 1 by PECVD process;

[0130] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are: temperature is 500 °C; process chamber pressure is 150 Pa; process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O and Ar is 1:8.

[0131] S2. Deposit a 55-nm phosphorus-doped polysilicon layer (phosphorus doping concentration is 1×10 19 cm -3 ) and a 2.5-nm second tunneling oxide layer on the second tunneling oxide layer by PECVD process;

[0132] Among them, the process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are: temperature is 350 °C; pressure condition is 1300 mTorr; process gas is a mixed gas of PH 3 , SiH 4 and H 2 , and the volume ratio of PH 3 , SiH 4 and H 2 is 1:1:3;

[0133] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are: temperature is 400 °C; process chamber pressure is 100 Pa; process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O and Ar is 1:6.

[0134] S3. Form a 15-nm indium tin oxide transparent conductive film on the second tunneling oxide layer;

[0135] Among them, the process parameters of PVD for preparing the transparent conductive film are as follows: the deposition pressure is 0.1 Pa, the deposition temperature is 200 °C, and the power density is 1 W / cm 2 .

[0136] S4. Prepare a 30-μm silicon nitride layer on the transparent conductive film; sequentially prepare a 2-μm aluminum oxide layer and a 30-μm silicon nitride layer on the front surface of the silicon substrate; and simultaneously perform a curing and repair treatment at 350 °C;

[0137] S5. Form an N-region electrode on the back surface of the cell by metallization to obtain the TOPCon cell with reduced back parasitic absorption.

[0138] Comparative Example 2

[0139] This comparative example provides a method for preparing a TOPCon cell, and the preparation method specifically includes the following steps:

[0140] S1. Use PECVD process to form a 1-nm first tunneling oxide layer on the back surface of the pretreated N-type crystalline silicon substrate provided in Preparation Example 1;

[0141] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are as follows: the temperature is 500 °C; the process chamber pressure is 150 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:8.

[0142] S2. Use PECVD process to deposit a 55-nm intrinsic polysilicon layer and a 2.5-nm second tunneling oxide layer on the first tunneling oxide layer;

[0143] Among them, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are as follows: the temperature is 350 °C; the pressure condition is 1300 mTorr; the process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of SiH 4 to H 2 is 1:3;

[0144] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are as follows: the temperature is 400 °C; the process chamber pressure is 100 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:6.

[0145] S3. Form a 15-nm indium tin oxide transparent conductive film on the second tunneling oxide layer;

[0146] Among them, the process parameters of PVD for preparing the transparent conductive film are as follows: the deposition pressure is 0.1 Pa, the deposition temperature is 200 °C, and the power density is 1 W / cm 2 .

[0147] S4. Deposit a 30-μm silicon nitride layer on the transparent conductive film; sequentially deposit a 2-μm aluminum oxide layer and a 30-μm silicon nitride layer on the front side of the silicon substrate; simultaneously perform a curing and repair treatment at 350 °C;

[0148] S5. Form an N-region electrode on the back of the cell by metallization treatment to obtain the TOPCon cell with reduced back parasitic absorption.

[0149] Comparative Example 3

[0150] This comparative example provides a method for preparing a TOPCon cell, and the preparation method specifically includes the following steps:

[0151] S1. Use the PECVD process to form a 1-nm first tunneling oxide layer on the back of the pre-treated N-type crystalline silicon substrate provided in Preparation Example 1;

[0152] Among them, the process parameters of the PECVD process for depositing the first tunneling oxide layer are as follows: the temperature is 500 °C; the process chamber pressure is 150 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:8.

[0153] S2. Use the PECVD process to deposit a 5-nm intrinsic polysilicon layer and a 0.8-nm second tunneling oxide layer on the first tunneling oxide layer;

[0154] Among them, the process parameters of the PECVD process for depositing the intrinsic polysilicon layer are as follows: the temperature is 350 °C; the pressure condition is 1300 mTorr; the process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of SiH 4 to H 2 is 1:3;

[0155] Among them, the process parameters of the PECVD process for depositing the second tunneling oxide layer are as follows: the temperature is 400 °C; the process chamber pressure is 100 Pa; the process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:6.

[0156] S3. Use the PECVD process to deposit a 50-nm phosphorus-doped polysilicon layer (the doping concentration of phosphorus is 1×1019 cm -3 ) and a third tunneling oxide layer of 1.5 nm;

[0157] Among them, the process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are: the temperature is 350 °C; the pressure condition is 1300 mTorr; the process gas is PH 3 , SiH 4 and H 2 mixed gas, and the volume ratio of the PH 3 , SiH 4 and H 2 is 1:1:3;

[0158] Among them, the process parameters of the PECVD process for depositing the third tunneling oxide layer are: the temperature is 400 °C; the process chamber pressure is 100 Pa; the process gas is N 2 O and Ar mixed gas, and the volume ratio of the N 2 O and Ar is 1:6.

[0159] S4. Prepare a 30-μm-thick silicon nitride layer on the third tunneling oxide layer; sequentially prepare a 2-μm-thick aluminum oxide layer and a 30-μm-thick silicon nitride layer on the front surface of the silicon substrate; and perform a curing repair treatment at 350 °C at the same time.

[0160] S5. Form an N-region electrode on the back surface of the cell by metallization treatment to obtain the TOPCon cell with reduced back parasitic absorption.

[0161] Comparative Example 4

[0162] This comparative example provides a method for preparing a TOPCon cell, which is only different from Example 1 in that in S4, the curing repair treatment is no longer performed, but directly the S5 metallization treatment is carried out.

[0163] Test Example

[0164] Test samples: TOPCon cells with reduced back parasitic absorption provided in Examples 1 to 5, and TOPCon cells provided in Comparative Examples 1 to 4;

[0165] Test method: Use a solar simulation electrical efficiency tester to perform electrical performance tests, and test under standard conditions (atmospheric mass AM1.5, light intensity 1000 W / m 2 , test temperature 25 °C);

[0166] The test results are shown in Table 1 below:

[0167] Table 1

[0168]

[0169]

[0170] As shown in Table 1, the conversion efficiency of the double-sided tunneling passivated contact battery prepared by the present invention is significantly improved. Thus, it can be seen that the TOPCon cell for reducing the backside parasitic absorption described in the present invention has the advantages of good passivation effect, less parasitic absorption, high conversion efficiency, etc. This fully demonstrates that the preparation method described in the present invention reduces the thickness of the backside Poly-Si layer, reduces the parasitic absorption, increases the light utilization rate, and improves the efficiency of the cell; and the Poly-Si layer adopts a stacked structure to block the inward diffusion of the phosphorus source and reduce the corrosion damage of the silver paste to the Poly-Si layer and the tunneling layer, reduce the recombination, and improve the efficiency of the cell.

[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a TOPCon cell with reduced back side parasitic absorption, characterized in that: The preparation method comprises the following steps: forming a first tunneling oxide layer on the back side of the N-type crystalline silicon substrate; Wherein, the thickness of the first tunneling oxide layer is 1 to 1.6 nm; depositing an intrinsic polysilicon layer and a second tunneling oxide layer on the first tunneling oxide layer; Wherein, the thickness of the intrinsic polysilicon layer is 5 to 20 nm; the thickness of the second tunneling oxide layer is 0.8 to 1.5 nm; depositing a phosphorus-doped polysilicon layer and a third tunneling oxide layer on the second tunneling oxide layer; The thickness of the phosphorus-doped polysilicon layer is 20-50 nm; the thickness of the third tunnel oxide layer is 0.8-1.5 nm; and the phosphorus doping concentration in the phosphorus-doped polysilicon layer is 1×10 19 ~1×10 21 cm -3 ; forming a transparent conductive film on the third tunneling oxide layer; The material of the transparent conductive film is selected from any one of indium tin oxide, aluminum zinc oxide or indium zinc oxide or a combination of at least two thereof; the thickness of the transparent conductive film is 15 to 70 nm; After the transparent conductive film is formed, it also includes surface passivation treatment and metallization treatment in sequence; the surface passivation treatment specifically includes the following steps: preparing a silicon nitride layer on the transparent conductive film; preparing an aluminum oxide layer and a silicon nitride layer in sequence on the front side of the silicon substrate; and performing a curing repair treatment at the same time; the temperature of the curing repair treatment is 350-500°C.

2. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The first tunnel oxide layer is deposited by a PECVD process.

3. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 2, characterized in that: The process parameters of the PECVD process for depositing the first tunnel oxide layer are: temperature of 500-600° C.; process chamber pressure of 150-200 Pa; process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:(8-10).

4. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The intrinsic polysilicon layer and the second tunnel oxide layer are both deposited by a PECVD process.

5. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 4, characterized in that: The process parameters of the PECVD process for depositing the intrinsic polysilicon layer are: temperature of 350-450° C.; pressure condition of 1300-1800 mTorr; process gas is a mixed gas of SiH 4 and H 2 , and the volume ratio of SiH 4 to H 2 is 1:(3-5).

6. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 4, characterized in that: The process parameters of the PECVD process for depositing the second tunnel oxide layer are: temperature of 400-480° C.; process chamber pressure of 100-150 Pa; process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:(6-8).

7. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The phosphorus-doped polysilicon layer and the third tunnel oxide layer are both deposited by a PECVD process.

8. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 7, characterized in that: The process parameters of the PECVD process for depositing the phosphorus-doped polysilicon layer are: temperature of 350-400°C; pressure condition of 1300-1800mTorr; process gas is a mixed gas of PH3, SiH4 and H2, and the volume ratio of PH3, SiH4 and H2 is 1:(1-3):(3-5).

9. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 7, characterized in that: The process parameters of the PECVD process for depositing the third tunnel oxide layer are: temperature of 400-480° C.; process chamber pressure of 100-150 Pa; process gas is a mixed gas of N 2 O and Ar, and the volume ratio of N 2 O to Ar is 1:(6-8).

10. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The transparent conductive film is prepared by PVD sputtering method.

11. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 10, characterized in that: The PVD process parameters for preparing the transparent conductive film are: deposition pressure of 0.1-1.0 Pa, deposition temperature of 200-300° C., power density of 1-5 W / cm 2 .

12. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The silicon substrate needs to be pre-treated when preparing the first tunnel oxide layer, and the pre-treatment specifically includes: texturing, primary boron diffusion, selective re-doping, secondary boron diffusion, BSG removal and alkali polishing.

13. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The thickness of the silicon nitride layer is 30-40 μm.

14. The method for preparing a TOPCon cell with reduced back side parasitic absorption according to claim 1, characterized in that: The thickness of the aluminum oxide layer is 1 to 10 μm.

15. The method for preparing a TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The metallization treatment is: forming an N-region electrode on the back side of the battery cell through the metallization treatment.

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