Residue calculation method and device, password processing method and related equipment

Abstract

Embodiments of the present application provide a remainder calculation method and device, a password processing method and related equipment. The remainder calculation method comprises: obtaining to-be-calculated data, the to-be-calculated data being an integer with a bit number greater than or equal to 128; converting the to-be-calculated data into a preset expression form, a preset coefficient in the preset expression form being obtained based on preset bit number division of the to-be-calculated data, the preset bit number being the bit width of the calculation device; and performing remainder operation of the to-be-calculated data and the prime number based on conversion of the preset coefficient in the preset expression form. The remainder calculation method can greatly improve the calculation efficiency of the remainder operation, thereby improving the corresponding password operation efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer processing technology, specifically to a modulo calculation method and apparatus, a cryptographic processing method and related equipment. Background Technology

[0002] To enhance data security, encrypted computations are typically performed on the data. A typical encrypted computation process includes modular addition, modular subtraction, modular multiplication, and modular squaring. Modular multiplication can be broken down into multiplication of multi-precision integers and the remainder operation. The remainder operation is used to calculate the remainder when the dividend is divided by the divisor.

[0003] On current general-purpose computers, the remainder operation is relatively time-consuming. Therefore, how to improve the computational efficiency of the remainder operation is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a modulo calculation method and apparatus, a cryptographic processing method and related equipment, to improve the computational efficiency of modulo operations.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, embodiments of the present invention provide a remainder calculation method, applied to a computing device to calculate the remainder of a data to be calculated with respect to a prime number, comprising:

[0007] Obtain the data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128;

[0008] The data to be calculated is converted into a preset expression form, and the preset coefficients in the preset expression form are obtained by dividing the data to be calculated by a preset number of bits, wherein the preset number of bits is the bit width of the computing device.

[0009] Based on the preset coefficients in the preset expression form, a modulo operation adapted to the preset number of digits is performed to obtain the remainder between the data to be calculated and the prime number.

[0010] Optionally, the step of performing a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form to obtain the remainder between the data to be calculated and the prime number includes:

[0011] Based on the conversion of the preset coefficients, the first coefficient of the initial expression of the remainder operation is calculated; the initial expression is obtained based on the initial substitution of prime numbers into the expression during the remainder operation.

[0012] Based on the first coefficient, a second coefficient that conforms to the bit width expression of the computing device is calculated;

[0013] Based on the second coefficient, the third coefficient of the target expression of the remainder operation is calculated; the target expression is obtained by substituting prime numbers into the expression again during the remainder operation.

[0014] The result of the modulo operation is determined based on the target expression and the third coefficient.

[0015] Optionally, if the highest digit level of the target expression corresponding to the third coefficient is greater than or equal to the highest digit level of the prime number substitution expression, determining the result of the modulo operation based on the target expression and the third coefficient includes:

[0016] Based on the third coefficient, the fourth coefficient of the reduction expression of the remainder operation is calculated; the reduction expression is obtained by reducing the prime number after the third substitution in the prime number substitution expression during the remainder operation.

[0017] The result of the remainder operation is determined based on the value of the reduction expression corresponding to the fourth coefficient.

[0018] Optionally, determining the result of the modulo operation based on the value of the reduction expression corresponding to the fourth coefficient includes:

[0019] Determine whether the value of the reduction expression corresponding to the fourth coefficient is less than the prime number;

[0020] If so, the value of the reduction expression corresponding to the fourth coefficient is taken as the result of the remainder operation;

[0021] If not, perform the subtraction operation between the value of the reduction expression corresponding to the fourth coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0022] Optionally, if the highest digit level of the target expression corresponding to the third coefficient is less than the highest digit level of the prime number substitution expression, determining the result of the modulo operation based on the target expression and the third coefficient includes:

[0023] Determine whether the value of the target expression corresponding to the third coefficient is less than the prime number;

[0024] If so, the value of the target expression corresponding to the third coefficient is taken as the result of the modulo operation;

[0025] If not, perform the subtraction of the target expression corresponding to the third coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0026] Optionally, the bit width of the computing device is 64, the preset bit width is 64, the data to be calculated is 512 bits, and the preset expression form is: ;

[0027] Z = z7·2 448 +z6·2 384 +z5·2 320 +z4·2 256 +z3·2 192 +z2·2 128 +z1·2 64 +z0;

[0028] Among them, z i is a preset coefficient, and i is an integer.

[0029] Optionally, in the step of obtaining the first coefficient of the initial expression of the modulo operation based on the conversion of the preset coefficients, the initial expression is:

[0030] Z mod p = d7·2 224 +d6·2 192 +d5·2 160 +d4·2 128 +d3·2 96 +D2·2 64 +d1·2 32 +d0;

[0031] Where, d i The set of is the first coefficient, where i is an integer. The conversion from the preset coefficient to the first coefficient is specifically as follows:

[0032] d7=z4+z5+2·z6+2·z7, d6=z7, d5=z5+z7, d4=z6+2·z7, d3=z4+z6+z7, d2=-(z4+z7), d1=z5+z6+2·z7, d0=z4+z5+z6+2·z7;

[0033] The prime number substitution expression is:

[0034] 2 256 =2 224 +2 96 -2 64 +1mod p.

[0035] Optionally, in the step of converting the first coefficient in the initial expression to a second coefficient that conforms to the bit width expression of the computing device, the expression corresponding to the second coefficient is designated as an intermediate expression, wherein the intermediate expression is:

[0036] Z mod p = f4·2 256 +F3·2 192+f2·2 128 +f1·2 64 +f0;

[0037] Among them, f i The set of is the second coefficient, where i is an integer. The conversion from the first coefficient to the second coefficient is as follows:

[0038] f0 = e0 + e1 << 32,

[0039] f1=e1>>32+e2+e3<<32,

[0040] f2=e3>>32+e4+e5<<32,

[0041] f3=e5>>32+e6+e7<<32,

[0042] f4 = e7 >> 32 + e8 << 32;

[0043] in:

[0044] e0 = d0 & 0xFFFFFFFFFFFFFFFF,

[0045] e i =d i &0xFFFFFFFFFFFFFFFF+d i-1 >>64, i = 1, 2, ..., 7;

[0046] e8 = d7 >> 64.

[0047] Optionally, in the step of obtaining the third coefficient of the target expression for the modulo operation based on the transformation of the second coefficient, the target expression is:

[0048] Z mod p = g4·2 256 +g3·2 192 +g2·2 128 +g1·2 64 +g0;

[0049] Among them, g i The set of coefficients is the third coefficient, where i is an integer. The conversion from the second coefficient to the third coefficient is as follows:

[0050] g0=t0&0xFFFFFFFFFFFFFFFF, where t0=f0+f4;

[0051] g1 = t1 & 0xFFFFFFFFFFFFFFFF,

[0052] Where, t1 = t0 >> 64 + f1 - f4 + (f4 & 0xFFFFFFFF) << 32;

[0053] g2=t2&0xFFFFFFFFFFFFFFFFF, where t2=t1>>64+f2+f4>>32;

[0054] g3 = t3 & 0xFFFFFFFFFFFFFFFF,

[0055] Where, t3 = t2 >> 64 + f3 + (f4 & 0xFFFFFFFF) << 32;

[0056] g4 = t3 >> 64 + f4 >> 32.

[0057] Optionally, in the step of calculating the fourth coefficient of the reduction expression of the modulo operation based on the third coefficient, the reduction expression is:

[0058] Z mod p = h3·2 192 +h2·2 128 +h1·2 64 +h0;

[0059] Among them, h i The set of coefficients is the fourth coefficient, where i is an integer. The conversion from the third coefficient to the fourth coefficient is as follows:

[0060] h0=k0&0xFFFFFFFFFFFFFFFF, where k0=g0+g4;

[0061] h1 = k1 & 0xFFFFFFFFFFFFFFFF,

[0062] Where, k1 = k0 >> 64 + g1 - g4 + (g4 & 0xFFFFFFFF) << 32;

[0063] h2=k2&0xFFFFFFFFFFFFFFFF, where k2=k1>>64+g2+g4>>32;

[0064] h3 = k3 & 0xFFFFFFFFFFFFFFFF,

[0065] Among them, k3=k2>>64+g3+(g4&0xFFFFFFFF)<<32.

[0066] Secondly, embodiments of the present invention also provide a remainder calculation device, comprising:

[0067] The data acquisition module is used to acquire data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128.

[0068] The data conversion module is used to convert the data to be calculated into a preset expression form, wherein the preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of bits, and the preset number of bits is the bit width of the computing device;

[0069] The data calculation module is used to perform a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form, so as to obtain the remainder between the data to be calculated and the prime number.

[0070] Thirdly, embodiments of the present invention also provide a cryptographic processing method, which uses the remainder calculation method provided in embodiments of the present invention to calculate the remainder between the data to be calculated and a prime number.

[0071] Fourthly, embodiments of the present invention also provide a cryptographic coprocessor, including a processing module and a storage module. The storage module stores a program, and the processing module is used to call the program in the storage module to execute the modulo calculation method provided in embodiments of the present invention.

[0072] Fifthly, embodiments of the present invention also provide a chip including the cryptographic coprocessor provided in embodiments of the present invention.

[0073] In a sixth aspect, embodiments of the present invention also provide a computer device, including the chip provided in the embodiments of the present invention.

[0074] This invention provides a modulo operation method and apparatus, a cryptographic processing method, and related equipment. The modulo operation method includes: acquiring data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128; converting the data to be calculated into a preset expression form, wherein preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of digits, wherein the preset number of digits is the bit width of the computing device; and performing a modulo operation between the data to be calculated and the prime number based on the conversion of the preset coefficients in the preset expression form.

[0075] As can be seen, in this embodiment of the invention, when calculating the remainder of the data to be calculated, the data to be calculated is transformed into a preset expression form. In this preset expression form, preset coefficients are obtained by dividing the data to be calculated into preset number of bits. The preset number of bits is equal to the bit width of the computing device. That is to say, in this embodiment of the invention, the data to be calculated is transformed into a preset expression form adapted to the bit width of the computing device. Then, based on the preset coefficients in this preset expression form, a remainder operation adapted to the preset number of bits is performed to obtain the remainder of the data to be calculated and a prime number. In other words, the remainder calculation method described in this embodiment of the invention can perform a remainder operation adapted to the preset number of bits (i.e., the bit width of the computing device) based on the preset expression form of the data to be calculated, thereby greatly improving the calculation efficiency of the remainder operation, and thus improving the efficiency of the corresponding cryptographic operations. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0077] Figure 1 A schematic diagram of an optional process for a remainder calculation method provided in an embodiment of the present invention;

[0078] Figure 2 This is an optional flowchart illustrating step S120 provided in an embodiment of the present invention;

[0079] Figure 3 This is an optional flowchart illustrating step S124 provided in an embodiment of the present invention;

[0080] Figure 4 This is an optional flowchart illustrating step S242 provided in an embodiment of the present invention;

[0081] Figure 5 This is another optional flowchart illustrating step S124 provided in an embodiment of the present invention;

[0082] Figure 6 This is an optional block diagram of the remainder calculation device provided in an embodiment of the present invention. Detailed Implementation

[0083] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0084] Data encryption processed by computers is typically based on specific cryptographic algorithms. Common cryptographic algorithms include elliptic curve cryptosystems (ECC) and RSA (Rivest-Shamir-Adleman) cryptosystems. A specific elliptic curve cryptosystem algorithm is the SM2 algorithm, which was released by the China Cryptography Administration in 2012 and is described in detail in the standard "GMT 0003-2012 SM2 Elliptic Curve Public Key Cryptography Algorithm". The SM2 algorithm consists of three parts: a signature algorithm, an encryption algorithm, and a key negotiation algorithm. Among these three parts, the dot product operation of elliptic curves accounts for the majority of the time consumption. Elliptic curve dot product can be decomposed into multiple prime field operations. In specific implementations, prime field operations can include modular addition, modular subtraction, modular multiplication, and modular squaring. Modular multiplication is further decomposed into multiplication of multi-precision integers and modulo operations. It is understandable that the modulo operation is used to calculate the remainder after dividing the dividend by the divisor. Utilizing the special form of the divisor can improve the efficiency of the modulo operation.

[0085] Clearly, the computational efficiency of the remainder operation is crucial to improving the efficiency of cryptographic operations.

[0086] The inventors argue that existing general-purpose computers can only perform modulo operations based on preset calculation methods, which are fixed and pre-defined to suit current hardware conditions. However, the inventors further believe that with continuous technological advancements and the development of integrated circuits, the hardware conditions of computing devices are constantly improving. Clearly, when the hardware conditions of computing devices improve, but the corresponding calculation methods are no longer suitable for those conditions, the computational efficiency of modulo operations will be constrained by the existing methods.

[0087] Taking the existing general-purpose computing method as an example, which is adapted to computing devices with a bit width of 32 bits (i.e., 32-bit machines), when using computing devices with a bit width of 64 bits (i.e., 64-bit machines) to perform the modulo operation, the limitation of the computing method will prevent the 64-bit machine from effectively utilizing its own computing power, and the corresponding computing efficiency needs to be improved.

[0088] In view of this, embodiments of the present invention provide a modulo calculation method and apparatus, a cryptographic processing method and related equipment. The modulo calculation method includes: acquiring data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128; converting the data to be calculated into a preset expression form, wherein preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of digits, wherein the preset number of digits is the bit width of the computing device; and performing a modulo operation between the data to be calculated and the prime number based on the conversion of the preset coefficients in the preset expression form.

[0089] As can be seen, in this embodiment of the invention, when calculating the remainder of the data to be calculated, the data to be calculated is transformed into a preset expression form. In this preset expression form, preset coefficients are obtained by dividing the data to be calculated into preset number of bits. The preset number of bits is equal to the bit width of the computing device. That is to say, in this embodiment of the invention, the data to be calculated is transformed into a preset expression form adapted to the bit width of the computing device. Then, based on the preset coefficients in this preset expression form, a remainder operation adapted to the preset number of bits is performed to obtain the remainder of the data to be calculated and a prime number. In other words, the remainder calculation method described in this embodiment of the invention can perform a remainder operation adapted to the preset number of bits (i.e., the bit width of the computing device) based on the preset expression form of the data to be calculated, thereby greatly improving the calculation efficiency of the remainder operation, and thus improving the efficiency of the corresponding cryptographic operations.

[0090] For ease of understanding, please refer to Figure 1 , Figure 1 This is a schematic diagram of an optional flowchart of a modulo calculation method provided by an embodiment of the present invention. The modulo calculation method can run on the processor of a computing device, or on the coprocessor of the computing device, such as a cryptographic coprocessor, or it can run on a separate device on the computing device specifically designed for cryptographic calculations, such as a security processor. Specifically, the modulo calculation method includes:

[0091] Step S100: Obtain the data to be calculated, wherein the data to be calculated is an integer with 128 or more digits;

[0092] The data to be calculated is the dividend in the modulo operation, used to perform division with the divisor (i.e., the prime number in this embodiment of the invention) to obtain the corresponding remainder. The data to be calculated is an integer with more than or equal to 128 digits, where an integer greater than or equal to 128 can be understood as a large integer. In a specific example, the data to be calculated can have 512 digits.

[0093] The prime number is the divisor in this embodiment of the invention. The prime number is a fixed value selected in the cryptographic operation; this fixed value is a natural number greater than 1 and has only two positive factors: 1 and itself. Specifically, in the SM2 standard, the prime number is selected in the special form p = 2. 256 -2 224 -2 96 +2 64 -1 is used to improve the efficiency of the modulo operation. Based on this prime number, a prime field is constructed. The elliptic curve discrete logarithm problem over this prime field is computationally difficult, providing sufficient security for the SM2 cryptographic algorithm.

[0094] In this embodiment of the invention, the prime number expression is p = 2. 256 -2 224 -2 96 +2 64 Let's take -1 as an example to illustrate.

[0095] Step S110: Convert the data to be calculated into a preset expression form;

[0096] The preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of bits, where the preset number of bits is the bit width of the computing device.

[0097] The preset expression form is used to express the data to be calculated in a computing device based on an existing form (i.e., a formula). Since the data to be calculated is a large integer (an integer with 128 or more bits), in a computing device, such as a 32-bit or 64-bit device, the complete large integer cannot be stored based on that bit width. Instead, it needs to be expressed based on a corresponding form to record the data to be calculated. It is understood that this preset expression form is the basis for the modulo operation, and different preset expressions correspond to modulo operations with different preset bit widths.

[0098] In this embodiment of the invention, the preset expression can be segmented based on the bit width of the computing device. Specifically, the preset expression includes preset coefficients, which are obtained by segmenting the data to be calculated into preset number of bits. The preset number of bits is the bit width of the computing device, thereby enabling the modulo operation in this embodiment of the invention to be performed based on the preset expression with the preset number of bits (the bit width of the computing device), thus improving the computational efficiency of the modulo operation.

[0099] In a specific example, the preset coefficient refers to the set of coefficients in the preset expression. The preset coefficient may include multiple preset sub-coefficients, each corresponding to a different bit level and having a corresponding segmentation value. For example, the highest level (all levels mentioned in this embodiment are bit levels) of the preset sub-coefficient corresponds to the first N bits of the data to be calculated, the next level of the preset sub-coefficient corresponds to the N+1 to 2N bits of the data to be calculated, and so on, until the lowest level of the preset sub-coefficient corresponds to the last N bits of the data to be calculated. Here, N is the preset bit level, and in this embodiment, N is also the bit width of the computing device.

[0100] Taking a 64-bit computing device, a preset bit depth of 64 bits, and 512 bits of data to be calculated as an example, the preset expression is as follows:

[0101] Z = z7·2 448 +z6·2 384 +z5·2 320 +z4·2 256 +z3·2 192 +z2·2 128 +z1·2 64 +z0

[0102] Among them, z i The preset coefficients are denoted by i, where i is an integer. It can be understood that in the above expression, z7 is the value of the first 64 bits of the 512-bit data to be calculated, z6 is the value of bits 65 to 128 of the 512-bit data to be calculated, and so on.

[0103] Step S120: Based on the preset coefficients in the preset expression form, perform a modulo operation adapted to the preset number of digits to obtain the remainder between the data to be calculated and the prime number;

[0104] It is understandable that after the data to be calculated is converted into a preset expression form, the preset coefficients in the preset expression form are determined. Accordingly, the remainder between the data to be calculated and the prime number can be calculated based on the preset coefficients.

[0105] In this embodiment of the invention, the modulo operation is also adapted to the preset number of bits, so that the operation process of the modulo operation is adapted to the bit width of the computing device, thereby improving the calculation efficiency of the modulo operation.

[0106] Among them, reference Figure 2 , Figure 2 This is an optional flowchart illustrating step S120 provided in an embodiment of the present invention. The modulo operation adapted to the preset number of bits may include:

[0107] Step S121: Based on the conversion of the preset coefficients, calculate the first coefficient of the initial expression of the modulo operation;

[0108] The initial expression is obtained based on the initial substitution of prime numbers into the expression during the remainder operation, and is used as the initial expression of the remainder based on the first coefficient.

[0109] It should be noted that the first coefficient is used to refer to the set of coefficients in the initial expression. The first coefficient may include multiple first sub-coefficients. Different first sub-coefficients correspond to different bit levels and have corresponding coefficient values. For example, the highest level first sub-coefficient corresponds to the value of the first N bits of the initial expression, the next level first sub-coefficient corresponds to the value of the N+1 to 2N bits of the initial expression, and so on, until the lowest level first sub-coefficient corresponds to the value of the last N bits of the initial expression. Here, N is a preset number of bits. In this embodiment of the invention, N is also the bit width of the computing device.

[0110] The prime number substitution expression is as follows:

[0111] 2 256 =2 224 +2 96 -2 64 +1mod p

[0112] Based on the example where the computing device is a 64-bit computing device, the preset bit length is 64 bits, and the data to be calculated is 512 bits, the initial expression obtained by substituting the prime number into the preset expression is:

[0113] Z mod p = d7·2 224 +d6·2 192 +d5·2 160 +d4·2 128 +d3·2 96 +d2·2 64 +d1·2 32 +d0

[0114] Where, d i d is the first sub-coefficient. i The set of is the first coefficient, where i is an integer. The conversion from the preset coefficient to the first coefficient is specifically as follows:

[0115] d7 = z4 + z5 + 2·z6 + 2·z7,

[0116] d6 = z7,

[0117] d5 = z5 + z7,

[0118] d4 = z6 + 2·z7,

[0119] d3 = z4 + z6 + z7,

[0120] d2=-(z4+z7),

[0121] d1 = z5 + z6 + 2·z7,

[0122] d0 = z4 + z5 + z6 + 2·z7,

[0123] In a 64-bit computing device, the above calculation includes 17 64-bit additions and 2 64-bit subtractions. Since each 64-bit addition and subtraction requires one clock cycle, the above calculation can be completed in only 19 clock cycles.

[0124] It is understood that, based on the above coefficient transformation, the first coefficient and its corresponding initial expression described in the embodiments of the present invention can be obtained.

[0125] Step S122: Based on the first coefficient, calculate the second coefficient that conforms to the bit width expression of the computing device;

[0126] It should be noted that the bit width of the computing device is not considered in the initial expression. Therefore, after the conversion from the first coefficient to the second coefficient, the second coefficient is expressed in accordance with the bit width of the computing device.

[0127] Specifically, an expression conforming to the bit width of the computing device can be made based on an intermediate expression, where the second coefficient is a coefficient in the intermediate expression.

[0128] It should be noted that the second coefficient is used to refer to the set of coefficients in the intermediate expression. The second coefficient may include multiple second sub-coefficients. Different second sub-coefficients correspond to different bit levels and have corresponding coefficient values. For example, the highest level second sub-coefficient corresponds to the value of the first N bits of the intermediate expression, the next level second sub-coefficient corresponds to the value of the N+1 to 2N bits of the intermediate expression, and so on, until the lowest level second sub-coefficient corresponds to the value of the last N bits of the intermediate expression. Here, N is a preset number of bits. In this embodiment of the invention, N is also the bit width of the computing device.

[0129] Based on the example of a 64-bit computing device, a preset bit depth of 64 bits, and a 512-bit data to be calculated, the following intermediate expression is obtained after the initial expression derived from this example:

[0130] Z mod p = f4·2 256 +f3·2 192 +f2·2 128 +f1·2 64 +f0

[0131] Among them, f i f is the second sub-coefficient. i The set of is the second coefficient, where i is an integer. The conversion from the first coefficient to the second coefficient is as follows:

[0132] f0 = e0 + e1 << 32,

[0133] f1=e1>>32+e2+e3<<32,

[0134] f2=e3>>32+e4+e5<<32,

[0135] f3=e5>>32+e6+e7<<32,

[0136] f4 = e7 >> 32 + e8 << 32;

[0137] in:

[0138] e0 = d0 & 0xFFFFFFFFFFFFFFFFF,

[0139] e i =d i &0xFFFFFFFFFFFFFFFF+d i-1 >>64, i = 1, 2, ..., 7,

[0140] e8 = d7 >> 64

[0141] In 64-bit computing devices, the above e i The calculation, in performing the aforementioned initial expression d i The calculation can be performed simultaneously using 64-bit adder with carry (adc) and subtractor with borrow (sbb), thus eliminating the need for clock cycles.

[0142] The above f i The calculation involves eight 64-bit additions and nine shifts. The shifts and additions can be performed in parallel based on different arithmetic units, so the above calculation only requires nine clock cycles.

[0143] It is understood that, based on the above coefficient conversion, the second coefficient and its corresponding intermediate expression described in the embodiments of the present invention can be obtained.

[0144] Step S123: Based on the second coefficient, calculate the third coefficient of the target expression of the modulo operation;

[0145] After determining the second coefficient, a target expression for representing the remainder can be calculated, wherein the target expression is obtained by substituting prime numbers into the expression again during the modulo operation. It is understood that, based on the intermediate expression conforming to the bit width of the computing device, the calculation process for the third coefficient of the target expression also conforms to the calculation method for the bit width of the computing device.

[0146] The target expression can be understood as the preliminary result of the modulo operation. Specifically, in the target expression represented by the third coefficient, the third coefficient refers to the set of coefficients in the target expression. The third coefficient may include multiple third sub-coefficients, each corresponding to a different bit level and having a corresponding coefficient value. For example, the highest-level third sub-coefficient corresponds to the first N bits of the target expression, the next highest-level third sub-coefficient corresponds to the N+1 to 2N bits of the target expression, and so on, until the lowest-level third sub-coefficient corresponds to the last N bits of the target expression. Here, N is a preset bit width, and in this embodiment of the invention, N is also the bit width of the computing device.

[0147] Based on the example of a 64-bit computing device, a preset bit depth of 64 bits, and a 512-bit data to be calculated, the target expression obtained after obtaining the intermediate expression from this example is as follows:

[0148] Z mod p = g4·2 256 +g3·2 192 +g2·2 128 +g1·2 64 +g0

[0149] Among them, g i For the third sub-coefficient, g i The set of coefficients is the third coefficient, where i is an integer. The conversion from the second coefficient to the third coefficient is as follows:

[0150] g0=t0&0xFFFFFFFFFFFFFFFF, where t0=f0+f4;

[0151] g1=t1&0xFFFFFFFFFFFFFFFFFF,

[0152] Where, t1 = t0 >> 64 + f1 - f4 + (f4 & 0xFFFFFFFF) << 32;

[0153] g2=t2&0xFFFFFFFFFFFFFFFF, where t2=t1>>64+f2+f4>>32;

[0154] g3 = t3 & 0xFFFFFFFFFFFFFFFF,

[0155] Where, t3 = t2 >> 64 + f3 + (f4 & 0xFFFFFFFF) << 32;

[0156] g4 = t3 >> 64 + f4 >> 32;

[0157] In 64-bit computing devices, the above g i The calculation includes eight 64-bit additions and one 64-bit subtraction, and eight shifts. The shift operations can be performed in parallel during the execution of the 64-bit add instruction with carry (adc), without requiring additional clock cycles. Therefore, the above calculation only requires nine clock cycles.

[0158] It is understood that, based on the above coefficient conversion, the values ​​of the third coefficient and its corresponding target expression described in the embodiments of the present invention can be obtained.

[0159] Step S124: Determine the result of the modulo operation based on the target expression and the third coefficient;

[0160] Specifically, based on the target expression and the third coefficient, the value of the target expression can be determined, and it can be determined whether the value of the target expression is the result of the modulo operation. If the value of the target expression is not the result of the modulo operation, the result of the modulo operation can be calculated based on further reduction and other algorithms.

[0161] As can be seen, the modulo operation method described in this embodiment of the invention can perform a modulo operation adapted to a preset number of bits (i.e., the bit width of the computing device) based on a preset expression form of the data to be calculated, thereby maximizing the computational efficiency of the modulo operation and thus improving the efficiency of the corresponding cryptographic operation.

[0162] In an optional example, step S124 can roughly determine whether the value of the target expression is the result of a modulo operation based on the highest digit level of the target expression. It is understood that the highest digit level in the target expression may be higher than the highest digit level of the expression substituted with a prime number. In this case, it is necessary to determine the highest digit level of the corresponding target expression value to determine the magnitude of the target expression value, i.e., whether it is much larger than a prime number, and thus determine whether the value of the target expression corresponding to the third coefficient is a possible result of a modulo operation.

[0163] It should be noted that the highest bit level in the target expression can be the same as or different from the highest bit level of the corresponding target expression value. Specifically, if the third sub-coefficient corresponding to the highest bit level in the target expression is non-zero, then the highest bit level of the target expression value corresponding to that third coefficient is that highest bit level; if the third sub-coefficient corresponding to the highest bit level in the target expression is zero, and the third sub-coefficient corresponding to the next lower bit level in the target expression is non-zero, then the highest bit level of the target expression value corresponding to that third coefficient is that next lower bit level.

[0164] Taking a 64-bit computing device, a preset bit depth of 64 bits, and a target expression of 512 bits for the data to be calculated as an example, if g4 is non-zero, the highest bit depth of the target expression corresponding to the third coefficient is 2. 256 If g4 is 0 and g3 is non-zero, then the highest bit level of the objective expression corresponding to the third coefficient is 2. 192 .

[0165] In a specific example, if the highest digit level of the target expression corresponding to the third coefficient is greater than or equal to the highest digit level of the prime number substitution expression, then the value of the target expression corresponding to the third coefficient is considered to be much greater than the prime number. Accordingly, the target expression corresponding to the third coefficient needs to be further reduced.

[0166] Based on the above, the prime number expression is p = 2. 256 -2 224 -2 96 +2 64 -1 corresponds to a superlative number of 2. 256 Therefore, in the above example, if g4 is non-zero, it is considered that the highest bit level of the target expression corresponding to the third coefficient is greater than or equal to the highest bit level of the prime number substitution expression; if g4 is 0, it is considered that the highest bit level of the target expression corresponding to the third coefficient is less than the highest bit level of the prime number substitution expression.

[0167] Specifically, if the highest digit level of the target expression corresponding to the third coefficient is greater than or equal to the highest digit level of the prime number substituted into the expression, refer to... Figure 3 , Figure 3 This is an optional flowchart illustrating step S124 provided in an embodiment of the present invention. Step S124 may include:

[0168] Step S241: Based on the third coefficient, calculate the fourth coefficient of the reduction expression of the remainder operation; the reduction expression is obtained by reducing the prime number substitution expression after the third substitution in the remainder operation process;

[0169] After determining the third coefficient, a reduction calculation can be performed. The reduction expression is obtained by reducing the prime number after the third substitution in the expression during the modulo operation. It is understood that, since the target expression conforms to the bit width of the computing device, the calculation process for the fourth coefficient of the reduction expression also conforms to the bit width calculation method of the computing device.

[0170] By reducing the target expression, a rough result of the remainder operation is obtained. The reduced expression can be understood as a rough representation of the remainder operation, which is a value close to a prime number.

[0171] Specifically, in the reduction expression represented by the fourth coefficient, the fourth coefficient refers to the set of coefficients in the reduction expression. The fourth coefficient may include multiple fourth sub-coefficients, each corresponding to a different bit level and having a corresponding coefficient value. For example, the highest-level fourth sub-coefficient corresponds to the first N bits of the reduction expression, the next-highest-level fourth sub-coefficient corresponds to the N+1 to 2N bits of the reduction expression, and so on, until the lowest-level fourth sub-coefficient corresponds to the last N bits of the reduction expression. Here, N is a preset number of bits. In this embodiment of the invention, N is also the bit width of the computing device.

[0172] Based on the example of a 64-bit computing device, a preset bit depth of 64 bits, and a 512-bit data to be calculated, the following reduction expression is obtained after obtaining the target expression from this example:

[0173] Z mod p = h3·2 192 +h2·2 128 +h1·2 64 +h0

[0174] Among them, h i The fourth sub-coefficient, where i is an integer, is the conversion from the third coefficient to the fourth coefficient as follows:

[0175] h0=k0&0xFFFFFFFFFFFFFFFF, where k0=g0+g4

[0176] h1 = k1 & 0xFFFFFFFFFFFFFFFF, where...

[0177] k1=k0>>64+g1-g4+(g4&0xFFFFFFFF)<<32

[0178] k2=k2&0xFFFFFFFFFFFFFFFF, where k2=k1>>64+g2+g4>>32

[0179] h3=k3&0xFFFFFFFFFFFFFFFF, where,

[0180] k3=k2>>64+f3+(g4&0xFFFFFFFF)<<32;

[0181] In 64-bit computing devices, the above h i The calculation includes seven 64-bit additions and one 64-bit subtraction, and six shifts. The shift operations can be performed in parallel during the execution of the 64-bit add instruction with carry (adc), without requiring additional clock cycles. Therefore, the above calculation only requires eight clock cycles.

[0182] It is understood that, based on the above coefficient conversion, the value of the fourth coefficient and its corresponding reduction expression described in the embodiments of the present invention can be obtained, and the calculation of subsequent steps can be further performed based on the value of the reduction expression.

[0183] Step S242: Determine the result of the remainder operation based on the value of the fourth coefficient and the reduction expression.

[0184] Specifically, based on the reduction expression and the fourth coefficient, the value of the reduction expression can be determined, and then it can be determined whether the value of the reduction expression is the result of the remainder operation. If the value of the reduction expression is not the result of the remainder operation, the result of the remainder operation can be calculated based on a further algorithm.

[0185] In specific examples, refer to Figure 4 , Figure 4 This is an optional flowchart illustrating step S242 provided in an embodiment of the present invention. Step S242 may further include:

[0186] Step S242a: Determine whether the value of the reduction expression corresponding to the fourth coefficient is less than the prime number;

[0187] By comparing the value of the reduction expression corresponding to the fourth coefficient with the value of the prime number, it can be determined whether the value of the reduction expression corresponding to the fourth coefficient should be used as the result of the modulo operation. In a specific example, the value of the reduction expression corresponding to the fourth coefficient can be compared with the prime number expression, for example, comparing the corresponding parameters at the same bit level one by one from high to low, thereby determining whether the value of the reduction expression corresponding to the fourth coefficient is less than the prime number.

[0188] If yes, proceed to step S242b; if no, proceed to step S242c.

[0189] S242b: The value of the reduction expression corresponding to the fourth coefficient is used as the result of the remainder operation;

[0190] It is understandable that if the value of the reduction expression corresponding to the fourth coefficient is less than the prime number, then the value of the reduction expression corresponding to the fourth coefficient is the result of the modulo operation.

[0191] S242c: Perform the subtraction operation between the value of the reduction expression corresponding to the fourth coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0192] It is understood that the value of the reduction expression is a rough result obtained by substituting prime numbers into the expression three times. This rough result is close to the value of a prime number. Therefore, when the value of the reduction expression corresponding to the fourth coefficient is greater than a prime number, the result of the remainder operation can be obtained through further subtraction.

[0193] Specifically, when calculating the difference between the value of the reduction expression and the prime number, the reduction expression can be converted into a first conversion expression adapted to the bit width of the computing device before calculating the difference with the prime number expression; alternatively, the prime number expression can be converted into a second conversion expression adapted to the level of the reduction expression before performing the subtraction operation between the value of the reduction expression and the prime number.

[0194] Taking the conversion of the prime number expression into a second transformation expression that adapts to the level of the reduction expression as an example, the prime number expression can be:

[0195] p = 2 256 -2 224 -2 96 +2 64 -1;

[0196] Convert to the second transformation expression:

[0197] p = p3·2 192 +p2·2 128 +p1·2 64 +p0

[0198] Here, p i Here, p3 represents the coefficient of the second transformation, where i is an integer. Specifically, p3 = 2. 64 -2 32 p2 = 0, p1 = 1 - 2 32 p0 = -1;

[0199] Accordingly, based on the preset expression in the example where the computing device is a 64-bit computing device, the preset bit length is 64 bits, and the data to be calculated is 512 bits, the difference obtained after the reduction expression based on this example is:

[0200] Z1-p=(h3-p3)·2 192 +(h2-p2)·2 128 +(h1-p1)·2 64 +(h0-p0).

[0201] Where Z1 is Z mod p in the reduction expression.

[0202] In a 64-bit computing device, the above calculation is a 256-bit subtraction, which is equivalent to four 64-bit subtractions, and therefore only requires four clock cycles.

[0203] After obtaining the difference, the difference is used as the result of the remainder operation.

[0204] It can be seen that the reduction process of the target expression is also adapted to the calculation method of the bit width of the computing device, thereby improving the calculation efficiency of the modulo operation, and thus improving the efficiency of the corresponding cryptographic operation.

[0205] It should be further explained that the above 64-bit modulo operation requires a maximum of 19+9+9+8+4=49 clock cycles, which is much more efficient than the existing scheme where a single modulo operation takes more than sixty or seventy clock cycles, or even hundreds of clock cycles.

[0206] In a further example, if the highest digit level of the target expression corresponding to the third coefficient is less than the highest digit level of the prime number substitution expression, then the value of the target expression corresponding to the third coefficient is considered to be close to the prime number. Thus, the value can be considered to be a rough result of the modulo operation. Accordingly, the value of the target expression corresponding to the third coefficient can be directly judged without further reduction of the target expression corresponding to the third coefficient.

[0207] Since the value of the target expression corresponding to the third coefficient is close to the prime number, it is considered a rough result of the modulo operation. Therefore, this value can be compared with the magnitude of the prime number to determine whether it is the final result of the modulo operation. In a specific example, refer to... Figure 5 , Figure 5 This is another optional flowchart illustrating step S124 provided in an embodiment of the present invention. Step S124 may further include:

[0208] Step S243: Determine whether the value of the target expression corresponding to the third coefficient is less than the prime number;

[0209] By comparing the value of the target expression corresponding to the third coefficient with the value of the prime number, it can be determined whether the value of the target expression corresponding to the third coefficient should be used as the result of the modulo operation. In a specific example, the value of the target expression corresponding to the third coefficient can be compared with the prime number expression, for example, comparing the corresponding parameters at the same bit level one by one from high to low, thereby determining whether the value of the target expression corresponding to the third coefficient is less than the prime number.

[0210] If yes, proceed to step S244; if no, proceed to step S245.

[0211] Step S244: Use the value of the target expression corresponding to the third coefficient as the result of the modulo operation;

[0212] It is understandable that if the value of the objective expression corresponding to the third coefficient is less than the prime number, then the value of the objective expression corresponding to the third coefficient is the result of the modulo operation.

[0213] S245: Perform a subtraction operation between the value of the target expression corresponding to the third coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0214] It is understood that the value of the target expression is a rough result obtained by substituting a prime number into the expression and reducing it. This rough result is close to the value of a prime number. Therefore, when the value of the target expression corresponding to the third coefficient is greater than a prime number, the result of the remainder operation can be obtained by further subtraction.

[0215] Specifically, the target expression can be converted into a third transformation expression with a level of digits suitable for the prime number expression before the difference is calculated with the prime number expression. Alternatively, the prime number expression can be converted into a fourth transformation expression with a level of digits suitable for the target expression before the subtraction operation between the target expression and the prime number is performed. Taking the conversion of the prime number expression into a fourth transformation expression with a level of digits suitable for the target expression as an example, the prime number expression can be:

[0216] p = 2 256 -2 224 -2 96 +2 64 -1,

[0217] Convert to the fourth transformation expression:

[0218] p = p3·2 192 +p2·2 128 +p1·2 64 +p0

[0219] Here, p iHere are the coefficients of the fourth transformation, where i is an integer. Specifically, p3 = 2. 64 -2 32 p2 = 0, p1 = 1 - 2 32 p0 = -1;

[0220] Accordingly, based on the preset expression in the example where the computing device is a 64-bit computing device, the preset bit length is 64 bits, and the data to be calculated is 512 bits, the difference obtained after obtaining the target expression based on this example is:

[0221] The difference is:

[0222] Z2-p=(g3-p3)·2 192 +(g2-p2)·2 128 +(g1-p1)·2 64 +(g0-p0)

[0223] Where Z2 is Z mod p in the objective expression, and based on the foregoing explanation, the highest bit level g4 in the objective expression is 0.

[0224] After obtaining the difference, the difference is used as the result of the remainder operation.

[0225] It can be seen that the calculation process of the modulo operation result based on the target expression is also adapted to the bit width of the computing device, thereby improving the calculation efficiency of the modulo operation, and thus improving the efficiency of the corresponding cryptographic operation.

[0226] The remainder calculation device provided in the embodiments of the present invention will be described below. The remainder calculation device described below can be considered as a functional module required to implement the remainder calculation method provided in the embodiments of the present invention. The content of the remainder calculation device described below can be referred to in correspondence with the content of the method described above.

[0227] In the optional implementation, Figure 6 An optional block diagram of the modulo calculation device provided in an embodiment of the present invention is shown, such as... Figure 6 As shown, the remainder calculation device may include:

[0228] The data acquisition module 400 is used to acquire data to be calculated, wherein the data to be calculated is an integer with more than or equal to 128 digits;

[0229] Data conversion module 410 is used to convert the data to be calculated into a preset expression form, wherein the preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of bits, and the preset number of bits is the bit width of the computing device;

[0230] The data calculation module 420 is used to perform a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form, so as to obtain the remainder between the data to be calculated and the prime number.

[0231] Optionally, the data calculation module 420 is used to perform a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form, to obtain the remainder between the data to be calculated and a prime number, including:

[0232] Based on the conversion of the preset coefficients, the first coefficient of the initial expression of the remainder operation is calculated; the initial expression is obtained based on the initial substitution of prime numbers into the expression during the remainder operation.

[0233] Based on the first coefficient, a second coefficient that conforms to the bit width expression of the computing device is calculated;

[0234] Based on the second coefficient, the third coefficient of the target expression of the remainder operation is calculated; the target expression is obtained by substituting prime numbers into the expression again during the remainder operation.

[0235] The result of the modulo operation is determined based on the target expression and the third coefficient.

[0236] Optionally, if the highest digit level of the target expression corresponding to the third coefficient is greater than or equal to the highest digit level of the prime number substitution expression, the data calculation module 420 is used to determine the result of the modulo operation based on the target expression and the third coefficient, including:

[0237] Based on the third coefficient, the fourth coefficient of the reduction expression of the remainder operation is calculated; the reduction expression is obtained by reducing the prime number after the third substitution in the prime number substitution expression during the remainder operation.

[0238] The result of the remainder operation is determined based on the value of the reduction expression corresponding to the fourth coefficient.

[0239] Optionally, the data calculation module 420 is used to determine the result of the modulo operation based on the value of the reduction expression corresponding to the fourth coefficient, including:

[0240] Determine whether the value of the reduction expression corresponding to the fourth coefficient is less than the prime number;

[0241] If so, the value of the reduction expression corresponding to the fourth coefficient is taken as the result of the remainder operation;

[0242] If not, perform the subtraction operation between the value of the reduction expression corresponding to the fourth coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0243] Optionally, if the highest digit level of the target expression corresponding to the third coefficient is less than the highest digit level of the prime number substitution expression, the data calculation module 420 is used to determine the result of the modulo operation based on the target expression and the third coefficient, including:

[0244] Determine whether the value of the target expression corresponding to the third coefficient is less than the prime number;

[0245] If so, the value of the target expression corresponding to the third coefficient is taken as the result of the modulo operation;

[0246] If not, perform the subtraction operation between the value of the target expression corresponding to the third coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

[0247] Optionally, the bit width of the computing device is 64, the preset bit width is 64, the data to be calculated is 512 bits, and the preset expression form is:

[0248] Z = z7·2 448 +z6·2 384 +z5·2 320 +z4·2 256 +z3·2 192 +z2·2 128 +z1·2 64 +z0

[0249] Among them, z i is a preset coefficient, and i is an integer.

[0250] Optionally, in the step of obtaining the first coefficient of the initial expression of the modulo operation based on the conversion of the preset coefficients, the initial expression of the data calculation module 420 is:

[0251] Z mod p = d7·2 224 +d6·2 192 +d5·2 160 +d4·2 128 +d3·2 96 +d2·2 64 +d1·2 32 +d0

[0252] Where, d i The set of is the first coefficient, where i is an integer. The conversion from the preset coefficient to the first coefficient is specifically as follows:

[0253] d7=z4+z5+2·z6+2·z7, d6=z7, d5=z5+z7, d4=z6+2·zz7, d3=z4+z6+z7, d2=-(z4+z7), d1=z5+z6+2·z7, d0=z4+z5+z6+2·z7

[0254] The prime number substitution expression is:

[0255] 2 256 =2 224 +2 96 -2 64 +1mod p.

[0256] Optionally, in the step of converting the first coefficient in the initial expression to a second coefficient that conforms to the bit width expression of the computing device, the data calculation module 420 sets the expression corresponding to the second coefficient as an intermediate expression, wherein the intermediate expression is:

[0257] Z mod p = f4·2 256 +f3·2 192 +f2·2 128 +f1·2 64 +f0

[0258] Among them, f i The set of is the second coefficient, where i is an integer. The conversion from the first coefficient to the second coefficient is as follows:

[0259] f0 = e0 + e1 << 32,

[0260] f1=e1>>32+e2+e3<<32,

[0261] f2=e3>>32+e4+e5<<32,

[0262] f3=e5>>32+e6+e7<<32,

[0263] f4 = e7 >> 32 + e8 << 32;

[0264] in:

[0265] e0 = d0 & 0xFFFFFFFFFFFFFFFF,

[0266] e i =d i &0xFFFFFFFFFFFFFFFF+d i-1 >>64, i = 1, 2, ..., 7;

[0267] e8 = d7 >> 64.

[0268] Optionally, in the step of obtaining the third coefficient of the target expression of the modulo operation based on the transformation of the second coefficient, the target expression of the data calculation module 420 is:

[0269] Z mod p = g4·2 256 +g3·2 192 +g2·2 128 +g1·2 64 +g0

[0270] Among them, g i The set of coefficients is the third coefficient, where i is an integer. The conversion from the second coefficient to the third coefficient is as follows:

[0271] g0=t0&0xFFFFFFFFFFFFFFFF, where t0=f0+f4;

[0272] g1 = t1 & 0xFFFFFFFFFFFFFFFF,

[0273] Where, t1 = t0 >> 64 + f1 - f4 + (f4 & 0xFFFFFFFF) << 32;

[0274] g2=t2&0xFFFFFFFFFFFFFFFF, where t2=t1>>64+f2+f4>>32;

[0275] g3 = t3 & 0xFFFFFFFFFFFFFFFF,

[0276] Where, t3 = t2 >> 64 + f3 + (f4 & 0xFFFFFFFF) << 32;

[0277] g4 = t3 >> 64 + f4 >> 32.

[0278] Optionally, in the step of the data calculation module 420 calculating the fourth coefficient of the reduction expression of the modulo operation based on the third coefficient, the reduction expression is:

[0279] Z mod p = h3·2 192 +h2·2 128 +h1·2 64 +h0

[0280] Among them, h i The set of coefficients is the fourth coefficient, where i is an integer. The conversion from the third coefficient to the fourth coefficient is as follows:

[0281] h0=k0&0xFFFFFFFFFFFFFFFF, where k0=g0+g4

[0282] h1 = k1 & 0xFFFFFFFFFFFFFFFF,

[0283] Where, k1 = k0 >> 64 + g1 - g4 + (g4 & 0xFFFFFFFF) << 32

[0284] h2=k2&0xFFFFFFFFFFFFFFFF, where k2=k1>>64+g2+g4>>32

[0285] h3 = k3 & 0xFFFFFFFFFFFFFFFF,

[0286] Among them, k3=k2>>64+g3+(g4&0xFFFFFFFF)<<32.

[0287] The modulo operation method described in this embodiment of the invention can perform a modulo operation adapted to a preset number of bits (i.e., the bit width of the computing device) based on a preset expression form of the data to be calculated, thereby maximizing the computational efficiency of the modulo operation and thus improving the efficiency of the corresponding cryptographic operation.

[0288] In this embodiment of the invention, a cryptographic processing method is further provided, wherein the cryptographic processing method uses the remainder calculation method described in this embodiment of the invention to calculate the remainder between the data to be calculated and a prime number.

[0289] Furthermore, this embodiment of the invention also provides a cryptographic coprocessor, which includes a processing module and a storage module. The storage module stores a program, and the processing module is used to call the program in the storage module to execute the modulo calculation method described in this embodiment of the invention.

[0290] Furthermore, this embodiment of the invention also provides a chip, which includes the cryptographic coprocessor described in this embodiment of the invention.

[0291] This invention also provides a computer device including the chip described above.

[0292] The chip and computer device provided in this embodiment of the invention can perform a modulo operation adapted to a preset number of bits (i.e., the bit width of the computing device) based on a preset expression form of the data to be calculated, thereby maximizing the computational efficiency of the modulo operation and thus improving the efficiency of the corresponding cryptographic operation.

[0293] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0294] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0295] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A modulo operation method for cryptographic processing, characterized in that, Applications of computing devices to calculate the remainder of a data point with respect to a prime number include: Obtain the data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128; The data to be calculated is converted into a preset expression form, and the preset coefficients in the preset expression form are obtained by dividing the data to be calculated by a preset number of bits, wherein the preset number of bits is the bit width of the computing device. Based on the preset coefficients in the preset expression form, perform a modulo operation adapted to the preset number of digits to obtain the remainder between the data to be calculated and the prime number; Wherein, the step of performing a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form to obtain the remainder between the data to be calculated and the prime number includes: Based on the conversion of the preset coefficients, the first coefficient of the initial expression of the remainder operation is calculated; the initial expression is obtained based on the initial substitution of prime numbers into the expression during the remainder operation. Based on the first coefficient, a second coefficient that conforms to the bit width expression of the computing device is calculated; Based on the second coefficient, the third coefficient of the target expression of the remainder operation is calculated; the target expression is obtained by substituting prime numbers into the expression again during the remainder operation. The result of the modulo operation is determined based on the target expression and the third coefficient.

2. The remainder calculation method as described in claim 1, characterized in that, If the highest digit level of the target expression corresponding to the third coefficient is greater than or equal to the highest digit level of the prime number substitution expression, determining the result of the modulo operation based on the target expression and the third coefficient includes: Based on the third coefficient, the fourth coefficient of the reduction expression of the remainder operation is calculated; the reduction expression is obtained by reducing the prime number after the third substitution in the prime number substitution expression during the remainder operation. The result of the remainder operation is determined based on the value of the reduction expression corresponding to the fourth coefficient.

3. The remainder calculation method as described in claim 2, characterized in that, Determining the result of the modulo operation based on the value of the reduction expression corresponding to the fourth coefficient includes: Determine whether the value of the reduction expression corresponding to the fourth coefficient is less than the prime number; If so, the value of the reduction expression corresponding to the fourth coefficient is taken as the result of the remainder operation; If not, perform the subtraction operation between the value of the reduction expression corresponding to the fourth coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

4. The remainder calculation method as described in claim 1, characterized in that, If the highest digit level of the target expression corresponding to the third coefficient is less than the highest digit level of the prime number substitution expression, determining the result of the modulo operation based on the target expression and the third coefficient includes: Determine whether the value of the target expression corresponding to the third coefficient is less than the prime number; If so, the value of the target expression corresponding to the third coefficient is taken as the result of the modulo operation; If not, perform the subtraction operation between the value of the target expression corresponding to the third coefficient and the prime number, and use the resulting difference as the result of the remainder operation.

5. The remainder calculation method as described in claim 2, characterized in that, The computing device has a bit width of 64, the preset bit width is 64, the data to be calculated is 512 bits, and the preset expression form is: ； Among them, z i is a preset coefficient, and i is an integer.

6. The remainder calculation method as described in claim 5, characterized in that, In the step of obtaining the first coefficient of the initial expression for the modulo operation based on the conversion of the preset coefficients, the initial expression is: ； Where, d i The set of is the first coefficient, where i is an integer. The conversion from the preset coefficient to the first coefficient is specifically as follows: ， , , , , , , ； The prime number substitution expression is: 。 7. The remainder calculation method as described in claim 6, characterized in that, In the step of converting the first coefficient in the initial expression to a second coefficient that conforms to the bit width expression of the computing device, the expression corresponding to the second coefficient is designated as an intermediate expression, which is: ； Among them, f i The set of is the second coefficient, where i is an integer. The conversion from the first coefficient to the second coefficient is as follows: , , , , ； in: ， ， 。 8. The remainder calculation method as described in claim 7, characterized in that, In the step of obtaining the third coefficient of the target expression for the modulo operation based on the transformation of the second coefficient, the target expression is: ； Among them, g i The set of coefficients is the third coefficient, where i is an integer. The conversion from the second coefficient to the third coefficient is as follows: ,in, ; ， in, ; ,in, ; in, ; 。 9. The remainder calculation method as described in claim 8, characterized in that, In the step of calculating the fourth coefficient of the reduction expression based on the third coefficient, the reduction expression is: ； Among them, h i The set of coefficients is the fourth coefficient, where i is an integer. The conversion from the third coefficient to the fourth coefficient is as follows: ,in, ; , in, ; , in, ; ， in, .

10. A modulo calculation device for cryptographic processing, characterized in that, Applications of computing devices to calculate the remainder of a data point with respect to a prime number include: The data acquisition module is used to acquire data to be calculated, wherein the data to be calculated is an integer with a number of digits greater than or equal to 128. The data conversion module is used to convert the data to be calculated into a preset expression form, wherein the preset coefficients in the preset expression form are obtained by dividing the data to be calculated into preset number of bits, and the preset number of bits is the bit width of the computing device; The data calculation module is used to perform a modulo operation adapted to the preset number of digits based on the preset coefficients in the preset expression form, to obtain the remainder between the data to be calculated and a prime number, including: Based on the conversion of the preset coefficients, the first coefficient of the initial expression of the remainder operation is calculated; the initial expression is obtained based on the initial substitution of prime numbers into the expression during the remainder operation. Based on the first coefficient, a second coefficient that conforms to the bit width expression of the computing device is calculated; Based on the second coefficient, the third coefficient of the target expression of the remainder operation is calculated; the target expression is obtained by substituting prime numbers into the expression again during the remainder operation. The result of the modulo operation is determined based on the target expression and the third coefficient.

11. A cryptographic processing method, characterized in that, The remainder between the data to be calculated and a prime number is calculated using the remainder calculation method described in any one of claims 1 to 9.

12. A cryptographic coprocessor, characterized in that, It includes a processing module and a storage module, wherein the storage module stores a program, and the processing module is used to call the program in the storage module to execute the remainder calculation method according to any one of claims 1 to 9.

13. A chip, characterized in that, Includes the cryptographic coprocessor as described in claim 12.

14. A computer device, characterized in that, Includes the chip as described in claim 13.

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