Chip screening method and related device

Abstract

The embodiment of the present application discloses a chip screening method and related devices. The method embodiment obtains each wafer after chip sorting by sorting the chips on each wafer according to the chip distance, and the chip distance is determined based on the difference in device parameters between the two chips on the wafer; then the initial chip on each wafer after chip sorting is determined, and the order of chips on multiple wafers is rearranged according to the initial chip, so that in any two adjacent chips, the device parameters of the last chip of the upper wafer are similar to the device parameters of the initial chip of the next wafer. By adopting the embodiment of the present application, the parameter difference between adjacent chips can be reduced, thereby reducing the imbalance of current. When multiple chips are packaged in parallel, there is no need to screen or group them, and only needs to perform patch packaging in sequence to fully constrain the discreteness and randomness of the device parameters of the parallel chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a chip screening method and related devices. Background Art

[0002] With the rapid development of the power electronics industry, demand for high-current-capacity power conversion systems has surged. To meet this demand, power modules require more chips connected in parallel. However, due to the discrete and random nature of chip device parameters, connecting multiple chips in parallel often leads to uneven current distribution, potentially causing thermal imbalance within the module and even irreversible damage. Therefore, it is crucial to research chip screening strategies that minimize chip parameter variations and, therefore, reduce current imbalance. Summary of the Invention

[0003] The embodiments of the present application provide a chip screening method and related devices, which can reduce parameter differences between adjacent chips and thereby reduce current imbalance.

[0004] In a first aspect, an embodiment of the present application provides a chip screening method, the method comprising:

[0005] Obtaining a plurality of wafers, each wafer including at least one chip to be sorted;

[0006] sorting the chips on each wafer according to chip distance to obtain each wafer after chip sorting, wherein the chip distance is determined based on the difference in device parameters between two chips on the wafer;

[0007] The initial chip on each wafer after chip sorting is determined, and the order of the chips on the multiple wafers is rearranged according to the initial chip so that the device parameters of the last chip of the upper wafer and the initial chip of the next wafer in any two adjacent chips are similar.

[0008] Optionally, the chip distance is determined based on the following formula:

[0009] , ,

[0010] in, represents the chip distance between the adjacent i-th chip and i+1-th chip, and represent the jth device parameters of the i-th chip and the i+1-th chip, respectively. represents the weight of the jth device parameter in the chip distance, and k represents the number of device parameters.

[0011] Optionally, sorting the chips on each wafer according to chip distance to obtain each wafer after chip sorting includes:

[0012] Determine N sorting methods;

[0013] Sure The sum of chip distances in each sorting method;

[0014] Determine the sorting method corresponding to the minimum value of the sum of the chip distances as the target sorting method;

[0015] The chips on each wafer are sorted according to the target sorting method to obtain each wafer after chip sorting.

[0016] Optionally, the number of chips on the wafer is m, and N is equal to .

[0017] Optionally, the number of chips on the wafer is m, and N is less than , the N sorting methods are determined by repeated iterations of a genetic algorithm.

[0018] Optionally, the termination condition of the genetic algorithm includes at least one of the following: reaching a maximum number of iterations, a device parameter between adjacent chips being less than a preset threshold, and fitness value convergence.

[0019] Optionally, determining an initial chip on each wafer after chip sorting, and rearranging the order of chips on the plurality of wafers according to the initial chip includes:

[0020] Determining the average value of the device parameters of the chips on the first wafer as the center value of the first wafer, and determining the center value of the wafer other than the first wafer as the device parameter of the last chip after the chips on the previous wafer are rearranged;

[0021] The chips on each wafer are sequentially shifted cyclically according to the center value so that the difference between the device parameters of the initial chips on the wafer and the center value is minimized, thereby obtaining a wafer with rearranged chip sequence.

[0022] A second aspect of an embodiment of the present application provides a chip screening device, comprising:

[0023] A parameter acquisition unit, configured to acquire a plurality of wafers, each wafer including at least one chip to be sorted;

[0024] a chip sorting unit, configured to sort the chips on each wafer according to chip distance, to obtain each wafer after chip sorting, wherein the chip distance is determined based on the difference in device parameters between two chips on the wafer;

[0025] The chip rearrangement unit is used to determine the initial chip on each wafer after the chips are sorted, and to rearrange the order of the chips on the multiple wafers according to the initial chip, so that among any two adjacent chips, the device parameters of the last chip of the upper wafer and the initial chip of the next wafer are similar.

[0026] A third aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory;

[0027] The processor is connected to the memory, wherein the memory is used to store the computer program, and the processor is used to call the computer program to execute the method in the first aspect of the embodiment of the present application.

[0028] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the method in the first aspect of the embodiment of the present application is executed.

[0029] This application obtains each wafer after chip sorting by sorting the chips on each wafer according to the chip distance, and the chip distance is determined based on the difference in device parameters between the two chips on the wafer; then the initial chip on each wafer after chip sorting is determined, and the order of chips on multiple wafers is rearranged according to the initial chip, so that in any two adjacent chips, the device parameters of the last chip of the upper wafer are similar to the device parameters of the initial chip of the next wafer. It can be seen that the application embodiment can reduce the parameter differences between adjacent chips, thereby reducing the imbalance of current. When multiple chips are packaged in parallel, there is no need to screen or group them, and only needs to perform patch packaging in sequence to fully constrain the discreteness and randomness of the device parameters of the parallel chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a chip screening application operating environment provided by one embodiment of the present application is shown;

[0032] Figure 2 A schematic diagram of a chip screening method according to an embodiment of the present application is shown;

[0033] Figure 3A schematic diagram of a chip screening method according to another embodiment of the present application is shown;

[0034] Figure 4 A schematic structural diagram of a chip screening device provided in one embodiment of the present application is shown;

[0035] Figure 5 A schematic structural diagram of a computer device provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] Please refer to Figure 1 , which shows a schematic diagram of a chip screening application running environment provided by an embodiment of the present application. The application running environment may include: a terminal 10 and a server 20.

[0038] The terminal 10 includes, but is not limited to, electronic devices such as mobile phones, computers, intelligent voice interaction devices, smart home appliances, car terminals, game consoles, e-book readers, multimedia playback devices, wearable devices, etc. The terminal 10 may be installed with a client of an application.

[0039] In the embodiment of the present application, the above-mentioned application can be any application that can provide chip screening services. Typically, the application is an industrial application. Of course, in addition to industrial applications, other types of applications can also provide services that rely on chip screening. For example, scientific research applications, browser applications, virtual reality (VR) applications, augmented reality (AR) applications, etc., which are not limited in the embodiment of the present application. The embodiment of the present application is not limited in this regard. Optionally, the terminal 10 runs a client of the above-mentioned application.

[0040] Server 20 is used to provide backend services for the client applications in terminal 10. For example, server 20 can be the backend server for the aforementioned applications. Server 20 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, server 20 provides backend services for applications in multiple terminals 10 simultaneously.

[0041] Optionally, the terminal 10 and the server 20 may communicate with each other via a network 30. The terminal 10 and the server 20 may be directly or indirectly connected via wired or wireless communication, which is not limited in this application.

[0042] Please refer to Figure 2 , which shows a flow chart of a chip screening method provided by an embodiment of the present application. The method can be applied to a computer device, which refers to an electronic device with data calculation and processing capabilities. For example, the execution subject of each step can be Figure 1 The terminal 10 or server 20 in the application running environment shown. The method may include the following steps:

[0043] Step 201: Acquire multiple wafers, each wafer including at least one chip to be sorted.

[0044] A wafer is a thin film used to manufacture silicon semiconductor circuits, made of semiconductor materials such as silicon and silicon carbide. Through processing, oxidation, photolithography, etching, thin-film deposition, interconnection, testing, and packaging, multiple chips are formed from the wafer. Due to the precision of the equipment used in each process step or uncontrollable environmental factors, the parameters of the produced chip devices may be discrete and random. Therefore, they need to be sorted.

[0045] Step 202: sorting the chips on each wafer according to chip distance to obtain each wafer after chip sorting, wherein the chip distance is determined based on the difference in device parameters between two chips on the wafer.

[0046] The device parameters of the chip may include, for example, operating voltage, load current, dissipated power, conductivity, operating temperature, resistivity, pulse peak value, and the like.

[0047] The chip distance can be determined based on the difference in device parameters between two chips on the wafer. For example, the difference in each device parameter can be summed and then squared as the chip distance. The chip distance can be determined based on the difference between the device parameter of each chip and the average value of the device parameter. For example, the average value of a certain device parameter is first calculated, and then the square of the difference between the device parameter of each chip and the average value is determined. The degree of dispersion is determined based on the square value, and the degree of dispersion is used as the chip distance.

[0048] Step 203: Determine the initial chip on each wafer after chip sorting, and rearrange the order of chips on the multiple wafers according to the initial chip, so that among any two adjacent chips, the device parameters of the last chip of the previous wafer and the initial chip of the next wafer are similar.

[0049] To determine the initial chip on each wafer after chip sorting, for example, the sequence number of the last chip in the current order can be used as the previous chip of the first chip, forming a circular sequence. A chip is then selected from this circular sequence as the initial chip, and the circular chip is disconnected at this point to form a new linear sequence, with the initial chip as the first chip in the new linear sequence, and the last chip in the new linear sequence as the last chip. For example, if the linear sequence is 1-2-3-4-5-6-7-8, and sequence number 1 is used as the sequence number of the chip following sequence number 8, the linear sequence becomes a circular sequence. For example, if the initial chip is number 4, the circular sequence is disconnected at 4, forming a new linear sequence of 4-5-6-7-8-1-2-3, with chip 3 being the last chip.

[0050] The initial chip may have the smallest chip distance or the largest chip distance; it may have the smallest device parameters or the largest device parameters, and there is no limitation here.

[0051] It can be seen that in the application embodiment, the chips on each wafer are sorted according to the chip distance to obtain each wafer after chip sorting, and the chip distance is determined based on the difference in device parameters between the two chips on the wafer; then the initial chip on each wafer after chip sorting is determined, and the order of chips on multiple wafers is rearranged according to the initial chip, so that in any two adjacent chips, the device parameters of the last chip of the upper wafer are similar to the initial chip of the next wafer. The application embodiment can reduce the parameter differences between adjacent chips, thereby reducing the imbalance of current. When multiple chips are packaged in parallel, there is no need to screen or group them, and only sequential patch packaging is required to fully constrain the discreteness and randomness of the device parameters of the parallel chips.

[0052] In one embodiment of the present application, the chip distance is determined based on the following formula:

[0053] , ,

[0054] in, represents the chip distance between the adjacent i-th chip and i+1-th chip, and represent the jth device parameters of the i-th chip and the i+1-th chip, respectively. represents the weight of the jth device parameter in the chip distance, and k represents the number of device parameters.

[0055] The proportion of device parameters in chip distance can be determined by their importance in the chip's application scenario. For example, if operating voltage is of particular concern, the weight coefficient for operating voltage can be set higher, while other device parameters can be set lower.

[0056] It can be seen that in the embodiment of the present application, the chip distance is defined by the device parameters, and then the chips are sorted by the chip distance. The device parameters are combined with the chip sorting, and the relationship between the device parameters and the chip sorting is fully considered, which can reduce the device parameter differences between adjacent chips.

[0057] In one embodiment of the present application, sorting the chips on each wafer according to chip distance to obtain each wafer after chip sorting includes:

[0058] Determine N sorting methods;

[0059] Sure The sum of chip distances in each sorting method;

[0060] Determine the sorting method corresponding to the minimum value of the sum of the chip distances as the target sorting method;

[0061] The chips on each wafer are sorted according to the target sorting method to obtain each wafer after chip sorting.

[0062] Among them, the number of chips on the wafer is m.

[0063] In one embodiment, N is equal to That is, all sorting methods are enumerated, and then the optimal sorting method is selected from all sorting methods, that is, the sorting method corresponding to the minimum sum of chip distances.

[0064] This method can accurately find the optimal sorting method for wafers with a small number of chips, helping to reduce the device parameter differences between adjacent chips. However, for wafers with a large number of chips, exhaustively enumerating all sorting methods and calculating the sum of chip distances takes too long and is inefficient.

[0065] Therefore, this application also provides another method. When the number of chips is large, the N is less than , the N sorting methods are determined by repeated iterations of a genetic algorithm.

[0066] Specifically, N sorting methods are determined by repeated iterations of the genetic algorithm, including:

[0067] M sorting methods are randomly generated according to the number of chips on each wafer. Each sorting method is used as a parent individual. The genes in the parent individual are the positions of the chips. The M is less than ;

[0068] Performing a crossover operation on the genes in the parent individuals to generate offspring individuals;

[0069] performing a mutation operation on the genes in the offspring individuals to produce mutated individuals;

[0070] Using the chip distance as fitness, and determining the parent individuals of the next generation population from the offspring individuals and the mutated offspring individuals according to the fitness, and performing the step of performing a crossover operation on the genes in the parent individuals to generate offspring individuals;

[0071] When the termination condition is met, N sorting methods are determined based on the parent individuals of the current population.

[0072] The step of determining the parent individuals of the next generation population from the offspring individuals and the mutated offspring individuals according to the fitness includes: taking a preset number of offspring individuals with small fitness and the mutated offspring individuals as the parent individuals of the next generation population.

[0073] The termination condition of the genetic algorithm includes at least one of the following: reaching a maximum number of iterations, device parameters between adjacent chips being less than a preset threshold, and fitness values ​​converging.

[0074] In one embodiment of the present application, determining the initial chips on each wafer after chip sorting, and rearranging the order of chips on the plurality of wafers according to the initial chips, includes:

[0075] Determining the average value of the device parameters of the chips on the first wafer as the center value of the first wafer, and determining the center value of the wafer other than the first wafer as the device parameter of the last chip after the chips on the previous wafer are rearranged;

[0076] The chips on each wafer are sequentially shifted cyclically according to the center value so that the difference between the device parameters of the initial chips on the wafer and the center value is minimized, thereby obtaining a wafer with rearranged chip sequence.

[0077] Furthermore, the method further includes: determining the order of wafers from the plurality of wafers, and determining the first wafer based on the order of the wafers. For example, the ordering may be based on the average value of at least one device parameter, specifically, in ascending order or descending order. Alternatively, the ordering may be based on the aforementioned chip distance, for example, by calculating the chip distance between each pair of chips in each wafer, then summing all chip distances as the total chip distance for the wafer, and then sorting the wafers based on the total chip distance or the average value of the total chip distance.

[0078] Please refer to Figure 3 , which shows a flow chart of a chip screening method provided by another embodiment of the present application. This method can be applied to a computer device, which refers to an electronic device with data calculation and processing capabilities. For example, the execution subject of each step can be Figure 1 The terminal 10 or server 20 in the application running environment shown. The method may include the following steps:

[0079] Step 301: Acquire multiple wafers, each wafer including at least one chip to be sorted.

[0080] Step 302: Obtain device parameters of the chips to be sorted.

[0081] Step 303: Determine the fitness of the genetic algorithm according to the device parameters.

[0082] Step 304: Sort the chips on each wafer according to the genetic algorithm and the fitness.

[0083] Step 305: Determine whether the current wafer after sorting is the first wafer.

[0084] If yes, execute step 306;

[0085] If not, execute step 307.

[0086] Step 306: Determine the average value of the device parameters of the chips on the wafer as the center value of the wafer.

[0087] Step 307: Determine the device parameters of the last chip of the previous wafer as the center values ​​of the wafer.

[0088] Step 308: The chip corresponding to the device parameter with the smallest difference from the central value is used as the initial chip.

[0089] Step 309: cyclically shift the chips on the wafer until the initial chip is the first chip.

[0090] Step 310: Determine whether all wafers have been sorted.

[0091] If so, then end;

[0092] If not, execute step 302.

[0093] It should be noted that the specific execution method of each step in the embodiment of the present application is as follows Figure 2 The embodiments shown are not described in detail here.

[0094] Figure 4 The following is a schematic diagram of the structure of a chip screening device provided in one embodiment of the present application. The device includes:

[0095] The parameter acquisition unit 401 is used to acquire multiple wafers, each wafer including at least one chip to be sorted;

[0096] A chip sorting unit 402 is configured to sort the chips on each wafer according to chip distance, to obtain each wafer after chip sorting, wherein the chip distance is determined based on the difference in device parameters between two chips on the wafer;

[0097] The chip rearrangement unit 403 is used to determine the initial chip on each wafer after the chips are sorted, and to rearrange the order of the chips on the multiple wafers according to the initial chip, so that among any two adjacent chips, the device parameters of the last chip of the previous wafer are similar to the device parameters of the initial chip of the next wafer.

[0098] Figure 5 A structural schematic diagram of a computer device provided in one embodiment of the present application is shown, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the functions of the computer system of the chip screening method in any of the above-mentioned embodiments are realized.

[0099] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer performs the functions of the computer system of the chip screening method in any of the above embodiments.

[0100] The present application also provides a computer program product comprising instructions, which, when executed by a computer, enables the computer to perform the functions of the computer system of the chip screening method in any of the above embodiments.

[0101] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of the present invention.

[0102] It can be understood that in the various implementation methods of this application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation method of this application.

[0103] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0104] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those commonly understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise.

[0105] It is understood that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or software instructions. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0106] It will be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0107] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0110] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0111] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0112] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0113] The above are only specific embodiments of the present application, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip screening method, characterized in that: The method comprises: Obtaining a plurality of wafers, each wafer including at least one chip to be sorted; The chips on each wafer are sorted according to chip distance to obtain each wafer after chip sorting. The chip distance is determined based on the difference in device parameters between two chips on the wafer. The chip distance is determined based on the following formula: in, represents the chip distance between the adjacent i-th chip and the i+1-th chip, and represent the jth device parameters of the i-th chip and the i+1-th chip, respectively. represents the weight of the jth device parameter in the chip distance, and k represents the number of device parameters; The initial chip on each wafer after chip sorting is determined, and the order of the chips on the multiple wafers is rearranged according to the initial chip so that the device parameters of the last chip of the upper wafer and the initial chip of the next wafer in any two adjacent chips are similar.

2. The method according to claim 1, characterized in that The chips on each wafer are sorted according to the chip distance to obtain each wafer after chip sorting, including: Determine N sorting methods; Sure The sum of chip distances in each sorting method; Determine the sorting method corresponding to the minimum value of the sum of the chip distances as the target sorting method; The chips on each wafer are sorted according to the target sorting method to obtain each wafer after chip sorting.

3. The method according to claim 2, characterized in that The number of chips on the wafer is m, and N is equal to , the N sorting methods are determined according to the number of chips on each wafer.

4. The method according to claim 2, characterized in that The number of chips on the wafer is m, and N is less than , the N sorting methods are determined by repeated iterations of a genetic algorithm.

5. The method according to claim 4, characterized in that The termination condition of the genetic algorithm includes at least one of the following: reaching a maximum number of iterations, a device parameter between adjacent chips being less than a preset threshold, and a fitness value converging.

6. The method according to claim 1, wherein The determining of the initial chips on each wafer after chip sorting, and rearranging the order of the chips on the plurality of wafers according to the initial chips, comprises: Determining the average value of the device parameters of the chips on the first wafer as the center value of the first wafer, and determining the center value of the wafer other than the first wafer as the device parameter of the last chip after the chips on the previous wafer are rearranged; The chips on each wafer are sequentially shifted cyclically according to the center value so that the difference between the device parameters of the initial chips on the wafer and the center value is minimized, thereby obtaining a wafer with rearranged chip sequence.

7. A chip screening device, characterized in that: The device comprises: A parameter acquisition unit, configured to acquire a plurality of wafers, each wafer including at least one chip to be sorted; The chip sorting unit is used to sort the chips on each wafer according to the chip distance to obtain each wafer after chip sorting. The chip distance is determined based on the difference in device parameters between two chips on the wafer. The chip distance is determined based on the following formula: in, represents the chip distance between the adjacent i-th chip and the i+1-th chip, and represent the jth device parameters of the i-th chip and the i+1-th chip, respectively. represents the weight of the jth device parameter in the chip distance, and k represents the number of device parameters; The chip rearrangement unit is used to determine the initial chip on each wafer after the chips are sorted, and to rearrange the order of the chips on the multiple wafers according to the initial chip, so that among any two adjacent chips, the device parameters of the last chip of the upper wafer and the initial chip of the next wafer are similar.

8. An electronic device, characterized in that: include: processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the method according to any one of claims 1 to 6 is executed.

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