Speculative register reclamation

Abstract

This disclosure relates to speculative register reclamation. A system determines an original instruction having a first logical register (LR) mapped to a first physical register (PR). The system determines a current instruction having a current LR. A previous instruction is associated with a second LR mapped to a second PR. The system assigns the current LR to a third PR. In response to determining that the current instruction and the previous instruction were executed in different iterations, the system marks the second PR as ineligible for early release. In response to determining that the current LR was previously mapped to the first PR, the assignment includes a redefinition of the first LR. In response to determining that the first PR is eligible for early release and that the current instruction and the original instruction were executed in the same iteration or consecutive iterations, the system releases the first PR based on the redefinition rather than the completion of the previous instruction or the commit of the current instruction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 441,087 (Attorney General’s File No. HPE-P170927USPRV), filed on January 25, 2023, by inventor Sanyam Mehta, entitled “Speculative Register Reclamation”. Background Technology

[0003] The number of in-flight instructions continues to increase. While the benefits of more in-flight instructions can involve achieving higher instruction-level parallelism (ILP) and thus better single-threaded performance, the trade-off is the potential involvement of larger structures within the kernel, such as the physical register file (PRF), which can increase power consumption and degrade performance. Therefore, this trade-off can be mitigated by efficiently freeing physical registers while ensuring correct recovery from miscalculations. Attached Figure Description

[0004] Figure 1 The diagram illustrates the physical register lifecycle under various designs according to one aspect of this application.

[0005] Figure 2A The illustration shows a code excerpt according to one aspect of this application.

[0006] Figure 2B The illustration shows a side of the application with Figure 2A The code snippet contains the corresponding assembly language instructions.

[0007] Figure 2C A table illustrating a comparison of the physical register lifetimes across various systems, according to one aspect of this application, is provided.

[0008] Figure 3 The diagram illustrates a kernel structure for processing instructions according to one aspect of this application, the instructions including changes to entries in the Register Alias ​​Table (RAT), Reorder Buffer (ROB), and Scheduler.

[0009] Figure 4 The diagram illustrates a pipeline stage of a processing instruction according to one aspect of this application, the instruction including a timing change of a register read stage.

[0010] Figure 5 The diagram illustrates a data write-back and bypass of a payload random access memory (RAM) according to one aspect of this application.

[0011] Figure 6A flowchart illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented.

[0012] Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E A flowchart illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented.

[0013] Figure 8 The illustration shows a computer system that facilitates speculative register retrieval according to one aspect of this application.

[0014] In these accompanying drawings, the same reference numerals refer to the same elements. Detailed Implementation

[0015] The aspects of this application offer improvements in reducing the size of the Physical Register File (PRF) to sustain an increasing number of in-flight instructions. The described aspects (also known as speculative register reclamation or “SRR”) can leverage the insight that, in loops where most of the time typically is spent, most logical registers are redefined in the same iteration or the immediately following iteration. This allows physical registers allocated to most of these logical registers to be actively and speculatively freed upon redefinition, rather than upon redefinition instruction commit (as in traditional systems). The described aspects can extend existing tables and data structures (e.g., Register Alias ​​Table (RAT), Reorder Buffer (ROB), and scheduler) to determine eligibility for “early release” (i.e., freeing previously mapped physical registers upon redefinition of the corresponding logical register). The described aspects can further employ payload random access memory (RAM) for data write-back and bypassing and allow switching between SRR mode and normal mode, thus providing an improved system for speculative register reclamation.

[0016] The transition from one generation of chips to the next is becoming increasingly expensive in terms of both cost and time. Current trends in implementing this transition may involve, for example, building custom chips, optimizing software / code, and using chiplets to support the migration of monolithic chips to smaller process nodes (and more cores). However, while building custom chips may be useful for certain domains / applications (such as artificial intelligence), many users continue to utilize central processing units (CPUs) for example, the general-purpose computing power offered in the cloud. For these users, single-threaded performance remains a significant factor. On the other hand, co-locating multiple users / applications on a single node (as tenant users) can lead to an increase in the core count on the chip. As a result, improvements in core microarchitecture design remain crucial for providing performance gains with similar transistor counts, allowing for an increase in core count while ensuring Quality of Service (QoS) for each tenant user.

[0017] The number of in-flight commands continues to increase due to the following factors: the breakthrough from pure multi-core to hybrid architectures, which combine high-performance and low-efficiency cores to account for total chip power; better cooling technologies that allow drawing more than 400W of power in server chips; the move to chiplet architectures to achieve larger cores, where core area does not significantly limit the total core count; and the growing demand for single-threaded performance.

[0018] A large instruction window can mean increasing the size of kernel structures such as the physical register file (PRF) and the scheduler. Because these structures are multi-ported and sometimes very wide (e.g., vector / floating-point register files), they can consume considerable area and power, and may also affect the kernel's critical path.

[0019] The described aspects address the problem of large physical register files by providing a system and method that can utilize SRR (Special Releasing) to actively and speculatively release physical registers when redefining corresponding logical registers (as discussed below). Figures 1 to 3 (as described) and the use of payload RAM for data write-back and bypass (as described below) Figure 5 (as described) to reduce the size of the PRF.

[0020] The terms “functional unit” and “execution unit” are used interchangeably in this disclosure to refer to a part, component, unit, or module of a process or unit that can perform operations and calculations forwarded from instructions or instruction units. The terms “conventional systems,” “existing systems,” “conventional designs,” and “existing designs” are used interchangeably in this disclosure and refer to any currently existing manner, system, method, architecture, or design that exhibits significant improvements over the aspects described in the SRR.

[0021] Speculative Register Reclaim (SRR)

[0022] The lifecycle of a physical register can be marked by four key phases or events. The first event (E1) can be called "definition," which occurs when the result (i.e., logical) register (LR) of instruction I1 is assigned to a physical register (e.g., PR1). The second event (E2) can be called "redefinition," which occurs when LR is redefined in another instruction I2 and reassigned to a different physical register (e.g., PR2). The third event (E3) can be called "finishEx," which occurs when instruction I1 completes execution (sometimes before "redefinition") and writes its result to PR1. The fourth event (E4) can be called "commit," which occurs when instruction I2 commits its result to the architectural state, and physical register PR1 is finally released. Although PR1 remains active until "commit," no instructions use PR1 after I2 (i.e., after "redefinition") to ensure proper misread recovery and accurate exception handling in the current microarchitecture.

[0023] Figure 1 Figure 100 illustrates the physical register lifecycle under various systems according to one aspect of this application. Figure 100 represents time 110 from left to right and includes the following “events” at various relative times: “definition” event 112 (E1) at time t = 0; “redefinition” event 114 (E2) at time t = 0.05; “completion” event 116 (E3) at time t = 0.4; and “commit” event 118 (E4) at time t = 1.

[0024] The aspects described in SRR provide a method and system that can actively and speculatively reclaim certain physical registers that have reached the “redefine” phase or event. On average, physical registers can spend about 40% of their total lifetime before “completion of execution” (event 116), and about 60% from “completion of execution” to “commit” (event 118). On the other hand, “redefinement” (event 112) can occur shortly after “definement” (event 112) (accounting for about 5% of the register’s total lifetime). Therefore, the aspects described in SRR can achieve greater savings compared to existing designs that can reclaim registers at “completion of execution” (e.g., checkpoint processing and recovery (CPR) 134) or allocate registers at “completion of execution” (e.g., virtual physical registers (VPR) 132). Furthermore, SRR occurs at the “redefinement” event and can be considered speculative because the redefinement instruction I2 is not guaranteed to commit.

[0025] Figure 100 illustrates the various times during a physical register's lifetime when it can be reclaimed or released, depending on the method used. For example, for existing or legacy systems, Figure 100 depicts the following: the VPR 132 method can change from "completion" to "commit" before the physical register is released; the CPR 134 method can change from "definition" to "completion" before the physical register is released; while other legacy systems may require the entire time from "definition" to "commit" to release the physical register. Conversely, Figure 100 also depicts SRR 130, which can change from "definition" to "redefine" only before the physical register is released, representing a significantly shorter amount of time in the total lifetime of the physical register.

[0026] Ensure correct recovery from branch misprediction

[0027] A key insight of SRR is that a prerequisite for any aggressive reclamation strategy is ensuring proper recovery from branch misprediction (and precise exceptions). Any recovery from branch misprediction can involve restoring the saved RAT state, which can be done only within a specific instruction interval. As a result, freeing registers on a "redefinement" must involve identifying an instruction window (e.g., "W1") whose destination physical registers are traced to see if some registers in the destination physical registers can be quickly reached for "redefinement" and thus can be aggressively and speculatively freed. Freeing registers on a "redefinement" must also involve identifying another instruction window following W1 (e.g., "W2"), before which instructions in W1 must be traced.

[0028] To determine these windows W1 and W2, W1 and W2 must satisfy two contradictory properties. On one hand, the first property is that W1 and W2 should be such that by the end of W2, the "redefined" registers are maximized, allowing for the early release of more registers. On the other hand, the second property is that W1 and W2 should not be large because, to ensure correct recovery from speculative errors, no instruction in W1 can be committed unless all instructions in W2 have completed execution and are no longer speculative. This is because W2 might incorrectly cause the release of physical registers in W1 due to speculative errors.

[0029] To determine the sizes of these windows W1 and W2, it has been observed that in loops that typically consume the majority of program time, most logical registers are redefined in the same iteration or the immediately following iteration (i.e., reaching a "redefined" state). Therefore, if W1 is a single loop iteration and W2 is the immediately following iteration, many physical registers allocated in W1 can potentially be freed by tracking their redefinition until W2, which thus satisfies the first property controlling window size. Furthermore, since the innermost loop is typically small, W1 and W2 are in the minority of instructions in most cases, which thus satisfies the second property controlling window size.

[0030] Of all the registers allocated in W1 (and redefined before W2), only those used in W2 before redefinition (i.e., registers with "cross-iteration" consumers) need to remain allocated until "committed," as these registers are crucial for recovering from misspeculation and achieving accurate exception handling. Typically, only inductive and reduction variables (such as these storage counts, etc.) have cross-iteration consumers, while many other variables are used as temporary storage and may only be used in a single iteration. For example, on average, 80% of all allocated physical registers may not have cross-iteration consumers and could therefore qualify for early release. The following section discusses... Figures 2A to 2C Describe a specific example. Therefore, leveraging observations related to this key insight can significantly shorten the lifespan of physical registers and, in particular, reduce the number of physical registers required.

[0031] Using the ROB ID of the producer instruction and using the payload RAM

[0032] However, a problem remains. In the current microarchitecture, even if a physical register can reach "redefinement," it still needs to remain allocated until at least "execution complete." This is because its physical register ID is used as a tag to wake up consumer instructions waiting in the scheduler and forward data to the PRF, where the data is buffered until the consumer instruction is ready to execute. In all aspects described in SRR, waiting for "execution complete" is not an option because the loops that require the most physical registers are those with one or more long lazy loads, and it is precisely in these loads that "execution complete" typically occurs significantly later than "redefinement." Therefore, for maximum benefit, SRR must continue to actively reclaim registers after "redefinement," rather than "execution complete."

[0033] If physical registers are to be reclaimed after "redefinition," then none of these physical registers can be used for buffering data before execution begins, and their physical register IDs cannot be used as tags for waking up (multiple) consumer instructions. In another key insight, the aspects described address this issue by storing the ROB entry ID of the producer instruction in the scheduler instead of its physical register ID for each instruction, as discussed below. Figure 3 As described. Therefore, the producer's ROB entry can be used as a tag for waking up dependent consumer instructions in the scheduler.

[0034] Furthermore, the described aspects can use payload RAM to buffer data for feeding execution units instead of PRF, which complements the SRR aspects described herein. Thus, the physical registers of an instruction can be freed early during "redefinition," at the cost of its payload RAM entries being allocated until "execution completes." Payload RAM essentially serves as an efficient alternative to expensive register files, resulting in smaller register files. Payload RAM can be a distributed structure (such as a scheduler) and does not hold data until instruction commit. Therefore, payload RAM may not be as large or power-intensive as PRF.

[0035] Furthermore, unlike traditional systems where the PRF is written for each complete instruction (with a destination), in SRR, using payload RAM reduces these costly PRF writes by approximately 80% (on average). Additionally, payload RAM can only be written to when at least one of the consumers is not yet ready to execute. Since producers typically have very few consumers, payload RAM writes may not be frequent, potentially resulting in crucial dynamic power savings. Finally, whenever physical registers cannot be freed early, data can be written to the PRF and read into the payload RAM entries of any consumer that may later enter execution, just as in traditional systems.

[0036] Therefore, the aspects of SRR described can leverage insights related to defining window IDs and sizes, using ROBIDs as tags, and utilizing payload RAM to provide a system that can speculatively and aggressively reclaim registers, leading to a reduction in PRF size and an overall improvement in the performance and efficiency of the core architecture. For example, SRR has been observed to achieve a 50% reduction in PRF size while still achieving a 1.05x performance improvement over existing designs. A 26% reduction in power consumption has been measured across various core architectures under SRR. By shifting these resource savings to other structures within the core (such as the scheduler and ROB), the performance improvement can be increased to 1.14x.

[0037] Improvements of SRR compared to previous methods

[0038] The aspects described in this application differ from various existing methods and provide improvements over them. One existing method (Checkpoint Processing and Recovery (CPR)) uses checkpoints instead of ROBs, which allows it to roll back to the checkpoint start instruction in case of misprediction or memory anomalies. Similarly, as a result, physical registers can be reclaimed for instructions where branch safety or memory safety is unknown. All allocated registers that are inactive at the next checkpoint start instruction (i.e., reach “redefined”) can be marked for immediate release upon reaching “completion of execution”. In CPR, registers within a window are not tracked outside that window for reclamation opportunities. Using the terminology of this disclosure, W1 and W2 are identical in CPR.

[0039] The aspects described differ from CPR in the three regions. In the first region, W2 and W1 are not the same. SRR can take advantage of the observation that aligning W1 and W2 with consecutive loop iterations (i.e., the same instructions in W1 and W2, just different iterations) can provide a significant opportunity to aggressively reclaim registers (as per the observation regarding...). Figures 2A to 2C(As shown). In the second difference, the described aspects do not wait for the instructions whose registers are marked for early release to complete execution (i.e., reach the "completion of execution" stage) before they are released. Instead, the described aspects can release these marked physical registers upon "redefinition," which can bring significant performance advantages to memory-constrained code (as shown regarding...). Figure 2C (As shown). In the third difference, checkpoint-based architectures have not yet been successful in the industry because there is currently no known commercial design for this. Instead, the described aspects utilize a ROB-based design, making it easier for the industry to adopt while still ensuring correct misjudgment recovery and accurate exception handling. Furthermore, the ROB-based design of the described aspects allows for a switch to normal execution when aggressive register reclamation may be deemed unhelpful.

[0040] Another previous approach (Continuous Flow Pipeline (CFP)) uses slice buffers to queue long, lazy loads and their associated instructions. While instructions entering a slice do not need to wait for the arrival stage to "complete execution" (as with CPR), a major difference from the described aspects may involve re-execution. When a slice re-enters the scheduler for re-execution, CFP may require physical-to-physical renaming (i.e., renaming with a new mapping table) due to aggressive register reclamation. Therefore, the CPR scheme may require too much additional structure, increasing design complexity and energy consumption, while also relying on checkpoints rather than ROBs.

[0041] In another existing approach, a Virtual Physical Register (VPR) can be used to artificially increase the number of physical registers and serve as physical registers for dependency detection between instructions. The VPR can eventually allocate physical registers during write-back (or execution). Unlike the aspects described above that release physical registers after "redefinition," the VPR allocates registers upon "execution completion," and these registers remain allocated during the "commit" process. (See above regarding...) Figure 1 As described, given sequential instruction commits, the number of loops spent between "completing execution" and "committing" can be significant (approximately 60% of the total register lifetime), thus making VPR less efficient than the aspects described.

[0042] This shows a code excerpt that uses SRR to reduce physical registers.

[0043] The following information is about Figures 2A to 2C The examples show that most registers in a loop tend to have a short active range, that is, most registers are defined and used in the same iteration (“iterative local active range”), while fewer registers are used across different iterations (“cross-iterational active range”). Figure 2AAn exemplary code extract 200 according to one aspect of this application is illustrated. The exemplary code extract 200 may be an extract from the Sphnix3 speech recognition benchmark of the Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 kit, and may include lines 210, indicated as lines 210.1 to 210.11. Figure 2B The illustration shows a side of the application with Figure 2A The code extract corresponds to the assembly language instruction 220. Assembly language instruction 220 may include line 230, which includes lines 230.1-230.13, where lines 230.2-230.12 correspond to instructions I1-I11 respectively. The corresponding code lines (210.1-210.11) are described as having their use for... Figure 2B Each line of code or instruction is marked with a line marker. Figure 2C Table 240, according to one aspect of this application, illustrates a comparison of physical register lifetimes (referred to as "SRR") for various aspects of conventional hardware designs, CPR systems, and the system described herein. Table 240 may include indications and correspondences Figure 2B Each of the instructions I1-I11 contains an entry 250, wherein the entries in table 240 may include the following fields or information: instruction identifier (ID) 242; logical register to physical register mapping 244; and the lifetime of physical registers 246 for hardware 247, CPR 248 and SRR 249.

[0044] exist Figure 2A In code excerpt 200, the nested loops in lines 210.6-210.9 may be the most time-consuming part of the benchmark code excerpt. Consider the innermost loop `i` starting from line 210.6. Note that the variable `diff1` is defined in line 210.7 and used in line 210.8. Because this variable is redefined in line 210.7 of the next iteration, its active scope is from line 210.7 to line 210.8 within the same iteration (i.e., iterative local active scope).

[0045] On the other hand, the variable dval1 (which is the reduction variable) is defined in line 210.8, and then reused in line 210.8 in the next iteration. dval1 also has a short active range, but it spans multiple iterations (i.e., crosses iterative active ranges). Besides dval1, the inductive variable i also similarly has a short active range spanning iterations. Therefore, based on the source, it can be seen that all variables in code excerpt 200 have short active ranges. Among these variables, a few have iteratively local active ranges, while others have cross-iterative active ranges. However, upon examining... Figure 2B When examining the corresponding assembly code, it can be seen that there are more variables with iterative local active scope than variables with cross-iterative active scope. For example, each of the three load operations in loop i is assigned a unique logical register (e.g., Figure 2B In instructions I2-I4, registers s1-s3 are all logical registers with iterative local active range. Similarly, register x12 in instruction I1 has iterative local active range. Therefore, code excerpts 200 and 220 show that there are more variables with iterative local active range than variables with cross-iterative active range.

[0046] Consider the outer loop j starting at line 210.1. Many variables / registers (such as...) Figure 2A Rows 210.2-210.5 in the text have iterative local active ranges. Although Figure 2A and Figure 2B The example depicted is a simplified one, but this observation is often likely correct because complex instructions in the source are broken down into micro-operations in the assembly / object code, which require the use of more registers with iterative local active ranges.

[0047] -SRR may reclaim more registers than CPR in the early stages.

[0048] Because previous designs of CPR relied on checkpoints, this application refers to instructions within two consecutive checkpoints as a CPR window (“CW”). In CPR, of all physical registers allocated within the CW, only those physical registers that are “redefined” within the same CW are eligible for early release. Therefore, using W1 and W2 as previously described in this application, if W1 equals CW, then W2 and W1 are identical in CPR; that is, CPR does not track registers allocated outside of W1 in W1 to gain more reclamation opportunities. Applying this standard... Figure 2A and Figure 2BFor example, assuming the checkpoint begins at the start of the loop, the physical registers used for instructions I1, I4, I5, I7, I9, I10, and I11 must all remain allocated because these instructions are not redefined until the next iteration / checkpoint begins (i.e., these instructions are only "redefined" when the next iteration / checkpoint arrives). This can involve a considerable number of physical registers, i.e., the number is not negligible.

[0049] Therefore, these instructions need to retain their physical registers until "commit"—in a checkpoint architecture, this could mean exiting the next checkpoint or completing all instructions in the next checkpoint. Because some of these instructions may depend on data from main memory, the lifetime of the physical registers associated with these instructions can be almost equal to the main memory access time (i.e., memory latency or "MemLat"), such as... Figure 2C The hardware 247 and CPR 248 are shown in the columns.

[0050] In contrast, the aspects described in SRR extend W2 beyond W1, which could lead to the anticipated redefinition of logical registers x12 (I1), s3 (I4), d2 (I7), d1 (I9), and cond (I10) defined in W1 in W2 without their use (i.e., without cross-iterative consumers), and therefore without having to retain their corresponding physical registers from W1 for mispredictable recovery. To achieve this, the described aspects can augment the Register Alias ​​Table (RAT) entries of instructions with the window ID (“WID”) of each issued instruction. The WID can be incremented at the start of the loop or after every certain number of instructions. Cross-iterative consumers can be determined by comparing the WIDs of each producer-consumer pair, while the redefinition within W2 can be confirmed by comparing the WIDs of previous and upcoming instructions mapped to the same logical registers in the RAT. Thus, in the aspects described in SRR, only PR4 and PR10 need to remain allocated until “commit”, making their lifetimes on the order of memory latency (i.e., “MemLat”), such as Figure 2C As shown in column SRR 249.

[0051] --Register reclamation in SRR may be faster than CPR

[0052] In existing designs, physical registers can be released upon "commit," which may occur long after "redefinition" and "execution completion." For example, in... Figure 2BEven for instructions with short latency (e.g., I1, I5, and I10), these instructions may still need to wait for older memory operations to complete and commit their results before freeing their physical registers. Furthermore, because instructions are committed sequentially, the actual lifetime of these instructions may be even longer than the memory access time (i.e., "MemLat"). Figure 2C As indicated. CPR might help shorten this exaggerated lifespan because physical registers that reach "redefined" at the end of the checkpoint no longer need to wait for "commit" but can be released after execution is complete (i.e., "completion") and the results are forwarded to all consumers. However, this may not be enough, as "completion" can often occur much later than "redefined".

[0053] For example, m1[i] (i.e., Figure 2B The operation indicated by instruction I2 in the code can represent an indirect load, typically from memory, implemented by bypassing the hardware prefetcher. As a result, this operation can be a long-latency operation. Therefore, even if PR1 (allocated by I2) quickly reaches "redefined" (in instruction I6 within the same iteration), PR1 must remain allocated until the load from memory is complete (i.e., until the operation reaches "completion execution"). Thus, as... Figure 2C As shown, the lifetime of PR1 can be almost equal to the main memory access time with CPR. The same is true for consumers of PR1 (such as instruction I6).

[0054] The aspects described by SRR can be handled more aggressively, releasing eligible registers without waiting until "execution completes." In the example, PR1 does not cross-iterate with the consumer and is therefore eligible for aggressive reclamation using SRR. Since SRR can reclaim PR1 after "redefinition" (based on the above insights), PR1 can be released within a very short cycle, i.e., as soon as instruction I6 is renamed. This rapid reclamation after "redefinition" can be achieved by extending the scheduler with payload RAM that provides data to the consumer while many producer physical registers are released early.

[0055] Similar to I2, another long lazy load involving PR3 in I4 can also be aggressively released using SRR. As a result, not only PR1 and PR3, but also their dependent chains (I6, I7, I8, I9, and I11) can release their physical registers early because they do not need to wait for the instruction to complete. The aspects described by SRR can lead to a reduction in the lifetime of these registers and their consumers from approximately the memory latency (i.e., "MemLat") in CPR to only a few cycles (i.e., about 1-2), as... Figure 2C As shown in the column of SRR249.

[0056] Therefore, SRR not only allows for the early reclamation of many registers but also significantly shortens the lifetime of many registers. Both of these improvements can potentially help reduce the number of physical registers required in a microarchitecture.

[0057] SRR Design for Facilitating Speculative Register Reclamation

[0058] Figure 3 Figure 300 illustrates a core structure for processing instructions according to one aspect of this application, the instructions including changes to entries in the Register Alias ​​Table (RAT), Reorder Buffer (ROB), and scheduler. Figure 300 depicts: a RAT 310 with entry 312; a ROB 320 with entry 322; a scheduler 330 with entry 332; a payload RAM 350; an execution unit 360, including execution units 362, 364, and 366; a physical register file (PRF) 370 with a floating-point register (“FP Reg”) 372 and an integer register (“Int Reg”) 374; and a free list 380. The fields of RAT entry 312, ROB entry 322, and scheduler entry 332 are described below. Expanded or newly added fields are indicated by bold borders, while replaced or deleted fields are indicated by a left-sloping diagonal fill pattern.

[0059] - Rename the register alias table (RAT)

[0060] A renaming unit (or RAT 310) can be a structure that stores the latest mapping of logical registers to physical registers. Each upcoming instruction can update the logical register-to-physical register mapping to represent the latest state. In a traditional system, a RAT entry (e.g., 312) may contain only the mapping of logical register IDs (LRID 313) to their corresponding physical register IDs (PRID 314) and a separate bit vector P 315 for each physical register (which can be updated directly upon instruction completion). Figure 3 For simplicity, LRID (313) and P bit (315) are depicted as part of a single RAT entry (312).

[0061] The newly decoded instruction can enter the renaming stage and update its destination logic register's RAT entry with its newly allocated physical register ID (from the free list 380 of physical registers) (via communication 396). The P bit can be reset (i.e., set to "0") to indicate that the instruction has not yet completed. When the instruction completes execution, the P bit can be set (i.e., set to "1"). The value of the P bit can be used to indicate to subsequent consumer instructions that their source operands(s) are ready.

[0062] The described aspects can be extended to the RAT using the upcoming instruction's ROBID (316) and window ID (WID 317) as well as reserved bits (H 318), such as Figure 3 As shown. When the RAT entry for an instruction is first created, the reserved bit H can be reset (i.e., set to the default value or initial value "0"). When the reserved bit is set (i.e., set to "1"), this indicates that the associated physical register must remain allocated and cannot be prematurely freed. The following section discusses... Figure 7A This describes the creation of a RAT entry. The section below, titled "Changes from Renaming," describes the updating of the WID.

[0063] -Scheduler

[0064] The scheduler (330) can track instructions that need to wait for source operands to become available, and select these instructions for execution once their operands become available (e.g., via communications 361 / 363 / 365 to execution units 362 / 364 / 366 respectively). In a conventional system, a scheduler entry (e.g., 332) may include the following fields: busy bit (B333); instruction / operation field (Op 334); ready bit (R1 335 and R2 336); source operand field containing the corresponding physical register ID (SRC1 342 and SRC2 344); and destination field (D 339) containing the physical register ID assigned to the destination register of the instruction.

[0065] The described aspects can be extended to include the ROB ID of the destination instruction (ROBID340) (obtained from the RAT) alongside the physical registers. On the other hand, the source physical register IDs (SRC1 342 and SRC2 344) can be replaced with the ROB IDs (ROB1 337 and ROB2 338) of the source instructions (also obtained from the RAT), such as... Figure 3 As shown. The following text is about Figure 7A Describes the creation of scheduler entries.

[0066] - Payload RAM

[0067] The system architecture can be designed with or without payload RAM. In an architecture without payload RAM, operands can reside solely in the Physical Register File (PRF). When an instruction is ready to proceed and is awakened by the scheduler, the PRF (indexed by the scheduler's SRC1 and SRC2 bits) provides the operand values ​​to the functional unit to begin execution. When the instruction completes execution, the functional unit can write the result to the destination physical register.

[0068] In an architecture with payload RAM (350), operands can be buffered in the payload RAM (e.g., as described below regarding...). Figure 5 As described in 520), the payload RAM can then provide operand values ​​to the execution unit (360, including 362, 364, and 366) separately, instead of both the payload RAM and the register file, which would require more ports at the execution unit. When the instruction completes execution, the result can be forwarded to the PRF (via communications 392 and 394), or to the waiting consumer in the payload RAM (via communication 390, and also as described below). Figure 5 (as described in output 574).

[0069] While designs without payload RAM may have the advantage of a smaller scheduler, designs with payload RAM result in fewer read ports in the PRF, which now becomes a function of dispatch width rather than the number of execution ports. This is because the PRF is read (into payload RAM) immediately after the renaming (i.e., "redefinition") phase, rather than at the start of execution (into the functional unit), as in designs without payload RAM.

[0070] Similarly, a design with payload RAM can significantly reduce the number of read ports for the scheduler because scheduler entries are no longer used to index the register file to provide data. The data is already in the payload RAM. On the other hand, write ports on the payload RAM can be expensive because the payload RAM must receive data from the physical register file (before / during instruction dispatch) and from functional units (when instructions complete).

[0071] However, the size of the payload RAM can be much smaller than the size of the physical register file. This is due to two factors. First, the lifetime of instructions in the payload RAM (such as the scheduler) can be much shorter than that in the physical register file. Second, unlike the physical register file, the scheduler (including the payload RAM) can be distributed across (multiple) functional units. The following section discusses... Figure 5 Describe data write-back and bypass.

[0072] Therefore, the various aspects described in SRR use a scheduler with payload RAM because this can lead to a significant reduction in the size of the physical register file.

[0073] --Reorder Buffer (ROB)

[0074] Even if instructions are executed out of order, the ROB (320) can enable sequential instruction commits. Therefore, the ROB allows for speculation across branches, enabling correct recovery from mispredicted branches and ensuring accurate exception handling. Because the ROB contains all active instructions at any given time, its size is the same as the instruction window size. In a traditional system, an ROB entry (e.g., 322) might contain the following fields: a busy bit (B 323); a status bit (S 324) indicating whether the instruction is suspended or completed; the physical register assigned to the instruction (Preg 325); and the previous physical register that mapped the logical register of the instruction (Ppreg 326 – obtained from the RAT). The ROB entry (322) may also include additional bits for bookkeeping. The Ppreg field (326) can be used to release the indicated register upon instruction commit, a mechanism used for register reclamation in traditional systems.

[0075] The described aspects can be expanded by adding a free bit (F 327) to indicate whether the Preg (325) associated with that ROB entry has been prematurely released. The following section discusses... Figure 7A Describes the creation of ROB entries.

[0076] -- Improvements in the renaming phase

[0077] As described above, aspects of SRR can be operated on instruction windows. During the renaming phase (i.e., "redefinition"), a window ID (WID) can be assigned to each instruction. A consecutive block of instructions can all be assigned the same WID, while the next block of instructions can be assigned WID+1, and so on. As discussed above, mapping windows to loop iterations can achieve improved results. To do this, the program counter (PC) of each issued instruction and the last PC of the starting window can be tracked. If the PC of the issued instruction matches the starting PC of the last window, a new window is started, which may cause it to naturally align with the loop. Additionally, the described aspects can use lower and upper limits of 5 and 24 instructions respectively for the window size. Unless a loop is identified, a new window can start at the next branch after the upper limit is reached. All new windows can start at a branch unless the absolute upper limit of the window size (e.g., 72 instructions) is reached. A branch can be a place where the processor has checked the RAT state. This choice can help to naturally align with individual loop iterations according to the desired SRR. The RAT state of a checkpoint may still need to be recovered from misjudgments, as in a traditional system, although the recovery mechanism in SRR may differ slightly from that in a traditional system. The lower bound of the window size, 5, can be controlled by the maximum number of checkpoints, while the upper bound, 24, and the absolute upper bound, 72, can be chosen to limit the re-execution overhead while benefiting from early reclamation.

[0078] In each loop, the issued instruction can perform two actions on the RAT. The issued instruction can update the RAT to indicate the new logical register to physical register mapping, and the issued instruction can read the physical register ID of its source operand and then pass it to the scheduler (via communication 382).

[0079] The aspects described in SRR can be subject to two additional checks. In the first check, the system can compare the window IDs (WIDs) of each producer-consumer pair. If these WIDs do not match (indicating cross-window or cross-iteration use), the system can set the H bit for the producer (i.e., set it to the value "1"). In the second check, for an entry being updated by an issued instruction, the system can check its H bit and compare its WID (i.e., the WID of the last mapped instruction) with the WID of the newly issued instruction. If the H bit is not set (i.e., set it to the value "0"), and the WIDs are the same or differ by 1, this indicates that the old physical register was redefined in the same window or immediately following window without any cross-window use, and the register can therefore be (early) freed without affecting mispredictable recovery.

[0080] In this case, if the last mapped instruction has not yet finished executing (indicated by the P bit in the RAT), the physical register associated with that last mapped instruction can be freed (i.e., added to the free list (380) of the physical registers), and the free bit F can be set in its ROB entry (i.e., set to the value "1"). The following section discusses... Figure 7B Describe these two additional checks, as well as the settings and early release of various fields.

[0081] Furthermore, to prevent the kernel from attempting to free a physical register that has already been freed during the "commit" phase, the system does not update the Ppreg field of the ROB entry for newly issued instructions with the PRID of the destination of the last mapped instruction (this is done in legacy systems). In all aspects described in SRR, the Ppreg field remains set to NULL, indicating that the corresponding physical register was freed early during the "redefine" phase.

[0082] --Improvements during the execution phase

[0083] In traditional systems, when an instruction enters execution, the scheduler can forward the destination's PR ID to the functional unit. This PR ID can be used as a tag to broadcast to the scheduler (when the instruction completes). The scheduler can then select consumers whose ready bits (R1 / R2) must be set, as well as those that must receive data from the payload RAM (if present). However, in SRR, the physical registers may have already been freed prematurely at this point.

[0084] In the aspects described in SRR, the scheduler can instead forward the destination's ROB ID to the functional units (via communications 361 / 363 / 365 to execution units 362 / 364 / 366 respectively), which can later be broadcast and used to set the ready bit and provide data to consumers. The consumer's PR ID (SRC1 342 and SRC2 344, indicated to be replaced or removed with a left-tilted diagonal fill pattern) in the scheduler may no longer be needed for tag matching purposes. This wake-up logic in the scheduler can be similar in SRR to that in a traditional system: matching is performed on the ROB ID instead of the PR ID. It should be noted that the destination's PR ID may still be needed in the scheduler and can be used to write data to the PRF whenever the corresponding physical register is not eligible for early release with SRR. The following section discusses... Figure 7C Describes broadcasts based on ROB ID.

[0085] -- Improvements during the write-back phase

[0086] During the write-back phase, traditional systems write the value of the completed instruction to the corresponding destination register in the PRF. However, in SRR, the destination physical register may typically have already been freed at this point and there are no future consumers. This condition can be determined by checking the free (F) bit of the ROB entry, which can be done along with updating the status (S) bit in the ROB to indicate instruction completion. If the F bit is set (i.e., set to the value "1"), the system in SRR can completely skip the write to the PRF.

[0087] Figure 5 Figure 500 illustrates a data write-back and bypass of payload random access memory (RAM) according to one aspect of this application. Figure 500 includes a scheduler 510, payload RAM 520, and functional units 540 and 550. Scheduler 510 may correspond to scheduler 330 of Figure 300, payload RAM 520 may correspond to payload RAM 350 of Figure 300, and functional units 540 and 550 may correspond to execution units 360 (including 362, 364, and 366) of Figure 300. For the corresponding instruction, each functional unit may include at least a ROB ID (542), a physical register ID (544), and data (546).

[0088] Payload RAM and data write-back In an architecture with payload RAM, in addition to the PRF, data must also be forwarded to waiting consumers in the payload RAM. This data forwarding can be performed as described in the aspects of the SRR. The functional unit (540) can broadcast the ROB ID of the completed producer instruction on the scheduler (510). This ROB ID can be matched against the ROB IDs of the two source operands of each scheduler entry using an associative lookup (560). Matches obtained can include, for example, ROB1 512 and ROB2 514 of 516 via associative lookup results 562 and 564, respectively. These matches can be used either to set the corresponding ready bit for the consumer in the scheduler or to directly index the corresponding payload RAM entries (e.g., data 1 522 of 526 and data 2 524 of 528) via direct indexing operations 566 and 568, respectively, to receive data from the functional unit on its write port. Direct indexing means that if the payload RAM is a RAM structure, no additional broadcasting is required.

[0089] Payload RAM and data bypassThe aforementioned data write-back scenario may occur when a consumer instruction is not ready to execute. When the last operand is ready and the instruction is invoked / selected for execution, the data is not written to the payload RAM but can be directly bypassed to the functional unit (e.g., data 2 in Figure 500 depicted via bypass bus 572). In this instance, the payload RAM may provide one or more operands (e.g., data 1 522 depicted as 530 communicated via data 1 (ready) 570), while another(multiple) operands may be received from the bypass bus (e.g., as depicted by communication 572). This can be similar to a conventional system where one or more operands come from the register file, while another(multiple) operands may come from the bypass bus.

[0090] Write to payload RAM and physical register file As described below, writes to the payload RAM (e.g., via output 574 and communication 576 / 578 for data 1 522 and data 2 524 respectively) can be significantly less than writes to the PRF for all (but no-destination) submitted instructions. This is because in many cases, there are few consumers ready to execute, in which case data can be directly bypassed to their execution units. In such cases, there may be no other waiting consumers requiring data (determined by ROB ID matching in the scheduler), and therefore the system can avoid writes to the payload RAM.

[0091] - Submitted improvements

[0092] In traditional systems, when an instruction is committed, the physical registers previously mapped to the instruction's logical registers (indicated by the Ppreg field 326) can be freed and added to the free list (380) of physical registers. In the aspects described in SRR, if the Ppreg field of the committed instruction is not NULL (indicating that the corresponding physical register was not freed prematurely), the same mechanism can be followed. However, if the Ppreg field is NULL, the system may not take any action to free the physical registers.

[0093] Beyond the actual instruction commit, SRR offers another significant improvement in the timing of instruction commits. In traditional systems, instructions are committed when they reach the header of the ROB and complete execution. In the aspects described in SRR, instructions within window W can begin to commit when they reach the header of the ROB and when all other instructions in that window W and the next window W+1 have completed execution. While this may increase latency associated with commits, the smaller window size can help maintain lower penalties. A counter for each window ID can be used to track the number of incomplete instructions; this counter increments when instructions are dispatched and decrements when instructions complete. This tracking counter ensures correct recovery from misjudgments. The following section discusses... Figure 7D Further description of the process for recovering from erroneous assumptions.

[0094] --Changes in the pipeline stage of SRR

[0095] Figure 4 Figure 400 illustrates the pipeline stages of a processing instruction according to one aspect of this application, the instruction including a change in the timing of a register read stage. Figure 400 illustrates that the conventional operation stages may occur in the following order: fetch stage 402; decode stage 404; rename stage 406; dispatch stage 410; schedule stage 412; register read stage 414 (depicted with a right-tilted diagonal filled pattern); execution stage 416; and write-back stage 418. Thus, in a conventional system, register read stage 414 occurs after schedule stage 412 (as indicated by arrow 422). Conversely, in the aspects described in SRR, register read stage 408 (depicted with a bold boundary) occurs earlier in the pipeline: after rename stage 406 (i.e., the “redefine” event) (as indicated by arrow 420).

[0096] --Recovering from Misjudgment

[0097] In traditional systems, when a branch outcome is mispredicted, instructions following the branch can be squeezed, and instruction dispatch can be recovered from the correct branch target using the RAT saved at the branch prior. Since no instructions following the incorrectly predicted branch are committed, recovery can be performed correctly.

[0098] In all aspects described by SRR, physical registers are speculatively freed in addition to speculatively executed instructions. Because SRR can be a function of instruction behavior in the current and next windows (e.g., where a redefinition not used in the next window can free registers from the previous window), instruction commits in window W can be suspended until all instructions in windows W and W+1 have completed execution. Furthermore, if a branch in window W+1 is mispredicted, progress must be rolled back to the beginning of window W. Similarly, if a branch in window W is mispredicted, progress must be rolled back to the beginning of window W-1. That is, all aspects described by SRR can be rolled back further after an actual mispredicted branch, potentially incurring the overhead of reissued and re-executed instructions from the beginning of the previous window up to the mispredicted branch.

[0099] However, recovery can be similar in principle to a traditional system: because the window starts as a branch, instruction dispatch can be restored using a RAT snapshot within that branch. SRR also guarantees that no instructions have been committed since the start of the previous window, as is the case in a traditional system. Since SRR does not release registers used by the cross-window, it guarantees the recovery of any physical registers used in window W-1 that were written in the previous window (assuming misprediction occurred within window W), thus ensuring correct misprediction recovery. Registers not used by cross-iterations in windows W-1 and W may have been released prematurely, but can be recalculated during re-execution. As part of this recovery, newly issued instructions can be assigned a WID starting with the old WID of the instruction to which the rollback was executed.

[0100] Switching between SRR mode and normal mode

[0101] Since the program counter (PC) moves to the beginning of the window before the culprit window (where the misjudgment occurred), the number of instructions reassigned and re-executed can be equal to the window size plus the number of instructions from the beginning of the culprit window to the actual misjudged instruction. Because SRR naturally favors small windows (e.g., aligning the window with the innermost loop) and also enforces an upper limit on window size in other ways, the penalty from the aforementioned extraneous reassignment and re-execution is usually likely to be small. While this penalty may not be significant compared to the memory latency of hundreds of loops, it can be quite significant for programs that enjoy L1 / L2 cache hits (i.e., computationally constrained) and contain frequent unpredictable branches (e.g., in some SPECINT code). However, it is precisely these highly computationally constrained programs that do not significantly benefit from SRR, while memory-constrained programs do.

[0102] This feature allows for a natural mode-switching strategy: enabling SRR to benefit from aggressive register reclamation in the presence of memory-constrained code that puts pressure on the register file; and disabling SRR for computationally constrained code with a high misprediction rate to restore normal mode execution (as in a legacy system) to minimize overhead. The described aspects can be implemented by tracking LLC per thousand instruction misses (MPKI), which is already supported in existing designs via performance counters. If the MPKI in a program region is below a first predetermined threshold combined with a high branch misprediction rate (e.g., above a second predetermined threshold), the system can disable SRR (i.e., "normal mode"); otherwise, the system can enable SRR (i.e., "SRR mode").

[0103] This switching between SRR mode and normal mode can be achieved through two simple functions. In the first function, in normal mode, all issued instructions can set the H bit in the RAT (i.e., set it to a value of "1"), which disables the F bit in the ROB, resulting in no registers being prematurely freed. In SRR mode, all issued instructions can continuously reset the H bit (i.e., set it to a value of "0"), which allows certain registers to be prematurely freed based on the aforementioned criteria. In the second function, in normal mode, the counter tracking the number of incomplete instructions per window is not updated and remains set to 0, allowing the ROB to properly classify instructions. In SRR mode, the counter can actually track the number of incomplete instructions per window to limit instruction classification, thus enabling false positive recovery. Therefore, these two functions allow the described system to efficiently switch between SRR mode and normal mode.

[0104] Improvements in power consumption and performance compared to previous methods

[0105] As described in this paper, aggressive speculative register reclamation using SRR can lead to a reduction in the size of the physical register file. This reduction can result in improved power consumption (i.e., a decrease) because access to the PRF may be cheaper (e.g., assuming a PRF size reduction of approximately 50%). SRR can also lead to a significant reduction in more expensive floating-point (FP) register writes due to earlier physical register reclamation (e.g., an average reduction of approximately 80%). Furthermore, in SRR, because many instructions can receive their operands directly from the bypass bus, writes to the payload RAM can be made less frequently, as discussed above. Figure 5 As described. Furthermore, the power consumption of SRR can be more evenly distributed among the floating-point register file, payload RAM, and load queue. Because the physical register file can be considered one of the hottest units on the chip, this allows for significant power reductions in all aspects of these improved SRRs.

[0106] The aspects described by SRR can also lead to performance improvements, for example, by redirecting power savings from a smaller physical register file to other resources within the core. The performance improvements of SRR can be a direct result of the reduced demand for physical registers themselves. Given the gradual reduction in physical registers, SRR can outperform CPR because SRR is more efficient at freeing up registers. That is, SRR can maximize the use of increased allocation of other resources at the expense of physical registers, while CPR cannot tolerate such a similar significant reduction in physical registers.

[0107] Therefore, when faced with a large and ever-increasing number of in-flight instructions, the described aspects can reduce the pressure on the physical register file in modern microarchitectures. SRR can leverage the property that logical registers used in loops are not typically used outside of the loop iterations defined with them; thus, SRR can release the corresponding allocated physical registers when the logical registers are redefined, unlike in existing designs where they are released when the instruction hierarchy is redefined. SRR can also use ROB IDs as tags for instruction wake-ups in the scheduler and can utilize payload RAM to provide data to functional units. As a result, SRR can even release the physical registers of qualified instructions before the instruction completes. This can lead to significant savings in the lifetime of physical registers, while reducing the size of the physical register file, and thus improving power savings and performance.

[0108] Methods for facilitating speculative register reclamation

[0109] Figure 6 A flowchart 600 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. During operation, the system determines the original instruction associated with a first logical register mapped to a first physical register, wherein the first physical register is initially marked as eligible for early release (operation 602). The system determines the current instruction associated with the current logical register and one or more operands having corresponding values ​​produced by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register (operation 604). The system allocates the current logical register to a third physical register (operation 606). In response to determining that the current instruction and previous instructions were executed in different iterations, the system marks the second physical register as not eligible for early release (operation 608). The operation returns and may also continue at operation 610.

[0110] In response to determining that the current logical register was previously mapped to a first physical register, the system determines that the allocation includes redefining the first logical register (operation 610). In response to determining that the first physical register is eligible for early release and that the current instruction and the original instruction are executed in the same iteration or consecutive iterations, the system releases the first physical register based on the redefinition of the first logical register rather than on the completion of the previous instruction or on the commit of the current instruction (operation 612). The system instructs the first physical register to be released early, thereby facilitating speculative reclamation of physical registers and reducing the size of the corresponding physical register file (operation 614).

[0111] The following text is about Figures 7A to 7E The described operations correspond to the aspects described in the SRR design, including those related to... Figures 3 to 4 The parts related to RAT 310, ROB 320, scheduler 330, payload RAM 350, execution unit 360, PRF 370 and free list 380, and related to Figure 5 The parts related to scheduler 510, payload RAM 520 and functional units 540 / 550.

[0112] Figure 7AA flowchart 700 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. During operation, the system determines the original instruction associated with a first logical register mapped to a first physical register, wherein the first physical register is initially marked as eligible for early release (operation 702). The system determines the current instruction associated with the current logical register and one or more operands having corresponding values ​​generated by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register (operation 704). A first entry in the RAT for the original instruction includes: a first LR to a first PR allocation; a first ROB ID; a first window ID (WID) for the associated loop iteration; and a reserved bit set to indicate that the first PR is eligible for early release; and a second entry in the RAT for the previous instruction includes: a second LR to a second PR allocation; a second ROB ID; a second WID for the associated loop iteration; and a reserved bit set to indicate that the second PR is eligible for early release (operation 706). The system creates a third entry in the RAT for the current instruction, wherein the third entry includes: the allocation from the current LR to the third PR; the third ROB ID; the third WID for the associated loop iteration; and a reserved bit set to indicate that the third PR is eligible for early release (operation 708). The system creates a reorder buffer (ROB) entry for the current instruction, wherein the ROB entry includes: the third PR as the corresponding PR of the current instruction; the first PR as the previously mapped PR; and a free bit set to indicate that the third PR has not been early released (operation 710). The system creates a scheduler entry for the current instruction based on the third RAT entry and the ROB entry, wherein the scheduler entry includes: the destination ROB ID; and the ROB ID corresponding to the previous instruction (operation 712). Figure 7B The mark A and / or Figure 7C Continue at mark B.

[0113] Figure 7B A flowchart 720 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. The system determines whether a third WID matches a second WID (decision 722). If the third WID does not match the second WID (decision 722), the system sets a reserved bit in the second RAT entry of the previous instruction to indicate that the second physical register is not eligible for early release (operation 724). If the third WID matches the second WID (decision 722), the operation continues or returns at marker B.

[0114] Figure 7CA flowchart 730 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. In response to determining that the current logical register was previously mapped to a first physical register, the system determines a redefinition of the first logical register (operation 732). If a reserved bit in the first RAT entry indicates that the first physical register is eligible for early release (decision 734) and the first WID and third WID match or differ by one (decision 736), the system releases the first physical register based on the redefinition of the first logical register rather than on the completion of a previous instruction or the commit of the current instruction, wherein the release includes early release (operation 738). The system marks the first physical register as available in the free list of physical registers (operation 740). The system sets a free bit in the ROB entry of the original instruction to indicate that the first physical register has been early released (operation 742). The system sets a null value in the ROB entry of the current instruction for the previously mapped physical register (operation 744). The operation in... Figure 7D Continue at marker C.

[0115] If the reserved bits of the first RAT entry do not indicate that the first physical register is eligible for early release (Decision 734), or if the reserved bits indicate that early release is eligible (Decision 734), but the first WID and the third WID do not match or differ by one (Decision 736), then the operation is performed in... Figure 7D Continue at marker C.

[0116] Figure 7D A flowchart 750 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. If the current instruction has not completed execution (decision 752), the operation continues until completion. If the current instruction has completed execution (decision 752), the system broadcasts the third ROB ID of the current instruction (operation 754). The system matches the third ROB ID with the ROB ID of the operand of the current instruction based on an association lookup of the obtained entry in the scheduler data structure (operation 756). The system sets the ready bit of the obtained entry in the scheduler data structure (operation 758). Without additional broadcasting, the system directly indexes the entry in the payload RAM based on the obtained entry, wherein the indexed entry in the payload RAM will receive data from the execution unit on the corresponding write port (operation 760). The execution unit can receive the value associated with the first operand of the current instruction from the payload RAM, and can further receive the value associated with the second operand of the current instruction via a bypass bus (not shown). Figure 7E Continue at marker D.

[0117] Figure 7EA flowchart 770 illustrating a method for facilitating speculative register reclamation according to one aspect of this application is presented. The system determines whether all instructions in the current iteration (e.g., window W) and the previous iteration (e.g., window W-1) have completed execution (decision 772). If not, the operation continues until it has completed execution. If the instructions in the current iteration and the previous iteration have completed execution (decision 772), the system commits the current instruction (operation 774). If the system does not identify a misspeculation of a branch in the current iteration (i.e., window W) (decision 776), the operation returns. If the system identifies a misspeculation of a branch in the current iteration (i.e., current window W) (decision 776), the system rolls back the execution of the instruction to the beginning of the previous iteration (i.e., previous window W-1) (operation 778). The operation returns. Although in Figure 7D Decision 776 and operation 778 are described as occurring after operation 774, but the logic for handling false guesses and rollbacks can occur at other times during the processing of the current instruction or any other instruction.

[0118] Computer systems for facilitating speculative register reclamation

[0119] Figure 8 The illustration depicts a computer system 800 facilitating speculative register retrieval according to one aspect of this application. The computer system 800 includes a processor 802, a memory 804, and a storage device 806. The memory 804 may include volatile memory (e.g., RAM) that serves as management memory and can be used to store one or more memory pools. Furthermore, the computer system 800 may be coupled to a peripheral input / output (I / O) user device 810 (e.g., a display device 811, a keyboard 812, and a pointing device 813). The storage device 806 may store an operating system 816, a content processing system 818, and data 836.

[0120] Content processing system 818 may include instructions that, when executed by computer system 800, cause computer system 800 to perform the methods and / or processes described in this disclosure. Specifically, content processing system 820 may include instructions for sending and / or receiving data (communication unit 820) to / from other modules / units / components within computer system 800 or to / from other network nodes on a computer network.

[0121] Content processing system 818 may further include instructions for determining the current instruction associated with a logical register and one or more operands having corresponding values ​​produced by one or more previous instructions (communication unit 820). Content processing system 818 may include instructions for allocating a logical register to a first physical register, wherein the first physical register is initially marked as eligible for early release (RAT management unit 522). Content processing system 818 may include instructions for determining allocation including redefining the logical register in response to the logical register being previously mapped to the original physical register (RAT management unit 822). Content processing system 818 may include instructions for marking the original physical register as ineligible for early release (early release management unit 828) in response to the current instruction not being executed in the same iteration as the previous instruction (window management unit 830). Content processing system 818 may include instructions for releasing the original physical register (physical register management unit 832) based on the redefinition of a logical register rather than based on the completion of a previous instruction or the commit of the current instruction, in response to determining that a first physical register is eligible for early release (early release management unit 828) and that the current instruction and previous instructions are executed in the same iteration or consecutive iterations (window management unit 830). Content processing system 818 may also include instructions for instructing the original physical register to be early released, thereby facilitating speculative reclamation of physical registers and reducing the size of the corresponding physical register file (early release management unit 828 and physical register management unit 832).

[0122] The content processing system 818 may include instructions for creating and managing RAT entries (RAT management unit 822), ROB entries (ROB management unit 824), and scheduler entries (scheduler management unit 826), as described above. Figure 3 , Figure 5 , Figure 6 and Figures 7A to 7E As described, the content processing system 818 may also include instructions for writing data to / from the payload RAM and physical register file (data writing unit 834).

[0123] Data 836 may include any data required as input or generated as output by the methods and / or processes described in this disclosure. Specifically, data 836 may store at least: data; instructions; operand values; RAT; RAT entries; logical registers or logical register IDs; physical registers or physical register IDs; pending indicators; ROB IDs; window IDs; reserved bits; ROBs; busy bits; status bits; previous physical registers mapped to logical registers; free bits; scheduler data structures; scheduler entries; busy indicators; opcodes or information; ready bits; destination indicators; destination ROB IDs; ROB IDs of source operands or corresponding to previous instructions; entries obtained based on associative lookups; entries in RAM designated for storing payload data; entries obtained based on direct indexes of the payload RAM; indications of completion of instruction execution phases, including "define," "redefine," "complete execution," and "commit"; indications of current, previous, or subsequent loops, iterations, loop iterations, or windows; and misjudgment indicators and corresponding branches.

[0124] Generally, the disclosed aspects provide a method, computer system, and non-transitory computer-readable storage medium for facilitating speculative register reclamation. In one aspect, the system determines an original instruction associated with a first logical register mapped to a first physical register, wherein the first physical register is initially marked as eligible for early release. The system determines a current instruction associated with a current logical register and one or more operands having corresponding values ​​produced by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register. The system allocates the current logical register to a third physical register. In response to determining that the current instruction and previous instructions execute in different iterations, the system marks the second physical register as not eligible for early release. In response to determining that the current logical register was previously mapped to a first physical register, the system determines that the allocation involves redefining the first logical register. In response to determining that the first physical register is eligible for early release and that the current instruction and the original instruction execute in the same iteration or consecutive iterations, the system releases the first physical register based on the redefinition of the first logical register rather than on the completion of execution of previous instructions or on the commit of the current instruction. The system instructs the first physical register to be released early, thereby facilitating speculative reclamation of physical registers and reducing the size of the corresponding physical register file.

[0125] In a variation of this, the first entry in the Register Alias ​​Table (RAT) for the original instruction includes: the allocation from the first logical register to the first physical register; a first ROB ID; a first window ID for the associated loop iteration; and a reserved bit set to indicate that the first PR is eligible for early release. The second entry in the RAT for the previous instruction includes: the allocation from the second logical register to the second physical register; a second ROB ID; a second window ID for the associated loop iteration; and a reserved bit set to indicate that the second physical register is eligible for early release. The system creates a third entry in the RAT for the current instruction, wherein the third entry includes: the allocation from the current logical register to the third physical register; a third ROB ID; a third window ID for the associated loop iteration; and a reserved bit set to indicate that the third physical register is eligible for early release. The system creates a Reorder Buffer (ROB) entry for the current instruction, wherein the ROB entry includes: the third physical register as the corresponding physical register of the current instruction; the first physical register as a previously mapped physical register; and a free bit set to indicate that the third physical register has not been early released. The system creates a scheduler entry for the current instruction based on the third RAT entry and ROB entry of the current instruction. The scheduler entry includes: the destination ROB ID; and the ROB ID corresponding to the previous instruction.

[0126] In another variation of this aspect, the system determines that the current instruction was not executed in the same iteration as the previous instruction. This includes determining that the third window ID of the current instruction does not match the second window ID of the previous instruction. Marking the second physical register as ineligible for early release includes setting a reserved bit in the second RAT entry of the previous instruction to indicate that the second physical register is ineligible for early release.

[0127] In another variation, the system determines that the first physical register is eligible for early release. This includes determining that the reserved bits in the first RAT entry indicate that the first physical register is eligible for early release. The system determines that the original instruction and the current instruction were executed in the same iteration or consecutive iterations. This includes determining that the first window ID of the original instruction matches or differs by one from the third window ID of the current instruction. Releasing the first physical register based on the redefinition of the first logical register rather than on the completion of the previous instruction or on the commit of the current instruction includes early release. The system sets a free bit in the ROB entry of the original instruction to indicate that the first physical register has been early released. The system sets a null value in the ROB entry of the current instruction for previously mapped physical registers.

[0128] In another variation, setting the idle bit in the ROB entry of the original instruction is based on the state of the pending bit of the original instruction.

[0129] In another variation, the size of the corresponding window, identified by the corresponding window ID corresponding to the corresponding loop iteration, is based on at least one of the following: the number of instructions in the corresponding loop iteration; a predetermined lower limit of the number of instructions corresponding to the size of the corresponding window; and a predetermined upper limit of the number of instructions corresponding to the size of the corresponding window.

[0130] In another variant, in response to determining that the first physical register has been released, the system writes the result of the current instruction to the random access memory (RAM) designated for storing payload data; and the system avoids writing the result to the physical register file.

[0131] In another variation, in response to the completion of the current instruction, the system broadcasts the third ROB ID of the current instruction. The system matches the third ROB ID with the ROB ID of the operand of the current instruction based on an association lookup of the obtained entry in the scheduler data structure. The system sets the ready bit of the result entry in the scheduler data structure. Without additional broadcasting, the system directly indexes the entry in the payload RAM based on the obtained entry, where the indexed entry in the payload RAM will receive data from the execution unit on the corresponding write port.

[0132] In another variation, the execution unit receives a value associated with a first operand of the current instruction from the payload RAM, and further receives a value associated with a second operand of the current instruction via a bypass bus.

[0133] In another variation, the system commits the current instruction in response to determining that all instructions in the current iteration and previous iterations have been executed, where the corresponding iteration corresponds to the corresponding instruction window. In response to determining that a branch in the current window is a misjudgment, the system rolls back to the beginning of the previous window, thus facilitating correct recovery from a misjudgment.

[0134] In another variation, in response to detecting a first condition, including a MPKI counter below a first predetermined threshold and a branch misprediction rate above a second predetermined threshold, the system switches from Speculative Register Reclamation (SRR) mode to normal mode, wherein all issued instructions set a reserved bit in their corresponding RAT entries to indicate that the corresponding physical register is not eligible for early release, and wherein the counter tracking the number of incomplete instructions for each window is not updated. In response to detecting that the first condition no longer exists, the system switches from normal mode to SRR mode, wherein all issued instructions set a reserved bit in their corresponding RAT entries to indicate that the corresponding physical register is eligible for early release, and wherein the counter tracking the number of incomplete instructions for each window is updated.

[0135] On the other hand, a non-transitory computer-readable storage medium stores instructions that, when executed by a computer, cause the computer to perform the above-described method, including instructions regarding... Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figures 7A to 7E The method may further include the following operations: switching from Speculative Register Reclamation (SRR) mode to normal mode based on the MPKI counter decreasing to below a first predetermined threshold and the branch misprediction rate decreasing to above a second predetermined threshold, wherein in normal mode, all allocated physical registers are initially marked as ineligible for early release; and switching from normal mode to SRR mode based on the MPKI counter no longer decreasing to below the first predetermined threshold and the branch misprediction rate no longer decreasing to above the second predetermined threshold, wherein in SRR mode, all allocated physical registers are initially marked as ineligible for early release.

[0136] In another aspect, a computer system includes a processor and a storage device, the storage device storing instructions that, when executed by the processor, cause the processor to perform the methods described above, including regarding... Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figures 7A to 7EThe method may further include the following operations: determining a current instruction associated with a logical register and one or more operands having corresponding values ​​produced by one or more previous instructions; allocating the logical register to a first physical register, wherein the first physical register was initially marked as eligible for early release, and wherein the logical register was previously mapped to an original physical register; determining that the first physical register is eligible for early release; determining that the current instruction and the previous instructions are executed in the same iteration or consecutive iterations; and releasing the original physical register based on a redefinition of the logical register, thereby facilitating a reduction in the size of the corresponding physical register file.

[0137] The foregoing description is presented to enable any person skilled in the art to make and use the aspects and examples, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects and applications without departing from the spirit and scope of this disclosure. Therefore, the aspects described herein are not limited to those shown, but are intended to be consistent with the maximum scope of the principles and features disclosed herein.

[0138] Furthermore, the foregoing descriptions of the various aspects have been presented solely for illustrative and descriptive purposes. These descriptions are not intended to be exhaustive or to limit the aspects described herein to the disclosed forms. Accordingly, many modifications and variations will be apparent to those skilled in the art. Additionally, the foregoing disclosure is not intended to limit the aspects described herein. The scope of the aspects described herein is defined by the appended claims.

Claims

1. A method comprising: Determine the original instruction associated with the first logical register mapped to the first physical register, wherein the first physical register was initially marked as eligible for early release; Determine the current instruction associated with the current logical register and one or more operands having corresponding values ​​produced by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register; Assign the current logical register to the third physical register; In response to determining that the current instruction and the previous instruction were executed in different iterations, the second physical register is marked as ineligible for early release; In response to determining that the current logical register was previously mapped to the first physical register, it is determined that the allocation includes a redefinition of the first logical register; In response to determining that the first physical register is eligible for early release and that the current instruction and the original instruction are executed in the same iteration or consecutive iterations, the first physical register is released based on a redefinition of the first logical register, regardless of whether the previous instruction has completed execution or whether the current instruction has been committed; and This instructs the first physical register to be released early, thereby promoting speculative reclamation of physical registers and reducing the size of the corresponding physical register file.

2. The method as described in claim 1, in, The first entry in the Register Alias ​​Table (RAT) for the original instruction includes: the allocation from the first logical register to the first physical register; the first reorder buffer (ROB) identifier ID; the first window ID for the associated loop iteration; and a reserved bit configured to indicate that the first physical register is eligible for early release; and The second entry in the RAT for the preceding instruction includes: the allocation from the second logical register to the second physical register; a second ROB ID; a second window ID for the associated loop iteration; and a reserved bit configured to indicate that the second physical register is eligible for early release. Furthermore, the method further includes: A third entry is created in the RAT for the current instruction, wherein the third entry includes: the allocation from the current logical register to the third physical register; a third ROB ID; a third window ID for the associated loop iteration; and a reserved bit set to indicate that the third physical register is eligible for early release; A ROB entry is created for the current instruction, wherein the ROB entry includes: the third physical register as the corresponding physical register of the current instruction; the first physical register as a previously mapped physical register; and a free bit, the free bit being set to indicate that the third physical register has not been prematurely freed; and Based on the ROB entry and the third RAT entry of the current instruction, a scheduler entry is created for the current instruction, wherein the scheduler entry includes: the destination ROB ID; and the ROB ID corresponding to the previous instruction.

3. The method of claim 2, further comprising: Determining that the current instruction was not executed in the same iteration as the previous instruction includes determining that the third window ID of the current instruction does not match the second window ID of the previous instruction. Marking the second physical register as ineligible for early release includes setting a reserved bit in the second RAT entry of the previous instruction to indicate that the second physical register is ineligible for early release.

4. The method of claim 3, further comprising: Determining that the first physical register is eligible for early release includes determining that the reserved bits of the first RAT entry indicate that the first physical register is eligible for early release; Determining that the original instruction and the current instruction are executed in the same iteration or consecutive iterations includes determining that the first window ID of the original instruction matches or differs by one from the third window ID of the current instruction. Among them, releasing the first physical register based on the redefinition of the first logical register rather than based on the completion of the previous instruction or the submission of the current instruction includes early release; Set a free bit in the ROB entry of the original instruction to indicate that the first physical register has been released prematurely; and Set a null value for the previously mapped physical register in the ROB entry of the current instruction.

5. The method as described in claim 4, in, Setting the idle bit in the ROB entry of the original instruction is based on the state of the suspended bit of the original instruction.

6. The method as described in claim 2, in, The size of the corresponding window, identified by the corresponding window ID corresponding to the corresponding loop iteration, is based on at least one of the following: The number of instructions in the corresponding loop iteration; A predetermined lower limit for the number of instructions corresponding to the corresponding window size; and A predetermined upper limit on the number of instructions corresponding to the corresponding window size.

7. The method of claim 2, further comprising: In response to determining that the first physical register has been released: Write the result of the current instruction to the designated random access memory (RAM) for storing payload data. as well as Avoid writing the results to the physical register file.

8. The method of claim 7, further comprising: Upon completion of the current instruction, broadcast the third ROB ID of the current instruction; Based on the association lookup of the obtained entries in the scheduler data structure, the third ROB ID is matched with the ROB ID of the operand of the current instruction; Set the ready bit of the obtained entry in the scheduler data structure; as well as Without additional broadcasting, entries are directly indexed in the payload RAM based on the obtained entries, wherein the indexed entries in the payload RAM will receive data from the execution unit on the corresponding write port.

9. The method as described in claim 8, in, The execution unit receives a value associated with a first operand of the current instruction from the payload RAM, and further receives a value associated with a second operand of the current instruction via a bypass bus.

10. The method of claim 1, further comprising: The current instruction is submitted in response to determining that all instructions in the current iteration and previous iterations have been completed, wherein the corresponding iteration corresponds to the corresponding instruction window; and In response to determining that the branch in the current window is a misjudgment, roll back to the beginning of the previous window. This facilitates the correct recovery from erroneous assumptions.

11. The method of claim 2, further comprising: In response to the detection of a first condition including the MPKI counter for each thousand instruction misses being lower than a first predetermined threshold and the branch misprediction rate being higher than a second predetermined threshold: Switch from speculative register reclamation SRR mode to normal mode. In this process, all issued instructions set a reserved bit in the corresponding RAT entry to indicate that the corresponding physical register is not eligible for early release, and This includes not updating the counter that tracks the number of incomplete instructions for each window; and In response to the detection that the first condition no longer exists: Switch from the normal mode to the SRR mode. Specifically, all issued instructions set the reserved bit in the corresponding RAT entry to indicate that the corresponding physical register is eligible for early release, and This includes updating a counter that tracks the number of incomplete instructions for each window.

12. A non-transitory computer-readable storage medium storing instructions, said instructions causing the computer to perform a method when executed by the computer, said method comprising: Determine the original instruction associated with the first logical register mapped to the first physical register, wherein the first physical register was initially marked as eligible for early release; Determine the current instruction associated with the current logical register and one or more operands having corresponding values ​​produced by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register; Assign the current logical register to the third physical register; In response to determining that the current instruction and the previous instruction were executed in different iterations, the second physical register is marked as ineligible for early release; In response to determining that the current logical register was previously mapped to the first physical register, it is determined that the allocation includes a redefinition of the first logical register; In response to determining that the first physical register is eligible for early release and that the current instruction and the original instruction are executed in the same iteration or consecutive iterations, the first physical register is released based on a redefinition of the first logical register, regardless of whether the previous instruction has completed execution or whether the current instruction has been committed; and This instructs the first physical register to be released early, thereby promoting speculative reclamation of physical registers and reducing the size of the corresponding physical register file.

13. The non-transitory computer-readable storage medium of claim 12, wherein, The method further include: The first entry in the Register Alias ​​Table (RAT) for the original instruction includes: the allocation from the first logical register to the first physical register; the first reorder buffer (ROB) identifier ID; the first window ID for the associated loop iteration; and a reserved bit configured to indicate that the first physical register is eligible for early release. The second entry in the RAT for the preceding instruction includes: the allocation from the second logical register to the second physical register; a second ROB ID; a second window ID for the associated loop iteration; and a reserved bit configured to indicate that the second physical register is eligible for early release. Furthermore, the method further includes: A third entry is created in the RAT for the current instruction, wherein the third entry includes: the allocation from the current logical register to the third physical register; a third ROB ID; a third window ID for the associated loop iteration; and a reserved bit set to indicate that the third physical register is eligible for early release; A ROB entry is created for the current instruction, wherein the ROB entry includes: the third physical register as the corresponding physical register of the current instruction; the first physical register as a previously mapped physical register; and a free bit, the free bit being set to indicate that the third physical register has not been prematurely freed; and Based on the ROB entry and the third RAT entry of the current instruction, a scheduler entry is created for the current instruction, wherein the scheduler entry includes: the destination ROB ID; and the ROB ID corresponding to the previous instruction.

14. The non-transitory computer-readable storage medium of claim 13, wherein, The method further includes: Determining that the current instruction was not executed in the same iteration as the previous instruction includes determining that the third window ID of the current instruction does not match the second window ID of the previous instruction. Marking the second physical register as ineligible for early release includes setting a reserved bit in the second RAT entry of the previous instruction to indicate that the second physical register is ineligible for early release.

15. The non-transitory computer-readable storage medium of claim 14, wherein, The method further includes: Determining that the first physical register is eligible for early release includes determining that the reserved bits of the first RAT entry indicate that the first physical register is eligible for early release; Determining that the original instruction and the current instruction are executed in the same iteration or consecutive iterations includes determining that the first window ID of the original instruction matches or differs by one from the third window ID of the current instruction. Among them, releasing the first physical register based on the redefinition of the first logical register rather than based on the completion of the previous instruction or the submission of the current instruction includes early release; Set a free bit in the ROB entry of the original instruction to indicate that the first physical register has been released prematurely; and Set a null value for the previously mapped physical register in the ROB entry of the current instruction.

16. The non-transitory computer-readable storage medium of claim 13, wherein, The method further includes: In response to determining that the first physical register has been released: Write the result of the current instruction to the designated random access memory (RAM) for storing payload data; and Avoid writing the results to the physical register file; Upon completion of the current instruction, broadcast the third ROB ID of the current instruction; Based on the association lookup of the obtained entries in the scheduler data structure, the third ROB ID is matched with the ROB ID of the operand of the current instruction; Set the ready bit of the obtained entry in the scheduler data structure; and Without additional broadcasting, entries are directly indexed in the payload RAM based on the obtained entries, wherein the indexed entries in the payload RAM will receive data from the execution unit on the corresponding write port.

17. The non-transitory computer-readable storage medium of claim 12, wherein, The method further includes: The current instruction is submitted in response to determining that all instructions in the current iteration and previous iterations have been completed, wherein the corresponding iteration corresponds to the corresponding instruction window; and In response to determining that the branch in the current window is a misjudgment, roll back to the beginning of the previous window. This facilitates the correct recovery from erroneous assumptions.

18. The non-transitory computer-readable storage medium of claim 12, wherein, The method further includes: Based on the MPKI counter for each thousand instruction misses decreasing below a first predetermined threshold and the branch misprediction rate decreasing above a second predetermined threshold, the system switches from speculative register reclamation SRR mode to normal mode. In the normal mode, all allocated physical registers are initially marked as ineligible for early release; and Based on the fact that the MPKI counter no longer drops below the first predetermined threshold and the branch misprediction rate no longer drops above the second predetermined threshold, the system switches from the normal mode to the SRR mode. In the SRR mode, all allocated physical registers are initially marked as eligible for early release.

19. A computer system comprising: processor; as well as A storage device storing instructions, which, when executed by the processor, cause the processor to perform a method, the method comprising: Determine the original instruction associated with the first logical register mapped to the first physical register, wherein the first physical register was initially marked as eligible for early release; Determine the current instruction associated with the current logical register and one or more operands having corresponding values ​​produced by one or more previous instructions, wherein the previous instructions are associated with a second logical register mapped to a second physical register; The current logical register is assigned to the third physical register, wherein the current logical register was previously mapped to the first physical register; It is determined that the first physical register is eligible for early release; Determine that the current instruction and the original instruction are executed in the same iteration or in consecutive iterations; and The first physical register is released by redefining the first logical register, regardless of whether the previous instruction has been executed or the current instruction has been committed, thereby facilitating a reduction in the size of the corresponding physical register file.

20. The computer system of claim 19, wherein, The method further includes: In response to determining that the current logical register was previously mapped to the first physical register, it is determined that the allocation includes a redefinition of the first logical register; In response to determining that the current instruction and the previous instruction were executed in different iterations, the second physical register is marked as ineligible for early release. Specifically, releasing the first physical register when redefining the first logical register is performed in response to determining that the first physical register is eligible for early release and that the current instruction and the original instruction are executed in the same iteration or consecutive iterations. Wherein, releasing the first physical register is not based on the completion of the previous instruction or the commit of the current instruction; and This indicates that the first physical register is released early, thereby promoting speculative reclamation of physical registers and reducing the size of the corresponding physical register file.

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