Common voltage compensation circuit, display substrate, display device and compensation method

Abstract

The present application provides a common voltage compensation circuit, a display substrate, a display device, and a compensation method. An output signal corresponding to a preset parasitic pole and a current parasitic frequency are transmitted to a second regulating subcircuit through a first regulating subcircuit. Since the voltage signal output by the first regulating subcircuit under the influence of the current parasitic frequency of the parasitic pole will produce large fluctuations, thereby affecting the image quality of the display device, the current parasitic frequency is adjusted to a target parasitic frequency so that the frequency of the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulating subcircuit. The parasitic pole is then offset using a cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first regulating subcircuit to amplify the input voltage signal without interference from the parasitic pole, thereby obtaining a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a common voltage compensation circuit, a display substrate, a display device, and a compensation method. Background Art

[0002] With the continuous advancement of information technology, display devices have become one of the indispensable devices. Various digital devices used in daily life require corresponding display devices to transmit and present digital information. However, display devices are often prone to flickering and poor grayscale display, which cannot guarantee the quality of the image. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a common voltage compensation circuit, a display substrate, a display device and a compensation method to solve or partially solve the above technical problems.

[0004] Based on the above purpose, a first aspect of the present application provides a common voltage compensation circuit, including a first regulating subcircuit and a second regulating subcircuit;

[0005] The first regulating subcircuit is configured to: receive an input voltage signal transmitted by the second regulating subcircuit, output an output signal corresponding to a preset parasitic pole based on the input voltage signal, determine a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmit the output signal and the current parasitic frequency to the second regulating subcircuit;

[0006] The second regulation subcircuit is configured to: determine a target parasitic frequency corresponding to the parasitic pole, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole, so that the first regulation subcircuit can amplify the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

[0007] Based on the same inventive concept, the second aspect of the present application proposes a display substrate, comprising the common voltage compensation circuit as described in the first aspect.

[0008] Based on the same inventive concept, the third aspect of the present application proposes a display device, comprising the display substrate as described in the second aspect.

[0009] Based on the same inventive concept, a fourth aspect of the present application proposes a common voltage compensation method, which is applied to the common voltage compensation circuit described in the first aspect. The method includes:

[0010] receiving, by the first regulating subcircuit, an input voltage signal transmitted by the second regulating subcircuit, outputting an output signal corresponding to a preset parasitic pole based on the input voltage signal, determining a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmitting the output signal and the current parasitic frequency to the second regulating subcircuit;

[0011] The target parasitic frequency corresponding to the parasitic pole is determined by the second regulation subcircuit, the current parasitic frequency is adjusted to the target parasitic frequency, and the parasitic pole is canceled using a cancellation signal generated by the output signal at the target parasitic frequency, so that the first regulation subcircuit amplifies the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

[0012] As can be seen from the above description, the common voltage compensation circuit, display substrate, display device, and compensation method provided by the present application transmit the output signal corresponding to the preset parasitic pole and the current parasitic frequency to the second regulation subcircuit through the first regulation subcircuit. Since the voltage signal output by the first regulation subcircuit will produce large fluctuations under the influence of the current parasitic frequency of the parasitic pole, thereby affecting the image quality of the display device, the current parasitic frequency is adjusted to the target parasitic frequency so that the frequency corresponding to the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulation subcircuit. The parasitic pole is then offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first regulation subcircuit to amplify the input voltage signal without interference from the parasitic pole, thereby obtaining a stable output amplified voltage signal, avoiding flickering and poor grayscale flickering, thereby ensuring the image quality of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1A This is a first schematic diagram of a common voltage compensation circuit according to an embodiment of the present application;

[0015] Figure 1B This is a first schematic diagram of waveforms of a common voltage compensation circuit according to an embodiment of the present application;

[0016] Figure 1C A second schematic diagram of waveforms of the common voltage compensation circuit according to an embodiment of the present application;

[0017] Figure 1D A third schematic diagram of waveforms of the common voltage compensation circuit according to an embodiment of the present application;

[0018] Figure 1E This is a structural block diagram of a common voltage compensation circuit according to an embodiment of the present application;

[0019] Figure 1F This is a second schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0020] Figure 1G A third schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0021] Figure 1H A fourth schematic diagram of waveforms of the common voltage compensation circuit according to an embodiment of the present application;

[0022] Figure 1I This is a fourth schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0023] Figure 1J This is a fifth schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0024] Figure 1K A fifth schematic diagram of waveforms of the common voltage compensation circuit according to an embodiment of the present application;

[0025] Figure 1L This is a sixth schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0026] Figure 1M This is a seventh schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0027] Figure 1N A sixth schematic diagram of waveforms of the common voltage compensation circuit according to an embodiment of the present application;

[0028] Figure 1O This is an eighth schematic diagram of the common voltage compensation circuit according to an embodiment of the present application;

[0029] Figure 2 This is a flowchart of common voltage compensation according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0031] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] It is understandable that before using the technical solutions of each embodiment of this application, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.

[0033] For example, in response to receiving a user's active request, a prompt message is sent to the user to clearly inform the user that the operation requested will require the acquisition and use of the user's personal information. Thus, the user can independently choose whether to provide personal information to the electronic device, application, server, storage medium, or other software or hardware that performs the operation of the technical solution of this application based on the prompt message.

[0034] As an optional but non-limiting implementation, in response to a user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. Furthermore, the pop-up window may also contain a selection control for the user to select "agree" or "disagree" to provide personal information to the electronic device.

[0035] It is understandable that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this application. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this application.

[0036] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] With the rapid development of the monitor (MNT) display market, the development and design of high-end display products has become an inevitable trend, and high-resolution / high refresh rate products have gradually become the mainstream market. Operational amplifiers are suitable for use in display devices because of their high input impedance, low output impedance, and ability to implement various circuit functions through circuit design.

[0038] The inventors of the present application discovered that the cause of flicker and poor grayscale display problems in display devices lies in the operational amplifier. Specifically, because the main pole of the operational amplifier is inside the operational amplifier chip, there is a parasitic pole at the inverting input and output of the operational amplifier. This parasitic pole affects the output of the operational amplifier and causes the output voltage signal (Vcomout) of the operational amplifier to become unstable, thereby causing the image quality of the display device to flicker and poor grayscale display problems.

[0039] Furthermore, operational amplifiers are manufactured using either a single-chip integration (Bipolar-CMOS-DMOS, BCD) process or a bipolar junction transistor (BJT) process. The single-chip integration process offers larger input resistance Rs and output resistance Ro. This results in lower input leakage current, greater open-loop gain, common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), and other characteristics, resulting in relatively better DC specifications (indicators used to measure DC voltage quality). However, due to the larger input resistance Rs and output resistance Ro of the single-chip integration process, the frequency of the parasitic pole is lower than that of the bipolar junction transistor process. As the load capacitance Cl is gradually increased, the parasitic pole frequency at the output of the single-chip integration operational amplifier decreases more rapidly, making the output voltage of the operational amplifier more susceptible to instability. When the corresponding parasitic capacitance of the operational amplifier is large, this can easily lead to unstable output voltage.

[0040] Display products use the voltage signal output by the operational amplifier for compensation, such as Figure 1A As shown, IC301 is a VOCM Buffer chip (i.e., an operational amplifier).

[0041] Among them, VCOMOUT_L1, VCOMOUT_L2, VCOMOUT_L3 and VCOMOUT_L4 all represent output voltage signals.

[0042] The output voltage signal VCOMOUT_L1 is used for far compensation; the output voltage signal VCOMOUT_L2 is used for middle compensation; the output voltage signals VCOMOUT_L3 and VCOMOUT_L4 are used for near compensation.

[0043] like Figure 1B As shown in the figure, the yellow, blue and purple channels are the voltage signals output by the operational amplifier for far compensation, the voltage signals output by the operational amplifier for intermediate compensation and the voltage signals output by the operational amplifier for near compensation, and there are obvious ripples in each channel. Figure 1C As shown, the yellow, blue and purple channels are connected to the voltage signal, common mode voltage (Vcom) and negative feedback signal (FEED) output by the operational amplifier in sequence, from which it can be seen that there is abnormal ripple.

[0044] The screen load was replaced with an ideal capacitive load for experimental fitting. The other peripheral configurations remained unchanged, and the capacitive load was gradually increased until oscillation occurred. No oscillation occurred when the load capacitance was increased from 0 to 680pF. Oscillation occurred when the load capacitance was increased to about 800pF, and the frequency was similar. When the load capacitance was further increased to 1nF, the oscillation frequency dropped to 5MHz. Therefore, it was judged that the equivalent capacitance of the screen load output end was about 800pF. Experiments have shown that the equivalent capacitance of different screens is different. If the equivalent capacitance of the screen is large, such as 800pF in this project, it will induce OP oscillation under the current peripheral configuration, causing unstable Vcom output. Figure 1D As shown in the figure, the ripple of the output voltage signal (VCOMOUT) still has obvious fluctuations, and the ripple frequency is around 7.5MHz.

[0045] Figure 1E The common voltage compensation circuit of an embodiment of the present application includes a first regulating subcircuit 110 and a second regulating subcircuit 120;

[0046] The first regulating subcircuit 110 is configured to: receive an input voltage signal transmitted by the second regulating subcircuit 120, output an output signal corresponding to a preset parasitic pole based on the input voltage signal, determine a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmit the output signal and the current parasitic frequency to the second regulating subcircuit 120;

[0047] The second regulating subcircuit 120 is configured to: determine a target parasitic frequency corresponding to the parasitic pole, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole, so that the first regulating subcircuit 110 can amplify the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

[0048] During specific implementation, due to the existence of the parasitic pole, the first regulating subcircuit 110 generates an interference signal at a preset parasitic pole based on the input voltage signal, generates an interference signal with a phase opposite to the interference signal according to the interference signal, and determines the current parasitic frequency corresponding to the parasitic pole under the input voltage signal.

[0049] Because the first regulating subcircuit 110 is affected by the current parasitic frequency of the parasitic pole, the voltage signal output by the first regulating subcircuit 110 may fluctuate significantly. Using an unstable output voltage signal may cause flickering and poor grayscale display on the display device. Therefore, the present application utilizes the second regulating subcircuit 120 to regulate the frequency of the parasitic pole to offset the influence of the parasitic pole. The specific method for regulating the frequency of the parasitic pole and offsetting the influence of the parasitic pole is as follows:

[0050] The target parasitic frequency corresponding to the parasitic pole is determined by the second adjustment subcircuit 120, and the current parasitic frequency is adjusted to the target parasitic frequency. The first adjustment subcircuit 110 will output a voltage signal with relatively large fluctuations at the current parasitic frequency. Therefore, by adjusting the current parasitic frequency to the target parasitic frequency, the frequency corresponding to the parasitic pole is kept away from the current parasitic frequency that can cause the voltage signal output by the first adjustment subcircuit 110 to have relatively large fluctuations.

[0051] In addition, the second regulating sub-circuit 120 generates a cancellation signal at the target parasitic frequency based on the interference signal (i.e., the output signal corresponding to the preset parasitic pole) with a phase opposite to that of the interference signal. Since the cancellation signal is in phase with the interference signal, the interference signal at the parasitic pole can be cancelled using the cancellation signal, thereby canceling the influence of the parasitic pole and generating a cancellation processing signal, wherein the cancellation processing signal is used to indicate the progress of the cancellation processing of the interference signal at the parasitic pole, so that the first regulating sub-circuit 110 can amplify the input voltage signal based on the cancellation processing signal in the absence of interference from the parasitic pole, and output a stable amplified voltage signal, thereby solving the problems of flickering and grayscale line flashing, and improving the picture quality.

[0052] Through the above scheme, the output signal corresponding to the preset parasitic pole and the current parasitic frequency are transmitted to the second regulating subcircuit 120 via the first regulating subcircuit 110. Since the voltage signal output by the first regulating subcircuit 110 will produce large fluctuations under the influence of the current parasitic frequency of the parasitic pole, thereby affecting the image quality of the display device, the current parasitic frequency is adjusted to the target parasitic frequency so that the frequency corresponding to the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulating subcircuit 110. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first regulating subcircuit 110 to amplify the input voltage signal without interference from the parasitic pole, thereby obtaining a stable output amplified voltage signal, avoiding flickering and poor grayscale flickering, thereby ensuring the image quality of the display device.

[0053] In some embodiments, as Figure 1F As shown, the first regulating subcircuit 110 includes: a parasitic capacitor 111 and an operational amplifier 112;

[0054] The parasitic capacitor 111 is connected to the second regulating sub-circuit 120 and the inverting input terminal of the operational amplifier 112 respectively;

[0055] The inverting input terminal of the operational amplifier 112 is connected to the parasitic capacitor 111 and the second regulating subcircuit 120 respectively, the output terminal of the operational amplifier 112 is connected to the second regulating subcircuit 120, and the non-inverting input terminal of the operational amplifier 112 is grounded.

[0056] In specific implementation, the parasitic capacitor 111 is used to receive the input voltage signal transmitted by the second regulating subcircuit, an initial interference signal is generated at a preset parasitic pole based on the input voltage signal, and the initial interference signal is filtered to obtain an interference signal.

[0057] The interference signal transmitted by the parasitic capacitor 111 is received by the operational amplifier 112, the interference signal is amplified to generate an interference signal with a phase opposite to the interference signal, and the current parasitic frequency corresponding to the parasitic pole under the input voltage signal is determined, and the interference signal, the interference signal with a phase opposite to the interference signal, and the current parasitic frequency are transmitted to the second regulation sub-circuit 120, and the cancellation processing signal transmitted by the second regulation sub-circuit 120 is received, and the input voltage signal is amplified based on the cancellation processing signal to obtain a stable amplified voltage signal, which can solve the problems of flickering and grayscale line flashing and improve image quality.

[0058] In some embodiments, as Figure 1F As shown, the operational amplifier 112 includes: an equivalent input resistor 1121 and an equivalent output resistor 1122;

[0059] The equivalent input resistor 1121 is connected to the parasitic capacitor 111 and the second regulating sub-circuit 120 respectively;

[0060] The equivalent output resistor 1122 is connected to the second regulating sub-circuit 120 .

[0061] In specific implementation, the current input to the operational amplifier through the inverting input terminal of the operational amplifier is adjusted to zero through the equivalent output resistor 1121; the interference signal transmitted by the parasitic capacitor 111 is received; and the cancellation processing signal transmitted by the second adjustment sub-circuit 120 is received.

[0062] The interference signal is amplified by using the equivalent output resistor 1122 to generate an interference signal with a phase opposite to the interference signal; the current parasitic frequency corresponding to the parasitic pole under the input voltage signal is determined, and the interference signal with a phase opposite to the interference signal and the current parasitic frequency are transmitted to the second adjustment sub-circuit 120; and the input voltage signal is amplified based on the offset processing signal to obtain a stable amplified voltage signal, thereby solving the problems of flickering and grayscale line flashing and improving image quality.

[0063] In some embodiments, as Figure 1F As shown, the second regulating subcircuit 120 includes: a load capacitor 122 and a negative feedback unit 121;

[0064] The load capacitor 122 is connected to the first regulating sub-circuit 110 and the negative feedback unit 121 respectively;

[0065] The negative feedback unit 121 is connected to the first regulation sub-circuit 110 and the load capacitor 122, respectively, and is configured to: determine a target parasitic frequency corresponding to the parasitic pole, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole.

[0066] During specific implementation, the interference signal, the interference signal with a phase opposite to that of the interference signal, and the current parasitic frequency are received through the load capacitor 122 .

[0067] The negative feedback unit 121 is used to determine the target parasitic frequency corresponding to the parasitic pole, the current parasitic frequency is adjusted to the target parasitic frequency, and the target phase corresponding to the target parasitic frequency is determined. The interference signal having a phase opposite to that of the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled by the cancellation signal to generate a cancellation processing signal. The cancellation processing signal is transmitted to the first adjustment sub-circuit 110 so that 110 can amplify the input voltage signal based on the cancellation processing signal in the absence of parasitic pole interference to obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0068] In some embodiments, as Figure 1F As shown, the negative feedback unit 121 includes: a first feedback resistor 1211, a second feedback resistor 1212 and a feedback capacitor 1213;

[0069] The first feedback resistor 1211 is connected in series with the second feedback resistor 1212 and the feedback capacitor 1213 connected in parallel, and is connected to the first regulating sub-circuit 110;

[0070] The second feedback resistor 1212 is connected in parallel with the feedback capacitor 1213 and is respectively connected to the first feedback resistor 1211 , the first regulating sub-circuit 110 and the load capacitor 122 ;

[0071] The feedback capacitor 1213 is connected in parallel with the second feedback resistor 1212 , and is respectively connected to the first feedback resistor 1211 , the first regulating sub-circuit 110 , and the load capacitor 122 .

[0072] In a specific implementation, the target parasitic frequency corresponding to the parasitic pole is determined by the first feedback resistor 1211 , and the current parasitic frequency is reduced to the target parasitic frequency.

[0073] The second feedback resistor 1212 is combined with the feedback capacitor 1213 to determine the target phase corresponding to the target parasitic frequency, and the interference signal with a phase opposite to the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled using the cancellation signal to generate a cancellation processing signal, and the cancellation signal is transmitted to the first adjustment sub-circuit 110.

[0074] The target phase corresponding to the target parasitic frequency is determined by the feedback capacitor 1213 in combination with the second feedback resistor 1212, and the interference signal with a phase opposite to that of the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled by the cancellation signal to generate a cancellation processing signal, and the cancellation signal is transmitted to the first adjustment sub-circuit 110.

[0075] In the present application, the current parasitic frequency is reduced to the target parasitic frequency through the second feedback resistor 1212 and the feedback capacitor 1213 connected in parallel, so that the frequency corresponding to the parasitic pole at the inverting input terminal of the operational amplifier is far away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first adjustment sub-circuit 110. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole, so that the first adjustment sub-circuit 110 can amplify the input voltage signal without interference from the parasitic pole, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0076] For example, taking one channel as an example, capacitors are connected in parallel at both ends of resistor R331. This is required for all channels. Figure 1G As shown, the resistors corresponding to the first feedback resistor 1211 in the common voltage compensation circuit of the present application include resistor R321, resistor R322, resistor R323 and resistor R324, the resistors corresponding to the second feedback resistor 1212 in the common voltage compensation circuit of the present application include resistor R331, resistor R332, resistor R333 and resistor R334, the capacitors corresponding to the parasitic capacitor 111 in the common voltage compensation circuit of the present application include capacitor C3111, capacitor C312, capacitor C313 and capacitor C314, the operational amplifier 112 of the common voltage compensation circuit of the present application corresponds to IC301, and a 22pF capacitor (i.e., feedback capacitor 1213) is connected in parallel at both ends of the resistors R331 to R334.

[0077] like Figure 1H As shown, the yellow, blue, and purple channels are connected in sequence to the output voltage signal (VCOMOUT), the common mode voltage (VCOM), and the negative feedback signal (FEED). The second feedback resistor 1212 and the parallel connected feedback capacitor 1213 can avoid the occurrence of large ripple.

[0078] In some embodiments, as Figure 1I As shown, the negative feedback unit 121 includes: a first feedback resistor 1211 and a second feedback resistor 1212;

[0079] The first feedback resistor 1211 is connected to the second feedback resistor 1212 and the first regulating sub-circuit 110 respectively;

[0080] The second feedback resistor 1212 is connected to the load capacitor 122 , the first regulating sub-circuit 110 , and the first feedback resistor 1211 , respectively.

[0081] During specific implementation, the target parasitic frequency corresponding to the parasitic pole is determined by the first feedback resistor 1211, the resistance of the first feedback resistor is reduced according to a preset ratio, and the current parasitic frequency is increased to the target parasitic frequency in combination with the second feedback resistor whose resistance is reduced in proportion, and the target phase corresponding to the target parasitic frequency is determined. The interference signal with a phase opposite to that of the interference signal is adjusted according to the target phase to obtain a cancellation signal, and the interference signal is canceled by using the cancellation signal to generate a cancellation processing signal, which is transmitted to the first adjustment sub-circuit 110.

[0082] The target parasitic frequency corresponding to the parasitic pole is determined using the second feedback resistor 1212, and the resistance of the second feedback resistor 1212 is reduced proportionally. The current parasitic frequency is increased to the target parasitic frequency in combination with the first feedback resistor 1211 whose resistance is reduced proportionally. The target phase corresponding to the target parasitic frequency is determined, and the interference signal having a phase opposite to that of the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled using the cancellation signal to generate a cancellation processing signal, and the cancellation signal is transmitted to the first adjustment sub-circuit 110.

[0083] In the present application, the resistance of the first feedback resistor 1211 and the resistance of the second feedback resistor 1212 are proportionally reduced according to a preset ratio, so that the frequency of the parasitic poles at the inverting input and output terminals of the operational amplifier 112 is increased, thereby moving away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulation subcircuit 110, thereby enhancing the stability of the voltage signal output by the first regulation subcircuit 110, thereby ensuring the image quality of the display device.

[0084] For example, taking a channel as an example, Figure 1J As shown, to reduce the resistance R321, in order to keep the gain unchanged, the resistance R331 also needs to be reduced synchronously and proportionally, and this is required for all channels.

[0085] The resistors corresponding to the second feedback resistor in the common voltage compensation circuit of the present application include resistors R331, R332, R333, and R334. The resistors corresponding to the first feedback resistor in the common voltage compensation circuit of the present application include resistors R321, R322, R323, and R324. The resistors corresponding to the second feedback resistor 1212 in the common voltage compensation circuit of the present application include resistors R331, R332, R333, and R334. The capacitors corresponding to the parasitic capacitor 111 in the common voltage compensation circuit of the present application include capacitors C3111, C312, C313, and C314. The operational amplifier 112 of the common voltage compensation circuit of the present application corresponds to IC301. The resistors R321 to R324 are adjusted to 100Ω, the gain is kept unchanged, and R331 to R334 are all adjusted to 1 / 10 of the original value. Figure 1K As shown, the yellow and purple channels are connected to the output voltage signal (VCOMOUT) and the negative feedback signal (FEED) in sequence. By proportionally reducing the resistance of the first feedback resistor 1211 and the resistance of the second feedback resistor 1212 according to a preset ratio, large ripple fluctuations can be avoided.

[0086] In some embodiments, as Figure 1L As shown, the second regulating subcircuit 120 includes: a load resistor 123, a load capacitor 122 and a negative feedback unit 121;

[0087] The load resistor 123 is connected in series with the load capacitor 122 and is connected to the negative feedback unit 121 and the first regulating sub-circuit 110 respectively;

[0088] The load capacitor 122 is connected in series with the load resistor 123;

[0089] The negative feedback unit 121 is connected to the first regulating sub-circuit 110 and the load resistor 123 respectively, and is configured to transmit the offset processing signal to the first regulating sub-circuit.

[0090] During specific implementation, the load resistor 123 is used to receive the interference signal, the interference signal with a phase opposite to the interference signal, and the current parasitic frequency, and the target parasitic frequency corresponding to the parasitic pole is determined. The current parasitic frequency is reduced to the target parasitic frequency in combination with the load capacitance, and the target parasitic frequency corresponding to the parasitic pole is determined. The target phase corresponding to the target parasitic frequency is determined, and the interference signal with a phase opposite to the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled by the cancellation signal to generate a cancellation processing signal, and the cancellation processing signal is transmitted to the negative feedback unit 121.

[0091] An interference signal, an interference signal with a phase opposite to that of the interference signal, and a current parasitic frequency are received through the load capacitor 122, and a target parasitic frequency corresponding to the parasitic pole is determined. The current parasitic frequency is reduced to the target parasitic frequency in combination with the load resistance, and the target parasitic frequency corresponding to the parasitic pole is determined. The target phase corresponding to the target parasitic frequency is determined, and the interference signal with a phase opposite to that of the interference signal is adjusted according to the target phase to obtain a cancellation signal. The interference signal is canceled using the cancellation signal to generate a cancellation processing signal.

[0092] The negative feedback unit 121 is used to transmit the offset processing signal to the first regulating sub-circuit 110, so that the first regulating sub-circuit 110 can amplify the input voltage signal without parasitic pole interference, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0093] The present application creates a zero point by connecting a load resistor 123 in series between the output end of the operational amplifier 112 and the load capacitor 122, thereby reducing the frequency of the parasitic pole at the output end of the operational amplifier 112, thereby moving away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulation subcircuit 110, thereby enhancing the stability of the voltage signal output by the first regulation subcircuit 110, thereby ensuring the image quality of the display device.

[0094] For example, taking a channel as an example, Figure 1M As shown, increase the 0Ω resistor R301, and all channels need to do so. The resistors corresponding to the first feedback resistor 1211 in the common voltage compensation circuit of the present application include resistors R321, R322, R323, and R324. The resistors corresponding to the second feedback resistor 1212 in the common voltage compensation circuit of the present application include resistors R331, R332, R333, and R334. The capacitors corresponding to the parasitic capacitor 111 in the common voltage compensation circuit of the present application include capacitors C3111, C312, C313, and C314. The operational amplifier 112 of the common voltage compensation circuit of the present application corresponds to IC301. The resistors corresponding to the load resistor 123 in the common voltage compensation circuit of the present application include resistors R301, R302, R303, and R304. Increase resistors R301 to R304 to 30Ω. As shown Figure 1N As shown, the yellow and purple channels are connected to the output voltage signal (VCOMOUT) and the negative feedback signal (FEED) in sequence. By connecting a load resistor 123 in series between the output terminal of the operational amplifier 112 and the load capacitor 122, large ripples can be avoided.

[0095] In some embodiments, as Figure 1L As shown, the negative feedback unit includes: a first feedback resistor 1211 and a second feedback resistor 1212;

[0096] The first feedback resistor 1211 is connected to the second feedback resistor 1212 and the first regulating sub-circuit 110 respectively;

[0097] The second feedback resistor 1212 is connected to the first feedback resistor 1211 , the load resistor 123 , and the first regulating sub-circuit 110 , respectively.

[0098] In specific implementation, the cancellation processing signal is transmitted to the first regulation sub-circuit 110 through the first feedback resistor 1211 in combination with the second feedback resistor 1212, and the cancellation processing signal is transmitted to the first regulation sub-circuit 110 using the second feedback resistor 1212 in combination with the first feedback resistor 1211, so that the first regulation sub-circuit 110 can amplify the input voltage signal without parasitic pole interference, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0099] Based on the same inventive concept, an embodiment of the present application proposes a display substrate, comprising the common voltage compensation circuit described in any of the above embodiments.

[0100] In a specific implementation, the display substrate includes a common voltage compensation circuit, which adjusts the current parasitic frequency to the target parasitic frequency so that the frequency corresponding to the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first adjustment sub-circuit. Then, the parasitic pole is offset using a cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole, so that the first adjustment sub-circuit can amplify the input voltage signal without interference from the parasitic pole, and obtain a stable output amplified voltage signal.

[0101] Based on the same inventive concept, an embodiment of the present application provides a display device, including the display substrate described in the above embodiment.

[0102] In a specific implementation, the display substrate includes a common voltage compensation circuit, which adjusts the current parasitic frequency to the target parasitic frequency so that the frequency corresponding to the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first adjustment sub-circuit. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first adjustment sub-circuit to amplify the input voltage signal without interference from the parasitic pole, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device including the display substrate.

[0103] Based on the same inventive concept, Figure 2 As shown, an embodiment of the present application proposes a common voltage compensation method, which is applied to the common voltage compensation circuit of any of the above embodiments. The method includes:

[0104] Step 201: Utilize a first regulating subcircuit to receive an input voltage signal transmitted by a second regulating subcircuit, output an output signal corresponding to a preset parasitic pole based on the input voltage signal, determine a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmit the output signal and the current parasitic frequency to the second regulating subcircuit;

[0105] Step 202: Determine a target parasitic frequency corresponding to the parasitic pole through the second adjustment subcircuit, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole, so that the first adjustment subcircuit can amplify the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

[0106] During specific implementation, due to the existence of the parasitic pole, the first regulating subcircuit 110 generates an interference signal at a preset parasitic pole based on the input voltage signal, generates an interference signal with a phase opposite to the interference signal according to the interference signal, and determines the current parasitic frequency corresponding to the parasitic pole under the input voltage signal.

[0107] Because the first regulating subcircuit 110 is affected by the current parasitic frequency of the parasitic pole, the voltage signal output by the first regulating subcircuit 110 may fluctuate significantly. Using an unstable output voltage signal may cause flickering and poor grayscale display on the display device. Therefore, the present application utilizes the second regulating subcircuit 120 to regulate the frequency of the parasitic pole to offset the influence of the parasitic pole. The specific method for regulating the frequency of the parasitic pole and offsetting the influence of the parasitic pole is as follows:

[0108] The target parasitic frequency corresponding to the parasitic pole is determined by the second adjustment subcircuit 120, and the current parasitic frequency is adjusted to the target parasitic frequency. The first adjustment subcircuit 110 will output a voltage signal with relatively large fluctuations at the current parasitic frequency. Therefore, by adjusting the current parasitic frequency to the target parasitic frequency, the frequency corresponding to the parasitic pole is kept away from the current parasitic frequency that can cause the voltage signal output by the first adjustment subcircuit 110 to have relatively large fluctuations.

[0109] In addition, the second regulating sub-circuit 120 generates a cancellation signal at the target parasitic frequency based on the interference signal (i.e., the output signal corresponding to the preset parasitic pole) with a phase opposite to that of the interference signal. Since the cancellation signal is in phase with the interference signal, the interference signal at the parasitic pole can be cancelled using the cancellation signal, thereby canceling the influence of the parasitic pole and generating a cancellation processing signal, wherein the cancellation processing signal is used to indicate the progress of the cancellation processing of the interference signal at the parasitic pole, so that the first regulating sub-circuit 110 can amplify the input voltage signal based on the cancellation processing signal in the absence of interference from the parasitic pole, and output a stable amplified voltage signal, thereby solving the problems of flickering and grayscale line flashing, and improving the picture quality.

[0110] In some embodiments, the second regulation subcircuit includes a second feedback resistor and a feedback capacitor connected in parallel.

[0111] In step 202, determining the target parasitic frequency corresponding to the parasitic pole includes:

[0112] Step A1: Obtain the resistance value of the second feedback resistor and the capacitance value of the feedback capacitor.

[0113] Step A2: performing product processing on the preset first parasitic frequency parameter, the resistance value of the second feedback resistor, and the capacitance value of the feedback capacitor to obtain a first product processing result.

[0114] Step A3: performing ratio processing on the first product processing result using a preset second parasitic frequency parameter to obtain a target parasitic frequency corresponding to the parasitic pole.

[0115] When implementing it specifically, Figure 1O As shown, the main pole is inside the operational amplifier chip. There is a parasitic pole at the inverting input of the operational amplifier chip, which affects the stability of the circuit. The current parasitic frequency of the parasitic pole at the inverting input can be expressed as follows:

[0116] fs=1 / 2π(Rs / / Rg)*Cs

[0117] Among them, fs represents the current parasitic frequency of the parasitic pole of the inverting input terminal, Rs represents the equivalent input resistance of the inverting input terminal of the operational amplifier, Rg represents the feedback resistor (i.e., the first feedback resistor), and Cs represents the parasitic capacitance of the inverting input terminal of the operational amplifier chip.

[0118] The target parasitic frequency of the parasitic pole at the inverting input of the op amp is expressed as follows:

[0119] fz1=1 / 2πRf*Cf

[0120] Wherein, fz1 represents the target parasitic frequency of the parasitic pole of the inverting input terminal of the operational amplifier, Rf represents the feedback resistor (ie, the second feedback resistor), and Cf represents the feedback capacitor.

[0121] By adjusting the current parasitic frequency to the target parasitic frequency, the frequency corresponding to the parasitic pole is kept away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first adjustment sub-circuit 110. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first adjustment sub-circuit 110 to amplify the input voltage signal without interference from the parasitic pole, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0122] In some embodiments, the second regulating subcircuit includes a load resistor and a load capacitor connected in series.

[0123] In step 202, determining the target parasitic frequency corresponding to the parasitic pole includes:

[0124] Step B1, obtaining the resistance value of the load resistor and the capacitance value of the load capacitor.

[0125] Step B2: performing product processing on the preset first parasitic frequency parameter, the resistance value of the load resistor, and the capacitance value of the load capacitor to obtain a second product processing result.

[0126] Step B3: performing ratio processing on the second product processing result using a preset second parasitic frequency parameter to obtain a target parasitic frequency corresponding to the parasitic pole.

[0127] When implementing it specifically, Figure 1O As shown, the main pole is inside the operational amplifier chip, and there is a parasitic pole at the output end of the operational amplifier chip that affects the stability of the circuit.

[0128] The current parasitic frequency of the parasitic pole at the output can be expressed as follows:

[0129] fo=1 / 2π(Ro / / Rf)*Cl

[0130] Among them, fo represents the current parasitic frequency of the parasitic pole at the output end, Ro represents the equivalent resistance of the output end of the operational amplifier chip, Rf represents the feedback resistor (i.e., the second feedback resistor), and Cl represents the load capacitance of the operational amplifier chip.

[0131] The target parasitic frequency of the parasitic pole at the output of the operational amplifier is expressed as follows:

[0132] fz2=1 / 2πRm*Cl

[0133] Wherein, fz2 represents the target parasitic frequency of the parasitic pole at the output of the operational amplifier, Em represents the load resistance, and Cl represents the load capacitance.

[0134] By adjusting the current parasitic frequency to the target parasitic frequency, the frequency corresponding to the parasitic pole is kept away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first adjustment sub-circuit 110. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first adjustment sub-circuit 110 to amplify the input voltage signal without interference from the parasitic pole, and obtain a stable output amplified voltage signal, thereby ensuring the image quality of the display device.

[0135] Through the above scheme, the output signal corresponding to the preset parasitic pole and the current parasitic frequency are transmitted to the second regulating subcircuit 120 via the first regulating subcircuit 110. Since the voltage signal output by the first regulating subcircuit 110 will produce large fluctuations under the influence of the current parasitic frequency of the parasitic pole, thereby affecting the image quality of the display device, the current parasitic frequency is adjusted to the target parasitic frequency so that the frequency corresponding to the parasitic pole is away from the current parasitic frequency that can cause large fluctuations in the voltage signal output by the first regulating subcircuit 110. Then, the parasitic pole is offset using the cancellation signal generated by the output signal at the target parasitic frequency, thereby offsetting the influence of the parasitic pole. This allows the first regulating subcircuit 110 to amplify the input voltage signal without interference from the parasitic pole, thereby obtaining a stable output amplified voltage signal, avoiding flickering and poor grayscale flickering, thereby ensuring the image quality of the display device.

[0136] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied in a distributed scenario and performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the method.

[0137] It should be noted that the above description is limited to some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0138] For simplicity of description and discussion, and in order not to make the embodiment of the application difficult to understand, the known power supply / ground connection with integrated circuit (IC) chip and other components may or may not be shown in the accompanying drawings provided. In addition, the device can be shown in the form of a block diagram to avoid making the embodiment of the application difficult to understand, and this also takes into account the following fact, that is, the details of the embodiment of these block diagram devices are highly dependent on the platform to be implemented in the embodiment of the application (that is, these details should be fully within the scope of understanding of those skilled in the art). When specific details (for example, circuit) are set forth to describe exemplary embodiments of the application, it will be apparent to those skilled in the art that the embodiment of the application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0139] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the embodiments discussed.

[0140] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the above embodiments or technical features in different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0141] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A common voltage compensation circuit, characterized in that: comprising a first regulating subcircuit and a second regulating subcircuit; The first regulating subcircuit includes: a parasitic capacitor and an operational amplifier; The parasitic capacitor is connected to the second regulating sub-circuit and the inverting input terminal of the operational amplifier respectively; The inverting input terminal of the operational amplifier is connected to the parasitic capacitor and the second regulating sub-circuit respectively, the output terminal of the operational amplifier is connected to the second regulating sub-circuit, and the non-inverting input terminal of the operational amplifier is grounded; The operational amplifier includes: an equivalent input resistor and an equivalent output resistor; The equivalent input resistor is connected to the parasitic capacitor and the second regulating sub-circuit respectively; The equivalent output resistor is connected to the second regulating sub-circuit; The first regulating subcircuit is configured to: receive an input voltage signal transmitted by the second regulating subcircuit, output an output signal corresponding to a preset parasitic pole based on the input voltage signal, determine a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmit the output signal and the current parasitic frequency to the second regulating subcircuit, wherein the parasitic pole is set at the inverting input terminal and the output terminal of the operational amplifier; The second regulation subcircuit is configured to: determine a target parasitic frequency corresponding to the parasitic pole, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole, so that the first regulation subcircuit can amplify the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

2. The common voltage compensation circuit according to claim 1, characterized in that: The second regulating subcircuit includes: a load capacitor and a negative feedback unit; The load capacitor is connected to the first regulating sub-circuit and the negative feedback unit respectively; The negative feedback unit is connected to the first regulation subcircuit and the load capacitor, respectively, and is configured to: determine a target parasitic frequency corresponding to the parasitic pole, adjust the current parasitic frequency to the target parasitic frequency, and use the cancellation signal generated by the output signal at the target parasitic frequency to cancel the parasitic pole.

3. The common voltage compensation circuit according to claim 2, characterized in that: The negative feedback unit includes: a first feedback resistor, a second feedback resistor and a feedback capacitor; The first feedback resistor is connected in series with the second feedback resistor and the feedback capacitor connected in parallel, and is connected to the first regulating sub-circuit; The second feedback resistor is connected in parallel with the feedback capacitor, and is respectively connected to the first feedback resistor, the first regulating sub-circuit and the load capacitor; The feedback capacitor is connected in parallel with the second feedback resistor, and is respectively connected with the first feedback resistor, the first regulating sub-circuit and the load capacitor.

4. The common voltage compensation circuit according to claim 2, wherein: The negative feedback unit includes: a first feedback resistor and a second feedback resistor; The first feedback resistor is connected to the second feedback resistor and the first regulating sub-circuit respectively; The second feedback resistor is connected to the load capacitor, the first regulating sub-circuit and the first feedback resistor respectively.

5. The common voltage compensation circuit according to claim 1, wherein: The second regulating subcircuit includes: a load resistor, a load capacitor and a negative feedback unit; The load resistor is connected in series with the load capacitor, and is respectively connected to the negative feedback unit and the first regulating sub-circuit; The load capacitor is connected in series with the load resistor; The negative feedback unit is connected to the first regulating sub-circuit and the load resistor respectively, and is configured to transmit the cancellation signal to the first regulating sub-circuit.

6. The common voltage compensation circuit according to claim 5, characterized in that: The negative feedback unit includes: a first feedback resistor and a second feedback resistor; The first feedback resistor is connected to the second feedback resistor and the first regulating sub-circuit respectively; The second feedback resistor is connected to the first feedback resistor, the load resistor and the first regulating sub-circuit respectively.

7. A display substrate, characterized in that: The common voltage compensation circuit comprises the common voltage compensation circuit according to any one of claims 1 to 6.

8. A display device, characterized in that: Comprising the display substrate as claimed in claim 7.

9. A common voltage compensation method applied to the common voltage compensation circuit according to any one of claims 1 to 6, characterized in that: The common voltage compensation method includes: receiving, by the first regulating subcircuit, an input voltage signal transmitted by the second regulating subcircuit, outputting an output signal corresponding to a preset parasitic pole based on the input voltage signal, determining a current parasitic frequency corresponding to the parasitic pole under the input voltage, and transmitting the output signal and the current parasitic frequency to the second regulating subcircuit; The target parasitic frequency corresponding to the parasitic pole is determined by the second regulation subcircuit, the current parasitic frequency is adjusted to the target parasitic frequency, and the parasitic pole is canceled using a cancellation signal generated by the output signal at the target parasitic frequency, so that the first regulation subcircuit amplifies the input voltage signal after the cancellation processing to obtain an amplified voltage signal.

10. The method according to claim 9, characterized in that The second regulating subcircuit includes a second feedback resistor and a feedback capacitor arranged in parallel; The determining of a target parasitic frequency corresponding to the parasitic pole includes: Obtaining the resistance value of the second feedback resistor and the capacitance value of the feedback capacitor; Performing product processing on a preset first parasitic frequency parameter, the resistance value of the second feedback resistor, and the capacitance value of the feedback capacitor to obtain a first product processing result; A preset second parasitic frequency parameter is used to perform ratio processing on the first product processing result to obtain a target parasitic frequency corresponding to the parasitic pole.

11. The method according to claim 9, characterized in that The second regulating subcircuit includes a load resistor and a load capacitor arranged in series; The determining of a target parasitic frequency corresponding to the parasitic pole includes: Obtaining the resistance value of the load resistor and the capacitance value of the load capacitor; Performing product processing on a preset first parasitic frequency parameter, the resistance value of the load resistor, and the capacitance value of the load capacitor to obtain a second product processing result; The second product processing result is ratio-processed using a preset second parasitic frequency parameter to obtain a target parasitic frequency corresponding to the parasitic pole.

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