Organic electroluminescent display panels

Abstract

The present application provides an organic electroluminescent display panel, which includes multiple pixel units, each of which includes at least: a light-emitting device; a first capacitor; two first-type transistors, including a first transistor and a second transistor; and multiple second-type transistors, wherein a portion of the multiple second-type transistors is electrically connected to a first node of the pixel unit through the first transistor, and another portion of the multiple second-type transistors is electrically connected to a second node of the pixel unit through the second transistor, the first node is electrically connected to a first plate of the first capacitor, and the second node is electrically connected to a second plate of the first capacitor. In the present application, the first node and the second node are each connected to only one transistor, and it is only necessary to ensure that the two transistors are designed with low leakage current to complete the normal pixel operation process through timing control, while achieving low-frequency and high-frequency display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an organic electroluminescent display panel. Background Art

[0002] Existing organic electroluminescent display panels can achieve low refresh rate display and high refresh rate reality.

[0003] Because the first node Q1 and the second node Q2 of the pixel unit of the organic electroluminescent display panel are respectively electrically connected to multiple transistors, these transistors are prone to leakage to the first node Q1 and the second node Q2 during the process of the organic electroluminescent display panel achieving low refresh rate display. Therefore, existing organic electroluminescent display panels have difficulty in ensuring the stability of the first node Q1 and the second node Q2. Summary of the Invention

[0004] The present application provides an organic electroluminescent display panel to solve the problem that it is difficult to ensure the stability of the first node and the second node of the pixel unit in the existing organic electroluminescent display panel.

[0005] In a first aspect, the present application provides an organic electroluminescent display panel, comprising: a plurality of pixel units, each pixel unit comprising at least:

[0006] a light emitting device;

[0007] Two first-type transistors, the two first-type transistors including a first transistor and a second transistor, one of a source and a drain of the first transistor being electrically connected to a first node of the pixel unit, and one of a source and a drain of the second transistor being electrically connected to a second node of the pixel unit;

[0008] a first capacitor, wherein one plate of the first capacitor is electrically connected to the first node, and another plate of the first capacitor is electrically connected to the second node; and

[0009] A plurality of second-type transistors, wherein the plurality of second-type transistors include at least three partial transistors, a first partial transistor of the at least three partial transistors includes a third transistor, one of the source and the drain of the third transistor is electrically connected to the light-emitting device, a gate of the third transistor is electrically connected to the first node, a second partial transistor of the at least three partial transistors is electrically connected to the other of the source and the drain of the first transistor, and a third partial transistor of the at least three partial transistors is electrically connected to the other of the source and the drain of the second transistor.

[0010] In the organic electroluminescent display panel provided in the present application, the first type transistor is an oxide semiconductor thin film transistor or a dual-gate low-temperature polysilicon thin film transistor, and the second type transistor is a single-gate low-temperature polysilicon thin film transistor or an amorphous silicon thin film transistor.

[0011] In the organic electroluminescent display panel provided in the present application, the organic electroluminescent display panel further includes a plurality of first scan signal input terminals;

[0012] The first scan signal input terminal is electrically connected to the gate of the first transistor and the gate of the second transistor, the first node is electrically connected to one of the source and the drain of the first transistor, a part of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the first transistor, the second node is electrically connected to one of the source and the drain of the second transistor, and another part of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the second transistor.

[0013] In the organic electroluminescent display panel provided in the present application, the organic electroluminescent display panel further includes a plurality of second scan signal input terminals, a plurality of third scan signal input terminals, a plurality of fourth scan signal input terminals, a plurality of first reset signal input terminals, a plurality of second reset signal input terminals, a plurality of third reset signal input terminals, a plurality of fourth reset signal input terminals, a plurality of first light emission control signal input terminals, a plurality of second light emission control signal input terminals, a plurality of high potential terminals, a plurality of low potential terminals, and a plurality of data signal input terminals;

[0014] A portion of the plurality of second-type transistors includes:

[0015] a third transistor, wherein a gate of the third transistor is electrically connected to the first node, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;

[0016] a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the third scan signal input terminal, one of a source and a drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor;

[0017] a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the second light-emitting control signal input terminal, one of a source and a drain of the fifth transistor is electrically connected to the high potential terminal, and the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;

[0018] a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the first light-emitting control signal input terminal, one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected to the first terminal of the light-emitting device;

[0019] an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the fourth scan signal input terminal, one of a source and a drain of the eighth transistor is electrically connected to the third reset signal input terminal, and the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor;

[0020] Another portion of the plurality of second-type transistors includes:

[0021] a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the second scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the second transistor;

[0022] a tenth transistor, wherein the gate of the tenth transistor is electrically connected to the second light-emitting control signal input terminal, one of the source and the drain of the tenth transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the second transistor.

[0023] In the organic electroluminescent display panel provided in the present application, in a first time period, the first light-emitting control signal inputted to the first light-emitting control signal input terminal remains a low-level signal, the signals inputted to the second light-emitting control signal input terminal and the first scan signal input terminal change from a low-level signal to a high-level signal, the signals inputted to the second scan signal input terminal and the fourth scan signal input terminal remain high-level signals, and the signal inputted to the third scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the first transistor, the fourth transistor, the sixth transistor, and the second transistor are turned on;

[0024] In the second time period, the signals input to the first light-emitting control signal input terminal, the first scan signal input terminal, the second scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals; the second light-emitting control signal input to the second light-emitting control signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the fifth transistor, the second transistor, and the tenth transistor are turned on;

[0025] In a third time period, the signals inputted to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the first scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals, and the second scan signal inputted to the second scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the second transistor, the first transistor, and the ninth transistor are turned on;

[0026] During a fourth time period, the signals input to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the second scan signal input terminal, and the third scan signal input terminal are high-level signals, and the signals input to the fourth scan signal input terminal and the first scan signal input terminal are changed from high-level signals to low-level signals, so that the eighth transistor is turned on;

[0027] In the fifth time period, the signals input to the first light-emitting control signal input terminal and the second light-emitting control signal input terminal are changed from a high level to a low level signal, the first scan signal input to the first scan signal input terminal remains a low level signal, the signals input to the second scan signal input terminal and the third scan signal input terminal are high level signals, and the fourth scan signal input to the fourth scan signal input terminal is changed from a low level to a high level signal, so that the fifth transistor and the sixth transistor are turned on, and the light-emitting element emits light.

[0028] In the organic electroluminescent display panel provided in the present application, a portion of the plurality of second-type transistors further includes:

[0029] a seventh transistor, wherein the gate of the seventh transistor is electrically connected to the third scan signal input terminal, one of the source and the drain of the seventh transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the seventh transistor is electrically connected to the first end of the light-emitting device.

[0030] In the organic electroluminescent display panel provided in the present application, in a first time period, the signals input to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, and the first scan signal input terminal are changed from low-level signals to high-level signals, the signals input to the second scan signal input terminal and the fourth scan signal input terminal remain high-level signals, and the signal input to the third scan signal input terminal is changed from a high-level signal to a low-level signal and then to a high-level signal, so that the first transistor, the fourth transistor, the seventh transistor, and the second transistor are turned on;

[0031] In the second time period, the signals input to the first light-emitting control signal input terminal, the first scan signal input terminal, the second scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals; the second light-emitting control signal input to the second light-emitting control signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the fifth transistor, the second transistor, and the tenth transistor are turned on;

[0032] In a third time period, the signals inputted to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the first scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals, and the second scan signal inputted to the second scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the second transistor, the first transistor, and the ninth transistor are turned on;

[0033] During a fourth time period, the signals input to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the second scan signal input terminal, and the third scan signal input terminal are high-level signals, and the signals input to the fourth scan signal input terminal and the first scan signal input terminal are changed from high-level signals to low-level signals, so that the eighth transistor is turned on;

[0034] In the fifth time period, the signals input to the first light-emitting control signal input terminal and the second light-emitting control signal input terminal are changed from a high level to a low level signal, the first scan signal input to the first scan signal input terminal remains a low level signal, the signals input to the second scan signal input terminal and the third scan signal input terminal are high level signals, and the fourth scan signal input to the fourth scan signal input terminal is changed from a low level to a high level signal, so that the fifth transistor and the sixth transistor are turned on, and the light-emitting element emits light.

[0035] In the organic electroluminescent display panel provided in the present application, the organic electroluminescent display panel further includes a plurality of second scan signal input terminals, a plurality of third scan signal input terminals, a plurality of fourth scan signal input terminals, a plurality of first reset signal input terminals, a plurality of second reset signal input terminals, a plurality of first light emission control signal input terminals, a plurality of high potential terminals, a plurality of low potential terminals, and a plurality of data signal input terminals;

[0036] The third scan signal input terminal is electrically connected to the gate of the first transistor, the first node is electrically connected to one of the source and the drain of the first transistor, and some of the plurality of second-type transistors are electrically connected to the other of the source and the drain of the first transistor;

[0037] The fourth scan signal input terminal is electrically connected to the gate of the second transistor, the second node is electrically connected to one of the source and the drain of the second transistor, and another part of the multiple second-type transistors is electrically connected to the other one of the source and the drain of the second transistor.

[0038] In the organic electroluminescent display panel provided in the present application, a portion of the plurality of second-type transistors includes:

[0039] a third transistor, wherein a gate of the third transistor is electrically connected to the first node, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;

[0040] a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the first light-emitting control signal input terminal, one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected to the first terminal of the light-emitting device;

[0041] a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the fourth scan signal input terminal, one of a source and a drain of the seventh transistor is electrically connected to the first reset signal input terminal, and the other of the source and the drain of the seventh transistor is electrically connected to the first terminal of the light-emitting device;

[0042] Another portion of the plurality of second-type transistors includes:

[0043] a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the second scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the second transistor;

[0044] a tenth transistor, wherein the gate of the tenth transistor is electrically connected to the third scan control signal input terminal, one of the source and the drain of the tenth transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the second transistor.

[0045] In the organic electroluminescent display panel provided in the present application, in a first time period, the first light-emitting control signal input to the first light-emitting control signal input terminal changes from a low-level signal to a high-level signal, the second scan signal input to the second scan signal input terminal remains at a high-level signal, the third scan signal input to the third scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, and the fourth scan signal input to the fourth scan signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the second transistor, the tenth transistor, and the seventh transistor are turned on;

[0046] In the second time period, the first light-emitting control signal inputted to the first light-emitting control signal input terminal remains at a high level signal, the second scanning signal inputted to the second scanning signal input terminal changes from a high level signal to a low level signal and then to a high level signal, the third scanning signal inputted to the third scanning signal input terminal remains at a high level signal, and the fourth scanning signal inputted to the fourth scanning signal input terminal changes from a low level signal to a high level signal, so that the second transistor and the ninth transistor are turned on;

[0047] In the third time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal changes from a high-level signal to a low-level signal, and the signals inputted by the second scan signal input terminal, the third scan signal input terminal and the fourth scan signal input terminal remain high-level signals, so that the sixth transistor is turned on and the light-emitting element emits light.

[0048] The beneficial effect of the present application is that: in the organic electroluminescent display panel provided by the present application, the first node Q1 and the second node Q2 of the pixel unit are respectively connected to only one TFT. Compared with the existing organic electroluminescent display panel, in the present application, the resetting of the first node Q1 and the second node Q2 can be performed through two TFTs connected in series, and the writing of the data signal DATA of the second node Q2 can also be performed through two TFTs connected in series. In this process, it is only necessary to ensure that the two TFTs connected to the first node Q1 and the second node adopt a low leakage current design, so that the normal pixel operation process can be completed through timing control, and low-frequency and high-frequency (1Hz~240Hz) display can be achieved at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of an organic electroluminescent display panel provided in an embodiment of the present application;

[0050] Figure 2 Based on Figure 1 Control timing diagram of organic electroluminescent display panel;

[0051] Figure 3A schematic diagram of another organic electroluminescent display panel provided in an embodiment of the present application;

[0052] Figure 4 Based on Figure 3 Control timing diagram of organic electroluminescent display panel;

[0053] Figure 5 A schematic diagram of another organic electroluminescent display panel provided in an embodiment of the present application;

[0054] Figure 6 Based on Figure 5 Control timing diagram of the organic electroluminescent display panel. DETAILED DESCRIPTION

[0055] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described embodiments are only used to explain the ideas created by the present invention and should not be regarded as limiting the scope of protection of this application.

[0056] In addition, the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0057] like Figure 1 、 3 As shown in FIG. 5 , an embodiment of the present application provides an organic electroluminescent display panel, which includes a plurality of pixel units, and the pixel units include at least:

[0058] a light emitting device;

[0059] a first capacitor C2;

[0060] Two first-type transistors, the two first-type transistors including a first transistor T3 and a second transistor T9;

[0061] multiple second-type transistors, a portion of the multiple second-type transistors is electrically connected to the first node Q1 of the pixel unit through the first transistor T3, another portion of the multiple second-type transistors is electrically connected to the second node Q2 of the pixel unit through the second transistor T9, the first node Q1 is electrically connected to the first plate of the first capacitor C2, and the second node Q2 is electrically connected to the second plate of the first capacitor C2.

[0062] The first type transistor is an oxide semiconductor thin film transistor or a dual-gate low-temperature polysilicon thin film transistor, and the second type transistor is a single-gate low-temperature polysilicon thin film transistor or an amorphous silicon thin film transistor.

[0063] In some embodiments of the present application, the organic electroluminescent display panel further includes a plurality of first scan signal input terminals NSCAN;

[0064] The first scan signal input terminal NSCAN is electrically connected to the gate of the first transistor T3 and the gate of the second transistor T9, the first node Q1 is electrically connected to one of the source and drain of the first transistor T3, a portion of the plurality of second-type transistors is electrically connected to the other of the source and drain of the first transistor T3, the second node Q2 is electrically connected to one of the source and drain of the second transistor T9, and another portion of the plurality of second-type transistors is electrically connected to the other of the source and drain of the second transistor T9. The organic electroluminescent display panel further includes a plurality of second scan signal input terminals PSCAN1, a plurality of third scan signal input terminals PSCAN2, a plurality of fourth scan signal input terminals PSCAN3, a plurality of first reset signal input terminals VI1, a plurality of second reset signal input terminals VI2, a plurality of third reset signal input terminals VI3, a plurality of fourth reset signal input terminals VI4, a plurality of first emission control signal input terminals EM1, a plurality of second emission control signal input terminals EM2, a plurality of high potential terminals VDD, a plurality of low potential terminals VSS, and a plurality of data signal input terminals Data;

[0065] A portion of the plurality of second-type transistors includes:

[0066] a third transistor T1, wherein a gate of the third transistor is electrically connected to the first node Q1, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor T3;

[0067] a fourth transistor T4, wherein a gate of the fourth transistor is electrically connected to the third scan signal input terminal PSCAN2, one of a source and a drain of the fourth transistor is electrically connected to the first reset signal input terminal VI1, and the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor T3;

[0068] a fifth transistor T5, wherein a gate of the fifth transistor T5 is electrically connected to the second light-emitting control signal input terminal EM2, one of a source and a drain of the fifth transistor T5 is electrically connected to the high potential terminal VDD, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the other of the source and the drain of the third transistor T1;

[0069] a sixth transistor T6, wherein a gate of the sixth transistor T6 is electrically connected to the first light-emitting control signal input terminal EM1, one of a source and a drain of the sixth transistor T6 is electrically connected to the other of the source and the drain of the first transistor T3, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting device;

[0070] a seventh transistor T7, wherein a gate of the seventh transistor T7 is electrically connected to the third scan signal input terminal PSCAN2, one of a source and a drain of the seventh transistor T7 is electrically connected to the second reset signal input terminal VI2, and the other of the source and the drain of the seventh transistor T7 is electrically connected to the first terminal of the light-emitting device;

[0071] an eighth transistor T8, wherein a gate of the eighth transistor T8 is electrically connected to the fourth scan signal input terminal PSCAN3, one of a source and a drain of the eighth transistor T8 is electrically connected to the third reset signal input terminal VI3, and the other of the source and the drain of the eighth transistor T8 is electrically connected to the other of the source and the drain of the third transistor T1;

[0072] Another portion of the plurality of second-type transistors includes:

[0073] a ninth transistor T2, wherein a gate of the ninth transistor T2 is electrically connected to the second scan signal input terminal PSCAN1, one of a source and a drain of the ninth transistor T2 is electrically connected to the data signal input terminal Data, and the other of the source and the drain of the ninth transistor T2 is electrically connected to the other of the source and the drain of the second transistor T9;

[0074] a tenth transistor T10, wherein the gate of the tenth transistor T10 is electrically connected to the second light-emitting control signal input terminal, one of the source and the drain of the tenth transistor T10 is electrically connected to the second reset signal input terminal VI2, and the other of the source and the drain of the tenth transistor T10 is electrically connected to the other of the source and the drain of the second transistor T9.

[0075] In these embodiments, the timing control method of the pixel unit is as follows:

[0076] In a first time period, the first light control signal inputted by the first light control signal input terminal EM1 is a high-level signal, the second light control signal inputted by the second light control signal input terminal EM2 is a high-level signal, the first scan signal inputted by the first scan signal input terminal NSCAN is a high-level signal, the second scan signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scan signal inputted by the third scan signal input terminal PSCAN2 is a low-level signal, and the fourth scan signal inputted by the fourth scan signal input terminal PSCAN3 is a high-level signal;

[0077] In the second time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second light-emitting control signal inputted by the second light-emitting control signal input terminal EM2 is a low-level signal, the first scanning signal inputted by the first scan signal input terminal NSCAN is a high-level signal, the second scanning signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scanning signal inputted by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scanning signal inputted by the fourth scan signal input terminal PSCAN3 is a high-level signal;

[0078] In a third time period, the first light control signal inputted by the first light control signal input terminal EM1 is a high level signal, the second light control signal inputted by the second light control signal input terminal EM2 is a high level signal, the first scan signal inputted by the first scan signal input terminal NSCAN is a high level signal, the second scan signal inputted by the second scan signal input terminal PSCAN1 is a low level signal, the third scan signal inputted by the third scan signal input terminal PSCAN2 is a high level signal, and the fourth scan signal inputted by the fourth scan signal input terminal PSCAN3 is a high level signal;

[0079] In a fourth time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second light-emitting control signal inputted by the second light-emitting control signal input terminal EM2 is a high-level signal, the first scanning signal inputted by the first scan signal input terminal NSCAN is a low-level signal, the second scanning signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scanning signal inputted by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scanning signal inputted by the fourth scan signal input terminal PSCAN3 is a low-level signal;

[0080] In the fifth time period, the first light-emitting control signal input by the first light-emitting control signal input terminal EM1 is a low-level signal, the second light-emitting control signal input by the second light-emitting control signal input terminal EM2 is a low-level signal, the first scan signal input by the first scan signal input terminal NSCAN is a low-level signal, the second scan signal input by the second scan signal input terminal PSCAN1 is a high-level signal, the third scan signal input by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scan signal input by the fourth scan signal input terminal PSCAN3 is a high-level signal.

[0081] In some other embodiments of the present application, the pixel unit may also include:

[0082] a plurality of first scanning signal input terminals NSCAN;

[0083] The first scan signal input terminal NSCAN is electrically connected to the gate of the first transistor T3 and the gate of the second transistor T9, the first node Q1 is electrically connected to one of the source and drain of the first transistor T3, a portion of the plurality of second-type transistors is electrically connected to the other of the source and drain of the first transistor T3, the second node Q2 is electrically connected to one of the source and drain of the second transistor T9, and another portion of the plurality of second-type transistors is electrically connected to the other of the source and drain of the second transistor T9. A plurality of second scan signal input terminals PSCAN1, a plurality of third scan signal input terminals PSCAN2, a plurality of fourth scan signal input terminals PSCAN3, a plurality of first reset signal input terminals VI1, a plurality of second reset signal input terminals VI2, a plurality of third reset signal input terminals VI3, a plurality of fourth reset signal input terminals VI4, a plurality of first emission control signal input terminals EM1, a plurality of second emission control signal input terminals EM2, a plurality of high potential terminals VDD, a plurality of low potential terminals VSS, and a plurality of data signal input terminals Data;

[0084] A portion of the plurality of second-type transistors includes:

[0085] a third transistor T1, wherein a gate of the third transistor is electrically connected to the first node Q1, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor T3;

[0086] a fourth transistor T4, wherein a gate of the fourth transistor is electrically connected to the third scan signal input terminal PSCAN2, one of a source and a drain of the fourth transistor is electrically connected to the first reset signal input terminal VI1, and the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor T3;

[0087] a fifth transistor T5, wherein a gate of the fifth transistor T5 is electrically connected to the second light-emitting control signal input terminal EM2, one of a source and a drain of the fifth transistor T5 is electrically connected to the high potential terminal VDD, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the other of the source and the drain of the third transistor T1;

[0088] a sixth transistor T6, wherein a gate of the sixth transistor T6 is electrically connected to the first light-emitting control signal input terminal EM1, one of a source and a drain of the sixth transistor T6 is electrically connected to the other of the source and the drain of the first transistor T3, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting device;

[0089] an eighth transistor T8, wherein a gate of the eighth transistor T8 is electrically connected to the fourth scan signal input terminal PSCAN3, one of a source and a drain of the eighth transistor T8 is electrically connected to the third reset signal input terminal VI3, and the other of the source and the drain of the eighth transistor T8 is electrically connected to the other of the source and the drain of the third transistor T1;

[0090] Another portion of the plurality of second-type transistors includes:

[0091] a ninth transistor T2, wherein a gate of the ninth transistor T2 is electrically connected to the second scan signal input terminal PSCAN1, one of a source and a drain of the ninth transistor T2 is electrically connected to the data signal input terminal Data, and the other of the source and the drain of the ninth transistor T2 is electrically connected to the other of the source and the drain of the second transistor T9;

[0092] a tenth transistor T10, wherein the gate of the tenth transistor T10 is electrically connected to the second light-emitting control signal input terminal, one of the source and the drain of the tenth transistor T10 is electrically connected to the second reset signal input terminal VI2, and the other of the source and the drain of the tenth transistor T10 is electrically connected to the other of the source and the drain of the second transistor T9.

[0093] In these embodiments, the timing control method of the pixel unit is as follows:

[0094] In a first time period, the first light control signal inputted by the first light control signal input terminal EM1 is a low-level signal, the second light control signal inputted by the second light control signal input terminal EM2 is a high-level signal, the first scan signal inputted by the first scan signal input terminal NSCAN is a high-level signal, the second scan signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scan signal inputted by the third scan signal input terminal PSCAN2 is a low-level signal, and the fourth scan signal inputted by the fourth scan signal input terminal PSCAN3 is a high-level signal;

[0095] In the second time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second light-emitting control signal inputted by the second light-emitting control signal input terminal EM2 is a low-level signal, the first scanning signal inputted by the first scan signal input terminal NSCAN is a high-level signal, the second scanning signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scanning signal inputted by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scanning signal inputted by the fourth scan signal input terminal PSCAN3 is a high-level signal;

[0096] In a third time period, the first light control signal inputted by the first light control signal input terminal EM1 is a high level signal, the second light control signal inputted by the second light control signal input terminal EM2 is a high level signal, the first scan signal inputted by the first scan signal input terminal NSCAN is a high level signal, the second scan signal inputted by the second scan signal input terminal PSCAN1 is a low level signal, the third scan signal inputted by the third scan signal input terminal PSCAN2 is a high level signal, and the fourth scan signal inputted by the fourth scan signal input terminal PSCAN3 is a high level signal;

[0097] In a fourth time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second light-emitting control signal inputted by the second light-emitting control signal input terminal EM2 is a high-level signal, the first scanning signal inputted by the first scan signal input terminal NSCAN is a low-level signal, the second scanning signal inputted by the second scan signal input terminal PSCAN1 is a high-level signal, the third scanning signal inputted by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scanning signal inputted by the fourth scan signal input terminal PSCAN3 is a low-level signal;

[0098] In the fifth time period, the first light-emitting control signal input by the first light-emitting control signal input terminal EM1 is a low-level signal, the second light-emitting control signal input by the second light-emitting control signal input terminal EM2 is a low-level signal, the first scan signal input by the first scan signal input terminal NSCAN is a low-level signal, the second scan signal input by the second scan signal input terminal PSCAN1 is a high-level signal, the third scan signal input by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scan signal input by the fourth scan signal input terminal PSCAN3 is a high-level signal.

[0099] In addition, in some other embodiments of the present application, the organic electroluminescent display panel may further include:

[0100] The organic electroluminescent display panel further includes a plurality of second scan signal input terminals PSCAN1, a plurality of third scan signal input terminals PSCAN2, a plurality of fourth scan signal input terminals PSCAN3, a plurality of first reset signal input terminals VI1, a plurality of second reset signal input terminals VI2, a plurality of first light emitting control signal input terminals EM1, a plurality of high potential terminals VDD, a plurality of low potential terminals VSS and a plurality of data signal input terminals Data;

[0101] The third scan signal input terminal PSCAN2 is electrically connected to the gate of the first transistor T3, the first node Q1 is electrically connected to one of the source and the drain of the first transistor T3, and a portion of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the first transistor T3;

[0102] The fourth scan signal input terminal PSCAN3 is electrically connected to the gate of the second transistor T9, the second node Q2 is electrically connected to one of the source and the drain of the second transistor T9, and another part of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the second transistor T9.

[0103] Part of the plurality of second-type transistors includes:

[0104] a third transistor T1, wherein a gate of the third transistor is electrically connected to the first node Q1, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor T3;

[0105] a sixth transistor T6, wherein a gate of the sixth transistor T6 is electrically connected to the first light-emitting control signal input terminal EM1, one of a source and a drain of the sixth transistor T6 is electrically connected to the other of the source and the drain of the first transistor T3, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting device;

[0106] a seventh transistor T7, wherein a gate of the seventh transistor T7 is electrically connected to the fourth scan signal input terminal PSCAN3, one of a source and a drain of the seventh transistor T7 is electrically connected to the second reset signal input terminal VI2, and the other of the source and the drain of the seventh transistor T7 is electrically connected to the first terminal of the light-emitting device;

[0107] Another portion of the plurality of second-type transistors includes:

[0108] a ninth transistor T2, wherein a gate of the ninth transistor T2 is electrically connected to the second scan signal input terminal PSCAN1, one of a source and a drain of the ninth transistor T2 is electrically connected to the data signal input terminal Data, and the other of the source and the drain of the ninth transistor T2 is electrically connected to the other of the source and the drain of the second transistor T9;

[0109] a tenth transistor T10, wherein a gate of the tenth transistor T10 is electrically connected to the third scan control signal input terminal PSCAN2, one of a source and a drain of the tenth transistor T10 is electrically connected to the second reset signal input terminal VI2, and the other of the source and the drain of the tenth transistor T10 is electrically connected to the other of the source and the drain of the second transistor T9.

[0110] In these embodiments, the timing control method of the pixel unit is as follows:

[0111] In the first time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second scanning signal inputted by the second scanning signal input terminal PSCAN1 is a high-level signal, the third scanning signal inputted by the third scanning signal input terminal PSCAN2 is a low-level signal, and the fourth scanning signal inputted by the fourth scanning signal input terminal PSCAN3 is a low-level signal;

[0112] In the second time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal EM1 is a high-level signal, the second scanning signal inputted by the second scanning signal input terminal PSCAN1 is a low-level signal, the third scanning signal inputted by the third scanning signal input terminal PSCAN2 is a high-level signal, and the fourth scanning signal inputted by the fourth scanning signal input terminal PSCAN3 is a low-level signal;

[0113] In the third time period, the first light-emitting control signal input by the first light-emitting control signal input terminal EM1 is a low-level signal, the second scan signal input by the second scan signal input terminal PSCAN1 is a high-level signal, the third scan signal input by the third scan signal input terminal PSCAN2 is a high-level signal, and the fourth scan signal input by the fourth scan signal input terminal PSCAN3 is a high-level signal.

[0114] Based on the above embodiments, this application provides some more specific embodiments:

[0115] Example 1

[0116] like Figure 1 As shown, a 10T2C organic electroluminescent display panel is provided, and the organic electroluminescent display panel includes:

[0117] A third transistor T1, a data writing circuit D1, a threshold compensation circuit D2, a first reset circuit D3, a control circuit D4, a second reset circuit D5, a second capacitor C1, a first capacitor C2 and a light emitting device.

[0118] The third transistor T1 is a driving transistor, a gate of the third transistor T1 is connected to the first node Q1, a first electrode of the third transistor T1 is connected to the third node A, and a second electrode of the third transistor T1 is connected to the fourth node B.

[0119] One end of the first capacitor C2 is connected to the first node Q1 , and the other end is connected to the second node Q2 .

[0120] The data writing circuit D1 is connected to the second node Q2 and is configured to write the data signal DATA into the second node Q2 in response to the second scan signal input terminal PSCAN1 and the first scan signal input terminal NSCAN.

[0121] The threshold compensation circuit D2 is connected to the first node Q1 and the fourth node B. The threshold compensation circuit D2 is configured to connect the first node Q1 and the fourth node B in response to the first scan signal input terminal NSCAN.

[0122] The first reset circuit D3 is connected to the first node Q1 and the first reset signal input terminal VI1, and is configured to transmit the signal of the first reset signal input terminal VI1 to the first node Q1 in response to the first scan signal input terminal NSCAN and the third scan signal input terminal PSCAN2.

[0123] The control circuit D4 is connected to the high potential end, the third node A, the fourth node B and the fifth node C. The control circuit D4 is used to respond to the first light-emitting control signal input terminal EM1 to connect the fourth node B and the fifth node C, and respond to the second light-emitting control signal input terminal EM2 to transmit the signal VDD of the high potential end to the third node A.

[0124] The second reset circuit D5 is connected to the second node Q2 and the second reset signal input terminal VI2. The second reset circuit D5 is used to transmit the signal of the second reset signal input terminal VI2 to the second node Q2 in response to the second light-emitting control signal input terminal EM2 and the first scan signal input terminal NSCAN.

[0125] One end of the second capacitor C1 is connected to the second node Q2 , and the other end is connected to the high potential end.

[0126] The anode of the light emitting device is connected to the fifth node C, and the cathode of the light emitting device is connected to the low potential terminal signal VSS. Optionally, the light emitting device may be a light emitting diode.

[0127] Optionally, the organic electroluminescent display panel of the present application further includes a third reset circuit D6 and a fourth reset circuit D7.

[0128] The third reset circuit D6 is connected to the third node A and the third reset signal input terminal VI3. The third reset circuit D6 is configured to transmit the signal of the third reset signal input terminal VI3 to the third node A in response to the fourth scan signal input terminal PSCAN3.

[0129] The fourth reset circuit D7 is connected to the fifth node C and the fourth reset signal input terminal VI4. The fourth reset circuit D7 is used to respond to the third scan signal input terminal PSCAN2 to transmit the signal of the fourth reset signal input terminal VI4 to the fifth node C. Writing the fourth reset signal input terminal VI4VI4 to the fifth node can eliminate the carriers that have not been recombined on the light-emitting interface inside the light-emitting diode, thereby alleviating the aging of the light-emitting diode.

[0130] The data writing circuit D1 includes a ninth transistor T2 and a second transistor T9. Optionally, the ninth transistor T2 is a PTFT polymer thin film transistor, and the second transistor T9 is an IGZO indium gallium zinc oxide TFT. The gate of the ninth transistor T2 is connected to the second scan signal input terminal PSCAN1, the first electrode of the ninth transistor T2 is connected to the data signal DATA, the second electrode of the ninth transistor T2 is connected to the first electrode of the second transistor T9, the second electrode of the second transistor T9 is connected to the second node Q2, and the gate of the second transistor T9 is connected to the first scan signal input terminal NSCAN.

[0131] The threshold compensation circuit D2 includes a first transistor T3. Optionally, the first transistor T3 is an IGZO TFT. The gate of the first transistor T3 is used to connect to the first scan signal input terminal NSCAN. The first electrode of the first transistor T3 is connected to the first node Q1. The second electrode of the first transistor T3 is connected to the fourth node B.

[0132] The first reset circuit D3 includes a fourth transistor T4 and the first transistor T3, the gate of the fourth transistor T4 is used to connect to the third scan signal input terminal PSCAN2, the first electrode of the fourth transistor T4 is connected to the second electrode of the first transistor T3, and the second electrode of the fourth transistor T4 is connected to the first reset signal input terminal VI1.

[0133] The control circuit D4 includes a sixth transistor T6 and a fifth transistor T5. The gate of the sixth transistor T6 is connected to the first light-emitting control signal input terminal EM1, the first electrode of the sixth transistor T6 is connected to the fourth node B, and the second electrode of the sixth transistor T6 is connected to the fifth node C. The gate of the fifth transistor T5 is connected to the second light-emitting control signal input terminal EM2, the first electrode of the fifth transistor T5 is connected to the power supply terminal, and the second electrode of the fifth transistor T5 is connected to the third node A.

[0134] The second reset circuit D5 includes a tenth transistor T10 and a second transistor T9, wherein the gate of the tenth transistor T10 is used to connect to the second light-emitting control signal input terminal EM2, the first electrode of the tenth transistor T10 is connected to the second reset signal input terminal VI2, the second electrode of the tenth transistor T10 is connected to the first electrode of the second transistor T9, the gate of the second transistor T9 is used to connect to the first scan signal input terminal NSCAN, and the second electrode of the second transistor T9 is connected to the second node Q2.

[0135] The third reset circuit D6 includes the eighth transistor T8, a first electrode of the eighth transistor T8 is connected to the third node A, a second electrode of the eighth transistor T8 is connected to the third reset signal input terminal VI3, and a gate of the eighth transistor T8 is used to connect to the fourth scan signal input terminal PSCAN3.

[0136] The fourth reset circuit D7 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the fourth reset signal input terminal VI4, a second electrode of the seventh transistor T7 is connected to the fifth node C, and a gate of the seventh transistor T7 is connected to the third scan signal input terminal PSCAN2.

[0137] In this embodiment, the first transistor T3 and the second transistor T9 are IGZO TFTs, and the other TFTs are PTFTs. Figure 2 The working process of the organic electroluminescent display panel of this embodiment includes five time periods, which are as follows:

[0138] Phase 1: The first light-emitting control signal input terminal EM1, the second light-emitting control signal input terminal EM2, and the first scan signal input terminal NSCAN output high-level signals. The third scan signal input terminal PSCAN2 changes from high to low and then to high. The second scan signal input terminal PSCAN1 and the fourth scan signal input terminal PSCAN3 remain high. The first transistor T3, the fourth transistor T4, the seventh transistor T7, and the second transistor T9 are turned on, and the other transistors are turned off. The signal from the first reset signal input terminal VI1 is transmitted to the first node Q1 to initialize the gate of the third transistor T1. The signal from the fourth reset signal input terminal VI4 is transmitted to the fifth node C to reset the anode of the light-emitting device.

[0139] Phase 2: The first light-emission control signal input terminal EM1, the first scan signal input terminal NSCAN, the third scan signal input terminal PSCAN2, the second scan signal input terminal PSCAN1, and the fourth scan signal input terminal PSCAN3 remain in a high-level state. The second light-emission control signal input terminal EM2 outputs a low-level signal. The first transistor T3, the fifth transistor T5, the second transistor T9, and the tenth transistor T10 are turned on, and the other transistors are turned off. The high-potential signal VDD is written to the gate of the third transistor T1, i.e., the first node Q1, to capture the threshold voltage Vth of the third transistor T1. The signal of the second reset signal input terminal VI2 is transmitted to the second node Q2, resetting the second node Q2.

[0140] Phase 3: the first light-emitting control signal input terminal EM1, the second light-emitting control signal input terminal EM2, the first scan signal input terminal NSCAN, the third scan signal input terminal PSCAN2, and the fourth scan signal input terminal PSCAN3 output high-level signals, the second scan signal input terminal PSCAN1 changes from a high level to a low level and then to a high level, the ninth transistor T2, the first transistor T3, and the second transistor T9 are turned on, and the other transistors are turned off, the data signal DATA is written to the second node Q2, and at the same time, the data signal DATA is coupled to the first node Q1 through the first capacitor C2.

[0141] Phase 4: The first light-emission control signal input terminal EM1, the second light-emission control signal input terminal EM2, the third scan signal input terminal PSCAN2, and the second scan signal input terminal PSCAN1 output high-level signals, the first scan signal input terminal NSCAN and the fourth scan signal input terminal PSCAN3 output low-level signals, the eighth transistor T8 is turned on, and the other transistors are turned off. The signal from the third reset signal input terminal VI3 is connected to the first electrode of the third transistor T1 to reset the third node A, thereby improving the hysteresis effect of the third transistor T1.

[0142] The fifth stage: the first light-emitting control signal input terminal EM1, the second light-emitting control signal input terminal EM2 and the first scan signal input terminal NSCAN output low-level signals, the third scan signal input terminal PSCAN2, the fourth scan signal input terminal PSCAN3 and the second scan signal input terminal PSCAN1 output high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, so that the light-emitting device emits light.

[0143] Example 2

[0144] like Figure 3 As shown, a 9T2C organic electroluminescent display panel is provided. The structure of the organic electroluminescent display panel in this embodiment is substantially the same as the corresponding structure in the previous embodiment. For the same structure, reference can be made to the corresponding description in the previous embodiment, which will not be repeated here. The main difference between the two is that, in this embodiment, the fourth reset circuit D7 connected to the fifth node C is no longer provided at the fifth node C. Similarly, in this embodiment, the first transistor T3 and the second transistor T9 are IGZO TFTs, and the other TFTs are PTFTs. Figure 4 The working process of the organic electroluminescent display panel of this embodiment includes five time periods, which are as follows:

[0145] Phase 1: The first light-emitting control signal input terminal EM1 outputs a low-level signal, the second light-emitting control signal input terminal EM2, the first scan signal input terminal NSCAN, the fourth scan signal input terminal PSCAN3, and the second scan signal input terminal PSCAN1 output high-level signals, the third scan signal input terminal PSCAN2 changes from high to low and then to high, the first transistor T3, the fourth transistor T4, the sixth transistor T6, and the second transistor T9 are turned on, and the other transistors are turned off. The signal from the first reset signal input terminal VI1 is transmitted to the first node Q1 to initialize the gate of the third transistor T1. Simultaneously, the signal from the first reset signal input terminal VI1 is transmitted to the fifth node C to initialize the anode of the light-emitting device.

[0146] Phase 2: The first light-emitting control signal input terminal EM1, the first scan signal input terminal NSCAN, the fourth scan signal input terminal PSCAN3, the third scan signal input terminal PSCAN2, and the second scan signal input terminal PSCAN1 output high-level signals, and the second light-emitting control signal input terminal EM2 outputs a low-level signal. The first transistor T3, the fifth transistor T5, the tenth transistor T10, and the second transistor T9 are turned on, and the other transistors are turned off. The high-potential signal VDD is written to the gate of the first transistor, i.e., the first node Q1, to capture the threshold voltage Vth of the third transistor T1. The signal of the second reset signal input terminal VI2 is transmitted to the second node Q2, resetting the second node Q2.

[0147] Phase 3: The first light-emitting control signal input terminal EM1, the second light-emitting control signal input terminal EM2, the first scan signal input terminal NSCAN, the fourth scan signal input terminal PSCAN3, and the third scan signal input terminal PSCAN2 output high-level signals. The second scan signal input terminal PSCAN1 changes from a high level to a low level and then to a high level. The ninth transistor T2, the first transistor T3, and the second transistor T9 are turned on, and the other transistors are turned off. The data signal DATA is written to the second node Q2. At the same time, the data signal DATA is coupled to the first node Q1 via the first capacitor C2.

[0148] Phase 4: The first light-emission control signal input terminal EM1, the second light-emission control signal input terminal EM2, the third scan signal input terminal PSCAN2, and the second scan signal input terminal PSCAN1 output high-level signals, the first scan signal input terminal NSCAN and the fourth scan signal input terminal PSCAN3 output low-level signals, the eighth transistor T8 is turned on, and the other transistors are turned off. The signal from the third reset signal input terminal VI3 is connected to the first electrode of the third transistor T1 to reset the third node A, thereby improving the hysteresis effect of the third transistor T1.

[0149] The fifth stage: the first light-emitting control signal input terminal EM1, the second light-emitting control signal input terminal EM2 and the first scan signal input terminal NSCAN output low-level signals, the fourth scan signal input terminal PSCAN3, the third scan signal input terminal PSCAN2 and the second scan signal input terminal PSCAN1 output high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, so that the light-emitting device emits light.

[0150] Example 3

[0151] like Figure 5 As shown, a 7T2C organic electroluminescent display panel is provided. The organic electroluminescent display panel in this embodiment includes: a third transistor T1, a data writing circuit D1, a threshold compensation circuit D2, a first reset circuit D3, a control circuit D4, a second reset circuit D5, a second capacitor C1, a first capacitor C2 and a light-emitting device, and a fourth reset circuit D7.

[0152] Different from the above embodiment, in the embodiment of the present application, the third reset circuit D6 is not included. More specifically, the third transistor T1 is a driving transistor, the gate of the third transistor T1 is connected to the first node Q1, the first electrode of the third transistor T1 is connected to the third node A, the second electrode of the third transistor T1 is connected to the fourth node B, and the third node A is directly connected to the high potential end.

[0153] In addition, in this embodiment, the data writing circuit D1 includes a ninth transistor T2 and a second transistor T9. Optionally, the ninth transistor T2 is a PTFT, and the second transistor T9 is a dual-gate TFT. The gate of the second transistor T2 is connected to the second scan signal input terminal PSCAN1, the first electrode of the ninth transistor T2 is connected to the data signal DATA, the second electrode of the ninth transistor T2 is connected to the first electrode of the second transistor T9, the second electrode of the second transistor T9 is connected to the second node Q2, and the gate of the second transistor T9 is connected to the fourth scan signal input terminal PSCAN3.

[0154] The threshold compensation circuit D2 includes a first transistor T3. Optionally, the first transistor T3 is a dual-gate TFT. The gate of the first transistor T3 is used to connect to the third scan signal input terminal PSCAN2. The first electrode of the first transistor T3 is connected to the first node Q1, and the second electrode of the first transistor T3 is connected to the fourth node B.

[0155] Furthermore, the first reset circuit D3 includes a first transistor T3, a sixth transistor T6, and a seventh transistor T7. The first electrode of the sixth transistor T6 is connected to the fourth node B, the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting device, namely the fifth node C, and the gate of the sixth transistor T6 is connected to the first light-emitting control signal input terminal EM1. The first electrode of the seventh transistor T7 is connected to the first reset signal input terminal VI1, the second electrode of the seventh transistor T7 is connected to the fifth node C, and the gate of the seventh transistor T7 is connected to the fourth scan signal input terminal PSCAN3. The sixth transistor T6 also serves as part of the control circuit D4, and is used to control the on and off of the light-emitting device.

[0156] The second reset circuit D5 includes a tenth transistor T10 and a second transistor T9, a first electrode of the tenth transistor T10 is connected to the second reset signal input terminal VI2, a second electrode of the tenth transistor T10 is connected to the first electrode of the second transistor T9, and a gate of the tenth transistor T10 is used to connect to the third scan signal input terminal PSCAN2.

[0157] The fourth reset circuit D7 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the first reset signal input terminal VI1, a second electrode of the seventh transistor T7 is connected to the fifth node C, and a gate of the seventh transistor T7 is connected to the fourth scan signal input terminal PSCAN3.

[0158] In this embodiment, the first transistor T3 and the second transistor T9 are dual-gate TFTs, and the other transistors are PTFTs. Figure 6 The working process of the organic electroluminescent display panel of this embodiment includes three time periods:

[0159] Phase 1: The first light-emitting control signal input terminal EM1 and the second scan signal input terminal PSCAN1 output high-level signals, the third scan signal input terminal PSCAN2 changes from high level to low level and then to high level, the fourth scan signal input terminal PSCAN3 changes from high level to low level, the first transistor T3, the second transistor T9, the tenth transistor T10 and the seventh transistor T7 are turned on, and the other transistors are turned off. The signal of the second reset signal input terminal VI2 is transmitted to the second node Q2, and the signal VDD of the high potential end is transmitted to the first node Q1, that is, the gate of the third transistor T1, to complete the capture of the threshold voltage Vth of the third transistor T1. At the same time, the signal of the first reset signal input terminal VI1 is transmitted to the fifth node C to complete the resetting of the anode of the light-emitting device.

[0160] Second stage: the first light-emitting control signal input terminal EM1 and the third scan signal input terminal PSCAN2 keep outputting high-level signals, the signal input by the fourth scan signal input terminal PSCAN changes to a high-level signal after being kept as a low-level signal for a period of time, the second scan signal input terminal PSCAN1 changes from a high level to a low level and then to a high level, the ninth transistor T2 and the second transistor T9 are turned on, the data signal DATA is written to the second node Q2, and at the same time, the data signal is coupled to the first node Q1 through the first capacitor C2.

[0161] Phase 3: The first light-emitting control signal EM1 changes from a high level to a low level, the third scan signal input terminal PSCAN2, the fourth scan signal input terminal PSCAN3 and the second scan signal input terminal PSCAN1 output high-level signals, and the sixth transistor T6 is turned on, causing the light-emitting device to emit light.

[0162] Correspondingly, an embodiment of the present application further provides a display panel, which includes the organic electroluminescent display panel as described in any one of the above embodiments.

[0163] Of course, the present application may have many other embodiments. Without departing from the spirit and essential points of the present application, technicians familiar with the field may make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

Claims

1. An organic electroluminescent display panel, characterized in that: The organic electroluminescent display panel includes a plurality of pixel units, each of which includes at least: a light emitting device; Two first-type transistors, the two first-type transistors including a first transistor and a second transistor, one of a source and a drain of the first transistor being electrically connected to a first node of the pixel unit, and one of a source and a drain of the second transistor being electrically connected to a second node of the pixel unit; a first capacitor, wherein one plate of the first capacitor is electrically connected to the first node, and another plate of the first capacitor is electrically connected to the second node; a plurality of second-type transistors, the plurality of second-type transistors including at least three sections of transistors, a first section of the at least three sections of transistors including a third transistor, one of a source and a drain of the third transistor being electrically connected to the light-emitting device, a gate of the third transistor being electrically connected to the first node, a second section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the first transistor, and a third section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the second transistor; and a plurality of first scan signal input terminals, a plurality of second scan signal input terminals, a plurality of third scan signal input terminals, a plurality of fourth scan signal input terminals, a plurality of first reset signal input terminals, a plurality of second reset signal input terminals, a plurality of third reset signal input terminals, a plurality of fourth reset signal input terminals, a plurality of first light emission control signal input terminals, a plurality of second light emission control signal input terminals, a plurality of high potential terminals, a plurality of low potential terminals, and a plurality of data signal input terminals; wherein the first scan signal input terminal is electrically connected to the gate of the first transistor and the gate of the second transistor, the first node is electrically connected to one of the source and the drain of the first transistor, a portion of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the first transistor, the second node is electrically connected to one of the source and the drain of the second transistor, and another portion of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the second transistor; A portion of the plurality of second-type transistors includes: a third transistor, wherein a gate of the third transistor is electrically connected to the first node, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the third scan signal input terminal, one of a source and a drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the second light-emitting control signal input terminal, one of a source and a drain of the fifth transistor is electrically connected to the high potential terminal, and the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the first light-emitting control signal input terminal, one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected to the first terminal of the light-emitting device; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the fourth scan signal input terminal, one of a source and a drain of the eighth transistor is electrically connected to the third reset signal input terminal, and the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor; Another portion of the plurality of second-type transistors includes: a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the second scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the second transistor; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second light-emitting control signal input terminal, one of a source and a drain of the tenth transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the second transistor; Wherein, in the first time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal remains a low-level signal, the signals inputted by the second light-emitting control signal input terminal and the first scan signal input terminal change from a low-level signal to a high-level signal, the signals inputted by the second scan signal input terminal and the fourth scan signal input terminal remain high-level signals, and the signal inputted by the third scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the first transistor, the fourth transistor, the sixth transistor, and the second transistor are turned on; In the second time period, the signals input to the first light-emitting control signal input terminal, the first scan signal input terminal, the second scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals; the second light-emitting control signal input to the second light-emitting control signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the fifth transistor, the second transistor, and the tenth transistor are turned on; In a third time period, the signals inputted to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the first scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals, and the second scan signal inputted to the second scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the second transistor, the first transistor, and the ninth transistor are turned on; During a fourth time period, the signals input to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the second scan signal input terminal, and the third scan signal input terminal are high-level signals, and the signals input to the fourth scan signal input terminal and the first scan signal input terminal are changed from high-level signals to low-level signals, so that the eighth transistor is turned on; In the fifth time period, the signals input to the first light-emitting control signal input terminal and the second light-emitting control signal input terminal are changed from a high level to a low level signal, the first scan signal input to the first scan signal input terminal remains a low level signal, the signals input to the second scan signal input terminal and the third scan signal input terminal are high level signals, and the fourth scan signal input to the fourth scan signal input terminal is changed from a low level to a high level signal, so that the fifth transistor and the sixth transistor are turned on, and the light-emitting element emits light.

2. The organic electroluminescent display panel according to claim 1, wherein: The first type transistor is an oxide semiconductor thin film transistor or a dual-gate low-temperature polysilicon thin film transistor, and the second type transistor is a single-gate low-temperature polysilicon thin film transistor or an amorphous silicon thin film transistor.

3. An organic electroluminescent display panel, characterized in that: The organic electroluminescent display panel includes a plurality of pixel units, each of which includes at least: a light emitting device; Two first-type transistors, the two first-type transistors including a first transistor and a second transistor, one of a source and a drain of the first transistor being electrically connected to a first node of the pixel unit, and one of a source and a drain of the second transistor being electrically connected to a second node of the pixel unit; a first capacitor, wherein one plate of the first capacitor is electrically connected to the first node, and another plate of the first capacitor is electrically connected to the second node; a plurality of second-type transistors, the plurality of second-type transistors including at least three sections of transistors, a first section of the at least three sections of transistors including a third transistor, one of a source and a drain of the third transistor being electrically connected to the light-emitting device, a gate of the third transistor being electrically connected to the first node, a second section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the first transistor, and a third section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the second transistor; and a plurality of first scan signal input terminals, a plurality of second scan signal input terminals, a plurality of third scan signal input terminals, a plurality of fourth scan signal input terminals, a plurality of first reset signal input terminals, a plurality of second reset signal input terminals, a plurality of third reset signal input terminals, a plurality of fourth reset signal input terminals, a plurality of first light emission control signal input terminals, a plurality of second light emission control signal input terminals, a plurality of high potential terminals, a plurality of low potential terminals, and a plurality of data signal input terminals; wherein the first scan signal input terminal is electrically connected to the gate of the first transistor and the gate of the second transistor, the first node is electrically connected to one of the source and the drain of the first transistor, a portion of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the first transistor, the second node is electrically connected to one of the source and the drain of the second transistor, and another portion of the plurality of second-type transistors is electrically connected to the other of the source and the drain of the second transistor; A portion of the plurality of second-type transistors includes: a third transistor, wherein a gate of the third transistor is electrically connected to the first node, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the third scan signal input terminal, one of a source and a drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the second light-emitting control signal input terminal, one of a source and a drain of the fifth transistor is electrically connected to the high potential terminal, and the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the first light-emitting control signal input terminal, one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected to the first terminal of the light-emitting device; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the fourth scan signal input terminal, one of a source and a drain of the eighth transistor is electrically connected to the third reset signal input terminal, and the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor; Another portion of the plurality of second-type transistors includes: a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the second scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the second transistor; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second light-emitting control signal input terminal, one of a source and a drain of the tenth transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the second transistor; A portion of the plurality of second-type transistors further includes: a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the third scan signal input terminal, one of a source and a drain of the seventh transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the seventh transistor is electrically connected to the first terminal of the light-emitting device; Wherein, in the first time period, the signals inputted to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, and the first scan signal input terminal are changed from low-level signals to high-level signals, the signals inputted to the second scan signal input terminal and the fourth scan signal input terminal are kept as high-level signals, and the signal inputted to the third scan signal input terminal is changed from a high-level signal to a low-level signal and then to a high-level signal, so that the first transistor, the fourth transistor, the seventh transistor, and the second transistor are turned on; In the second time period, the signals input to the first light-emitting control signal input terminal, the first scan signal input terminal, the second scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals; the second light-emitting control signal input to the second light-emitting control signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the fifth transistor, the second transistor, and the tenth transistor are turned on; In a third time period, the signals inputted to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the first scan signal input terminal, the third scan signal input terminal, and the fourth scan signal input terminal are high-level signals, and the second scan signal inputted to the second scan signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, so that the second transistor, the first transistor, and the ninth transistor are turned on; During a fourth time period, the signals input to the first light-emitting control signal input terminal, the second light-emitting control signal input terminal, the second scan signal input terminal, and the third scan signal input terminal are high-level signals, and the signals input to the fourth scan signal input terminal and the first scan signal input terminal are changed from high-level signals to low-level signals, so that the eighth transistor is turned on; In the fifth time period, the signals input to the first light-emitting control signal input terminal and the second light-emitting control signal input terminal are changed from a high level to a low level signal, the first scan signal input to the first scan signal input terminal remains a low level signal, the signals input to the second scan signal input terminal and the third scan signal input terminal are high level signals, and the fourth scan signal input to the fourth scan signal input terminal is changed from a low level to a high level signal, so that the fifth transistor and the sixth transistor are turned on, and the light-emitting element emits light.

4. The organic electroluminescent display panel according to claim 3, wherein: The third scan signal input terminal is electrically connected to the gate of the first transistor, the first node is electrically connected to one of the source and the drain of the first transistor, and some of the plurality of second-type transistors are electrically connected to the other of the source and the drain of the first transistor; The fourth scan signal input terminal is electrically connected to the gate of the second transistor, the second node is electrically connected to one of the source and the drain of the second transistor, and another part of the multiple second-type transistors is electrically connected to the other one of the source and the drain of the second transistor.

5. An organic electroluminescent display panel, characterized in that: The organic electroluminescent display panel includes a plurality of pixel units, each of which includes at least: a light emitting device; Two first-type transistors, the two first-type transistors including a first transistor and a second transistor, one of a source and a drain of the first transistor being electrically connected to a first node of the pixel unit, and one of a source and a drain of the second transistor being electrically connected to a second node of the pixel unit; a first capacitor, wherein one plate of the first capacitor is electrically connected to the first node, and another plate of the first capacitor is electrically connected to the second node; a plurality of second-type transistors, the plurality of second-type transistors including at least three sections of transistors, a first section of the at least three sections of transistors including a third transistor, one of a source and a drain of the third transistor being electrically connected to the light-emitting device, a gate of the third transistor being electrically connected to the first node, a second section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the first transistor, and a third section of the at least three sections of transistors being electrically connected to the other of the source and the drain of the second transistor; and A portion of the plurality of second-type transistors includes: a third transistor, wherein a gate of the third transistor is electrically connected to the first node, and one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the first light-emitting control signal input terminal, one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the sixth transistor is electrically connected to the first terminal of the light-emitting device; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the fourth scan signal input terminal, one of a source and a drain of the seventh transistor is electrically connected to the first reset signal input terminal, and the other of the source and the drain of the seventh transistor is electrically connected to the first terminal of the light-emitting device; Another portion of the plurality of second-type transistors includes: a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the second scan signal input terminal, one of a source and a drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the second transistor; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the third scan signal input terminal, one of a source and a drain of the tenth transistor is electrically connected to the second reset signal input terminal, and the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the second transistor; In a first time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal changes from a low-level signal to a high-level signal, the second scanning signal inputted by the second scanning signal input terminal remains at a high-level signal, the third scanning signal inputted by the third scanning signal input terminal changes from a high-level signal to a low-level signal and then to a high-level signal, and the fourth scanning signal inputted by the fourth scanning signal input terminal changes from a high-level signal to a low-level signal, so that the first transistor, the second transistor, the tenth transistor, and the seventh transistor are turned on; In the second time period, the first light-emitting control signal inputted to the first light-emitting control signal input terminal remains at a high level signal, the second scanning signal inputted to the second scanning signal input terminal changes from a high level signal to a low level signal and then to a high level signal, the third scanning signal inputted to the third scanning signal input terminal remains at a high level signal, and the fourth scanning signal inputted to the fourth scanning signal input terminal changes from a low level signal to a high level signal, so that the second transistor and the ninth transistor are turned on; In the third time period, the first light-emitting control signal inputted by the first light-emitting control signal input terminal changes from a high-level signal to a low-level signal, and the signals inputted by the second scan signal input terminal, the third scan signal input terminal and the fourth scan signal input terminal remain high-level signals, so that the sixth transistor is turned on and the light-emitting element emits light.

Images