Array substrate and display panel

Abstract

This invention discloses an array substrate and a display panel. The array substrate includes scan lines, signal lines, and common electrodes disposed above a substrate. The common electrodes are slit electrodes in the pixel region, and the slit electrodes have multiple common electrode strips. The slit electrodes are symmetrical about the double-domain boundary line of the pixel unit. The common electrode strip near the signal line is a first common electrode strip, which is parallel to the edge adjacent to the signal line. The first common electrode strip includes a first electrode portion and a second electrode portion arranged sequentially along a direction away from the double-domain boundary line. The common electrode strip near the first common electrode strip is a second common electrode strip, which includes a third electrode portion and a fourth electrode portion arranged sequentially along a direction away from the double-domain boundary line. On the convex side near the signal line, the distance between the ends of the first electrode portion and the third electrode portion near the double-domain boundary line is not less than the distance between the second electrode portion and the fourth electrode portion, so as to improve the Mura phenomenon.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Liquid crystal display (LCD) panels have advantages such as high image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, making them dominant in the flat panel display field. With the rapid development of display technology, touch display panels have become widely accepted and used, such as in smartphones and tablets. Touch display panels utilize embedded touch technology to combine the touch panel and LCD panel into one unit, embedding the touch panel functionality within the LCD panel, thus enabling the LCD panel to simultaneously display and sense touch input.

[0003] Depending on how the touch sensing layer is positioned within the display panel, touch display panels are categorized into add-on, in-cell, and on-cell structures. In-cell touchscreens integrate touch functionality into the display screen, effectively reducing the overall thickness of the display and simplifying the manufacturing process, resulting in thinner, lighter products with lower production costs, making them widely popular.

[0004] Currently, for in-cell touchscreens, the touchscreen structure is typically mounted directly on the array substrate. This mainly involves reusing structural components used for transmitting display signals within the array substrate as touch electrodes; a common approach is to reuse common electrode blocks as touch electrodes. For example... Figures 1-4 As shown, the array substrate needs to be equipped with not only scan lines 111 and data lines 131, but also touch traces 134. Common signals and touch signals are then transmitted to the common electrode block via the touch traces 134. To enhance the touch effect, the common electrode block is typically positioned above the pixel electrode 141, closer to the external environment. This necessitates the use of slit electrodes with multiple slits 152 in the corresponding pixel area. Each slit electrode has multiple common electrode strips 151, with slits 152 formed between adjacent common electrode strips 151, thus creating a fringe field switching (FFS) mode with the pixel electrode.

[0005] In existing technologies, to improve viewing angles, FFS mode display panels often employ dual-domain displays. To accommodate this dual-domain design, the common electrode needs to be adapted, often requiring bending of the common electrode strip 151 at the dual-domain boundary region, with the common electrode strip 151 symmetrical about the dual-domain boundary line D. In existing technologies, the bending position of the common electrode strip 151 near the signal lines (data line 131, touch trace 134) is usually the same as the bending position of the signal lines, while the bending positions of the common electrode strip 151 in other areas are different. This results in a significant difference in the width of the slit 152 near the signal lines in the dual-domain boundary region, causing differences in the liquid crystal driving electric field and leading to Mura (display unevenness) problems. Specifically, during normal pH exposure, due to insufficient equipment capacity resulting in poor resolution at the slit 152, the slit 152 near the convex side of the signal lines may appear smaller in the dual-domain boundary region. Figure 4 The problem is that the slit 152 near the concave side of the signal line is too large in the dual-domain boundary region. Figure 4 The problem with the dashed box (b) is that the Mura phenomenon caused by the smaller slit 152 is more obvious. Summary of the Invention

[0006] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate and a display panel to solve the problem that the width of the slits near the signal lines in the double-domain boundary region of the prior art is significantly different, causing differences in the liquid crystal driving electric field and resulting in Mura.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] The present invention provides an array substrate, comprising: a substrate; a plurality of scan lines, a plurality of signal lines, and a common electrode disposed above the substrate, wherein the plurality of scan lines and the plurality of signal lines intersect to define a plurality of pixel units, the common electrode being a slit electrode with a slit in the region corresponding to the pixel unit, the slit electrode having a plurality of common electrode strips, the slit being located between two adjacent common electrode strips, and both the common electrode strips and the slits being zigzag structures and symmetrical about the dual-domain boundary line of the pixel unit;

[0009] The common electrode strip near the signal line is a first common electrode strip. The first common electrode strip is parallel to the edge of the signal line. The first common electrode strip includes a first electrode portion and a second electrode portion arranged sequentially along the direction away from the double domain boundary line. The common electrode strip near the first common electrode strip is a second common electrode strip. The second common electrode strip includes a third electrode portion and a fourth electrode portion arranged sequentially along the direction away from the double domain boundary line. Any edge lines of the second electrode portion and the fourth electrode portion are parallel to each other. The corner between the first electrode portion and the second electrode portion and the corner between the third electrode portion and the fourth electrode portion and the corner away from the first common electrode strip are located on different straight lines.

[0010] On the convex side near the signal line, the distance between the first electrode portion and the third electrode portion near the end of the double domain boundary line is not less than the distance between the second electrode portion and the fourth electrode portion.

[0011] Furthermore, on the convex side near the signal line, the distance between the first electrode portion and the third electrode portion gradually increases in the direction toward the double-domain boundary line.

[0012] Furthermore, on the convex side near the signal line, the electrode width of the first electrode portion gradually decreases in the direction toward the double-domain boundary line; or / and the electrode width of the third electrode portion gradually decreases in the direction toward the double-domain boundary line.

[0013] Furthermore, on the concave side near the signal line, the distance between the first electrode portion and the third electrode portion near the end of the double domain boundary line is not greater than the distance between the second electrode portion and the fourth electrode portion.

[0014] Furthermore, on the concave side near the signal line, the distance between the first electrode portion and the third electrode portion gradually decreases in the direction toward the double-domain boundary line.

[0015] Furthermore, on the concave side near the signal line, the electrode width of the first electrode portion gradually increases in the direction toward the double-domain boundary line; or / and the electrode width of the third electrode portion gradually increases in the direction toward the double-domain boundary line.

[0016] Furthermore, on the convex and / or concave side near the signal line, the adjacent edges of the first electrode portion and the third electrode portion are parallel to each other, the distance between the first electrode portion and the third electrode portion is equal to the distance between the second electrode portion and the fourth electrode portion, and the corners between the first electrode portion and the second electrode portion facing the second common electrode strip and the corners between the third electrode portion and the fourth electrode portion facing the first common electrode strip are located on the same straight line parallel to the dual-domain boundary line.

[0017] Furthermore, the corner between the first electrode portion and the second electrode portion and on the side away from the second common electrode strip is located on a first straight line, and the corner between the third electrode portion and the fourth electrode portion and on the side away from the first common electrode strip is located on a second straight line. Both the first straight line and the second straight line are parallel to the dual-domain boundary line.

[0018] The corners between the first electrode portion and the second electrode portion and towards the second common electrode strip, as well as the corners between the third electrode portion and the fourth electrode portion and towards the first common electrode strip, are all located on the first straight line; or the corners between the first electrode portion and the second electrode portion and towards the second common electrode strip, as well as the corners between the third electrode portion and the fourth electrode portion and towards the first common electrode strip, are all located on the second straight line; or the corners between the first electrode portion and the second electrode portion and towards the second common electrode strip, as well as the corners between the third electrode portion and the fourth electrode portion and towards the first common electrode strip, are all located on the third straight line, which is located between the first straight line and the second straight line.

[0019] Furthermore, the signal line includes a data line and a touch trace, and the common electrode includes a plurality of common electrode blocks, each of which is electrically connected to the corresponding touch trace.

[0020] This application also provides a display panel, including the array substrate described above.

[0021] The beneficial effects of this invention are as follows: On the convex side near the signal line, by ensuring that the distance between the first electrode portion of the first common electrode strip and the third electrode portion of the second common electrode strip near the end of the double domain boundary line is not less than the distance between the second electrode portion and the fourth electrode portion, the difference in the slit width of the common electrode in the double domain boundary region is reduced, thereby reducing the difference in the liquid crystal driving electric field, improving the Mura phenomenon, increasing yield, and reducing cost. Attached Figure Description

[0022] Figure 1This is a schematic diagram of the planar structure of an array substrate in the prior art;

[0023] Figure 2 This is a schematic diagram of the planar structure of the array substrate without a common electrode in the prior art;

[0024] Figure 3 This is a schematic diagram of the planar structure of the common electrode and signal line in the prior art;

[0025] Figure 4 yes Figure 3 Enlarged structural diagram at point A;

[0026] Figure 5 This is a schematic diagram of the planar circuit structure of the common electrode in Embodiment 1 of the present invention;

[0027] Figure 6 This is a schematic diagram of the planar circuit structure of the array substrate in Embodiment 1 of the present invention;

[0028] Figure 7 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention;

[0029] Figure 8 This is a schematic diagram of the planar structure of the array substrate without a common electrode in Embodiment 1 of the present invention;

[0030] Figure 9 This is a schematic diagram of the planar structure of the common electrode and signal line in Embodiment 1 of the present invention;

[0031] Figure 10 yes Figure 9 Enlarged structural diagram at point C;

[0032] Figure 11 This is a schematic diagram of the planar structure of the first common electrode strip and the second common electrode strip in Embodiment 1 of the present invention;

[0033] Figure 12 In Embodiment 1 of the present invention, the array substrate along... Figure 7 Schematic diagram of the cross section in the BB direction;

[0034] Figures 13a to 13e This is a schematic diagram of the fabrication method of the array substrate in Embodiment 1 of the present invention;

[0035] Figure 14 In Embodiment 2 of the present invention Figure 9 Enlarged structural diagram of region C in the middle;

[0036] Figure 15 In Embodiment 3 of the present invention Figure 9 Enlarged structural diagram of region C in the middle;

[0037] Figure 16In Embodiment 4 of the present invention Figure 9 Enlarged structural diagram of region C in the middle;

[0038] Figure 17 In Embodiment 5 of the present invention Figure 9 Enlarged structural diagram of region C in the middle;

[0039] Figure 18 In Embodiment Six of the present invention Figure 9 Enlarged structural diagram of region C in the middle;

[0040] Figure 19 This is a schematic diagram of the display device in the dark state according to the present invention;

[0041] Figure 20 This is a schematic diagram of the display device in the bright state in this invention. Detailed Implementation

[0042] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and display panel proposed according to the present invention:

[0043] [Example 1]

[0044] Figure 5 This is a schematic diagram of the planar circuit structure of the common electrode in Embodiment 1 of the present invention. Figure 6 This is a schematic diagram of the planar circuit structure of the array substrate in Embodiment 1 of the present invention. Figure 7 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of the planar structure of the array substrate without a common electrode in Embodiment 1 of the present invention. Figure 9 This is a schematic diagram of the planar structure of the common electrode and signal line in Embodiment 1 of the present invention. Figure 10 yes Figure 9 A magnified structural diagram at point C. Figure 11 This is a schematic diagram of the planar structure of the first common electrode strip and the second common electrode strip in Embodiment 1 of the present invention. Figure 12 In Embodiment 1 of the present invention, the array substrate along... Figure 7 A schematic diagram of the cross-section in the BB direction.

[0045] like Figures 5 to 12As shown, an array substrate provided in Embodiment 1 of the present invention includes: a substrate 10, on which multiple scan lines 111, multiple signal lines, and a common electrode 15 are provided. The multiple scan lines 111 and multiple signal lines intersect to define multiple pixel units SP. In this embodiment, the signal lines include data lines 131 and touch traces 134. The touch traces 134 and data lines 131 are located on the same layer and are arranged alternately and parallel to each other. The common electrode 15 includes multiple common electrode blocks. Each common electrode block is electrically connected to a corresponding touch trace 134, that is, the extension direction of the touch trace 134 is parallel to the extension direction of the data line 131. Each common electrode block is electrically connected to a corresponding touch trace 134. A common signal and a touch signal are applied to the common electrode block through the touch trace 134, thereby enabling the common electrode block to be multiplexed as a touch electrode, thereby realizing in-cell touch. Multiple touch traces 134 can be electrically connected to the same common electrode block, i.e., multiple touch traces 134 are connected in parallel to each other, thereby reducing impedance. Of course, in other embodiments, the signal line can also refer to either the data line 131 or the touch trace 134.

[0046] The common electrode 15 is a slit electrode with a slit 152 in the region corresponding to the pixel unit SP. The slit electrode has multiple common electrode strips 151, and the slit 152 is located between two adjacent common electrode strips 151. Both the common electrode strips 151 and the slit 152 are zigzag structures and are symmetrical about the dual-domain boundary line D of the pixel unit SP, thereby enabling the display panel to achieve dual domains and improve the viewing angle. The boundary line between the upper and lower domains in each pixel unit SP is called the dual-domain boundary line D, which distinguishes the upper and lower domains of the pixel unit SP.

[0047] The common electrode strip 151 closest to the signal line is the first common electrode strip 1511. The first common electrode strip 1511 is parallel to the edge adjacent to the signal line. The first common electrode strip 1511 includes a first electrode portion 1511a and a second electrode portion 1511b arranged sequentially along a direction away from the double-domain boundary line D. The common electrode strip 151 closest to the first common electrode strip 1511 is the second common electrode strip 1512. The second common electrode strip 1512 includes a third electrode portion 1512a and a fourth electrode portion 1512b arranged sequentially along a direction away from the double-domain boundary line D. Any edge lines of the second electrode portion 1511b and the fourth electrode portion 1512b are parallel to each other, that is, the second electrode portion 1511b and the fourth electrode portion 1512b extend in the same direction. The angle between the first electrode portion 1511a and the double-domain boundary line D is smaller than the angle between the second electrode portion 1511b and the double-domain boundary line D, and the angle between the third electrode portion 1512a and the double-domain boundary line D is smaller than the angle between the fourth electrode portion 1512b and the double-domain boundary line D. For example... Figures 9-11As shown, the first common electrode strip 151 on the left and the first common electrode strip 151 on the right of the signal line (data line 131, touch trace 134) are both first common electrode strips 1511. The second common electrode strip 151 on the left and the second common electrode strip 151 on the right of the signal line are both second common electrode strips 1512. The common electrode strips 151 in other areas can be named third common electrode strips 1513. That is, in a pixel unit SP, the common electrode strip 151 located at the outermost edge of the pixel unit SP is the first common electrode strip 151, followed by the second common electrode strip 1512, and the common electrode strip 151 between the two second common electrode strips 1512 is the third common electrode strip 1513.

[0048] The corner between the first electrode section 1511a and the second electrode section 1511b, and on the side away from the second common electrode strip 1512, and the corner between the third electrode section 1512a and the fourth electrode section 1512b, and on the side away from the first common electrode strip 1511, are located on different straight lines. For example... Figure 10 As shown, the corner between the first electrode portion 1511a and the second electrode portion 1511b, on the side away from the second common electrode strip 1512, is located on the first straight line L1. The corner between the third electrode portion 1512a and the fourth electrode portion 1512b, on the side away from the first common electrode strip 1511, is located on the second straight line L2. Both the first straight line L1 and the second straight line L2 are parallel to the double-domain boundary line D. In this embodiment, the corners between the first electrode portion 1511a and the second electrode portion 1511b are all located on the first straight line L1, and the corners between the third electrode portion 1512a and the fourth electrode portion 1512b are all located on the second straight line L2. Optionally, the third common electrode strip 1513 has the same size and structure as the second common electrode strip 1512, that is, the corner positions of the third common electrode strip 1513 and the second common electrode strip 1512 are the same.

[0049] Furthermore, such as Figure 11As shown, the first common electrode strip 1511 further includes a fifth electrode portion 1511c, which is connected to the end of the second electrode portion 1511b away from the first electrode portion 1511a. That is, the first common electrode strip 1511 is formed by sequentially connecting the fifth electrode portion 1511c, the second electrode portion 1511b, the first electrode portion 1511a, the first electrode portion 1511a, the second electrode portion 1511b, and the fifth electrode portion 1511c. The second common electrode strip 1512 further includes a sixth electrode portion 1512c, which is connected to the end of the fourth electrode portion 1512b away from the third electrode portion 1512a. That is, the second common electrode strip 1512 is formed by sequentially connecting the sixth electrode portion 1512c, the fourth electrode portion 1512b, the third electrode portion 1512a, the third electrode portion 1512a, the fourth electrode portion 1512b, and the sixth electrode portion 1512c. The first common electrode strip 1511, the second common electrode strip 1512, the third common electrode strip 1513, and the signal line are generally parallel, with differences only in the corner position and angle near the dual-domain boundary region.

[0050] On the convex surface 13a near the signal line Figure 8 On the side of the signal line protruding towards the pixel unit SP (convex surface 13a), the distance between the first electrode portion 1511a and the third electrode portion 1512a near the end of the double-domain boundary line D is not less than (greater than or equal to) the distance between the second electrode portion 1511b and the fourth electrode portion 1512b. In this embodiment, on the side of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases in the direction towards the double-domain boundary line D. Compared with the prior art ( Figure 3 and Figure 4 In the case of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a is gradually increased in the direction towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, improves the Mura phenomenon, increases yield, and reduces cost.

[0051] In this embodiment, on the side of the convex surface 13a near the signal line, the electrode width of the first electrode portion 1511a gradually decreases towards the double-domain boundary line D, meaning that the edge lines on both sides of the first electrode portion 1511a are non-parallel lines. By reducing the electrode width of the first electrode portion 1511a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a.

[0052] like Figure 10 As shown, on the concave surface 13b near the signal line ( Figure 8 On the side of the signal line facing the recessed pixel unit SP (concave surface 13b), the distance between the first electrode portion 1511a and the third electrode portion 1512a near the double-domain boundary line D is not greater than (less than or equal to) the distance between the second electrode portion 1511b and the fourth electrode portion 1512b. In this embodiment, on the side of the concave surface 13b near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually decreases in the direction towards the double-domain boundary line D. Compared to the prior art ( Figure 3 and Figure 4 In the case of the concave surface 13b near the signal line, by gradually reducing the distance between the first electrode portion 1511a and the third electrode portion 1512a toward the double-domain boundary line D, the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region is reduced. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, further improves the Mura phenomenon, increases yield, and reduces cost.

[0053] In this embodiment, on the concave surface 13a side near the signal line, the electrode width of the first electrode portion 1511a gradually increases towards the double-domain boundary line D, meaning that the edge lines on both sides of the first electrode portion 1511a are non-parallel lines. By increasing the electrode width of the first electrode portion 1511a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually decreases towards the double-domain boundary line D, thereby reducing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a.

[0054] Furthermore, such as Figures 6 to 8 as well as Figure 12As shown, the pixel unit SP includes a pixel electrode 141 and a thin-film transistor 1. The pixel electrode 141 is electrically connected to the scan line 111 and data line 131 adjacent to the thin-film transistor 1 through the thin-film transistor 1. The thin-film transistor includes a gate 112, an active layer 121, a source 132, and a drain 133. The gate 112 and the scan line 111 are located on the same layer and electrically connected. The gate 112 and the active layer 121 are separated by a first insulating layer 101. The source 132 is electrically connected to the data line 131. The drain 133 is connected to the pixel electrode 141 through a first contact hole H1. Figure 13c Electrical connection, that is, the pixel electrode 141 is electrically connected to the corresponding data line 131 through the drain 133, the active layer 121 and the source 132 in sequence.

[0055] The common electrode 15 is disposed above the pixel electrode 141 and is insulated from each other by the second insulating layer 103. The common electrode 15 is a slit electrode with a slit 152 in the region corresponding to the pixel unit SP, and the pixel electrode 141 is a block electrode, thereby forming a fringe field switching (FFS) mode.

[0056] Furthermore, a planarization layer 102 is also provided on the substrate 10. The common electrode 15, the pixel electrode 141, and the second insulating layer 103 are all located above the planarization layer 102. The planarization layer 102 has a first contact hole H1 in the region corresponding to the drain electrode 133. Figure 13c The second insulating layer 103 and the planarization layer 102 have a second contact hole H2 in the area corresponding to the touch trace 134. Figure 13d The common electrode block is electrically connected to the corresponding touch trace 134 through the second contact hole H2.

[0057] Figures 13a to 13e This is a schematic diagram of the fabrication method of the array substrate in Embodiment 1 of the present invention. Figures 13a to 13e As shown, the method for fabricating the array substrate in this embodiment includes:

[0058] like Figure 13a As shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0059] A first metal layer 11 is formed above the substrate 10, and the first metal layer 11 is disposed directly on the upper surface of the substrate 10. The first metal layer 11 is etched using a first masking process to form patterned scan lines 111. Figure 8 The first metal layer 11 consists of a gate 112 and a scan line 111, which are electrically connected to the scan line 111. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0060] A first insulating layer 101 is formed above the first metal layer 11, covering the scan line 111 and the gate 112. The first insulating layer 101 is directly disposed on the upper surface of the substrate 10 and the first metal layer 11 and covers the scan line 111 and the gate 112. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0061] like Figure 13b As shown, a semiconductor layer 12 is formed above the first insulating layer 101. The semiconductor layer 12 is etched using a second masking process, forming an active layer 121 corresponding to the gate 112. The semiconductor layer 12 is made of amorphous silicon (a-Si) and doped amorphous silicon.

[0062] like Figure 13c As shown, a second metal layer 13 is formed above the first insulating layer 101 and the semiconductor layer 12, covering the first insulating layer 101 and the semiconductor layer 12. The second metal layer 13 is etched using a third masking process, forming patterned data lines 131, source electrodes 132, drain electrodes 133, and touch traces 134. The data lines 131 are electrically connected to the source electrodes 132, and the source electrodes 132 and drain electrodes 133 are electrically connected through the active layer 121. The touch traces 134 are parallel to and alternate with the data lines 131, meaning the extension direction of the touch traces 134 is parallel to the extension direction of the data lines 131. The second metal layer 131 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of these metals such as Al / Mo or Cu / Mo.

[0063] A planarization layer 102 is formed above the second metal layer 13, covering the data line 131, source 132, drain 133, touch trace 134, and active layer 121. The planarization layer 102 is etched using a fourth masking process, forming a first contact hole H1 in the region corresponding to the drain 133, through which the drain 133 is exposed. The material of the planarization layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0064] like Figure 13d As shown, a first transparent conductive layer 14 is formed above the planarization layer 102. The first transparent conductive layer 14 is etched using a fifth masking process. The first transparent conductive layer 14 forms a pixel electrode 141 corresponding to the pixel unit SP. The pixel electrode 141 is electrically contacted with the corresponding drain electrode 133 through the first contact hole H1. The material of the first transparent conductive layer 14 can be a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0065] A second insulating layer 103 is formed above the first transparent conductive layer 14, covering the pixel electrode 141. A sixth masking process is used to simultaneously etch the second insulating layer 103 and the planarization layer 102. The second insulating layer 103 and the planarization layer 102 form a second contact hole H2 in the region corresponding to the touch trace 134, and the touch trace 134 is exposed through the second contact hole H2. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0066] like Figure 13e As shown, a second transparent conductive layer is formed above the second insulating layer 103. The second transparent conductive layer is etched using a seventh masking process, forming a patterned common electrode 15. The common electrode 15 includes multiple common electrode blocks, each of which is electrically connected to a corresponding touch trace 134 through a second contact hole H2. In the region corresponding to a pixel unit SP pair, the common electrode block is a slit electrode with a slit 152. The slit electrode has multiple common electrode strips 151, and the slit 152 is located between two adjacent common electrode strips 151. Both the common electrode strips 151 and the slit 152 are zigzag structures and symmetrical about the dual-domain boundary line D of the pixel unit SP, thereby enabling the display panel to achieve dual domains and improve viewing angle. The material of the second transparent conductive layer can be a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0067] Among them, the common electrode strip 151 near the signal lines (data line 131, touch trace 134) is the first common electrode strip 1511. The first common electrode strip 1511 is parallel to the edge adjacent to the signal line. The first common electrode strip 1511 includes a first electrode portion 1511a and a second electrode portion 1511b arranged sequentially along the direction away from the double-domain boundary line D. The common electrode strip 151 near the first common electrode strip 1511 is the second common electrode strip 1512. The second common electrode strip 1512 includes a third electrode portion 1512a and a fourth electrode portion 1512b arranged sequentially along the direction away from the double-domain boundary line D. Any edge lines of the second electrode portion 1511b and the fourth electrode portion 1512b are parallel to each other, that is, the second electrode portion 1511b and the fourth electrode portion 1512b extend in the same direction. Reference Figures 9-11As shown, the first common electrode strip 151 on the left and the first common electrode strip 151 on the right of the signal line (data line 131, touch trace 134) are both first common electrode strips 1511. The second common electrode strip 151 on the left and the second common electrode strip 151 on the right of the signal line are both second common electrode strips 1512. The common electrode strips 151 in other areas can be named third common electrode strips 1513. That is, in a pixel unit SP, the common electrode strip 151 located at the outermost edge of the pixel unit SP is the first common electrode strip 151, followed by the second common electrode strip 1512, and the common electrode strip 151 between the two second common electrode strips 1512 is the third common electrode strip 1513.

[0068] The corner between the first electrode section 1511a and the second electrode section 1511b, and on the side away from the second common electrode strip 1512, and the corner between the third electrode section 1512a and the fourth electrode section 1512b, and on the side away from the first common electrode strip 1511, are located on different straight lines. (Reference) Figure 10 As shown, the corner between the first electrode portion 1511a and the second electrode portion 1511b, on the side away from the second common electrode strip 1512, is located on the first straight line L1. The corner between the third electrode portion 1512a and the fourth electrode portion 1512b, on the side away from the first common electrode strip 1511, is located on the second straight line L2. Both the first straight line L1 and the second straight line L2 are parallel to the double-domain boundary line D. In this embodiment, the corners between the first electrode portion 1511a and the second electrode portion 1511b are all located on the first straight line L1, and the corners between the third electrode portion 1512a and the fourth electrode portion 1512b are all located on the second straight line L2. Optionally, the third common electrode strip 1513 has the same size and structure as the second common electrode strip 1512, that is, the corner positions of the third common electrode strip 1513 and the second common electrode strip 1512 are the same.

[0069] Further, refer to Figure 11As shown, the first common electrode strip 1511 further includes a fifth electrode portion 1511c, which is connected to the end of the second electrode portion 1511b away from the first electrode portion 1511a. That is, the first common electrode strip 1511 is formed by sequentially connecting the fifth electrode portion 1511c, the second electrode portion 1511b, the first electrode portion 1511a, the first electrode portion 1511a, the second electrode portion 1511b, and the fifth electrode portion 1511c. The second common electrode strip 1512 further includes a sixth electrode portion 1512c, which is connected to the end of the fourth electrode portion 1512b away from the third electrode portion 1512a. That is, the second common electrode strip 1512 is formed by sequentially connecting the sixth electrode portion 1512c, the fourth electrode portion 1512b, the third electrode portion 1512a, the third electrode portion 1512a, the fourth electrode portion 1512b, and the sixth electrode portion 1512c. The first common electrode strip 1511, the second common electrode strip 1512, the third common electrode strip 1513, and the signal line are generally parallel, with differences only in the corner position and angle near the dual-domain boundary line D.

[0070] On the convex surface 13a near the signal line Figure 8 On the side of the signal line protruding towards the pixel unit SP (convex surface 13a), the distance between the first electrode portion 1511a and the third electrode portion 1512a near the end of the double-domain boundary line D is not less than the distance between the second electrode portion 1511b and the fourth electrode portion 1512b. In this embodiment, on the side of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases in the direction towards the double-domain boundary line D. Compared with the prior art ( Figure 3 and Figure 4 In the case of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a is gradually increased in the direction towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, improves the Mura phenomenon, increases yield, and reduces cost.

[0071] In this embodiment, on the side of the convex surface 13a near the signal line, the electrode width of the first electrode portion 1511a gradually decreases towards the double-domain boundary line D, meaning that the edge lines on both sides of the first electrode portion 1511a are non-parallel lines. By reducing the electrode width of the first electrode portion 1511a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a.

[0072] refer to Figure 10 As shown, on the concave surface 13b near the signal line ( Figure 8 On the side of the signal line facing the recessed pixel unit SP (concave surface 13b), the distance between the first electrode portion 1511a and the third electrode portion 1512a near the double-domain boundary line D is no greater than the distance between the second electrode portion 1511b and the fourth electrode portion 1512b. In this embodiment, on the side of the concave surface 13b near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually decreases in the direction towards the double-domain boundary line D. Compared to the prior art ( Figure 3 and Figure 4 In the case of the concave surface 13b near the signal line, by gradually reducing the distance between the first electrode portion 1511a and the third electrode portion 1512a toward the double-domain boundary line D, the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region is reduced. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, further improves the Mura phenomenon, increases yield, and reduces cost.

[0073] In this embodiment, on the concave surface 13a side near the signal line, the electrode width of the first electrode portion 1511a gradually increases towards the double-domain boundary line D, meaning that the edge lines on both sides of the first electrode portion 1511a are non-parallel lines. By increasing the electrode width of the first electrode portion 1511a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually decreases towards the double-domain boundary line D, thereby reducing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a.

[0074] [Example 2]

[0075] Figure 14 In Embodiment 2 of the present invention Figure 9 A magnified structural diagram of the region at point C. (See diagram below.) Figure 14 As shown, the array substrate provided in Embodiment 2 of the present invention is similar to that in Embodiment 1. Figures 5 to 12 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0076] On the convex surface 13a side near the signal line, the electrode width of the third electrode portion 1512a gradually decreases towards the double-domain boundary line D, meaning the edge lines on both sides of the third electrode portion 1512a are non-parallel lines. By reducing the electrode width of the third electrode portion 1512a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a. Compared to the prior art ( Figure 3 and Figure 4 In the case of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a is gradually increased in the direction towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, improves the Mura phenomenon, increases yield, and reduces cost.

[0077] Furthermore, on the concave side 13b near the signal line, the electrode width of the third electrode portion 1512a gradually increases towards the double-domain boundary line D, meaning the edge lines on both sides of the third electrode portion 1512a are non-parallel lines. By increasing the electrode width of the third electrode portion 1512a, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually decreases towards the double-domain boundary line D, thereby reducing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a. Compared to the prior art ( Figure 3 and Figure 4 In the case of the concave surface 13b near the signal line, by gradually reducing the distance between the first electrode portion 1511a and the third electrode portion 1512a toward the double-domain boundary line D, the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region is reduced. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, further improves the Mura phenomenon, increases yield, and reduces cost.

[0078] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0079] [Example 3]

[0080] Figure 15 In Embodiment 3 of the present invention Figure 9 A magnified structural diagram of the region at point C. (See diagram below.) Figure 15As shown, the array substrate provided in Embodiment 3 of the present invention is similar to that in Embodiment 1 ( Figures 5 to 12 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0081] On the convex surface 13a side near the signal line, the electrode width of the first electrode portion 1511a gradually decreases towards the double-domain boundary line D, and the electrode width of the third electrode portion 1512a also gradually decreases towards the double-domain boundary line D. That is, the edge lines on both sides of the first electrode portion 1511a and the third electrode portion 1512a are non-parallel lines. By reducing the electrode widths of the first electrode portion 1511a and the third electrode portion 1512a, the distance between them gradually increases towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a. Compared to the prior art (… Figure 3 and Figure 4 In the case of the convex surface 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a is gradually increased in the direction towards the double-domain boundary line D, thereby increasing the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, improves the Mura phenomenon, increases yield, and reduces cost.

[0082] Furthermore, on the concave surface 13a side near the signal line, the electrode width of the first electrode portion 1511a gradually increases towards the double-domain boundary line D, and the electrode width of the third electrode portion 1512a also gradually increases towards the double-domain boundary line D. That is, the edge lines on both sides of the first electrode portion 1511a and the third electrode portion 1512a are non-parallel lines. By increasing the electrode widths of the first electrode portion 1511a and the third electrode portion 1512a, the distance between them gradually decreases towards the double-domain boundary line D, thereby reducing the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a. Compared to the prior art (… Figure 3 and Figure 4 In the case of the concave surface 13b near the signal line, by gradually reducing the distance between the first electrode portion 1511a and the third electrode portion 1512a toward the double-domain boundary line D, the width of the slit 152 between the first common electrode strip 1511 and the second common electrode strip 1512 in the double-domain boundary region is reduced. This reduces the width difference of the slit 152 of the common electrode 15 in the double-domain boundary region, reduces the difference in the liquid crystal driving electric field in the double-domain boundary region, further improves the Mura phenomenon, increases yield, and reduces cost.

[0083] In this embodiment, on the convex surface 13a side near the signal line, the electrode widths of both the first electrode portion 1511a and the third electrode portion 1512a are gradually reduced in the direction towards the dual-domain boundary line D; and on the concave surface 13a side near the signal line, the electrode widths of both the first electrode portion 1511a and the third electrode portion 1512a are gradually increased in the direction towards the dual-domain boundary line D. This reduces the difference in electrode widths at both ends of the first electrode portion 1511a and the third electrode portion 1512a, making the electrode widths of the first electrode portion 1511a and the third electrode portion 1512a more uniform and further improving the dual-domain display effect.

[0084] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0085] [Example 4]

[0086] Figure 16 In Embodiment 4 of the present invention Figure 9 A magnified structural diagram of the region at point C. (See diagram below.) Figure 16 As shown, the array substrate provided in Embodiment 4 of the present invention is similar to that in Embodiment 1 ( Figures 5 to 12 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0087] On the convex surface 13a and concave surface 13a near the signal line, the adjacent edges of the first electrode portion 1511a and the third electrode portion 1512a are parallel to each other, that is, the adjacent edge structures of the first electrode portion 1511a and the third electrode portion 1512a are the same (e.g., the side length, corner position, corner direction, and corner size are all the same). The edge lines on both sides of the first electrode portion 1511a and the third electrode portion 1512a are parallel lines. Among them, the corner between the first electrode portion 1511a and the second electrode portion 1511b and the corner facing the second common electrode strip 1512, and the corner between the third electrode portion 1512a and the fourth electrode portion 1512b and the corner facing the first common electrode strip 1511, are all located on the same straight line parallel to the double domain boundary line D. The distance between the first electrode portion 1511a and the third electrode portion 1512a is equal to the distance between the second electrode portion 1511b and the fourth electrode portion 1512b, thereby ensuring that all slits 152 have the same width. This completely avoids width differences in the slits 152 of the common electrode 15 in the double-domain boundary region, preventing differences in the liquid crystal driving electric field in the double-domain boundary region, thus preventing the Mura phenomenon, improving yield, and reducing costs. Alternatively, in other embodiments, on the convex surface 13a side near the signal line, the adjacent edges of the first electrode portion 1511a and the third electrode portion 1512a may be parallel to each other; while on the concave surface 13b side near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a may gradually decrease towards the double-domain boundary line D. Alternatively, on the convex side 13a near the signal line, the distance between the first electrode portion 1511a and the third electrode portion 1512a gradually increases in the direction toward the double domain boundary line D; while on the concave side 13b near the signal line, the adjacent edges of the first electrode portion 1511a and the third electrode portion 1512a are parallel to each other.

[0088] In this embodiment, the corners between the first electrode portion 1511a and the second electrode portion 1511b and away from the second common electrode strip 1512, the corners between the first electrode portion 1511a and the second electrode portion 1511b and towards the second common electrode strip 1512, and the corners between the third electrode portion 1512a and the fourth electrode portion 1512b and towards the first common electrode strip 1511 are all located on the first straight line L1. The corner between the third electrode portion 1512a and the fourth electrode portion 1512b and away from the first common electrode strip 1511 is located on the second straight line L2. That is, in this embodiment, by reducing the electrode width of the third electrode portion 1512a, the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a is increased, so that the distance between the first electrode portion 1511a and the third electrode portion 1512a is equal to the distance between the second electrode portion 1511b and the fourth electrode portion 1512b.

[0089] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0090] [Example 5]

[0091] Figure 17 In Embodiment 5 of the present invention Figure 9 A magnified structural diagram of the region at point C. (See diagram below.) Figure 17 As shown, the array substrate provided in Embodiment 5 of the present invention is similar to that in Embodiment 4. Figure 16 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0092] The corner between the first electrode portion 1511a and the second electrode portion 1511b, away from the second common electrode strip 1512, is located on the first straight line L1. The corners between the first electrode portion 1511a and the second electrode portion 1511b, facing the second common electrode strip 1512, the corners between the third electrode portion 1512a and the fourth electrode portion 1512b, facing the first common electrode strip 1511, and the corners between the third electrode portion 1512a and the fourth electrode portion 1512b, away from the first common electrode strip 1511, are all located on the second straight line L2. That is, in this embodiment, by reducing the electrode width of the first electrode portion 1511a, the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a is increased, so that the distance between the first electrode portion 1511a and the third electrode portion 1512a is equal to the distance between the second electrode portion 1511b and the fourth electrode portion 1512b.

[0093] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 4, and will not be repeated here.

[0094] [Example 6]

[0095] Figure 18 In Embodiment Six of the present invention Figure 9 A magnified structural diagram of the region at point C. (See diagram below.) Figure 18 As shown, the array substrate provided in Embodiment Six of the present invention is similar to that in Embodiment Four ( Figure 16 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0096] The corner between the first electrode portion 1511a and the second electrode portion 1511b, away from the second common electrode strip 1512, is located on the first straight line L1. The corner between the third electrode portion 1512a and the fourth electrode portion 1512b, away from the first common electrode strip 1511, is located on the second straight line L2. The corners between the first electrode portion 1511a and the second electrode portion 1511b, and the corners between the third electrode portion 1512a and the fourth electrode portion 1512b, and the corners towards the first common electrode strip 1511, are all located on the third straight line L3. The third straight line L3 is located between the first straight line L1 and the second straight line L2. Optionally, the third straight line L3 is the center line between the first straight line L1 and the second straight line L2. In this embodiment, by reducing the electrode width of the first electrode portion 1511a and the third electrode portion 1512a, the width of the slit 152 between the first electrode portion 1511a and the third electrode portion 1512a is increased, so that the distance between the first electrode portion 1511a and the third electrode portion 1512a is equal to the distance between the second electrode portion 1511b and the fourth electrode portion 1512b.

[0097] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 4, and will not be repeated here.

[0098] Figure 19 This is a schematic diagram of the cross-sectional structure of the display device in the dark state in this invention. Figure 20 This is a schematic cross-sectional view of the display device in the present invention in the bright state. For example... Figure 19 and Figure 20 As shown, this application also provides a display panel, including the array substrate described above. The display panel includes a color filter substrate 20 disposed opposite to the array substrate and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20. An upper polarizer 41 is provided on the color filter substrate 20, and a lower polarizer 42 is provided on the array substrate. The transmission axis of the upper polarizer 41 and the transmission axis of the lower polarizer 42 are perpendicular to each other. The liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy). In the initial state, the positive liquid crystal molecules are in a flat position, and the alignment direction of the positive liquid crystal molecules near the color filter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules near the array substrate. It can be understood that the array substrate and the color filter substrate 20 also have an alignment layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.

[0099] In this embodiment, the color filter substrate 20 is provided with a black matrix 21 and a color resist layer 22. The black matrix 21 corresponds to the scan line 111, data line 131, touch line 134, thin film transistor 1, and the peripheral non-display area. The black matrix 21 separates multiple color resist layers 22. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, and correspondingly forms red (R), green (G), and blue (B) sub-pixels.

[0100] like Figure 19 and Figure 20 As shown, the present invention also provides a display device, including a display panel as described above and a backlight module 50, wherein the backlight module 50 is located below the display panel and is used to provide a backlight source for the display panel.

[0101] The backlight module 50 includes a backlight source 51 and a privacy layer 52, which reduces the range of light emission angles. A brightness enhancement film 53 is also provided between the backlight source 51 and the privacy layer 52, increasing the brightness of the backlight module 50. The privacy layer 52 acts like a miniature venetian blind, blocking light with a large incident angle while allowing light with a smaller incident angle to pass through, thus reducing the range of light angles passing through the privacy layer 52. The privacy layer 52 includes multiple parallel light-blocking walls and light-transmitting holes located between adjacent light-blocking walls. Light-absorbing material is provided on both sides of the light-blocking walls. Alternatively, the backlight source 51 can be a light-collecting backlight, eliminating the need for a privacy layer 52; however, light-collecting backlights are more expensive than conventional backlights.

[0102] The backlight module 50 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect.

[0103] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0104] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, include: Substrate (10); multiple scan lines (111), multiple signal lines, and a common electrode (15) are disposed above the substrate (10). The multiple scan lines (111) and the multiple signal lines intersect to define multiple pixel units (SP). The common electrode (15) is a slit electrode with a slit (152) in the region corresponding to the pixel unit (SP). The slit electrode has multiple common electrode strips (151). The slit (152) is located between two adjacent common electrode strips (151). The common electrode strips (151) and the slit (152) are both zigzag structures and are symmetrical about the double domain boundary line (D) of the pixel unit (SP). The common electrode strip (151) near the signal line is a first common electrode strip (1511). The first common electrode strip (1511) is parallel to the edge adjacent to the signal line. The first common electrode strip (1511) includes a first electrode portion (1511a) and a second electrode portion (1511b) arranged sequentially along a direction away from the double domain boundary line (D). The common electrode strip (151) near the first common electrode strip (1511) is a second common electrode strip (1512). The second common electrode strip (1512) is arranged along a direction away from the double domain boundary line (D). The direction of the dividing line (D) includes a third electrode portion (1512a) and a fourth electrode portion (1512b) arranged sequentially. Any edge lines of the second electrode portion (1511b) and the fourth electrode portion (1512b) are parallel to each other. The corner between the first electrode portion (1511a) and the second electrode portion (1511b) and away from the second common electrode strip (1512) is on a different straight line from the corner between the third electrode portion (1512a) and the fourth electrode portion (1512b) and away from the first common electrode strip (1511). On the convex side (13a) near the signal line, the distance between the first electrode portion (1511a) and the third electrode portion (1512a) near the end of the double domain boundary line (D) is greater than the distance between the second electrode portion (1511b) and the fourth electrode portion (1512b); on the concave side (13b) near the signal line, the distance between the first electrode portion (1511a) and the third electrode portion (1512a) near the end of the double domain boundary line (D) is less than the distance between the second electrode portion (1511b) and the fourth electrode portion (1512b).

2. The array substrate according to claim 1, characterized in that, On the side of the convex surface (13a) near the signal line, the distance between the first electrode portion (1511a) and the third electrode portion (1512a) gradually increases in the direction toward the double domain boundary line (D).

3. The array substrate according to claim 2, characterized in that, On the side of the convex surface (13a) near the signal line, the electrode width of the first electrode portion (1511a) gradually decreases in the direction toward the double domain boundary line (D); or / and the electrode width of the third electrode portion (1512a) gradually decreases in the direction toward the double domain boundary line (D).

4. The array substrate according to claim 1, characterized in that, On the concave side (13b) near the signal line, the distance between the first electrode portion (1511a) and the third electrode portion (1512a) gradually decreases in the direction toward the double domain boundary line (D).

5. The array substrate according to claim 4, characterized in that, On the concave side (13b) near the signal line, the electrode width of the first electrode portion (1511a) gradually increases in the direction toward the double domain boundary line (D); or / and the electrode width of the third electrode portion (1512a) gradually increases in the direction toward the double domain boundary line (D).

6. The array substrate according to any one of claims 1-5, characterized in that, The signal lines include data lines (131) and touch traces (134). The common electrode (15) includes multiple common electrode blocks, each of which is electrically connected to the corresponding touch trace (134).

7. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-6.

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