Display panel, manufacturing method and display device

Abstract

The present application belongs to the field of display technology, and specifically relates to a display panel, a preparation method and a display device, wherein the display panel comprises a substrate, a transistor provided on the substrate, a first protective structure, a gold terminal and a second protective structure, wherein the first protective structure is provided on a side of the insulating dielectric layer away from the substrate, and the first protective structure is provided with a via; the gold terminal is provided on a side of the first protective structure away from the substrate, and the gold terminal is connected to the first electrode through the via, and the second protective structure is provided on a side of the first protective structure away from the first protective structure, and the second protective structure is provided with a groove, and the groove exposes at least part of the gold terminal. The present application scheme utilizes the second protective structure to prevent the transistor device from being corroded and damaged during the gold process, and can also effectively limit the area of ​​the gold terminal, thereby improving the stability of the gold process.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display panel, a preparation method and a display device. Background Art

[0002] Oxide semiconductor thin-film transistors have the advantages of high mobility, good stability, and simple manufacturing process. Oxide semiconductor materials represented by indium gallium zinc oxide (IGZO) are widely used in fields such as thin-film transistor liquid crystal displays (TFT LCDs) and active-matrix organic light-emitting diode panels (AMOLEDs).

[0003] Thin-film transistors (TFTs) can be divided into top-gate and bottom-gate structures based on the position of the gate electrode relative to the semiconductor layer. Regardless of whether they are bottom-gate or top-gate, metal oxide semiconductor (MOS) display panels used in sub-millimeter light-emitting diodes (Mini LEDs) face the high temperature, high humidity, and acidic environment of the post-processing gold deposition process. If microcracks in the film layer of the metal oxide display panel device are caused by stress or other reasons, the gold deposition process can cause electrical failure of the device and corrosion of the metal wiring, leading to display failure. Summary of the Invention

[0004] The purpose of this application is to provide a display panel, a manufacturing method and a display device, which can ensure the integrity of transistor devices and ensure the display effect of the display panel.

[0005] According to a first aspect of the present application, a display panel is provided. The display panel includes a base substrate and a transistor disposed on the base substrate. The transistor includes a gate, a semiconductor layer, a first electrode, and a second electrode. The gate is disposed on a side of the semiconductor layer close to the base substrate, and an insulating dielectric layer is disposed between the gate and the semiconductor layer. The semiconductor layer is disposed on a side of the insulating dielectric layer away from the base substrate, and the first electrode and the second electrode are disposed on opposite sides of the semiconductor layer, respectively. The display panel further includes:

[0006] a first protective structure, the first protective structure being provided on a side of the insulating dielectric layer away from the base substrate, the first protective structure being provided with a via hole;

[0007] A gold terminal is provided on a side of the first protection structure away from the base substrate, and the gold terminal is connected to the first electrode through the via hole.

[0008] The second protective structure is provided on a side of the first protective structure away from the first protective structure, and the second protective structure is provided with a groove, wherein the groove exposes at least a portion of the gold terminal.

[0009] In an exemplary embodiment of the present application, the second protection structure includes at least two insulating protection layers, and the at least two insulating protection layers are sequentially arranged in a thickness direction of the base substrate.

[0010] In an exemplary embodiment of the present application, the second protective structure includes a first insulating protective layer, a second insulating protective layer and a third insulating protective layer arranged in sequence in the thickness direction of the base substrate, and the first insulating protective layer is arranged on the side of the first protective structure away from the base substrate.

[0011] In an exemplary embodiment of the present application, the first insulating protection layer and the third insulating protection layer include the same material;

[0012] The material of the second insulating protective layer is different from the materials of the first insulating protective layer and the third insulating protective layer.

[0013] In an exemplary embodiment of the present application, the first insulating protection layer / the third insulating protection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide;

[0014] The second insulating protective layer includes an organic film layer.

[0015] In an exemplary embodiment of the present application, in a direction from the first insulating protection layer to the third insulating protection layer: a cross-sectional area of ​​the groove gradually increases.

[0016] In an exemplary embodiment of the present application, the first protection structure includes at least two insulating protection layers.

[0017] In an exemplary embodiment of the present application, the display panel further includes a third protective structure, which is provided between the first protective structure and the second protective structure, and covers a portion of the gold terminal.

[0018] A second aspect of the present application provides a method for preparing a display panel as described in any one of the above items, the method comprising the following steps:

[0019] forming a first metal layer on a base substrate, and patterning the first metal layer to form a gate;

[0020] forming an insulating dielectric layer and a semiconductor layer in sequence on the substrate, wherein the insulating dielectric layer covers the gate;

[0021] Depositing a second metal layer on the insulating dielectric layer and the semiconductor layer, and patterning the second metal layer to form a first electrode and a second electrode;

[0022] forming a first protection structure on the insulating dielectric layer and the semiconductor layer, and opening a via hole in a portion corresponding to the first electrode, wherein the via hole leaks a portion of the first electrode;

[0023] Coating a third metal layer on the first protection structure and patterning the third metal layer to form the gold terminal, wherein the gold terminal is connected to the first electrode through the via hole;

[0024] A second protective structure is formed on the first protective structure, and a groove is opened at a portion corresponding to the electroplated gold terminal, wherein the groove exposes a portion of the electroplated gold terminal.

[0025] A third aspect of the present application provides a display device, comprising a light-emitting chip and any one of the display panels described above, wherein the light-emitting chip is connected to the gold terminal through the groove.

[0026] The display panel, preparation method, and display device of the present application have at least the following beneficial effects:

[0027] This display panel includes a base substrate, a transistor, a first protective structure, a gold terminal, and a second protective structure. The first protective structure is disposed on a side of the insulating dielectric layer away from the base substrate. The first protective structure is provided with a via, and the gold terminal is electrically connected to the first electrode through the via to transmit electrical signals through the gate electrode, the second electrode, the semiconductor layer, and the first electrode. The first protective structure can protect the gate electrode, the first electrode, the second electrode, the semiconductor layer, and the gate electrode. The second protective structure is disposed on a side of the first protective structure away from the base substrate. The second protective structure is provided with a groove, which exposes a portion of the gold terminal to facilitate electrical connection between the light-emitting chip in the sub-millimeter light-emitting diode and the gold terminal. This second protective structure can prevent corrosion and damage to the transistor device during the gold process, and can also effectively limit the area of ​​the gold terminal, thereby improving the stability of the gold process.

[0028] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0031] Figure 1 A schematic cross-sectional structure diagram of a display panel provided in the first, fifth, or sixth embodiment of the present application is shown;

[0032] Figure 2 A schematic diagram of a structure in which a gate is formed on a substrate provided in Embodiment 1, Embodiment 2, Embodiment 5 or Embodiment 6 of the present application is shown;

[0033] Figure 3 A schematic structural diagram of forming an insulating dielectric layer on a substrate provided in Embodiment 1, Embodiment 2, Embodiment 5 or Embodiment 6 of the present application is shown;

[0034] Figure 4 A schematic structural diagram of forming a semiconductor layer on an insulating dielectric layer provided in the first, second, fifth or sixth embodiment of the present application is shown;

[0035] Figure 5 A schematic structural diagram of forming a first electrode and a second electrode on an insulating dielectric layer provided in Embodiment 1, Embodiment 2, Embodiment 5 or Embodiment 6 of the present application is shown;

[0036] Figure 6 A schematic diagram of a structure in which a via hole is formed on the first protective structure provided in the first, second, fifth or sixth embodiment of the present application is shown;

[0037] Figure 7 A schematic diagram of the structure of forming a gold terminal in a via hole provided in the first, second, fifth or sixth embodiment of the present application is shown;

[0038] Figure 8 A schematic structural diagram showing a second protective structure formed on a first protective structure provided in Embodiment 1, Embodiment 5 or Embodiment 6 of the present application is shown;

[0039] Figure 9 A schematic structural diagram showing a third protective structure formed between the first protective structure and the second protective structure provided in the second, fifth or sixth embodiment of the present application is shown;

[0040] Figure 10 A schematic diagram showing the structure of a top-gate transistor provided in the third or sixth embodiment of the present application is shown;

[0041] Figure 11 A schematic structural diagram of forming a semiconductor layer on a first insulating dielectric layer provided in the third, fourth or sixth embodiment of the present application is shown;

[0042] Figure 12 A schematic structural diagram of forming a second insulating dielectric layer and a gate on the semiconductor layer provided in the third, fourth or sixth embodiment of the present application is shown;

[0043] Figure 13 A schematic structural diagram of forming a seventh insulating protective layer on the first insulating dielectric layer provided in the third, fourth or sixth embodiment of the present application is shown;

[0044] Figure 14 A schematic diagram of the structure of the connection between the first electrode and the second electrode and the semiconductor layer provided in the third, fourth or sixth embodiment of the present application is shown;

[0045] Figure 15 A schematic structural diagram showing a first protective structure formed on the seventh insulating protective layer provided in the third, fourth or sixth embodiment of the present application is shown;

[0046] Figure 16 A schematic structural diagram showing the connection between the gold-plated terminal and the first electrode provided in the third, fourth or sixth embodiment of the present application is shown;

[0047] Figure 17 A schematic structural diagram showing a second protective structure formed on a first protective structure provided in Embodiment 3, Embodiment 4 or Embodiment 6 of the present application is shown;

[0048] Figure 18 A schematic structural diagram of a third protective structure formed between the first protective structure and the second protective structure provided in the fourth or sixth embodiment of the present application is shown;

[0049] Figure 19 A schematic diagram of the process for preparing the display panel provided in Example 1, Example 5 or Example 6 of the present application is shown.

[0050] Description of reference numerals:

[0051] 10. Display panel; 100. Base substrate; 110. Transistor; 111. Gate; 112. Semiconductor layer; 113. First electrode; 114. Second electrode; 120. First protection structure; 121. Fourth insulating protection layer; 122. Fifth insulating protection layer; 123. Sixth insulating protection layer; 130. Gold terminal; 140. Second protection structure; 141. First insulating protection layer; 142. Second insulating protection layer; 143. Third insulating protection layer; 150. Via; 160. Insulating dielectric layer; 160a. First insulating dielectric layer; 160b. Second insulating dielectric layer; 170. Groove; 180. Third protection structure; 190. Seventh insulating protection layer. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0053] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0054] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0055] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0056] Example 1

[0057] A first embodiment of the present application provides a display panel 10 , which may be a sub-millimeter light-emitting diode (Mini Light-Emitting Diode, Mini LED).

[0058] See also Figure 1As shown, the display panel 10 may include a base substrate 100, a transistor 110, a first protective structure 120, a gold terminal 130, and a second protective structure 140. The transistor 110 is provided on the base substrate 100 and includes a gate 111, a semiconductor layer 112, and a first electrode 113 and a second electrode 114 provided on the same layer. The first protective structure 120 is provided with a via 150, which exposes a portion of the first electrode 113 to facilitate electrical connection between the gold terminal 130 and the first electrode 113, and to achieve transmission of electrical signals through the gate 111, the second electrode 114, the semiconductor layer 112, and the first electrode 113. The gold terminal 130 is electrically connected to the light-emitting chip. To prevent damage to the components in the transistor 110 during the gold deposition process, the second protective structure 140 protects the components of the transistor 110, preventing the components of the transistor 110 from being corroded by the chemical solution during the gold deposition process. It can effectively limit the area of ​​the gold terminal 130 and improve the stability of the gold deposition process.

[0059] The structure of the display panel 10 will be described in detail below with reference to the accompanying drawings:

[0060] The display panel 10 may include a base substrate 100 , and the base substrate 100 may be made of any one of plastic, FR-4 grade material, resin, glass, quartz, polyimide, or polymethyl methacrylate (PMMA).

[0061] The display panel 10 may further include a plurality of sub-pixels, and the plurality of sub-pixels may be arranged in an array along row and column directions on the base substrate 100 .

[0062] The display panel 10 may further include a plurality of transistors 110 disposed on the base substrate 100 , where each transistor 110 corresponds to a sub-pixel.

[0063] Transistor 110 includes a gate 111, a semiconductor layer 112, and a first electrode 113 and a second electrode 114 disposed in the same layer. An insulating dielectric layer 160 may be disposed between gate 111 and semiconductor layer 112 to insulate gate 111 from semiconductor layer 112. The first electrode 113 and the second electrode 114 may be connected to the source and drain doped regions of semiconductor layer 112, respectively. The specific connection relationship between the first electrode 113 and the second electrode 114 and the source and drain doped regions of semiconductor layer 112 is determined by whether transistor 110 is N-type or P-type, and is not described in detail here.

[0064] For example, if Figures 2 to 5As shown, the transistor 110 of the embodiment of the present application may be a bottom-gate type, that is, the gate 111 may be first formed on the substrate 100; then, an insulating dielectric layer 160 is formed on the substrate 100, and this insulating dielectric layer 160 covers the gate 111; then, a semiconductor layer 112 is formed on the side of the insulating dielectric layer 160 away from the substrate 100, that is, the semiconductor layer 112 is located on the side of the gate 111 away from the substrate 100, and the semiconductor layer 112 overlaps with the orthographic projection of the gate 111 on the substrate 100; for example, the orthographic projection of the semiconductor layer 112 on the substrate 100 may be located within the orthographic projection of the gate 111 on the substrate 100. The first electrode 113 and the second electrode 114 can be formed after the semiconductor layer 112 is formed. At least a portion of the first electrode 113 can overlap on one doped region of the source and drain doped regions of the semiconductor layer 112; at least a portion of the second electrode 114 can overlap on the other doped region of the source and drain doped regions of the semiconductor layer 112.

[0065] The gate 111 can be configured as a single-layer, double-layer, or multi-layer metal composite or a single metal. Metal alloys or single metal elements include, but are not limited to, copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), and magnesium (Mg). The gate 111 is formed by depositing a first metal layer on the substrate 100 via magnetron sputtering and patterning the first metal layer. This patterning process includes resist coating, exposure, development, and wet etching.

[0066] After forming the gate 111 on the substrate 100, an insulating dielectric layer 160 is formed on the surface of the gate 111 using a chemical vapor deposition method. The insulating dielectric layer 160 includes at least two of silicon oxide, silicon nitride, and silicon oxynitride; that is, the insulating dielectric layer 160 is a composite film layer composed of at least the aforementioned silicon oxide, silicon nitride, and silicon oxynitride materials.

[0067] The insulating dielectric layer 160 is made of silicon nitride or silicon oxynitride near the gate 111 , and is made of silicon oxide near the top.

[0068] Furthermore, a metal oxide semiconductor is deposited on the insulating dielectric layer 160 by magnetron sputtering and patterned to form a semiconductor layer 112. Elements contained in the semiconductor layer 112 include, but are not limited to, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The carrier concentration of the semiconductor layer 112 is 5 to 30 cm2 / V*s.

[0069] It should be noted that a metal oxide semiconductor film is formed on the insulating dielectric layer 160, which is then coated, exposed, and developed. The metal oxide semiconductor is then patterned by wet etching and stripping. Finally, the patterned substrate 100 is annealed at a temperature of 350-500°C for 30-65 minutes. The annealing temperature can be 350°C, 400°C, 450°C, or 500°C, and the annealing time can be 30 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, or 65 minutes, etc.

[0070] Furthermore, a second metal layer is deposited on the insulating dielectric layer 160 using magnetron sputtering and patterned to form a first electrode 113 and a second electrode 114 disposed on the same layer. The first electrode 113 and the second electrode 114 are separated from each other and overlap the first electrode 113 and the second electrode 114 on opposite sides of the semiconductor layer 112.

[0071] It should be noted that, in this application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0072] Furthermore, the first electrode 113 and the second electrode 114 can be formed as a single layer, double layer, or multilayer metal alloy or single metal element. The metal alloy or single metal element includes copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and niobium (Nb). The second metal layer is then patterned by resist coating, exposure, development, and wet etching to obtain the first electrode 113 and the second electrode 114.

[0073] After forming the first pole 113 and the second pole 114, see Figure 6 As shown, a first protective structure 120 is formed on the insulating dielectric layer 160. The first protective structure 120 covers the first electrode 113, the second electrode 114 and the semiconductor layer 112 to protect the transistor 110 when the gold terminal 130 is subsequently prepared, thereby ensuring the integrity and stability of the transistor 110.

[0074] Among them, see Figure 6As shown, the first protection structure 120 is provided with a via hole 150 , and the via hole 150 can expose a portion of the first electrode 113 , so as to facilitate the subsequent electrical connection between the gold terminal 130 and the first electrode 113 , thereby realizing data transmission.

[0075] In the embodiment of the present application, the first protection structure 120 includes at least two insulating protection layers, which can not only play an insulating role but also protect the transistor 110 device.

[0076] See also Figure 6 As shown, the first protection structure 120 includes a fourth insulating protection layer 121, a fifth insulating protection layer 122, and a sixth insulating protection layer 123. After the first electrode 113 and the second electrode 114 are formed, the fourth insulating protection layer 121, the fifth insulating protection layer 122, and the sixth insulating protection layer 123 are sequentially deposited on their surfaces using chemical vapor deposition and coating methods. The fourth insulating protection layer 121 covers the insulating dielectric layer 160, the first electrode 113, the semiconductor layer 112, and the second electrode 114.

[0077] The fourth insulating protective layer 121 includes at least one of silicon oxide and silicon nitride, and may also be formed of other materials. After the fourth insulating protective layer 121 is formed, an annealing treatment is performed at a temperature of 240°C to 300°C for a time of 30 to 65 minutes. The annealing temperature may be 240°C, 260°C, 280°C, or 300°C, and the annealing time may be 30 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, or 65 minutes, etc.

[0078] Then, a fifth insulating protective layer 122 is coated on the fourth insulating protective layer 121 . The fifth insulating protective layer 122 is a photosensitive resin material with high sensitivity and high adhesion.

[0079] A sixth insulating protection layer 123 is deposited on the fifth insulating protection layer 122 . The sixth insulating protection layer 123 may be made of one or more structures selected from silicon oxide, silicon nitride, and an organic insulating film.

[0080] Finally, after performing resist coating, exposure, development, and dry etching on the fourth insulating protection layer 121 , the fifth insulating protection layer 122 , and the sixth insulating protection layer 123 , a via hole 150 is formed to expose a portion of the first electrode 113 , and the gold terminal 130 is connected to the first electrode 113 through the via hole 150 .

[0081] For further information, see Figure 7As shown, a third metal layer is coated on the sixth insulating protective layer 123 using magnetron sputtering, with a portion of the metal in the third metal layer falling into the via 150. The third metal layer is then patterned to form the gold terminal 130. The third metal layer comprises a composite structure of copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and niobium (Nb). The top layer of the gold terminal 130 is a copper film layer, which is used to deposit copper in the subsequent gold deposition process to facilitate subsequent soldering to the light-emitting chip.

[0082] The patterning process for the third metal layer includes coating the third metal layer with glue, exposing, developing, and wet etching and stripping.

[0083] See also Figure 8 As shown, to prevent damage to the transistor 110 during the gold deposition process, after the gold deposition terminal 130 is formed, a second protection structure 140 is formed on the gold deposition terminal 130. The second protection structure 140 has a groove 170, which exposes at least a portion of the gold deposition terminal 130 to facilitate connection between the gold deposition terminal 130 and the light-emitting chip to control the light emission of the light-emitting chip.

[0084] Among them, this second protection structure 140 includes at least two layers of insulating protection layers, and at least two layers of insulating protection layers are arranged in sequence in the thickness direction of the base substrate 100, so as to improve the protection effect of the transistor 110 device, ensure that the transistor 110 device will not be damaged during the gold deposition process, improve the working stability of the transistor 110, and thereby improve the display stability of the display panel 10.

[0085] In the examples of this application, see Figure 8 As shown, the second protection structure 140 includes a first insulating protection layer 141, a second insulating protection layer 142, and a third insulating protection layer 143, which are sequentially arranged in the thickness direction of the base substrate 100. The first insulating protection layer 141 is arranged on the side of the sixth insulating protection layer 123 away from the base substrate 100, and the first insulating protection layer 141 covers a portion of the gold terminal 130.

[0086] Among them, the first insulating protection layer 141 and the third insulating protection layer 143 include the same material, and the first insulating protection layer 141 and the third insulating protection layer 143 use a material different from the material of the second insulating protection layer 142 to improve the protection of the first electrode 113, the semiconductor layer 112, the gate 111 and the second electrode 114.

[0087] The first insulating protective layer 141 includes a single-layer film structure of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, or a combination of the above film layers, but is not limited thereto. The second insulating protective layer 142 is an organic film layer, which is mainly a photosensitive resin material of high sensitivity and high adhesion. The second insulating protective layer 142 mainly functions as a leveling agent to provide a smooth working surface for subsequent electroless gold processing and welding processes. The third insulating protective layer 143 includes a single-layer film structure of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, or a combination of the above film layers, but is not limited thereto. In other words, the first insulating protective layer 141 and the third insulating protective layer 143 are inorganic layers, and the second insulating protective layer 142 is an organic layer. The use of different film layers can improve the protective performance of the second protective structure 140 and can better protect the devices of the transistor 110.

[0088] The method of forming the above-mentioned groove 170 includes coating, exposure, development, dry etching and stripping. In addition, the cross-sectional area of ​​the groove 170 gradually increases in the direction from the first insulating protective layer 141 to the third insulating protective layer 143; that is, the aperture of the groove 170 gradually increases, such as Figure 8 As shown, the light emitting chip can be firmly fixed in the slot 170 and the light emitting chip will not be skewed, thereby ensuring the display effect.

[0089] It should be noted that the groove 170 can penetrate the three insulating protection layers by a single photolithography etching, and the process implementation is relatively easy.

[0090] The first insulating protective layer 141, the second insulating protective layer 142 and the third insulating protective layer 143 in this second protective structure 140 can improve the protection of the transistor 110 device, avoid electrical failure of the transistor 110 device and corrosion of the metal wiring under high temperature, high humidity and acidic conditions in the gold deposition process, ensure the integrity and stability of the transistor 110 device, and effectively limit the area of ​​the gold deposition terminal 130, thereby improving the stability of the gold deposition process.

[0091] Example 2

[0092] The difference between the second embodiment of the present application and the first embodiment is that the display panel 10 further includes a third protective structure 180, which is provided between the first insulating protective layer 141 and the sixth insulating protective layer 123. The third protective structure 180 covers a portion of the gold terminal 130. Figure 9 shown.

[0093] In the embodiment of the present application, the third protective structure 180 may be a metal oxide protective layer. The metal oxide protective layer may be made of the same material as the semiconductor layer 112. Elements contained in the metal oxide protective layer include, but are not limited to, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The primary function of the third protective structure 180 is to prevent the first insulating protective layer 141 from being directly deposited during the process of forming the gold terminal 130. This could result in the gold terminal 130 being susceptible to high temperatures and easily causing the film layer to fall off. This could result in the gold terminal 130 not being able to properly deposit copper, thereby affecting the soldering between the gold terminal 130 and the light-emitting chip.

[0094] It is understandable that if the first insulating protective layer 141 is formed using a low-temperature film forming process, the third protective structure 180 may not be added, thereby optimizing the thickness of the display panel 10 .

[0095] In addition, after the third protective structure 180, the first insulating protective layer 141, the second insulating protective layer 142, and the third insulating protective layer 143 are formed in sequence on the sixth insulating protective layer 123, the third protective structure 180, the first insulating protective layer 141, the second insulating protective layer 142, and the third insulating protective layer 143 are patterned by coating, exposing, developing, and dry etching to form a groove 170 that exposes a portion of the gold terminal 130.

[0096] Example 3

[0097] The difference between the third embodiment of the present application and the first embodiment is that the third embodiment adopts a top-gate transistor 110, see Figure 10 shown.

[0098] The manufacturing method of the top-gate transistor 110 is as follows:

[0099] First, a film is formed on the base substrate 100 by magnetron sputtering, and then a bottom gate electrode is formed by patterning treatments such as coating, exposure, development, and etching and stripping. The bottom gate electrode can be set to a single layer, double layer, or multilayer metal alloy or single metal. The metal alloy or single metal element includes copper Cu, molybdenum Mo, aluminum Al, titanium Ti, niobium Nb, and magnesium Mg.

[0100] Then, a first insulating dielectric layer 160a is formed on the bottom gate electrode by chemical vapor deposition. The first insulating dielectric layer 160a includes at least two of silicon oxide, silicon nitride, and silicon oxynitride; that is, the insulating dielectric layer 160 is at least a composite film layer composed of the above-mentioned silicon oxide, silicon nitride, and silicon oxynitride materials.

[0101] The first insulating dielectric layer 160a is made of one of silicon nitride and silicon oxynitride near the bottom gate electrode, and is made of a silicon oxide film near the top.

[0102] Then, a metal oxide semiconductor is formed on the surface of the first insulating dielectric layer 160a by magnetron sputtering. The semiconductor includes, but is not limited to, indium (In), gallium (Ga), zinc (Zn), oxygen (O), etc. Then, a patterned semiconductor layer 112 is formed by coating, exposing, developing, and etching. Figure 11 shown.

[0103] See Figure 12 As shown, a second insulating dielectric layer 160b is formed by chemical vapor deposition. This second insulating dielectric layer 160b includes a silicon oxide material. An annealing process is then performed at 260-340°C for 45-75 minutes. The annealing temperature can be 260°C, 280°C, 300°C, or 340°C, and the annealing time can be 45 minutes, 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, or 75 minutes. Then, resist coating, exposure, development, dry etching, and stripping are performed to form a perforated patterning process for the second insulating dielectric layer 160b.

[0104] See Figure 12 As shown, a first metal layer is formed on the first insulating dielectric layer 160a by magnetron sputtering and subjected to patterning processes such as photoresist coating, exposure, development, and etching to form a top gate electrode. This top gate electrode can be configured as a single-layer, double-layer, or multi-layer metal composite or a single metal. Metal alloys or single metal elements include, but are not limited to, copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), and magnesium (Mg). This top gate electrode is connected to the bottom gate electrode through patterned holes formed in the second insulating dielectric layer 160b.

[0105] The second insulating dielectric layer 160b is then etched using dry etching to expose the semiconductor layer 112 not covered by the top gate electrode. The exposed semiconductor layer 112 is then bombarded with gas plasma to perform a conductive treatment on the exposed semiconductor layer 112. The gas includes, but is not limited to, helium and argon, as long as it can perform a conductive treatment on the semiconductor layer 112.

[0106] See Figure 13 As shown, a seventh insulating protective layer 190 is finally formed on the first insulating dielectric layer 160a. This seventh insulating protective layer 190 covers the semiconductor layer 112, the second insulating dielectric layer 160b, and the top gate electrode. This seventh insulating protective layer 190 comprises at least one of silicon oxide and silicon nitride and can be a single layer or a composite layer. A process of resist coating, exposure, development, dry etching, and stripping is then performed to form a patterned opening in the seventh insulating protective layer 190, exposing portions of the semiconductor layer 112.

[0107] See Figure 14As shown, a second metal layer is then coated on the seventh insulating protective layer 190, and the second metal layer is subjected to patterning treatments such as coating, exposure, development, wet etching and stripping to form a first electrode 113 and a second electrode 114. The material of the first electrode 113 and the second electrode 114 is consistent with the material of the top gate electrode, and the first electrode 113 and the second electrode 114 are connected to the bottom semiconductor layer 112 through an opening.

[0108] See Figure 15 As shown, a first protection structure 120 is formed on the seventh insulating protection layer 190, that is, a fourth insulating protection layer 121, a fifth insulating protection layer 122, and a sixth insulating protection layer 123 are sequentially deposited on the seventh insulating protection layer 190. The fourth insulating protection layer 121, the fifth insulating protection layer 122, and the sixth insulating protection layer 123 are made of the same materials and deposited using the same method as in the first embodiment.

[0109] See Figure 15 As shown, the fourth insulating protection layer 121 , the fifth insulating protection layer 122 and the sixth insulating protection layer 123 are punched to expose a portion of the first electrode 113 .

[0110] See Figure 16 As shown, a third metal layer is coated on the sixth insulating protection layer 123 by magnetron sputtering. The material of the third metal layer is the same as that of the third metal layer in Example 1. The third metal layer is then patterned to obtain the gold terminal 130.

[0111] See Figure 17 As shown, finally, a second protective structure 140 is formed in sequence on the sixth insulating protective layer 123, that is, a first insulating protective layer 141, a second insulating protective layer 142 and a third insulating protective layer 143 are deposited in sequence on the sixth insulating protective layer 123, and the first insulating protective layer 141, the second insulating protective layer 142 and the third insulating protective layer 143 are dry-etched to obtain a groove 170.

[0112] Example 4

[0113] The difference between the fourth embodiment of the present application and the third embodiment is that the display panel 10 further includes a third protective structure 180. The third protective structure 180 is provided between the first insulating protective layer 141 and the sixth insulating protective layer 123. The third protective structure 180 covers a portion of the gold terminal 130. The third protective structure 180 is made of the same material as the third protective structure 180 in the second embodiment, such as Figure 18 shown.

[0114] Example 5

[0115] See Figure 19As shown, the fifth embodiment of the present application provides a method for preparing the display panel 10 in the first embodiment, and the preparation method includes the following steps:

[0116] Step S100: forming a first metal layer on the base substrate 100 and patterning the first metal layer to form a gate 111. Figure 2 shown.

[0117] The gate 111 can be configured as a single-layer, double-layer, or multi-layer metal composite or a single metal. Metal alloys or single metal elements include, but are not limited to, copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), and magnesium (Mg). The gate 111 is formed by depositing a first metal layer on the substrate 100 via magnetron sputtering and patterning the first metal layer. This patterning process includes resist coating, exposure, development, and wet etching.

[0118] Step S200: forming an insulating dielectric layer 160 and a semiconductor layer 112 on the substrate 100 in sequence, wherein the insulating dielectric layer 160 covers the gate 111. Figure 3 and Figure 4 shown.

[0119] After forming the gate 111 on the substrate 100, an insulating dielectric layer 160 is formed on the surface of the gate 111 using a chemical vapor deposition method. The insulating dielectric layer 160 includes at least two of silicon oxide, silicon nitride, and silicon oxynitride; that is, the insulating dielectric layer 160 is a composite film layer composed of at least the aforementioned silicon oxide, silicon nitride, and silicon oxynitride materials.

[0120] The insulating dielectric layer 160 is made of silicon nitride or silicon oxynitride near the gate 111 , and is made of silicon oxide near the top.

[0121] Furthermore, a metal oxide semiconductor is deposited on the insulating dielectric layer 160 by magnetron sputtering and patterned to form a semiconductor layer 112. Elements contained in the semiconductor layer 112 include, but are not limited to, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The carrier concentration of the semiconductor layer 112 is 5 to 30 cm2 / V*s.

[0122] It should be noted that a metal oxide semiconductor film is formed on the insulating dielectric layer 160, which is then coated, exposed, and developed. The metal oxide semiconductor is then patterned by wet etching and stripping. Finally, the patterned substrate 100 is annealed at a temperature of 350-500°C for 30-65 minutes. The annealing temperature can be 350°C, 400°C, 450°C, or 500°C, and the annealing time can be 30 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, or 65 minutes, etc.

[0123] Step S300: depositing a second metal layer on the insulating dielectric layer 160 and the semiconductor layer 112, and patterning the second metal layer to form a first electrode 113 and a second electrode 114, as shown in FIG. Figure 5 shown.

[0124] A second metal layer is deposited on the insulating dielectric layer 160 using magnetron sputtering and patterned to form a first electrode 113 and a second electrode 114 disposed in the same layer. The first electrode 113 and the second electrode 114 are separated from each other and overlap the first electrode 113 and the second electrode 114 on opposite sides of the semiconductor layer 112.

[0125] The first electrode 113 and the second electrode 114 can be formed as a single layer, double layer, or multilayer metal alloy or single metal element. The metal alloy or single metal element includes copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and niobium (Nb). The second metal layer is then patterned by resist coating, exposure, development, and wet etching to obtain the first electrode 113 and the second electrode 114.

[0126] Step S400: forming a first protection structure 120 on the insulating dielectric layer 160 and the semiconductor layer 112, and opening a via hole 150 at a portion corresponding to the first electrode 113, the via hole 150 leaking out a portion of the first electrode 113, as shown in FIG. Figure 6 shown.

[0127] The first protection structure 120 covers the first electrode 113 , the second electrode 114 and the semiconductor layer 112 to protect the transistor 110 when the gold terminal 130 is subsequently prepared, thereby ensuring the integrity and stability of the transistor 110 .

[0128] The first protection structure 120 is provided with a via hole 150 , and the via hole 150 can expose a portion of the first electrode 113 , so as to facilitate the subsequent electrical connection between the gold terminal 130 and the first electrode 113 , thereby realizing data transmission.

[0129] In the embodiment of the present application, the first protection structure 120 includes at least two insulating protection layers, which can not only play an insulating role but also protect the transistor 110 device.

[0130] The first protection structure 120 includes a fourth insulating protection layer 121, a fifth insulating protection layer 122, and a sixth insulating protection layer 123. After the first electrode 113 and the second electrode 114 are formed, the fourth insulating protection layer 121, the fifth insulating protection layer 122, and the sixth insulating protection layer 123 are sequentially deposited on their surfaces using chemical vapor deposition and coating methods. The fourth insulating protection layer 121 covers the insulating dielectric layer 160, the first electrode 113, the semiconductor layer 112, and the second electrode 114.

[0131] The fourth insulating protective layer 121 includes at least one of silicon oxide and silicon nitride, and may also be formed of other materials. After the fourth insulating protective layer 121 is formed, an annealing treatment is performed at a temperature of 240°C to 300°C for a time of 30 to 65 minutes. The annealing temperature may be 240°C, 260°C, 280°C, or 300°C, and the annealing time may be 30 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, or 65 minutes, etc.

[0132] Then, a fifth insulating protective layer 122 is coated on the fourth insulating protective layer 121 . The fifth insulating protective layer 122 is a photosensitive resin material with high sensitivity and high adhesion.

[0133] A sixth insulating protection layer 123 is deposited on the fifth insulating protection layer 122 . The sixth insulating protection layer 123 may be made of one or more structures selected from silicon oxide, silicon nitride, and an organic insulating film.

[0134] Finally, after performing resist coating, exposure, development, and dry etching on the fourth insulating protection layer 121 , the fifth insulating protection layer 122 , and the sixth insulating protection layer 123 , a via hole 150 is formed to expose a portion of the first electrode 113 , and the gold terminal 130 is connected to the first electrode 113 through the via hole 150 .

[0135] Step S500: coating a third metal layer on the first protection structure 120 and patterning the third metal layer to form a gold terminal 130. The gold terminal 130 is connected to the first electrode 113 through the via 150. Figure 7 shown.

[0136] A third metal layer is coated on the sixth insulating protective layer 123 using magnetron sputtering, with a portion of the metal in the third metal layer falling into the via 150. This third metal layer is then patterned to form the gold terminal 130. The third metal layer comprises a composite structure of copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and niobium (Nb). The top layer of the gold terminal 130 is a copper film layer, which allows copper to be deposited during the subsequent gold deposition process, facilitating subsequent soldering to the light-emitting chip.

[0137] The patterning process for the third metal layer includes coating the third metal layer with glue, exposing, developing, and wet etching and stripping.

[0138] Step S600: forming a second protection structure 140 on the first protection structure 120 and opening a groove 170 at a portion corresponding to the metallized gold terminal 130. The groove 170 exposes a portion of the metallized gold terminal 130. Figure 8 shown.

[0139] This second protective structure 140 includes at least two layers of insulating protective layers, which are arranged in sequence in the thickness direction of the base substrate 100 to improve the protection of the transistor 110 device, ensure that the transistor 110 device will not be damaged during the gold deposition process, improve the working stability of the transistor 110, and thereby improve the display stability of the display panel 10.

[0140] In the embodiment of the present application, the second protective structure 140 includes a first insulating protective layer 141, a second insulating protective layer 142, and a third insulating protective layer 143, which are sequentially arranged in the thickness direction of the base substrate 100. The first insulating protective layer 141 is arranged on the side of the sixth insulating protective layer 123 away from the base substrate 100, and the first insulating protective layer 141 covers a portion of the gold terminal 130.

[0141] Among them, the first insulating protection layer 141 and the third insulating protection layer 143 include the same material, and the first insulating protection layer 141 and the third insulating protection layer 143 use a material different from the material of the second insulating protection layer 142 to improve the protection of the first electrode 113, the semiconductor layer 112, the gate 111 and the second electrode 114.

[0142] The first insulating protective layer 141 includes a single-layer film structure of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, or a combination of the above film layers, but is not limited thereto. The second insulating protective layer 142 is an organic film layer, which is mainly a photosensitive resin material of high sensitivity and high adhesion. The second insulating protective layer 142 mainly functions as a leveling agent to provide a smooth working surface for subsequent electroless gold processing and welding processes. The third insulating protective layer 143 includes a single-layer film structure of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, or a combination of the above film layers, but is not limited thereto. In other words, the first insulating protective layer 141 and the third insulating protective layer 143 are inorganic layers, and the second insulating protective layer 142 is an organic layer. The use of different film layers can improve the protective performance of the second protective structure 140 and can better protect the devices of the transistor 110.

[0143] The method for forming the above-mentioned groove 170 includes coating, exposure, development, and dry etching and stripping. Furthermore, the cross-sectional area of ​​the groove 170 gradually increases from the first insulating protective layer 141 to the third insulating protective layer 143; that is, the aperture of the groove 170 gradually increases, so that the light-emitting chip can be firmly fixed in the groove 170 and prevented from tilting, thereby ensuring the display effect.

[0144] It should be noted that the groove 170 can penetrate the three insulating protection layers by a single photolithography etching, and the process implementation is relatively easy.

[0145] The first insulating protective layer 141, the second insulating protective layer 142 and the third insulating protective layer 143 in this second protective structure 140 can improve the protection of the transistor 110 device, avoid electrical failure of the transistor 110 device and corrosion of the metal wiring under high temperature, high humidity and acidic conditions in the gold deposition process, ensure the integrity and stability of the transistor 110 device, and effectively limit the area of ​​the gold deposition terminal 130, thereby improving the stability of the gold deposition process.

[0146] Example 6

[0147] Embodiment 6 of the present application provides a display device, which includes a light-emitting chip and a display panel 10 described in any one of embodiments 1 to 4. The light-emitting chip is copper-welded with a gold terminal 130 through a groove 170 formed by a gold-plated process to control the light-emitting state of the light-emitting chip.

[0148] In the description of this specification, the descriptions with reference to the terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are mutually contradictory. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Those of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope covered by the patent of this application.

Claims

1. A display panel, comprising a base substrate and a transistor disposed on the base substrate, the transistor comprising a gate, a semiconductor layer, a first electrode, and a second electrode, the gate being disposed on a side of the semiconductor layer close to the base substrate, with an insulating dielectric layer disposed between the gate and the semiconductor layer, the semiconductor layer being disposed on a side of the insulating dielectric layer away from the base substrate, and the first electrode and the second electrode being disposed on opposite sides of the semiconductor layer, respectively; characterized in that: The display panel further includes: a first protective structure, the first protective structure being provided on a side of the insulating dielectric layer away from the base substrate, the first protective structure being provided with a via hole; A gold terminal is provided on a side of the first protection structure away from the base substrate, and the gold terminal is connected to the first electrode through the via hole. a second protective structure, the second protective structure being provided on a side of the first protective structure away from the base substrate, the second protective structure being provided with a groove, the groove exposing at least a portion of the gold terminal; The second protective structure includes a first insulating protective layer, a second insulating protective layer and a third insulating protective layer sequentially arranged in the thickness direction of the base substrate, and the first insulating protective layer is arranged on a side of the first protective structure away from the base substrate; The first insulating protective layer / the third insulating protective layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide; The second insulating protective layer includes an organic film layer.

2. The display panel according to claim 1, wherein: The first insulating protection layer and the third insulating protection layer comprise the same material; The material of the second insulating protective layer is different from the materials of the first insulating protective layer and the third insulating protective layer.

3. The display panel according to claim 1, wherein: In the direction from the first insulating protection layer to the third insulating protection layer: the cross-sectional area of ​​the groove gradually increases.

4. The display panel according to any one of claims 1 to 2, characterized in that: The first protection structure includes at least two insulating protection layers.

5. The display panel according to claim 1, wherein: The display panel further includes a third protective structure, which is disposed between the first protective structure and the second protective structure and covers a portion of the gold terminal.

6. A method for preparing a display panel according to any one of claims 1 to 4, characterized in that: The preparation method comprises the following steps: forming a first metal layer on a base substrate, and patterning the first metal layer to form a gate; forming an insulating dielectric layer and a semiconductor layer in sequence on the substrate, wherein the insulating dielectric layer covers the gate; Depositing a second metal layer on the insulating dielectric layer and the semiconductor layer, and patterning the second metal layer to form a first electrode and a second electrode; forming a first protection structure on the insulating dielectric layer and the semiconductor layer, and opening a via hole in a portion corresponding to the first electrode, wherein the via hole leaks a portion of the first electrode; Coating a third metal layer on the first protection structure and patterning the third metal layer to form the gold terminal, wherein the gold terminal is connected to the first electrode through the via hole; A second protective structure is formed on the first protective structure, and a groove is opened at a portion corresponding to the electroplated gold terminal, wherein the groove exposes a portion of the electroplated gold terminal.

7. A display device, characterized in that: The display device comprises a light-emitting chip and the display panel according to any one of claims 1 to 5, wherein the light-emitting chip is connected to the gold terminal through the groove.

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