A method to improve the short-range plasticity of synaptic transistors

Abstract

This invention discloses a method for improving the short-range plasticity of synaptic transistors, comprising the following steps: preparing a mixed solid electrolyte solution of chitosan and polyvinyl alcohol; spin-coating the solid electrolyte solution onto a substrate with a gate electrode and drying it; and fabricating the active layer and source / drain electrodes of the transistor on the electrolyte film. This method improves the voltage hysteresis effect of synaptic transistors, increases the voltage hysteresis window, reduces the off-state current, increases the device current on / off ratio, and enhances the short-range plasticity of synaptic transistors. The synaptic transistor provided by this invention exhibits excellent synaptic characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for improving the short-range plasticity of synaptic transistors. Background Technology

[0002] With the rapid development of information technology, traditional von Neumann computers have limitations in processing real and unstructured data. Traditional digital computers based on the von Neumann architecture, due to the separation of data storage and computing units, have shown limitations when dealing with massive amounts of data and complex problems. As is well known, the human brain's nervous system is a complex neural network structure that can perfectly achieve in-memory computing through neurons. Therefore, finding a computer architecture that mimics the in-memory computing of the human brain is urgently needed. In recent years, thanks to the rapid development of artificial intelligence, new materials, and new devices, researchers have proposed various types of neuromorphic devices to mimic the functions of basic units of the biological nervous system through the cross-integration of microelectronics and neuroscience. These include conductive bridges, memristors, or two-terminal synaptic devices based on ferroelectric mechanisms. While two-terminal synaptic devices have the advantages of simple structure and high compatibility, their synaptic learning function is very limited. Compared with two-terminal devices, three-terminal devices can simultaneously process pulse signals from multiple inputs and have good memory characteristics and learning functions, better mimicking the impulse response behavior of neural synapses and neurons, thus achieving the imitation of neuronal function. In three-terminal biomimetic synaptic devices, thin-film transistors with an electrolyte as the gate insulating layer rely on the migration of ions in the electrolyte to the semiconductor channel and electrolyte under the influence of the gate voltage, forming an ultra-thin electric double layer effect, which gives them the advantage of ultra-low power consumption. When a living organism is stimulated, the signal propagates through the synaptic structure in the neural network. At the synaptic precursor, the electrical signal is converted into a chemical signal, releasing neurotransmitters that act on the postsynaptic, and then the chemical signal is converted back into an electrical signal. This process is accompanied by the flow of ions. The formation of the electric double layer is achieved by the movement of mobile positive ions in the electrolyte to the interface between the gate dielectric and the active layer under the gate electric field. Without an external gate voltage, the positive ions at the interface diffuse into the electrolyte due to the concentration gradient, returning to an equilibrium state. This form of regulating channel current based on ion movement in the electric double-layer thin-film transistor is similar to that of biological synapses, and therefore has been widely studied in the fields of artificial synaptic devices and neuromorphic systems.

[0003] In synaptic transistors, the electric double layer is a key structure for simulating synaptic functions. Currently, the gate insulating layer materials used in electric double-layer transistors are typically polyelectrolytes, ionic liquids, ionic gels, or solid electrolytes. Compared to ionic liquids and ionic gels, solid electrolytes have more stable chemical properties and lower production costs.

[0004] Recent advances in solid electrolytes for synaptic transistors summarize the shortcomings of electrolyte synaptic transistors. Inorganic solid electrolytes, used as the gate dielectric layer of EDL TFTs, offer better chemical stability and superior ionic conductivity than polymeric electrolytes and ionic liquids, but they are biologically incompatible, and most materials are environmentally harmful. Organic solid electrolytes, on the other hand, are non-toxic, harmless, and highly biocompatible, can be fabricated on flexible substrates, have low production costs, and are suitable for large-scale production. While the application of solid electrolytes in synaptic transistors has developed rapidly, many problems and challenges remain in developing high-performance synaptic transistors. The coupling coefficient of artificial synaptic transistors is typically fixed, failing to simulate real, highly complex synaptic neural activity. Furthermore, the proton mobility of solid electrolytes still has room for improvement in applications for artificial neural synapses.

[0005] In a technique for modulating the short-term synaptic plasticity of solution-gated indium gallium zinc oxide electric double transistors (IGZO), it was found that the short-term synaptic plasticity of the synapse can be effectively modulated by the addition of alcohol and potassium chloride. Because the delivery of hydrated hydrogen and hydroxide ions can suppress (promote) alcohol molecules (salt ions), fewer (more) ions can trigger the same presynaptic peak in alcohol (potassium chloride) solution-gated IGZO synaptic transistors compared to water-gated IGZO synaptic transistors. In other words, the amplitude of the EPSC should be positively correlated with the ionic conductivity. These results are consistent with the capacitive behavior observed above. The results indicate that the amplitude of the EPSC can be modulated by ionic conductivity in solution-based gate media.

[0006] A synaptic transistor and its fabrication method involve adding nanofibers (CN112951925A) to the insulating layer material of the synaptic transistor, thereby improving the proton mobility and synaptic characteristics. Nanofibers possess unique carrier transport properties, providing channels for proton migration. Using them, along with a solid electrolyte, in the fabrication of the insulating layer of the synaptic transistor is beneficial for enhancing its synaptic characteristics.

[0007] Existing solid-state electrolyte materials suffer from proton conductivity issues. In electric double-layer transistors, proton conductivity significantly impacts the synaptic characteristics of the device. Therefore, improving proton conductivity can greatly enhance the short-range memory performance of synaptic devices. Consequently, addressing the proton conductivity issue in solid-state electrolyte materials to improve the synaptic characteristics of synaptic transistors is one of the critical technical challenges in fabricating high-performance synaptic transistors. Summary of the Invention

[0008] To address the problem of poor short-range plasticity of synaptic transistors due to the low proton conductivity of the aforementioned solid electrolyte materials, this invention provides a method for improving the short-range plasticity of synaptic transistors. This invention involves adding low-conductivity polyvinyl alcohol to high-conductivity chitosan to alter the proton conductivity in the gate insulating layer, thereby improving the short-range plasticity of the synaptic transistor.

[0009] The present invention is achieved by at least one of the following technical solutions.

[0010] A method for improving the short-range plasticity of synaptic transistors includes the following steps:

[0011] (1) Prepare a mixed solid electrolyte solution of chitosan and polyvinyl alcohol;

[0012] (2) Spin-coating the solid electrolyte solution onto a substrate with a gate electrode and then drying it;

[0013] (3) The active layer and source / drain electrodes of the transistor are prepared on the dried solid electrolyte.

[0014] Preferably, the mass ratio of chitosan to polyvinyl alcohol is (0.5-1):1.

[0015] Preferably, the specific process of preparing the solution in step (1) is as follows: first, chitosan and deionized water are mixed, then acetic acid is added and stirred to dissolve, forming a chitosan solution; polyvinyl alcohol is added to deionized water and stirred to dissolve.

[0016] A polyvinyl alcohol solution is formed; finally, the two solutions are mixed by ultrasound and placed in a vacuum chamber to remove air bubbles.

[0017] Preferably, the amount of acetic acid added is 1-2 wt% of the chitosan solution.

[0018] Preferably, in step (1), the stirring temperature of the chitosan solution is 50-60℃, the stirring temperature of the polyvinyl alcohol solution is 80-90℃, and the stirring speed is 200-500 rpm.

[0019] Preferably, the ultrasonic mixing time in step (1) is 30-60 min.

[0020] Preferably, in step (2), the substrate is one of silicon wafer, silicon dioxide, glass and polyimide.

[0021] Preferably, in step (2), the spin coating speed is 2000-4000 rpm and the spin coating time is 30-60 s.

[0022] Preferably, in step (2), the drying time is 2-4 hours and the drying temperature is 40-60℃.

[0023] Preferably, the gate electrode of the transistor is Al, the source and drain electrodes are Mo, and the active layer is IZO.

[0024] The basic principle of this invention: Two-pulse dissimilarity (PPF) is the most important means of characterizing the short-range plasticity of synaptic transistors. Specifically, when a synaptic transistor is continuously subjected to two identical stimuli with a certain interval, the second stimulus produces a larger response than the first. The ratio of the channel current triggered by the second stimulus to that triggered by the first stimulus is defined as the PPF factor. After the gate bias is removed, ions on the interface rapidly diffuse back to their initial positions, restoring the channel conductance to its original state. The proton migration velocity in the solid electrolyte determines the time it takes for the device to return to its original state. Therefore, the proton migration velocity in the solid electrolyte has a significant impact on the intensity of the device's two-pulse dissimilarity, thus affecting the short-range plasticity of the synapse. When two consecutive pulses are applied to the gate, the EPSC amplitude caused by the first pulse is called A1, and the EPSC amplitude caused by the second pulse is called A2. Neural synapses are divided into excitatory and inhibitory types. For excitatory synapses, A2 will be greater than A1, while for inhibitory synapses, A2 will be less than A1. In the field of neuroscience, A2 / A1 is called the PPF (Paired Pulse Facilitation) index, which is used to characterize the intensity of dual-pulse facilitation. The formula for calculating the PPF factor is shown below.

[0025]

[0026] Compared with existing technologies, the beneficial effects of the present invention are as follows:

[0027] The problem of proton conductivity in solid electrolytes was solved, the voltage hysteresis effect of transistors was improved, the voltage hysteresis window was increased, the off-state current of transistors was reduced, the device current switching ratio was improved, the magnitude of the device's double-pulse response was increased, and thus the synaptic short-range plasticity of synaptic transistors was improved. Attached Figure Description

[0028] Figure 1 This is a flowchart illustrating a method for improving the short-range plasticity of synaptic transistors according to an embodiment of the present invention;

[0029] Figure 2This is a schematic diagram of the device structure in Example 1;

[0030] Figure 3 The transfer characteristic curves of the synaptic transistors in Example 1 and Comparative Example 1 are shown.

[0031] Figure 4 The response curve of the synaptic transistor under double-pulse stimulation in Example 1;

[0032] Figure 5 The response curve of the synaptic transistor in Comparative Example 1 is shown as a two-pulse stimulus.

[0033] Figure 6 The response curve of the synaptic transistor in Comparative Example 2 is the response curve of the synaptic transistor under double-pulse stimulation.

[0034] Figure 7 The response curves of the synaptic transistor in Comparative Example 3 are shown in the form of a double-pulse stimulus. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0036] like Figure 1 As shown, a method for improving the short-range plasticity of synaptic transistors includes the following steps:

[0037] (1) Prepare a mixed solid electrolyte solution of chitosan and polyvinyl alcohol. Specifically, first mix chitosan and deionized water, then add acetic acid and stir to dissolve to form a chitosan solution; add polyvinyl alcohol to deionized water and stir to dissolve to form a polyvinyl alcohol solution; finally, mix the two solutions by ultrasound and place them in a vacuum chamber to remove air bubbles.

[0038] As one example, the mass ratio of chitosan to polyvinyl alcohol is (1-0.5):1, the content of acetic acid added is 1-2 wt% of the chitosan solution mass; the stirring temperature of the chitosan solution is 50-60℃, the stirring temperature of the polyvinyl alcohol solution is 80-90℃, the stirring speed of both is 200-500 rpm, and the ultrasonic time is 30-60 min.

[0039] (2) The solid electrolyte solution is spin-coated onto a substrate with a gate electrode and then dried. The spin-coating speed is 2000-4000 rpm and the spin-coating time is 30-60 s. The drying time is 2-4 h and the drying temperature is 40-60 °C. As one embodiment, the substrate is one of silicon wafer, silicon dioxide, glass, and polyimide.

[0040] (3) The active layer and source / drain electrodes of the transistor are prepared on the dried solid electrolyte. The gate electrode of the transistor is Al, the source / drain electrodes are Mo, and the active layer is IZO. Specific Implementation Example 1:

[0042] The structure of the synaptic transistor in this embodiment is as follows: Figure 2 As shown, it includes a substrate 1, a gate electrode 2, a gate insulating layer 3, an active layer 4, and source / drain electrodes 5, which are constructed sequentially from bottom to top.

[0043] This embodiment of a method for improving the short-range plasticity of synaptic transistors includes the following steps:

[0044] (1) Mix 0.4g chitosan and 10g deionized water, add 1mL acetic acid and stir with a constant temperature magnetic stirrer for 2h at a speed of 500rpm and a temperature of 60℃; take 1g polyvinyl alcohol and add it to 10g water, stir with a magnetic stirrer for 2h at a speed of 500rpm and a temperature of 80℃, mix the two solutions, put them in an ultrasonic device to mix them thoroughly, and then put them in a vacuum box to remove air bubbles to obtain a blended electrolyte solution;

[0045] (2) Use a dropper to draw up the blended solution from step (1) and add it to the substrate with the grid electrode; spin coater runs at 2000 rpm for 60 seconds, then place the substrate in a drying oven and heat at 40°C for 4 hours;

[0046] (3) Using a radio frequency magnetron sputtering deposition system, an IZO active layer is sputtered on a solid electrolyte by magnetron sputtering, and a patterned Mo source and drain electrode is obtained on the active layer by magnetron sputtering.

[0047] Comparative Example 1:

[0048] (1) Mix 0.4g chitosan and 20g deionized water, add 2mL acetic acid, and then stir with a constant temperature magnetic stirrer for 2h at a speed of 500rpm and a temperature of 60℃ to obtain a chitosan solution.

[0049] (2) Use a dropper to draw up the chitosan solution and add it to the substrate with the gate; run the spin coater at 2000 rpm for 60 seconds, and then put the substrate into the drying oven and heat it at 40°C for 4 hours;

[0050] (3) Using a radio frequency magnetron sputtering deposition system, an IZO active layer is sputtered on a solid electrolyte by magnetron sputtering, and a patterned Mo source and drain electrode is obtained on the active layer by magnetron sputtering.

[0051] Comparative Example 2:

[0052] (1) Mix 0.4g chitosan and 10g deionized water, add 1mL acetic acid and stir with a constant temperature magnetic stirrer for 2h at a speed of 500rpm and a temperature of 60℃; take 2g polyvinyl alcohol and add it to 10g water, stir with a magnetic stirrer for 2h at a speed of 500rpm and a temperature of 80℃, mix the two solutions, put them in an ultrasonic device to mix them thoroughly, and then put them in a vacuum box to remove air bubbles to obtain a blended electrolyte solution;

[0053] (2) Use a dropper to draw up the blended solution from step (1) and add it to the substrate with the grid electrode; spin coater runs at 2000 rpm for 60 seconds, then place the substrate in a drying oven and heat at 40°C for 4 hours;

[0054] (3) Using a radio frequency magnetron sputtering deposition system, an IZO active layer is sputtered on a solid electrolyte by magnetron sputtering, and a patterned Mo source and drain electrode is obtained on the active layer by magnetron sputtering.

[0055] Comparative Example 3:

[0056] (1) Mix 0.4g chitosan and 10g deionized water, add 1mL acetic acid and stir with a constant temperature magnetic stirrer for 2h at a speed of 500rpm and a temperature of 60℃; take 0.4g polyvinyl alcohol and add it to 10g water, stir with a magnetic stirrer for 2h at a speed of 500rpm and a temperature of 80℃, mix the two solutions, put them in an ultrasonic device to mix them thoroughly, and then put them in a vacuum box to remove air bubbles to obtain a blended electrolyte solution;

[0057] (2) Use a dropper to draw up the blended solution from step (1) and add it to the substrate with the grid electrode; spin coater runs at 2000 rpm for 60 seconds, then place the substrate in a drying oven and heat at 40°C for 4 hours;

[0058] (3) Using a radio frequency magnetron sputtering deposition system, an IZO active layer is sputtered on a solid electrolyte by magnetron sputtering, and a patterned Mo source and drain electrode is obtained on the active layer by magnetron sputtering.

[0059] The transfer characteristic curves of the optimized chitosan-added polyvinyl alcohol synaptic transistor in Specific Example 1 and the chitosan synaptic transistor in Comparative Example 1 are shown below. Figure 3 As shown. By Figure 3 It can be seen that adding polyvinyl alcohol reduces the off-state current of the synaptic transistor, increases the current on / off ratio, and increases the device hysteresis window.

[0060] The device was tested by applying a double pulse with a voltage of 0.1V, a pulse duration of 50ms, and a double pulse interval of 100ms.

[0061] The double-pulse response curves of the optimized chitosan-added polyvinyl alcohol synaptic transistor in Specific Example 1 and the chitosan synaptic transistor in Comparative Example 1 are shown below. Figure 4 and Figure 5 As shown. By Figure 4 and Figure 5 It can be seen that the device current in Specific Example 1 decreases more slowly than that in Comparative Example 1, and it takes longer for the current to recover to its initial state. In Example 1, the PPF of the device with added polyvinyl alcohol to chitosan reached 144%, while the PPF of the device without added polyvinyl alcohol to chitosan in Comparative Example 1 was only 119%. This reflects that by adding polyvinyl alcohol, the proton conductivity in the solid electrolyte is reduced, so after the first pulse ends, it takes longer for the ions to recover to their initial state. More ions remain at the double layer interface, so a larger current can be generated when the next pulse arrives, thereby improving the device's double-pulse response, that is, improving the device's short-range plasticity.

[0062] To further illustrate the effect of proton conductivity on device characteristics, Comparative Examples 2 and 3 were conducted by changing the content of polyvinyl alcohol in the device gate insulating layer to observe the effect on the device's PPF. In Comparative Example 2, the proportion of polyvinyl alcohol was increased, and in Comparative Example 3, the proportion of polyvinyl alcohol was decreased to further illustrate the effect of the device gate insulating layer.

[0063] The double-pulse response curve of the device after increasing the proportion of polyvinyl alcohol in Comparative Example 2 is shown below. Figure 6 As shown. By Figure 3 and Figure 6 It can be seen that the device current in Comparative Example 1 decreases more slowly than that in Example 1, and it takes longer for the current to recover to its initial state. Therefore, the device PPF increases to 153%.

[0064] The double-pulse response curve of the device after reducing the proportion of polyvinyl alcohol in Comparative Example 3 is shown below. Figure 7 As shown. By Figure 3 and 7 It can be seen that the device current in Comparative Example 1 decreases more rapidly than that in Example 1, and the current takes less time to recover to its initial state, so the device PPF decreases by 123%.

[0065] Based on the combined examples and comparative examples, it can be concluded that adding polyvinyl alcohol to chitosan can regulate the proton conductivity in the gate insulating layer. When the mass ratio of chitosan remains constant, changing the proportion of polyvinyl alcohol can accelerate or slow down proton movement. Increasing polyvinyl alcohol can weaken proton movement, while decreasing polyvinyl alcohol can enhance proton movement, thereby changing the PPF response of the device and further affecting the short-range synaptic plasticity of the device.

[0066] In summary, the method of the present invention can not only improve the current switching ratio of transistors and reduce the device off-state current, but also significantly improve the short-range flexibility of the device.

[0067] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for improving the short-range plasticity of synaptic transistors, characterized in that, Includes the following steps: (1) Prepare a mixed solid electrolyte solution of chitosan and polyvinyl alcohol; the mass ratio of chitosan to polyvinyl alcohol is (0.5~1):1; the specific process of preparing the solution in step (1) is as follows: first mix chitosan and deionized water, then add acetic acid and stir to dissolve to form a chitosan solution; add polyvinyl alcohol to deionized water and stir to dissolve to form a polyvinyl alcohol solution; finally, mix the two solutions by ultrasound and put them into a vacuum box to remove air bubbles; (2) Spin-coating the solid electrolyte solution onto a substrate with a gate electrode and then drying it; (3) The active layer and source / drain electrodes of the transistor are prepared on the dried solid electrolyte.

2. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, The amount of acetic acid added is 1-2 wt% of the chitosan solution.

3. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, Step (1) The stirring temperature of the chitosan solution is 50-60℃, the stirring temperature of the polyvinyl alcohol solution is 80-90℃, and the stirring speed is 200-500rpm.

4. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, The ultrasonic mixing time in step (1) is 30-60 min.

5. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, In step (2), the substrate is one of silicon wafer, silicon dioxide, glass and polyimide.

6. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, In step (2), the spin coating speed is 2000-4000 rpm and the spin coating time is 30-60 s.

7. The method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, In step (2), the drying time is 2-4 hours and the drying temperature is 40-60℃.

8. A method for improving the short-range plasticity of synaptic transistors according to claim 1, characterized in that, The gate electrode of the transistor is Al, the source and drain electrodes are Mo, and the active layer is IZO.

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