Document review and filing processing method, device and medium for chip design

Abstract

The present application relates to the field of computer technology and provides a document approval and archiving processing method, device and medium for chip design. The method includes: determining multiple nodes associated with the chip design process, including a start node and an end node, the first node satisfies at least one first dependency from the start node to the first node and then to the end node, and the development process associated with the first node includes: executing the development projects of the nodes located on at least one first dependency in the multiple nodes one by one in the order indicated by the first dependency; based on the first dependency, determining the first approval process of the first document of the development project of the first node; managing the update operation, rollback operation and archiving operation of the first document according to the first approval process. In this way, the needs of alignment and coordination between teams at different nodes are met, which is conducive to the efficient management of a large number of documents with different versions across multiple nodes and improves development efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a document review and filing processing method, device and medium for chip design. Background Art

[0002] The entire process of chip design includes two major stages: the front-end design stage and the back-end design stage, and can be further divided into multiple different nodes, such as the analog circuit design node and the digital circuit design node. These different nodes may have different development progress, so it involves alignment and coordination between different nodes, and may also involve feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage. Therefore, in the chip design process, the participation of a large number of developers and verifiers is required, and a large number of documents with different versions need to be managed, which poses challenges to personnel authority management, document management, version alignment, etc. In the prior art, the document approval and archiving processing method based on the version control system (Subversion, SVN) provides project-level access control through a centralized server, and centrally manages large-scale projects composed of multiple projects. However, the document approval and archiving processing method based on the version control system in the prior art is difficult to meet the needs of alignment and coordination between project development teams at different nodes, and is not convenient for managing a large number of documents with different versions across multiple nodes, which affects development efficiency.

[0003] To this end, the present application provides a document review and archiving processing method, device and medium for chip design, which are used to address the technical difficulties in the prior art. Summary of the invention

[0004] In the first aspect, the present application provides a document approval and archiving processing method for chip design. The document approval and archiving processing method includes: determining multiple nodes associated with the chip design process, the multiple nodes include a start node and an end node, the first node of the multiple nodes satisfies at least one first dependency from the start node to the first node and then to the end node, and the development process associated with the first node in the chip design process includes: executing the development projects of the nodes located on the at least one first dependency in the multiple nodes one by one in the order indicated by the at least one first dependency; determining the first approval process of the first document of the development project of the first node based on the at least one first dependency; managing the update operation of the first document, the rollback operation of the first document, and the archiving operation of the first document according to the first approval process.

[0005] Through the first aspect of the present application, by determining the first approval process for document approval and archiving processing of the first document applicable to the first node, and managing the update operation, rollback operation and archiving operation of the first document according to the first approval process, it is realized that the document approval and archiving processing operation is performed in response to the progress of the development project of the first node itself, the document approval and archiving processing operation is performed on the first node in response to the changes in the development projects of other nodes, and the document approval and archiving processing operation of the corresponding node is triggered in response to the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage; it can flexibly adapt to the division and composition of any nodes, links, process nodes, etc. in the chip design process and flexibly adapt to the serial and parallel execution methods between these nodes; it can effectively manage the respective documents across multiple nodes in the chip design process, including managing the update operation, rollback operation and archiving operation of these documents, meet the alignment and coordination needs between project development teams at different nodes, and is conducive to efficient management of a large number of documents with different versions across multiple nodes, which helps to improve development efficiency.

[0006] In a possible implementation of the first aspect of the present application, the first approval process includes associated projects of the first document, and the associated projects of the first document include at least development projects of nodes among the multiple nodes that are located on the at least one first dependency relationship and are located before the first node according to the order indicated by the at least one first dependency relationship.

[0007] In a possible implementation of the first aspect of the present application, managing the update operation of the first document in accordance with the first approval process includes: based on the version update status of each of the associated items of the first document, determining whether to generate a new version of the first document and overwriting the current version of the first document with the new version of the first document, wherein the version update status of each of the associated items of the first document includes whether each of the associated items of the first document has undergone a version update within a specified time period.

[0008] In a possible implementation manner of the first aspect of the present application, the specified time period is from generation of a current version of the first document to determining whether to generate a new version of the first document.

[0009] In a possible implementation of the first aspect of the present application, the first approval process also includes an associated person of the first document, and the associated person of the first document is the person in charge of the development project of the node located on the at least one first dependency relationship among the multiple nodes. The document approval archiving processing method also includes: notifying the associated person of the first document of the update operation of the first document, the rollback operation of the first document, or the archiving operation of the first document performed.

[0010] In a possible implementation of the first aspect of the present application, the rollback operation of the first document is managed in accordance with the first approval process, including: based on the current versions of the respective associated projects of the first document, determining whether to overwrite the current version of the first document with the old version of the first document.

[0011] In a possible implementation of the first aspect of the present application, the archiving operation of the first document is managed in accordance with the first approval process, including: when the development project of the first node is completed, initiating an approval request for the first document, modifying the first document according to feedback associated with the approval request, and, when the approval request is approved, archiving the first document to a designated archiving location.

[0012] In a possible implementation manner of the first aspect of the present application, the feedback associated with the approval request includes feedback of multiple approval nodes, and one or more of the multiple approval nodes are based on nodes among the multiple nodes that are located on the at least one first dependency relationship and are located after the first node according to the order indicated by the at least one first dependency relationship.

[0013] In a possible implementation manner of the first aspect of the present application, the archiving operation of the first document includes performing watermark processing on the first document and adding read-write permission protection.

[0014] In a possible implementation of the first aspect of the present application, the first document is configured to be previewed and approved through a file preview operation, and after performing an archiving operation of the first document, the archived first document is configured to be searchable through a mapping relationship between the document information of the first document and the designated archiving location.

[0015] In a possible implementation of the first aspect of the present application, after performing the archiving operation of the first document, if the archived first document is not found in the local cache, the archived first document is obtained from the version control system node corresponding to the first node.

[0016] In a possible implementation of the first aspect of the present application, the multiple nodes include one or more of the following: system planning node, module partitioning node, digital circuit design node, analog circuit design node, digital circuit simulation verification node, analog circuit simulation verification node, digital-analog mixed simulation verification node, layout planning node, top-level wiring node, post-simulation simulation node, and post-wiring optimization node.

[0017] In a possible implementation manner of the first aspect of the present application, the first node is any node among the multiple nodes except the start node and the end node.

[0018] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0019] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of multiple nodes associated with a chip design process;

[0023] Figure 2 A flowchart of a document approval and archiving processing method for chip design provided in an embodiment of the present application;

[0024] Figure 3 A method according to the embodiment of the present application Figure 2 A schematic diagram of a first approval process determined by the document approval and archiving processing method shown;

[0025] Figure 4 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0027] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0028] Figure 1 FIG. 1 is a schematic diagram of multiple nodes associated with a chip design process. Figure 1 As shown, the multiple nodes include: system planning node 102, module partitioning node 104, digital circuit design node 106, analog circuit design node 108, digital circuit simulation verification node 110, analog circuit simulation verification node 112, digital-analog hybrid simulation verification node 114, layout planning node 116, top-level wiring node 118, post-simulation simulation node 120, and post-wiring optimization node 122. It should be understood that Figure 1 The multiple nodes associated with the chip design process shown are only exemplary, and the chip design process may be replaced, added or deleted. Figure 1 The nodes shown can also be changed Figure 1 The connection relationship between the different nodes shown depends on the chip design scheme and actual needs, and is not specifically limited here. For example, the digital circuit design node 106 can be further divided into two or more nodes for circuit design of different digital circuit modules, respectively. The development projects of these digital circuit modules are managed separately and can be developed in parallel. In some embodiments, more links and process nodes may be included, such as mask generation process nodes, etc. In addition, according to the specific product requirements and application scenarios corresponding to the chip design and manufacturing process, the division and composition of the links and process nodes may also be adjusted. In addition, the advancement of chip manufacturing processes, such as new semiconductor preparation processes, new packaging processes, etc., may also affect the chip design and manufacturing process, such as setting up new links or setting up new process nodes.

[0029] See also Figure 1The chip design process can be divided into two stages: the front-end design stage and the back-end design stage, and can be further divided into multiple different nodes. Among them, the system planning node 102, the module division node 104, the digital circuit design node 106, the analog circuit design node 108, the digital circuit simulation verification node 110, the analog circuit simulation verification node 112, and the digital-analog hybrid simulation verification node 114 belong to the front-end design stage. The layout planning node 116, the top-level wiring node 118, the post-simulation simulation node 120, and the post-wiring optimization node 122 belong to the back-end design stage. Figure 1 The execution order between these different nodes is also shown in the example. Figure 1 For example, after executing the module division node 104, the analog circuit design node 108 and the digital circuit design node 106 are executed in parallel, and the analog circuit simulation verification node 112 is executed after executing the analog circuit design node 108 and the digital circuit simulation verification node 110 is executed after executing the digital circuit design node 106, and finally the nodes are summarized into the mixed analog and digital simulation verification node 114. Figure 1The multiple nodes shown correspond to development projects for achieving specific design objectives. The development projects corresponding to these nodes constitute a complete chip design process in a serial and parallel execution mode according to a certain execution order. Among them, the system planning node 102 refers to setting the purpose and performance of the chip and the protocol standards that need to be met, that is, determining the demand analysis of the chip and determining the overall design direction, such as determining the cost control level, power consumption sensitivity, supported connection methods, system security level, etc. The module division node 104 refers to further determining the chip architecture, business module, power supply system and other designs based on the determined purpose, performance and requirements of the chip, that is, performing function allocation and unit division, such as determining the interaction and specific interface between various systems. The digital circuit design node 106 and the analog circuit design node 108 are respectively for the digital circuit part and the analog circuit part, and for each module, specific circuit design is performed, for example, using a hardware description language (HDL) such as Verilog HDL to perform a register transfer level (RTL) code description of the hardware behavior, structure and data flow of the circuit system, and for example, using a circuit logic diagram to design the structure of the analog circuit. The digital circuit simulation verification node 110 and the analog circuit simulation verification node 112 are respectively used for simulation verification of the design results of the corresponding design nodes, for example, through electronic design automation (EDA) tools to verify the correctness of the code design. The digital-analog hybrid simulation verification node 114 is used to simulate and verify the digital circuit design results and the analog circuit design results together, simulating the actual operation of the chip. The results of the front-end design stage are finally converted into a gate-level netlist (netlist) by a logic synthesis tool such as the automatic synthesis function of the EDA tool, and the timing, area and other circuit parameters are determined to be up to standard. The back-end design stage refers to the circuit layout (floor plan) and winding (routing) based on the results of the front-end design stage, that is, the converted netlist, according to the given silicon wafer area, so as to obtain a specific circuit wiring structure, and the physical layout of the circuit wiring structure is subjected to various verifications of function and timing. For example, the layout planning node 116 can be executed successively for layout planning, the top-level routing node 118 can be executed for top-level routing, the post-simulation node 120 can be executed for determining whether the routing result meets the specification, and the post-routing optimization node 122 can be executed for optimizing power consumption, area utilization, etc.

[0030] See also Figure 1It can be seen that from the initial system planning node 102 to the final post-wiring optimization node 122, multiple different nodes are involved, and the execution order between these nodes is a complete chip design process in a serial-parallel execution mode according to a certain execution order. The development projects on these different nodes may have different development progress, so it involves alignment and coordination between different nodes, and may also involve feedback and modification between nodes in the front-end design stage and nodes in the back-end design stage. For example, the post-simulation simulation node 120 may find errors in circuit layout, and the modification of the circuit layout errors may need to be fed back to the front-end design stage, such as feedback to the digital circuit design node 106, and make corresponding adjustments at the digital circuit design node 106. For another example, the post-wiring optimization node 122 may respond to user needs and chip product specifications, and limit power consumption, design area utilization, etc., and these restrictions may be fed back to the module division node 104, so that adjustments may be made to the chip architecture, business module, power supply system, etc. Therefore, there may be a need for alignment and coordination between project development teams at different nodes. The progress of a development project at one node may affect the progress of a development project at another node. Timely alignment and coordination may need to be maintained between the project development teams at these two nodes. In addition, there are a large number of modifications and version iterations in the chip design process. The development project at each node will produce multiple versions of design plans, that is, a large number of documents. Therefore, it is necessary to manage a large number of documents of different versions across multiple nodes. The following is a detailed description of a document approval and archiving processing method, device, and medium for chip design provided by the present application, which meets the needs of alignment and coordination between project development teams at different nodes, and efficiently manages a large number of documents of different versions across multiple nodes.

[0031] Figure 2 The following is a flow chart of a document review and filing method for chip design provided in an embodiment of the present application. Figure 2 As shown, the document approval and archiving processing method includes the following steps.

[0032] Step S210: Determine multiple nodes associated with the chip design process, the multiple nodes include a start node and an end node, a first node among the multiple nodes satisfies at least one first dependency from the start node to the first node and then to the end node, and the development process associated with the first node in the chip design process includes: executing the respective development projects of the nodes among the multiple nodes located on the at least one first dependency one by one in the order indicated by the at least one first dependency.

[0033] Step S220: Determine a first approval process for a first document of a development project of the first node based on the at least one first dependency relationship.

[0034] Step S230: managing the update operation of the first document, the rollback operation of the first document, and the archiving operation of the first document according to the first approval process.

[0035] See also Figure 2By determining the at least one first dependency, the order of precedence indicated by the at least one first dependency can be determined, and then the development process associated with the first node in the chip design process can be determined, that is, according to the order of precedence indicated by the at least one first dependency, the development projects of the nodes located on the at least one first dependency among the multiple nodes are executed one by one. In this way, for any node among the multiple nodes, such as the first node, the at least one first dependency applicable to the first node can be determined, and then based on the at least one first dependency, the first approval process in the document approval and archiving processing of the first document applicable to the first node can be determined. In the chip design process, around the multiple nodes associated with the chip design process, there may be alignment and coordination requirements between project development teams at different nodes. The progress of a development project at one node may affect the progress of a development project at another node. In addition, there are a large number of modifications and version iterations in the chip design process. The development project of each node will generate multiple versions of design solutions, that is, a large number of documents, so it is necessary to manage a large number of documents of different versions across multiple nodes. Therefore, by determining the at least one first dependency relationship applicable to the first node, the development process associated with the first node in the chip design process includes: executing the development projects of the nodes located on the at least one first dependency relationship among the multiple nodes one by one in the order indicated by the at least one first dependency relationship; in this way, the division and composition of any nodes, links, process nodes, etc. in the chip design process can be flexibly adapted, as well as the serial and parallel execution methods between these nodes can be flexibly adapted. For example, according to the at least one first dependency relationship applicable to the first node, it can be determined that the previous node relative to the first node, the project progress of the previous node, such as the generation of a new version of the design results of the previous node, may affect the document approval and archiving processing operation of the first document of the first node, for example, the need to perform the update operation of the first document may be caused by the generation of a new version of the design results of the previous node at the previous node. By determining a first approval process for document approval and archiving processing of the first document applicable to the first node, and managing the update operation of the first document, the rollback operation of the first document, and the archiving operation of the first document according to the first approval process, respective documents across multiple nodes in the chip design process can be effectively managed, including managing the update operation, rollback operation, and archiving operation of these documents, which is conducive to efficiently managing a large number of documents with different versions across multiple nodes.

[0036] Continue reading Figure 2As mentioned above, the chip design process is associated with multiple nodes, and the development projects on these different nodes may have different development progress. Therefore, it involves alignment and coordination between different nodes, and may also involve feedback and modification between nodes in the front-end design stage and nodes in the back-end design stage. Figure 1 Taking the multiple nodes associated with the chip design process shown as an example, the post-simulation node 120 may discover errors in the circuit layout, and the modification of the circuit layout errors may need to be fed back to the front-end design stage, such as feedback to the digital circuit design node 106, and corresponding adjustments may be made at the digital circuit design node 106; the post-routing optimization node 122 may respond to user needs and chip product specifications, and impose restrictions on power consumption, design area utilization, etc., and these restrictions may be fed back to the module division node 104, which may require adjustments to the chip architecture, business modules, power supply system, etc. Therefore, a node among the multiple nodes associated with the chip design process, taking the first node as an example, on the one hand, may need to perform a document approval and archiving operation in response to the progress of the development project of the first node itself, such as generating a new version of the design results in response to the progress of the development project of the first node itself, that is, performing an update operation of the first document, or rolling back to the old version, that is, performing a rollback operation of the first document, or archiving the development project of the first node itself after it is completed, that is, performing an archiving operation of the first document; on the other hand, the first node may also be affected by the development projects of other nodes and need to perform a document approval and archiving operation on the first node, such as a new version of the design results of a previous node on which the first node depends may affect the document approval and archiving operation of the first document of the first node, such as the need to perform an update operation of the first document because a new version of the design results of the previous node is generated at the previous node. In addition, the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage need to be considered. This feedback and modification from the back-end design stage to the front-end design stage can be reflected as the progress of the development project of a node itself. For example, the first node can be set as Figure 1 The digital circuit simulation verification node 110 shown in FIG. Figure 1It can be seen that at least one first dependency relationship applicable to the digital circuit simulation verification node 110 indicates that the sequence is from the system planning node 102 to the module division node 104 to the digital circuit design node 106 and finally to the digital circuit simulation verification node 110; therefore, the first approval process of the document approval and archiving processing operation applicable to the digital circuit simulation verification node 110 involves the development projects of the system planning node 102, the module division node 104 and the digital circuit design node 106. When the post-simulation simulation node 120 finds errors in the circuit layout and feeds back to the digital circuit design node 106, the development project of the digital circuit design node 106 may need to make responsive adjustments and generate a new version, that is, it is necessary to perform an update operation. In this way, the digital circuit simulation verification node 110 may need to perform the update operation of the first document due to the influence of the new version of the design results of the digital circuit design node 106. For example, the digital circuit design node 106 changes the logic design or code description of the digital circuit part in response to the feedback of the circuit layout error. This means that the digital circuit simulation verification node 110 may need to generate a new simulation verification file, such as building a new verification environment and instantiating a new verification case, so as to provide simulation verification for the new changes made by the digital circuit design node 106. Therefore, the feedback and modification from the back-end design stage to the front-end design stage can be reflected by the progress of the development project of a corresponding node in the front-end design stage, which may trigger the document approval and archiving processing operations of more nodes.

[0037] In conclusion, Figure 2 The document approval and archiving processing method for chip design shown in the figure, by determining the first approval process for the document approval and archiving processing of the first document applicable to the first node, and managing the update operation, rollback operation and archiving operation of the first document according to the first approval process, realizes the document approval and archiving processing operation in response to the progress of the development project of the first node itself, realizes the document approval and archiving processing operation on the first node in response to the changes of the development projects of other nodes, and also realizes the document approval and archiving processing operation of the corresponding node triggered in response to the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage; it can flexibly adapt to the division and composition of any nodes, links, process nodes, etc. in the chip design process and flexibly adapt to the serial and parallel execution methods between these nodes; it can effectively manage the respective documents across multiple nodes in the chip design process, including managing the update operation, rollback operation and archiving operation of these documents, meet the alignment and coordination needs between project development teams at different nodes, and is conducive to efficient management of a large number of documents with different versions across multiple nodes, which helps to improve development efficiency.

[0038] Figure 3 A method according to the embodiment of the present application Figure 2 The schematic diagram of the first approval process determined by the document approval and archiving processing method shown in FIG. Figure 3 As shown, reference Figure 2 The document approval and archiving processing method shown in the figure determines multiple nodes associated with the chip design process, the multiple nodes include a start node and an end node, the first node among the multiple nodes satisfies at least one first dependency from the start node to the first node and then to the end node, and the development process associated with the first node in the chip design process includes: executing the development projects of the nodes located on the at least one first dependency among the multiple nodes one by one according to the sequence indicated by the at least one first dependency; determining the first approval process of the first document of the development project of the first node based on the at least one first dependency; managing the update operation of the first document, the rollback operation of the first document and the archiving operation of the first document according to the first approval process. The first approval process includes the associated projects of the first document, and the associated projects of the first document at least include the development projects of the nodes located on the at least one first dependency among the multiple nodes and located before the first node according to the sequence indicated by the at least one first dependency.

[0039] See also Figure 3 , assuming that the first node 300 is Figure 1 The mixed-signal simulation verification node 114 shown in FIG. Figure 1 The at least one first dependency relationship shown is applicable to the mixed-analog simulation verification node 114. Therefore, Figure 3 The first approval process shown is applicable to the first document of the development project of the first node 300, namely, the mixed analog and digital simulation verification project 314, including the associated projects of the first document, and the associated projects of the first document include at least the development projects of the nodes among the multiple nodes that are located on the at least one first dependency relationship and are located before the first node 300 according to the order indicated by the at least one first dependency relationship, specifically: system planning project 302, module division project 304, digital circuit design project 306, digital circuit simulation verification project 310, analog circuit design project 308 and analog circuit simulation verification project 312.

[0040] In this way, by determining the first approval process for the document approval and archiving processing of the first document applicable to the first node 300, and managing the update operation of the first document, the rollback operation of the first document, and the archiving operation of the first document according to the first approval process, it is realized that the document approval and archiving processing operation is performed in response to the progress of the development project (digital-analog hybrid simulation verification project 314) of the first node 300 itself, and the development project (system planning project 302, module division project 304, digital circuit design project 306, digital circuit simulation verification project 310, analog circuit design project 308, and analog circuit simulation verification project 312) of other nodes is changed. 00, and also realizes the document approval and archiving processing operations of the corresponding nodes triggered in response to the feedback and modifications between the nodes in the front-end design stage and the nodes in the back-end design stage; it can flexibly adapt to the division and composition of any nodes, links, process nodes, etc. in the chip design process, and flexibly adapt to the serial and parallel execution methods between these nodes; it can effectively manage the respective documents across multiple nodes in the chip design process, including the management of update operations, rollback operations and archiving operations of these documents, meet the alignment and coordination needs between project development teams at different nodes, and is conducive to the efficient management of a large number of documents with different versions across multiple nodes, which helps to improve development efficiency.

[0041] See above Figure 2 and Figure 3In a possible implementation, the first approval process includes associated projects of the first document, and the associated projects of the first document include at least development projects of nodes among the multiple nodes that are located on the at least one first dependency relationship and are located before the first node according to the order of precedence indicated by the at least one first dependency relationship. In this way, by determining the first approval process for the document approval and archiving processing of the first document applicable to the first node, and managing the update operation, rollback operation and archiving operation of the first document according to the first approval process, it is realized that the document approval and archiving processing operation is performed in response to the progress of the development project of the first node itself, the document approval and archiving processing operation is performed on the first node in response to the changes in the development projects of other nodes, and the document approval and archiving processing operation of the corresponding node is triggered in response to the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage; it can flexibly adapt to the division and composition of any nodes, links, process nodes, etc. in the chip design process and flexibly adapt to the serial and parallel execution methods between these nodes; it can effectively manage the respective documents across multiple nodes in the chip design process, including managing the update operation, rollback operation and archiving operation of these documents, which is conducive to efficiently managing a large number of documents with different versions across multiple nodes, and helps to improve development efficiency.

[0042] In some embodiments, managing the update operation of the first document according to the first approval process includes: based on the version update status of each of the associated items of the first document, determining whether to generate a new version of the first document and overwrite the current version of the first document with the new version of the first document, wherein the version update status of each of the associated items of the first document includes whether each of the associated items of the first document has undergone version updates within a specified time period. In this way, by checking whether each of the associated items of the first document has undergone version updates within a specified time period, it is possible to effectively determine whether the update operation of the first document needs to be performed. By determining the first approval process for the document approval and archiving processing of the first document applicable to the first node, and managing the update operation, rollback operation and archiving operation of the first document according to the first approval process, the document approval and archiving processing operation is implemented in response to the progress of the development project of the first node itself, the document approval and archiving processing operation is implemented on the first node in response to the changes of the development projects of other nodes, and the document approval and archiving processing operation of the corresponding node is triggered in response to the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage; the division and composition of any nodes, links, process nodes, etc. in the chip design process can be flexibly adapted, and the serial and parallel execution modes between these nodes can be flexibly adapted; the respective documents across multiple nodes in the chip design process can be effectively managed, including the update operation, rollback operation and archiving operation of these documents, which is conducive to efficiently managing a large number of documents with different versions across multiple nodes, and helps to improve development efficiency. In some examples, the specified time period is from the generation of the current version of the first document to the determination of whether to generate a new version of the first document. Here, by checking whether each of the associated items of the first document has undergone version updates during the period from the generation of the current version of the first document to the determination of whether to generate a new version of the first document, a judgment basis is provided for whether to perform the update operation of the first document. If it is determined that the update operation does not need to be performed, the current version of the first document can continue to be used; otherwise, a new version of the first document can be generated and the new version of the first document can be used to overwrite the current version of the first document.

[0043] In a possible implementation, the first approval process also includes an associated person of the first document, the associated person of the first document is the person in charge of the development project of the node located on the at least one first dependency relationship among the multiple nodes, and the document approval and archiving processing method also includes: notifying the associated person of the first document of the update operation of the first document, the rollback operation of the first document, or the archiving operation of the first document. Considering the needs of alignment and coordination between project development teams at different nodes, mainly the alignment and coordination between the persons in charge, it is beneficial to manage a large number of documents with different versions across multiple nodes by establishing an associated person of the first document and notifying the associated person of the update operation of the first document, the rollback operation of the first document, or the archiving operation of the first document. It should be understood that the associated person of the first document is the person in charge of the development project of the node located on the at least one first dependency relationship among the multiple nodes. Therefore, it covers not only the previous node relative to the first node, but also the subsequent node relative to the first node. This is because the document approval and archiving processing operations related to the first document performed on the first node (such as the update operation of the first document, the rollback operation of the first document, or the archiving operation of the first document) may affect the document approval and archiving processing operations of the design document on the subsequent node. Therefore, notifying the person in charge of the development project at the subsequent node helps to meet the alignment and coordination needs between project development teams at different nodes, and efficiently manage a large number of documents with different versions across multiple nodes.

[0044] In a possible implementation, managing the rollback operation of the first document in accordance with the first approval process includes: judging whether to overwrite the current version of the first document with the old version of the first document based on the current versions of the associated projects of the first document. The associated projects of the first document include at least development projects of nodes among the multiple nodes that are located on the at least one first dependency relationship and are located before the first node in the order indicated by the at least one first dependency relationship. In response to changes in development projects of other nodes, for example, the associated projects of the first document are rolled back to the old version, which may mean that the first node also needs to perform a rollback operation on the first document to apply the old version. Figure 1For example, assuming that the current version of the digital circuit design document of the digital circuit design node 106 is the old version after rolling back, the digital circuit simulation verification node 110 may also need to roll back the simulation verification document to adopt the old version so as to adapt to the old version of the digital circuit design document. Therefore, by determining the associated items of the first document, and then managing the rollback operation of the first document based on the current versions of the associated items of the first document, including determining whether to overwrite the current version of the first document with the old version of the first document, a large number of documents with different versions across multiple nodes are efficiently managed.

[0045] In a possible implementation, managing the archiving operation of the first document according to the first approval process includes: when the development project of the first node is completed, initiating an approval request for the first document, modifying the first document according to feedback associated with the approval request, and archiving the first document to a designated archiving location after the approval request is approved. In this way, each node or each project is managed separately, meeting the need that development projects on different nodes may have different development progress.

[0046] In some embodiments, the feedback associated with the approval request includes feedback from multiple approval nodes, and one or more approval nodes among the multiple approval nodes are based on nodes among the multiple nodes that are located on the at least one first dependency and are located after the first node in the order of precedence indicated by the at least one first dependency. As mentioned above, considering the feedback and modifications between the nodes in the front-end design stage and the nodes in the back-end design stage, such feedback and modifications from the back-end design stage to the front-end design stage can be reflected as the progress of the development project of a certain node itself. Here, the feedback from the approval node is used to determine whether to approve the approval request for executing the archiving operation of the first document. Therefore, by limiting one or more approval nodes to be nodes among the multiple nodes that are located on the at least one first dependency and are located after the first node in the order of precedence indicated by the at least one first dependency, the feedback from the back-end design stage can be reflected in advance in the archiving operation of the first document of the first node. Figure 1For example, when the post-simulation node 120 finds an error in the circuit layout and feeds back to the digital circuit design node 106, the development project of the digital circuit design node 106 may need to make responsive adjustments and generate a new version, that is, it is necessary to perform an update operation. This means that the approval node of the digital circuit design document (corresponding to the first document) of the digital circuit design node 106 includes the post-simulation node 120, that is, the feedback from the post-simulation node 120 can affect whether to agree to end the open project of the digital circuit design node 106 and perform an archiving operation on the digital circuit design document, which helps to trigger the document approval and archiving processing operation of the corresponding node in response to the feedback and modification between the nodes in the front-end design stage and the nodes in the back-end design stage.

[0047] In some embodiments, the archiving operation of the first document includes performing watermark processing on the first document and adding read-write permission protection. In this way, data security is improved. After the document processing is completed, the document can be subjected to corresponding watermark processing according to the design before approval, and watermarks can be added, deleted, modified, and read-write protected for external documents as required, and corresponding read-write protection can be performed for internal documents.

[0048] In some embodiments, the first document is configured to be previewed and approved through a file preview operation, and after the archiving operation of the first document is performed, the archived first document is configured to be searched through the mapping relationship between the document information of the first document and the specified archiving location. In this way, the search efficiency is improved. After the document approval is completed, the corresponding document is mapped with the document information, and the corresponding file can be searched according to the file information when searching for the corresponding file, so that accurate search can be performed, which solves the problem that the file cannot be found. In addition, in each approval node, the corresponding file can be directly clicked to perform the corresponding file preview operation. In some examples, after the archiving operation of the first document is performed, if the archived first document is not found in the local cache, the archived first document is obtained from the version control system node corresponding to the first node. In this way, the search efficiency is improved.

[0049] In a possible implementation, the multiple nodes include one or more of the following: system planning nodes, module partitioning nodes, digital circuit design nodes, analog circuit design nodes, digital circuit simulation verification nodes, analog circuit simulation verification nodes, digital-analog hybrid simulation verification nodes, layout planning nodes, top-level wiring nodes, post-simulation simulation nodes, and post-wiring optimization nodes. In this way, the division and composition of any nodes, links, process nodes, etc. in the chip design process can be flexibly adapted, as well as the serial and parallel execution modes between these nodes can be flexibly adapted.

[0050] In a possible implementation, the first node is any node among the multiple nodes except the start node and the end node. In this way, the division and composition of any nodes, links, process nodes, etc. in the chip design process can be flexibly adapted, as well as the serial and parallel execution modes between these nodes can be flexibly adapted.

[0051] Figure 4 4 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 400 includes: one or more processors 410, a communication interface 420 and a memory 430. The processor 410, the communication interface 420 and the memory 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, and the input / output interface 450 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 410 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the computing device 400 performing various operations can refer to the specific details in the above-mentioned embodiments, such as the processor 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 400 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 420 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 410 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0052] It should be understood that Figure 4 The computing device 400 may include one or more processors 410, and the multiple processors 410 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 410 may form a processor sequence or a processor array, or the multiple processors 410 may be divided into a main processor and an auxiliary processor, or the multiple processors 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 4 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 4 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0053] The processor 410 may have a variety of specific implementation forms. For example, the processor 410 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 410 may also be a single-core processor or a multi-core processor. The processor 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0054] The memory 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 may also be used to store program codes and data, so that the processor 410 calls the program codes stored in the memory 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 4 Show more or fewer components, or have different component configurations.

[0055] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0056] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0057] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0058] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0059] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0060] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A document review and filing method for chip design, characterized in that: The document approval and archiving processing method comprises: Determine a plurality of nodes associated with a chip design process, the plurality of nodes including a start node and an end node, a first node among the plurality of nodes satisfies at least one first dependency relationship from the start node to the first node and then to the end node, and a development flow associated with the first node in the chip design process includes: executing development projects of the nodes located on the at least one first dependency relationship among the plurality of nodes one by one in a sequence indicated by the at least one first dependency relationship; Based on the at least one first dependency, determining a first approval process for a first document of a development project of the first node; managing the update operation of the first document, the rollback operation of the first document, and the archiving operation of the first document according to the first approval process, The first approval process includes associated projects of the first document, and the associated projects of the first document at least include development projects of nodes among the multiple nodes that are located on the at least one first dependency relationship and are located before the first node according to the sequence indicated by the at least one first dependency relationship. Managing the update operation of the first document according to the first approval process includes: determining whether to generate a new version of the first document and overwriting the current version of the first document with the new version of the first document based on the version update status of each of the associated items of the first document, wherein the version update status of each of the associated items of the first document includes whether each of the associated items of the first document has undergone version update within a specified time period, The specified time period is from the generation of the current version of the first document to the determination of whether to generate a new version of the first document, The multiple nodes include one or more of the following: system planning node, module partitioning node, digital circuit design node, analog circuit design node, digital circuit simulation verification node, analog circuit simulation verification node, digital-analog mixed simulation verification node, layout planning node, top-level wiring node, post-simulation simulation node, and post-wiring optimization node.

2. The document approval and archiving processing method according to claim 1 is characterized in that: The first approval process also includes an associated person of the first document, and the associated person of the first document is a person in charge of a development project of a node among the multiple nodes located on at least one first dependency relationship. The document approval archiving processing method also includes: notifying the associated person of the first document of an update operation of the first document, a rollback operation of the first document, or an archiving operation of the first document performed.

3. The document approval and archiving processing method according to claim 1 is characterized in that: According to the first approval process, managing the rollback operation of the first document includes: based on the current versions of the associated items of the first document, determining whether to overwrite the current version of the first document with the old version of the first document.

4. The document approval and archiving processing method according to claim 1 is characterized in that: Managing the archiving operation of the first document in accordance with the first approval process includes: initiating an approval request for the first document when the development project of the first node is completed, modifying the first document according to feedback associated with the approval request, and archiving the first document to a designated archiving location after the approval request is approved.

5. The document approval and archiving processing method according to claim 4 is characterized in that: The feedback associated with the approval request includes feedback of multiple approval nodes, and one or more approval nodes among the multiple approval nodes are based on nodes among the multiple nodes that are located on the at least one first dependency relationship and are located after the first node according to the order indicated by the at least one first dependency relationship.

6. The document approval and archiving processing method according to claim 4 is characterized in that: The archiving operation of the first document includes performing watermark processing on the first document and adding read-write permission protection.

7. The document approval and archiving processing method according to claim 5 is characterized in that: The first document is configured to be previewable and approved through a file preview operation, and after performing an archiving operation of the first document, the archived first document is configured to be searchable through a mapping relationship between document information of the first document and the designated archiving location.

8. The document approval and archiving processing method according to claim 7 is characterized in that: After performing the archiving operation of the first document, if the archived first document is not found in the local cache, the archived first document is obtained from the version control system node corresponding to the first node.

9. The document approval and archiving processing method according to claim 1 is characterized in that: The first node is any one of the plurality of nodes except the start node and the end node.

10. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 9 when executing the computer program.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 9.

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