Text optimization operation method based on machine learning and related devices

Abstract

The present application provides a text optimization operation method based on machine learning and a related device, which is applied to FPGA chips, including: inputting text data corresponding to the code to be run in the machine learning model into a word segmenter to split the text data into multiple text units, and then adding task tags to the text units; inputting the text units and the corresponding task tags into a configurator to obtain the association information of the text units and the task tags and the sorting information of the multiple text units; inputting the text units, the association information and the task tags sorted according to the sorting information into a text conversion model to convert the code format of the text units into the target code format corresponding to the assembly language, and outputting the converted target text units; optimizing the loop text information and conditional text information in the target text unit, completing the optimization of the target text unit, so that the machine learning model can run the target text unit. The method can reduce the dependence of model operations on high-end processors.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular, relates to a text optimization operation method based on machine learning and related devices. Background Art

[0002] With the rapid development of artificial intelligence, the efficiency and performance of algorithms are crucial in the field of modern artificial intelligence, especially in machine learning and deep learning applications. Artificial neural network algorithms, such as convolutional neural networks for computer vision and recurrent neural networks for natural language processing, require a lot of computing resources for data processing and model training. These processes involve complex mathematical operations, especially matrix operations, which are the core components of these algorithms. Therefore, improving the efficiency of these basic operations is crucial to improving overall performance.

[0003] Currently, the implementation of machine learning models mainly relies on high-level programming languages ​​and various frameworks, such as Python with TensorFlow or PyTorch. Although these tools are easy to use and understand, high-level programming languages ​​usually cannot fully utilize hardware resources. Due to their high level of abstraction, it is difficult to perform underlying hardware optimization, resulting in the processor's computing power not being fully utilized. At the same time, high-level programming environments are usually optimized for general performance rather than for the characteristics of specific hardware. This means that even when running on high-performance hardware, optimal performance may not be achieved. When performing complex calculations, especially scenarios involving a large number of matrix operations, these high-level tools often introduce additional computing delays. Due to the lack of fine control over the hardware, the code written by high-level tools in application scenarios that need to run for a long time often consumes more energy when executed. Summary of the invention

[0004] The embodiment of the present application provides a text optimization operation method and related devices based on machine learning, which can solve the computing scenarios of traditional artificial intelligence models involving a large number of matrix operations. The introduction of complex models often introduces additional computing delays. Due to the lack of fine control over hardware, the code written by advanced tools in application scenarios that need to run for a long time often consumes more energy when executed. The method provided can perform complex mathematical operations faster, and the optimized code can run on lower-performance hardware while still maintaining efficient processing speed. This reduces the dependence of model operations on high-end processors, allowing the model to be deployed and used on a wider range of devices. At the same time, the code can be customized according to the characteristics of specific hardware to give full play to the advantages of specific processors, thereby achieving better performance.

[0005] In a first aspect, an embodiment of the present application provides a text optimization operation method based on machine learning, which is applied to an FPGA chip, wherein the FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter, and a configurator; the method comprises:

[0006] Inputting text data corresponding to the code to be run in the machine learning model into the word segmenter, the word segmenter is used to split the text data into multiple text units, and then add task tags to the text units; the task tags include a start tag, an end tag and a task description tag;

[0007] Inputting the text unit and the task mark corresponding to the text unit into the configurator, the configurator acquiring the association information between the text unit and the task mark and the sorting information of the text units according to the plurality of text units and the corresponding task marks;

[0008] Sorting the plurality of text units according to the sorting information, inputting the sorted plurality of text units, the associated information and the task tag into the text conversion model, the text conversion model being used to convert the code format of the text unit into a target code format, and outputting the converted target text unit; the target code format is a code format corresponding to the assembly language;

[0009] Acquire loop text information and conditional text information in the target text unit;

[0010] The loop text information and the conditional text information are optimized to complete the optimization of the target text unit so that the machine learning model can run the target text unit.

[0011] In some embodiments, a preset vocabulary is stored in the word segmenter, and the preset vocabulary includes preset words and preset tags corresponding to the preset words; the word segmenter is used to split the text data into multiple text units, and then add task tags to the text units, including: the word segmenter splits the text unit according to a preset text size to obtain multiple text units; the word segmenter is used to match the text unit with the preset vocabulary, and adds the preset tag corresponding to the successfully matched preset vocabulary as the task tag to the text unit.

[0012] In some embodiments, the configurator includes an input encoder, a task description encoder, a decoder and an output generation layer; the configurator obtains the association information between the text unit and the task tag and the sorting information of the multiple text units based on the multiple text units and the corresponding task tags, including: inputting the text unit into the input encoder to obtain text encoding information; inputting the task tag into the input task description encoder to obtain task encoding information; inputting the text encoding information and the task encoding information into the decoder, the decoder obtains the association information between the text encoding information and the corresponding task encoding information based on a self-attention mechanism, and also matches based on multiple text encoding information to obtain context information of multiple text encoding information, generates the sorting information based on the context information, and outputs the association information and the sorting information through the output generation layer.

[0013] In some embodiments, before inputting the sorted multiple text units, the associated information and the task tags into the text conversion model, the method also includes: obtaining first operation result information of the machine learning model running the text data; inputting the multiple text units and the task tags into the text conversion model to be trained, and obtaining the predicted text unit output by the text conversion model to be trained by converting the code format of the text unit into the target code format; inputting the predicted text unit into the machine learning model, and obtaining second operation result information of the machine learning model running the multiple predicted text units; and completing the training of the text conversion model to be trained according to the first operation result information and the second operation result information.

[0014] In some embodiments, the step of inputting the sorted plurality of text units, the associated information and the task tag into the text conversion model includes: determining a plurality of instruction types included in the text unit according to the task tag; the instruction type is used to determine the operation performed when the machine learning model runs the text unit; determining an instruction type to be optimized among the plurality of instruction types; the instruction type to be optimized is an instruction type having a priority lower than a preset priority; and optimizing the plurality of text units according to the associated information and the instruction type to be optimized.

[0015] In some embodiments, the code format of the text unit is the code format corresponding to Python; the text conversion model is used to convert the code format of the text unit into a target code format, including: obtaining the weight parameters of the text unit and the input position information of the weight parameters input into the machine learning model; the text conversion model converts the format of the weight parameters of the text unit into the target code format, and outputs the target weight parameters and the input position information corresponding to the target weight parameters.

[0016] Exemplarily, the weight parameters include a weight matrix. After completing the optimization of the target text unit so that the machine learning model can run the target text unit, it also includes: inputting the target text unit into the machine learning model; the machine learning model multiplies the column matrix of the text input matrix corresponding to the target text unit by the row matrix of the weight matrix to obtain values ​​corresponding to multiple third running result information.

[0017] In a second aspect, an embodiment of the present application provides a text optimization operation method device based on machine learning, which is applied to an FPGA chip, wherein the FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter, and a configurator; the device includes:

[0018] A word segmentation module, used for inputting text data corresponding to the code to be run in the machine learning model into the word segmenter, the word segmenter is used for splitting the text data into multiple text units, and then adding task tags to the text units; the task tags include a start tag, an end tag and a task description tag;

[0019] An input module, used for inputting the text unit and the task mark corresponding to the text unit into the configurator, and the configurator obtains the association information between the text unit and the task mark and the sorting information of the text units according to the multiple text units and the corresponding task marks;

[0020] A conversion module, used for sorting the plurality of text units according to the sorting information, inputting the sorted plurality of text units and the task tag into the text conversion model, the text conversion model is used for converting the code format of the text unit into a target code format, and outputting the converted target text unit; the target code format is a code format corresponding to the assembly language;

[0021] An acquisition module, used for acquiring the loop text information and conditional text information in the target text unit;

[0022] An optimization module is used to optimize the loop text information and the conditional text information to complete the optimization of the target text unit so that the machine learning model can run the target text unit.

[0023] In a third aspect, an embodiment of the present application provides an FPGA chip, wherein the FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter, and a configurator;

[0024] Among them, the FPGA chip also includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and is characterized in that when the processor executes the computer program, it implements the text optimization operation method based on machine learning as provided in any embodiment of the present application.

[0025] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0026] In the technical solution provided by the embodiment of the present application, first, the text data corresponding to the code to be run in the machine learning model is input into a word segmenter, which is used to split the text data into multiple text units, and then add task tags to the text units; the task tags include start tags, end tags and task description tags; secondly, the text units and the task tags corresponding to the text units are input into a configurator, and the configurator obtains the association information of the text units and the task tags and the sorting information of the multiple text units according to the multiple text units and the corresponding task tags; then, the multiple text units are sorted according to the sorting information, and the sorted multiple text units, the association information and the task tags are input into a text conversion model, and the text conversion model is used to convert the code format of the text unit into a target code format, and output the converted target text unit; the target code format is the code format corresponding to the assembly language; then, the loop text information and conditional text information in the target text unit are obtained; finally, the loop text information and the conditional text information are optimized to complete the optimization of the target text unit, so that the machine learning model can run the target text unit

[0027] In the embodiment of the present application, the method provided can perform complex mathematical operations faster by converting the code to be run according to the machine learning model into the code format corresponding to the assembly language, and the optimized code can be run on lower performance hardware while still maintaining efficient processing speed. This reduces the dependence on high-end processors and enables the model to be deployed and used on a wider range of devices. At the same time, the code can be customized according to the characteristics of specific hardware to give full play to the advantages of specific processors, thereby achieving better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a schematic flow chart of a text optimization operation method based on machine learning provided in an embodiment of the present application;

[0030] Figure 2 It is a structural schematic diagram of a text optimization operation method device based on machine learning provided in an embodiment of the present application;

[0031] Figure 3 It is a structural diagram of the DMA engine provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0033] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0034] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0035] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0036] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0037] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0038] To facilitate understanding of the contents of this application specification, some words that appear in the embodiments of this application are introduced below.

[0039] FPGA (Field-Programmable Gate Array) is a field-programmable gate array, which is a further development of programmable devices such as PAL, GAL, CPLD, etc. It is a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0040] t5-small model: t5 (Text-to-Text Transfer Transformer) model, in which the transformer model is a deep learning model based on the self-attention mechanism. Compared with the traditional recurrent neural network (RNN) and convolutional neural network (CNN) structures, it adopts a new self-attention mechanism and multi-head attention structure, which greatly improves the training speed and performance of the model. The t5-small model is a pre-trained model based on Transformer. Unlike previous pre-trained models such as BERT and GPT, the t5-small model unifies all natural language processing tasks into a text-to-text conversion task, and achieves better transfer learning effects through end-to-end training.

[0041] The technical solution of the embodiment of the present application is introduced below.

[0042] With the rapid development of artificial intelligence, the efficiency and performance of algorithms are crucial in the field of modern artificial intelligence, especially in machine learning and deep learning applications. Artificial neural network algorithms, such as convolutional neural networks for computer vision and recurrent neural networks for natural language processing, require a lot of computing resources for data processing and model training. These processes involve complex mathematical operations, especially matrix operations, which are the core components of these algorithms. Therefore, improving the efficiency of these basic operations is crucial to improving overall performance.

[0043] Currently, the implementation of machine learning models mainly relies on high-level programming languages ​​and various frameworks, such as Python with TensorFlow or PyTorch. Although these tools are easy to use and understand, high-level programming languages ​​usually cannot fully utilize hardware resources. Due to their high level of abstraction, it is difficult to perform underlying hardware optimization, resulting in the processor's computing power not being fully utilized. At the same time, high-level programming environments are usually optimized for general performance rather than for the characteristics of specific hardware. This means that even when running on high-performance hardware, optimal performance may not be achieved. When performing complex calculations, especially scenarios involving a large number of matrix operations, these high-level tools often introduce additional computing delays. Due to the lack of fine control over the hardware, the code written by high-level tools in application scenarios that need to run for a long time often consumes more energy when executed.

[0044] To solve the above problem, see Figure 1 , Figure 1 It is a schematic flowchart of the text optimization operation method based on machine learning provided in an embodiment of the present application. As an example but not a limitation, the method can be applied to an FPGA chip equipped with a machine learning model, a text conversion model, a word segmenter and a configurator.

[0045] In some embodiments, the text conversion model is a t5-small model, and the word segmenter is a Tokenizer, which is a component used to convert text into an input format acceptable to the model. It splits the input text into small units and then maps these units to tokens in the vocabulary of the model. The Tokenizer is also responsible for adding special start and end tags, as well as task description tags, to tell the model the start and end positions of the input, as well as the task type.

[0046] It should be noted that the machine learning model can be a model for any scenario to complete the corresponding task according to the user's settings. The embodiment of the present application does not limit the scenario and type of application of the machine learning model. The method includes the following steps:

[0047] S101. Input the text data corresponding to the code to be run in the machine learning model into a word segmenter. The word segmenter is used to split the text data into multiple text units, and then add task tags to the text units; the task tags include a start tag, an end tag and a task description tag.

[0048] Specifically, when the machine learning model carried by the FPGA chip needs to run any code, the text data corresponding to the code to be run is input into a preset word segmenter, such as a Tokenizer, so that the text data can be split into multiple text units, and the size of the text unit is set and adjusted according to the computing power of the FPGA chip and the needs of the user. At the same time, task tags for describing the type of text unit, such as start tags, end tags, and task description tags, are added to the text unit. Then the FPGA chip can split the text data corresponding to the code into individual text units, and can clarify the specific functions of the text units to improve the accuracy of subsequent text processing.

[0049] In some embodiments, the word segmenter stores a preset vocabulary, the preset vocabulary includes preset words and preset tags corresponding to the preset words; the word segmenter is used to split the text data into multiple text units, and then add task tags to the text units, including: the word segmenter splits the text unit according to the preset text size to obtain multiple text units; the word segmenter is used to match the text unit with the preset vocabulary, and the preset tag corresponding to the successfully matched preset vocabulary is added to the text unit as the task tag. By constructing a vocabulary, the FPGA chip can quickly determine the function of each text unit by mapping the text unit to the vocabulary.

[0050] S102: Input text units and task tags corresponding to the text units into a configurator, and the configurator obtains association information between the text units and the task tags and sorting information of the multiple text units according to the multiple text units and the corresponding task tags.

[0051] Specifically, the FPGA chip inputs the split text units and the task tags corresponding to the text units into the configurator, for example, the configurator is a T5Model that includes an input encoder, a task description encoder, a decoder, and an output generation layer. Then the configurator can obtain the association between the text unit and the task tag according to the tag corresponding to the text unit, that is, determine the dependency between the text unit and the task tag. And determine the sorting information of multiple text units according to the contextual word order relationship of the text unit, so that the corresponding sorting of the text unit can be determined according to its content in the future, ensuring that the text processed later is clear and continuous, and avoiding the converted text unit from failing to run normally.

[0052] In some embodiments, the configurator includes an input encoder, a task description encoder, a decoder, and an output generation layer; the configurator obtains the association information of the text unit and the task tag and the sorting information of the text unit according to the multiple text units and the corresponding task tags, including: inputting the text unit into the input encoder to obtain text encoding information; inputting the task tag into the input task description encoder to obtain task encoding information; inputting the text encoding information and the task encoding information into the decoder, the decoder obtains the association information of the text encoding information and the corresponding task encoding information based on the self-attention mechanism, and also matches according to the multiple text encoding information to obtain the context information of the multiple text encoding information, generates the sorting information according to the context information, and outputs the association information and the sorting information through the output generation layer. The provided method can clearly construct the dependency relationship between the text unit and the task tag and accurately sort the text units based on the context.

[0053] S103. Sort multiple text units according to the sorting information, and input the sorted multiple text units, related information and task tags into a text conversion model. The text conversion model is used to convert the code format of the text unit into a target code format, and output the converted target text unit; the target code format is a code format corresponding to the assembly language.

[0054] Specifically, the FPGA chip sorts the text units according to the obtained sorting information, and then inputs the sorted text units, associated information and task tags into the text conversion model to convert the text units from a high-performance code format to a target code format corresponding to the assembly language, so that complex mathematical operations can be performed faster by converting the code to be run according to the machine learning model into a code format corresponding to the assembly language. The optimized code can run on lower-performance hardware while still maintaining an efficient processing speed. This reduces the reliance on high-end processors and enables the model to be deployed and used on a wider range of devices.

[0055] In some embodiments, before inputting the sorted multiple text units, the associated information and the task tags into the text conversion model, the method also includes: obtaining first operation result information of the machine learning model running the text data; inputting the multiple text units and the task tags into the text conversion model to be trained, and obtaining the predicted text unit output by the text conversion model to be trained by converting the code format of the text unit into the target code format; inputting the predicted text unit into the machine learning model, and obtaining second operation result information of the machine learning model running the multiple predicted text units; and completing the training of the text conversion model to be trained according to the first operation result information and the second operation result information.

[0056] To ensure that the text conversion model can accurately convert the format of text units, the running results of the machine learning model based on the unconverted code are obtained and compared with the running results of the predicted text units in the assembly language format converted by the text conversion model to be trained. It is verified whether the output of the text conversion model under various input conditions matches the results of the Python version to ensure correct functionality. At the same time, performance testing is performed to ensure that the assembly implementation has sufficient speed and resource efficiency.

[0057] In some embodiments, the step of inputting the sorted plurality of text units, the associated information and the task tag into the text conversion model includes: determining a plurality of instruction types included in the text unit according to the task tag; the instruction type is used to determine the operation performed when the machine learning model runs the text unit; determining an instruction type to be optimized among the plurality of instruction types; the instruction type to be optimized is an instruction type having a priority lower than a preset priority; and optimizing the plurality of text units according to the associated information and the instruction type to be optimized.

[0058] For example, suppose there is a task to perform sentiment analysis on product reviews and predict the possibility of product sales based on the results of sentiment analysis. The text conversion model needs to process a large number of product reviews and extract sentiment information and other related features, such as product name, user ID, etc. The following is a specific example. Assume that there are the following three review text units: "This phone is really great! It is fast and the camera is clear", "The after-sales service is too poor. No one answered the phone after several calls", "The appearance design is beautiful, but the battery capacity is too small and the battery life is short." There is also related information, such as product name and user ID. The task tag may include a label for sentiment analysis, such as "positive", "negative" or "neutral". According to the steps in the description, first, determine the instruction type included in the text unit according to the task tag. For example, sentiment analysis can be identified as an instruction type for determining the sentiment tendency of the review. Then, determine the instruction type to be optimized. Assume that you want to prioritize sentiment analysis because sentiment analysis may be more critical to predicting sales. Optimize the text unit according to the related information and the instruction type to be optimized: For each comment, you can first extract the sentiment information, and use the related information (such as product name) and other possible features in this process. Then, the comments can be classified according to the results of the sentiment information, for example, the first comment may be classified as "positive", the second comment may be classified as "negative", and the third comment may be "neutral". Further, considering that modern computers have multi-core and parallel processing capabilities, multiple text units can be processed in parallel, thereby improving processing efficiency.

[0059] In the above example, in addition to sentiment analysis, other features that may have an impact on sales prediction can also be considered, such as the price of the product, brand reputation, etc. Therefore, feature selection can be performed before sentiment analysis to improve the accuracy and efficiency of the model. Alternatively, advanced model architectures and algorithms, such as deep learning models, can be used to better capture the complex relationships in text information and improve the accuracy of predictions. Alternatively, based on real-time feedback from the model, optimization strategies can be dynamically adjusted to further improve performance. Through these optimization measures, text transformation models can be more effectively used to process large amounts of text data and more accurately predict the likelihood of product sales.

[0060] For FPGA chips, since one instruction type has seven different operations, and two of the operations correspond to two slots, one instruction will correspond to nine slots. After each cycle instruction is taken out, all slots will be checked and processed. If each instruction only has one operation, it will not only reduce the utilization rate of the slot in the instruction, but also increase the number of instruction fetches. Therefore, when implementing a text conversion model such as a t5-small model, unrelated operations will be manually merged into one instruction according to the execution order of different operations and the logical dependencies, which can greatly reduce the number of instructions.

[0061] At the same time, the FPGA chip is equipped with a software simulator that can simulate the entire process of instruction acquisition and execution. Up to seven different operations can be packed into one instruction. All instructions will be stored in the instruction pool before execution. The general process includes: taking out an instruction from the instruction pool in each cycle, decoding the taken-out instructions, and transmitting the decoded content to the processor for execution.

[0062] At this time, without changing the logic of the original model, optimizing the arrangement of instructions, using multiple channels, eliminating the dependencies between upper and lower operations, etc. can greatly reduce the number of instructions and the instruction execution cycle.

[0063] S104: Acquire loop text information and conditional text information in the target text unit.

[0064] Specifically, the FPGA chip obtains loop text information and conditional text information in the target text unit, such as loop statements and conditional statements in the assembly language, and can perform secondary correction on code statements with strong logic.

[0065] S105. Optimize the loop text information and the conditional text information to complete the optimization of the target text unit so that the machine learning model can run the target text unit.

[0066] Specifically, the FPGA chip optimizes loop text information and conditional text information, such as loop statements and conditional statements, for example, by performing secondary correction or the built-in correction module in the FPGA chip has optimized the loop text information and conditional text information according to preset rules. Ultimately, it ensures that the machine learning model can run the converted target text unit normally. The provided method can perform complex mathematical operations faster by converting the code to be run according to the machine learning model into the code format corresponding to the assembly language. The optimized code can run on lower performance hardware while still maintaining an efficient processing speed. This reduces the dependence on high-end processors, allowing the model to be deployed and used on a wider range of devices. At the same time, the code can be customized according to the characteristics of specific hardware to give full play to the advantages of specific processors, thereby achieving better performance.

[0067] In some embodiments, the code format of the text unit is the code format corresponding to Python; the text conversion model is used to convert the code format of the text unit into a target code format, including: obtaining the weight parameters of the text unit and the input position information of the weight parameters input into the machine learning model; the text conversion model converts the format of the weight parameters of the text unit into the target code format, and outputs the target weight parameters and the input position information corresponding to the target weight parameters.

[0068] For the conversion of the target text unit, it involves matrix operations, activation functions, regularization, etc. in the text conversion model. For the weight parameters, the weight values ​​in the Python code need to be converted into assembly language format and loaded into the corresponding position of the model. It is necessary to ensure that the assembly version of the model has the same network structure and parameters as the Python version of the model so that they can produce similar results.

[0069] Exemplarily, the weight parameters include a weight matrix. After completing the optimization of the target text unit so that the machine learning model can run the target text unit, it also includes: inputting the target text unit into the machine learning model; the machine learning model multiplies the column matrix of the text input matrix corresponding to the target text unit by the row matrix of the weight matrix to obtain values ​​corresponding to multiple third running result information.

[0070] For any machine learning model, the core content is matrix multiplication. The mode of matrix multiplication will affect the number of cycles of instruction execution. This application multiplies the rows of the weight matrix with the corresponding columns of the input matrix. Generally speaking, the size of the weight matrix will be very large. The matrix multiplication method provided ensures that the submatrix corresponding to the weight matrix will only be taken once at most, and the input matrix will be taken multiple times. This improves the efficiency of the conversion.

[0071] It should be noted that in the process of matrix multiplication, multiple input matrices will be multiplied with the same weight matrix in sequence. At this time, there are several steps: loading the input matrix, matrix multiplication, and storing the answer. If any multiplication uses the registers in the same FPGA chip to perform the three steps, it is very likely that the next multiplication will have to wait until the current multiplication is completed before it can start. However, when the current multiplication is storing the answer, the next multiplication can start the step of loading the input matrix in advance. Therefore, unnecessary dependencies in the context will be manually reduced.

[0072] At the same time, when the text conversion model is the t5-small model, due to the complex neural network structure of the t5-small model, the matrix to be multiplied is often very large, and the entire matrix cannot be placed in the storage area to be operated at once. It is often necessary to first place the matrix in a large-capacity, high-bitwidth random access memory, and then use direct memory access to send the required sub-matrix to the storage area to be operated for multiplication each time. In order to improve the parallelism of instructions, direct memory access serves matrix multiplication, and each time the current matrix multiplication is started, the next required matrix content is transmitted. After the current matrix multiplication is completed, the next required matrix has been transmitted, so the matrix multiplication can be continued seamlessly, and the data transmission part is completely hidden in the matrix multiplication.

[0073] This example involves how to optimize data transmission and processing to improve the parallelism and efficiency of instructions when processing complex neural network models (such as T5-small). This process is illustrated by a specific example:

[0074] Suppose there is a text conversion task that requires the use of the T5-small model to process a large amount of text data. Encode each text data into a matrix and perform matrix multiplication operations on the T5-small model. Based on this, first, there is a text data matrix A to be processed, whose size is [1000x 500] (1000 words, each word is represented by a 500-dimensional vector). Put matrix A into a high-bit-width random access memory (RAM). At the same time, start transferring the next text data matrix B from the RAM to the storage area to be operated. Assume that the size of matrix B is also [1000x 500]. In the storage area to be operated, start multiplying matrices A and B, and transfer data at the same time. Since the calculation of multiplication and data transmission can be performed in parallel, the next matrix C has been transferred before the current multiplication operation is completed. Once the current multiplication operation is completed, there is no need to wait, and the multiplication operation on matrix C can be started immediately, and the next matrix D can be transferred at the same time. In this way, data transfer and matrix multiplication operations can be seamlessly alternating, making use of instruction-level parallelism throughout the entire process and improving computational efficiency.

[0075] In this way, the data transmission part can be completely hidden in the matrix multiplication operation, thereby maximizing the use of computing resources and improving the efficiency and performance of the T5-small model when processing large-scale text data.

[0076] In the embodiment of the present application, by converting the code to be run according to the machine learning model into the code format corresponding to the assembly language, complex mathematical operations can be performed faster, and the optimized code can be run on lower performance hardware while still maintaining efficient processing speed. This reduces the dependence on high-end processors, allowing the model to be deployed and used on a wider range of devices. At the same time, the code can be customized according to the characteristics of specific hardware, giving full play to the advantages of specific processors, thereby achieving better performance.

[0077] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0078] Corresponding to the text optimization operation method based on machine learning described in the above embodiment, Figure 2 The structure block diagram of the text optimization operation method device based on machine learning provided by the embodiment of the present application is shown. The device can be applied to an FPGA chip. The FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter and a configurator. Figure 2 , the device comprises:

[0079] The word segmentation module 201 is used to input the text data corresponding to the code to be run in the machine learning model into the word segmenter, and the word segmenter is used to split the text data into multiple text units, and then add task tags to the text units; the task tags include a start tag, an end tag and a task description tag.

[0080] The input module 202 is used to input the text unit and the task tag corresponding to the text unit into the configurator, and the configurator obtains the association information between the text unit and the task tag and the sorting information of the multiple text units based on the multiple text units and the corresponding task tags.

[0081] The conversion module 203 is used to sort the multiple text units according to the sorting information, and input the sorted multiple text units and the task tags into the text conversion model, and the text conversion model is used to convert the code format of the text unit into a target code format, and output the converted target text unit; the target code format is a code format corresponding to the assembly language.

[0082] The acquisition module 204 is used to acquire the loop text information and conditional text information in the target text unit.

[0083] The optimization module 205 is used to optimize the loop text information and the conditional text information, and complete the optimization of the target text unit so that the machine learning model can run the target text unit.

[0084] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0085] The FPGA chip provided in the present application includes a DMA engine 11 and a memory, and the DMA engine 11 is equipped with a strategy simulation module.

[0086] Please also refer to Figure 3 , Figure 3 A schematic diagram of the structure of the FPGA chip provided in the embodiment of the present application. Figure 3 The provided FPGA chip 11 includes: at least one processor 111, a memory 112, and a computer program 113 stored in the memory 112 and executable on the at least one processor 111. When the processor 111 executes the computer program 113, the steps in any of the above-mentioned method embodiments are implemented.

[0087] The FPGA chip 11 can be installed in computing devices such as desktop computers, notebooks, PDAs, and cloud servers. The computer device in which the FPGA chip 11 is installed may include, but is not limited to, a processor 111 and a memory 112. Those skilled in the art will appreciate that Figure 3 It is only an example of the DMA engine 11 and does not constitute a limitation on the FPGA chip 11. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, for example, it may also include input and output devices, network access devices, etc.

[0088] The processor 111 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0089] In some embodiments, the memory 112 may be an internal storage unit of the FPGA chip 11, such as a hard disk or memory of the FPGA chip 11. In other embodiments, the memory 112 may also be an external storage device of the DMA engine 11, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the FPGA chip 11. Further, the memory 112 may also include both an internal storage unit of the FPGA chip 11 and an external storage device. The memory 112 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 112 may also be used to temporarily store data that has been output or is to be output.

[0090] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0091] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0092] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the DMA engine, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0093] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0095] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0096] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A text optimization operation method based on machine learning, characterized in that: Applied to an FPGA chip, the FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter and a configurator; the method includes: Inputting text data corresponding to the code to be run in the machine learning model into the word segmenter, the word segmenter is used to split the text data into multiple text units, and then add task tags to the text units; the task tags include a start tag, an end tag and a task description tag; Inputting the text unit and the task mark corresponding to the text unit into the configurator, the configurator acquiring the association information between the text unit and the task mark and the sorting information of the text units according to the plurality of text units and the corresponding task marks; Sorting the plurality of text units according to the sorting information, inputting the sorted plurality of text units, the associated information and the task tag into the text conversion model, the text conversion model being used to convert the code format of the text unit into a target code format, and outputting the converted target text unit; the target code format is a code format corresponding to the assembly language; Acquire loop text information and conditional text information in the target text unit; Optimizing the loop text information and the conditional text information to complete the optimization of the target text unit so that the machine learning model can run the target text unit; The configurator includes an input encoder, a task description encoder, a decoder, and an output generation layer; the configurator obtains association information between the text units and the task tags and sorting information of the text units according to the text units and the corresponding task tags, including: Inputting the text unit into the input encoder to obtain text encoding information; Inputting the task tag into the task description encoder to obtain task encoding information; The text encoding information and the task encoding information are input into the decoder, and the decoder obtains the association information between the text encoding information and the corresponding task encoding information based on a self-attention mechanism, and also performs matching based on a plurality of the text encoding information to obtain context information of the plurality of the text encoding information, and generates the sorting information based on the context information, so as to output the association information and the sorting information through the output generation layer.

2. The method according to claim 1, characterized in that The word segmenter stores a preset vocabulary, wherein the preset vocabulary includes preset words and preset tags corresponding to the preset words; The word segmenter is used to split the text data into multiple text units, and then add task tags to the text units, including: The word segmenter splits the text unit according to a preset text size to obtain a plurality of the text units; The word segmenter is used to match the text unit with the preset vocabulary, and add the preset mark corresponding to the successfully matched preset vocabulary as the task mark to the text unit.

3. The method according to claim 1, characterized in that Before inputting the sorted plurality of text units, the associated information and the task tags into the text conversion model, the method further includes: Obtaining first operation result information of the machine learning model running the text data; Inputting the plurality of text units and the task tags into the text conversion model to be trained, obtaining a predicted text unit outputted by converting the code format of the text unit into a target code format by the text conversion model to be trained; Inputting the predicted text unit into the machine learning model, and obtaining second operation result information of the machine learning model running a plurality of the predicted text units; The training of the text conversion model to be trained is completed according to the first operation result information and the second operation result information.

4. The method according to claim 1, characterized in that: The step of inputting the sorted plurality of text units, the associated information and the task tags into the text conversion model comprises: Determining a plurality of instruction types included in the text unit according to the task tag; the instruction type is used to determine the operation performed when the machine learning model runs the text unit; Determining an instruction type to be optimized from the plurality of instruction types; the instruction type to be optimized is an instruction type having a priority lower than a preset priority; The plurality of text units are optimized according to the association information and the instruction type to be optimized.

5. The method according to claim 1, characterized in that The code format of the text unit is the code format corresponding to Python; The text conversion model is used to convert the code format of the text unit into a target code format, including: Obtaining a weight parameter of the text unit and input position information of the weight parameter input into the machine learning model; The text conversion model converts the format of the weight parameter of the text unit into the target code format, and outputs the target weight parameter and the input position information corresponding to the target weight parameter.

6. The method according to claim 5, characterized in that The weight parameters include a weight matrix, and after the optimization of the target text unit is completed so that the machine learning model can run the target text unit, further includes: Inputting the target text unit into the machine learning model; The machine learning model obtains values ​​corresponding to multiple third operation result information by multiplying the column matrix of the text input matrix corresponding to the target text unit with the row matrix of the weight matrix.

7. A text optimization operation method and device based on machine learning, characterized in that: Applied to an FPGA chip, the FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter and a configurator; the device includes: A word segmentation module, used for inputting text data corresponding to the code to be run in the machine learning model into the word segmenter, the word segmenter is used for splitting the text data into multiple text units, and then adding task tags to the text units; the task tags include a start tag, an end tag and a task description tag; An input module, used for inputting the text unit and the task mark corresponding to the text unit into the configurator, and the configurator obtains the association information between the text unit and the task mark and the sorting information of the text units according to the multiple text units and the corresponding task marks; A conversion module, used for sorting the plurality of text units according to the sorting information, inputting the sorted plurality of text units and the task tag into the text conversion model, the text conversion model is used for converting the code format of the text unit into a target code format, and outputting the converted target text unit; the target code format is a code format corresponding to the assembly language; An acquisition module, used for acquiring the loop text information and conditional text information in the target text unit; An optimization module, used to optimize the loop text information and the conditional text information, and complete the optimization of the target text unit so that the machine learning model can run the target text unit; The configurator includes an input encoder, a task description encoder, a decoder and an output generation layer; the configurator in the input module obtains the association information between the text units and the task tags and the sorting information of the text units according to the multiple text units and the corresponding task tags, for: The text unit is input into the input encoder to obtain text encoding information; the task tag is input into the task description encoder to obtain task encoding information; the text encoding information and the task encoding information are input into the decoder, and the decoder obtains the association information between the text encoding information and the corresponding task encoding information based on a self-attention mechanism, and also performs matching based on multiple text encoding information to obtain context information of multiple text encoding information, and generates the sorting information based on the context information, so as to output the association information and the sorting information through the output generation layer.

8. An FPGA chip, characterized in that: The FPGA chip is equipped with a machine learning model, a text conversion model, a word segmenter and a configurator; The FPGA chip further includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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