A storage system and method of operation thereof

Abstract

Embodiments of the present disclosure provide a storage system and an operating method thereof. The storage system includes a storage device including a plurality of storage units, and a memory controller coupled to the storage device and configured to: perform a statistic of a wear value in a preset size unit; determine whether a wear value of a subset of storage units having the preset size in the storage device satisfies a preset wear condition; and in response to the wear value satisfying the preset wear condition, adjust a read voltage for a read operation on the storage device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a storage system and an operating method thereof. BACKGROUND

[0002] The stability of amorphous phase in a phase-change memory (PCM) device can be affected by temperature-activated crystallization and resistance drift due to structural relaxation. As a result, threshold voltage drift can occur, thereby affecting the lifetime and reliability of the PCM device. SUMMARY

[0003] Embodiments of the present disclosure provide a storage system and an operating method thereof.

[0004] In a first aspect, embodiments of the present disclosure provide a storage system, comprising: a storage device, the storage device comprising a plurality of storage units; and a memory controller coupled to the storage device and configured to: perform a statistic of wear values in a preset size unit; determine whether a wear value of a subset of storage units with the preset size in the storage device satisfies a preset wear condition; and in response to the wear value satisfying the preset wear condition, adjust a read voltage for a read operation on the storage device.

[0005] In an optional implementation, the preset wear condition is that the wear value of the subset of storage units with the preset size in the storage device exceeds a preset wear threshold.

[0006] In an optional implementation, the memory controller is configured to: in response to the wear value satisfying the preset wear condition, decrease the read voltage for the read operation on the storage device; and the preset wear threshold is negatively correlated with the read voltage.

[0007] In an optional implementation, the memory controller is configured to: in response to the wear value satisfying the preset wear condition, adjust the preset size.

[0008] In an optional implementation, the memory controller is configured to: in response to the wear value satisfying the preset wear condition, increase the preset size; and the preset wear threshold is positively correlated with the preset size.

[0009] In an optional implementation, the memory controller is configured to determine the wear value based on a wear parameter; and the wear parameter comprises at least one of: an erase count, a write count, and a read count.

[0010] In an alternative embodiment, the memory device comprises a phase change memory (PCM) device, and each of the plurality of memory cells comprises a PCM cell.

[0011] In a second aspect, the embodiments of the present disclosure provide a memory system, comprising: a memory device comprising a plurality of memory cells; and a memory controller coupled to the memory device and configured to: count wear values in a preset size unit; determine whether a wear value of a subset of memory cells with the preset size in the memory device satisfies a preset wear condition; and adjust the preset size in response to the wear value satisfying the preset wear condition.

[0012] In a third aspect, the embodiments of the present disclosure provide a method for operating a memory system, the memory system comprising a memory device comprising a plurality of memory cells, the method comprising: counting wear values in a preset size unit; determining whether a wear value of a subset of memory cells with the preset size in the memory device satisfies a preset wear condition; and adjusting a read voltage for a read operation on the memory device in response to the wear value satisfying the preset wear condition.

[0013] In an alternative embodiment, the method further comprises: adjusting the preset size in response to the wear value satisfying the preset wear condition.

[0014] The embodiments of the present disclosure provide a memory system and a method for operating the same. The memory system comprises: a memory device comprising a plurality of memory cells; and a memory controller coupled to the memory device and configured to: count wear values in a preset size unit; determine whether a wear value of a subset of memory cells with the preset size in the memory device satisfies a preset wear condition; and adjust a read voltage for a read operation on the memory device in response to the wear value satisfying the preset wear condition. In the scheme provided by the present disclosure, the corresponding read voltage is determined according to the wear value counted in the preset size unit, which can effectively improve the adjustment accuracy of the read voltage and ensure the performance of the system. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1A A schematic diagram of read voltage offset due to threshold voltage offset is shown according to some aspects of the present disclosure;

[0016] Figure 1A A graph of the logarithmic relationship between the threshold voltage of the reset state and the cycling number;

[0017] Figure 2FIG. 1 shows a block diagram of an exemplary storage system 200 having a memory device according to some aspects of the present disclosure;

[0018] Figure 3 FIG. 4 shows an example diagram of wear parameters, read voltage, and preset size according to some aspects of the present disclosure;

[0019] Figure 4 FIG. 5 shows a flow diagram of an operating method of a storage system according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0021] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0022] In the drawings, the size and relative sizes of layers, regions, elements, and the like can be exaggerated for clarity. Identical reference numerals are used throughout the drawings to represent identical elements.

[0023] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0024] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description with reference to the drawings. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can have other implementations.

[0027] As technology advances, such as in cloud storage and autonomous navigation, higher demands are placed on the performance and density of memory devices due to the increasing demand for data size. For this reason, new types of storage devices, such as memory devices having phase change memory (PCM) cells, have been introduced to replace dynamic random access memory (DRAM) and NAND memory. PCM cells are non-volatile memory devices that store data using a phase change material. PCMs can exploit the difference in resistivity between amorphous and crystalline phases of a phase change material (e.g., a chalcogenide alloy) based on heating and quenching the phase change material in an electro-thermal manner. The phase change material in a PCM cell can be located between two electrodes and can be subjected to an electric current to repeatedly switch the material (or at least a portion of its blocking current path) between two phases to store data. The “set” state is a low resistance state of the PCM cell that can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration of time. Conversely, the “reset” state is a high resistance state of the PCM cell that can be obtained by creating amorphous regions in the chalcogenide material. The amorphous state can be created when the chalcogenide material is heated above its melting temperature and subsequently quenched to form an amorphous state. The “set” state can be referred to as the “on” state, while the “reset” state can be referred to as the “off’ state. Wherein the “set” state = 1 and the “reset” state = 0.

[0028] Figure 1A A schematic diagram of read voltage shift due to threshold voltage shift is shown in accordance with some aspects of the present disclosure. Figure 1A A set threshold voltage shift and a reset threshold voltage shift are shown in the middle, the set threshold voltage shift being the shift between set Vth1 to set Vth2, and the reset threshold voltage shift being the shift between reset Vth1 to reset Vth2. The shift between reset Vth2 to reset Vth1 can also be referred to as E3 loss (or E3 loss). The threshold voltage shift can be caused by temperature variation, increased read / write operation cycles, longer latency, and other factors. For example, as the read / write operation cycles increase, the set threshold voltage and the reset threshold voltage decrease. Thus, at the later state of the device after multiple repeated writes and erases (i.e., the EOL state), set Vth2 shifts to the left compared to set Vth1, and reset Vth2 shifts to the left compared to reset Vth1. As Figure 1AAs shown, the read voltage can depend on the threshold voltage associated with the SET state and the RESET state. Since the set threshold voltage and the reset threshold voltage shift, the read voltage also needs to change in order to accurately distinguish the SET state from the RESET state. The read voltage Vread-BOL used at the initial state of the device (i.e., the BOL state) and the read voltage Vread-EOL used at the EOL state are different.

[0029] Figure 1B A graph showing the threshold voltage of the RESET state versus the log of the cycling number is shown. As shown, as the cycling number (or the number of read / write cycles) increases and reaches a certain number, the threshold voltage associated with the RESET state changes accordingly. Given that Figure 1B and Figure 1A and 1B For various reasons, the threshold voltage of the PCM device can shift. Therefore, in response to the threshold voltage shift, the read voltage (Vread) can need to be modified in order to distinguish the SET state from the RESET state at the read time point after the write operation on the PCM device. One read / write cycle includes one write operation and one read operation on the memory device.

[0030] To address the above concerns and other concerns, the present disclosure provides the following technical solutions. A storage system according to some embodiments of the present disclosure can include a memory controller configured to count wear values in a preset size unit; determine whether the wear values of a subset of storage units with the preset size in the memory device satisfy a preset wear condition; and adjust a read voltage for a read operation on the memory device in response to the wear values satisfying the preset wear condition. A smaller preset size is used to count the wear values at the BOL state to improve the accuracy of wear leveling and to reduce the Read-Write-Modify (RWM) wear as much as possible. Further, the corresponding read voltage is determined according to the wear values. Therefore, the scheme provided by the present disclosure can effectively improve the adjustment accuracy of the read voltage to ensure the performance of the system.

[0031] Figure 2A block diagram illustrating an exemplary storage system 200 having a memory device according to some aspects of the present disclosure is shown. The storage system 200 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having storage therein. As Figure 2 shown, the storage system 200 can include a host 202, a memory controller 204, and a storage 201 including one or more memory devices. In some embodiments, the storage 401 can include a DRAM 206, a PCM device 208, and other suitable memory devices controlled by the memory controller 204.

[0032] As Figure 2 shown, the host 202 can be configured to generate instructions and send them to the memory controller 204. Based on the instructions or by its initiative, the memory controller 204 can generate command signals to control the storage 201. Although it is not shown in Figure 2 , in some embodiments, the host 202 can be directly connected with the storage 201 and can access the storage 201 by-passing the memory controller 204. The present disclosure is not limited thereto.

[0033] The host 202 can be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). In some implementations, the host 202 can be configured to send or receive data regarding the storage 201. In some implementations, the host 202 can include user logic or a user interface so that a user can give instructions to the host 202 and send instructions to the storage 201.

[0034] The one or more memory devices can include a PCM device 208, a DRAM 206, and other suitable memory devices, such as a NAND flash memory device. Each of the one or more memory devices can include a clock input, a command bus, a data bus, control logic, an address register, a row decoder / word line driver, a memory cell array having memory cells, a voltage generator, a page buffer / sense amplifier, a column decoder / bit line driver, data input / output (I / O). In some embodiments, one physical address can be configured to point to and provide access to one or more memory cells.

[0035] The memory controller 204 can be electrically connected or coupled with the memory device 201 and the host 202, and can be configured to control the memory device 201. The memory controller 204 can manage data stored in the memory device 201 and communicate with the host 202. In some embodiments, the memory controller 204 can be designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 204 can be designed for operation in a high duty cycle environment, such as a solid-state drive (SSD) or an embedded multi-media-card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablet computers, laptop computers, etc.) and enterprise storage arrays. The memory controller 204 can be configured to control the operation of one or more memory devices, such as read operations, erase operations, and write operations. The memory controller 204 can also be configured to manage various functions related to data stored or to be stored in the memory device 201, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 204 is also configured to process error correction codes (ECC) related to data read from or written to one or more memory devices. The memory controller 204 can also perform any other suitable functions, such as formatting one or more memory devices.

[0036] The memory controller 204 can communicate with external devices (e.g., the host 202) according to a particular communication protocol. For example, the memory controller 204 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0037] In addition, the memory controller 204 can also be configured to control the operation of one or more memory devices to perform a method according to some embodiments of the present disclosure. For example, in some embodiments, the memory controller 204 can perform statistics of wear values in units of preset sizes. In some embodiments, the memory controller 204 can determine whether a wear value of a subset of memory cells having the preset size in the memory device satisfies a preset wear condition. In some embodiments, the memory controller 204 can adjust a read voltage for a read operation on the memory device in response to the wear value satisfying the preset wear condition. In some embodiments, the memory controller 204 can adjust the preset size in response to the wear value satisfying the preset wear condition.

[0038] As an example, Figure 2 It is specifically shown that the DRAM 206 and the PCM device 208 can communicate with the memory controller 204 in a parallel manner. However, in some embodiments, the DRAM 206 and the PCM device 208 can communicate with each other and have internal data transmission within the storage apparatus 201.

[0039] In some embodiments, a wear leveling algorithm can be implemented on the storage system 200. The purpose of the wear leveling algorithm is to make the distribution of programming locations uniform, thereby increasing the lifetime of the storage apparatus 201.

[0040] In some embodiments, the wear leveling algorithm can be stored in the storage apparatus 201 and extracted by the memory controller 204 to perform wear leveling processing, as Figure 2The wear leveling mechanism can be configured to provide wear parameters associated with the PCM device 208, the wear parameters including at least one of: erase count, write count, read count. The wear parameters can be utilized by the disclosure to determine a wear value. It can be appreciated that, Figure 2 Only examples are given, and in other embodiments, the wear leveling process can be stored and executed by other devices internal or external to the storage system 200.

[0041] In some embodiments, the preset wear condition is that a wear value of a subset of storage units of the preset size in the storage device exceeds a preset wear threshold. In embodiments of the disclosure, the preset wear threshold is related to the preset size, and the preset wear threshold can be of the order of magnitude of about 10 5 to about 10 8 .

[0042] In some embodiments, the address space of the storage device is grouped, and each group has a preset size, the preset size including 32B, 128B, 256B, 1kB, 4kB, 32kB, 1MB, 16MB, etc. When implementing wear leveling, it is usually necessary to record the wear of each group in the storage device, and to track the wear value of the group in real time, and to determine the wear of the group according to the wear value. Each group can also be referred to as a subset of storage units of a preset size. The smaller the preset size, the higher the accuracy of the wear condition that the wear value can reflect, but the power consumption of the system will be greater, thereby greatly affecting the performance of the system; and the larger the preset size, the lower the accuracy of the wear condition that the wear value can reflect, but the power consumption of the system will be smaller, thereby ensuring the performance of the system.

[0043] In some embodiments, the storage controller is configured to: in response to the wear value satisfying the preset wear condition, reduce a read voltage for a read operation on the storage device; and the preset wear threshold is negatively correlated with the read voltage. The read voltage Vread is configured to be reduced in a decreasing manner to reach an adjusted read voltage Vread_n, where the adjusted read voltage Vread_n has a voltage offset ΔV compared to a previous read voltage Vread_n-1. Here, n can represent the number of times of adjusting the read voltage. In a specific example, the voltage offset ΔV can be related to E3 loss, and specifically, the voltage offset ΔV can be set to a value between -25mV and -200mV, for example, -50mV.

[0044] In some embodiments, the voltage offset ΔV can be a fixed value. In other embodiments, the voltage offset ΔV can also be a non-fixed value, for example, the absolute value of the voltage offset ΔV can increase with the increase of the preset size.

[0045] In some embodiments, the memory controller is configured to determine the wear value based on a wear parameter; the wear parameter comprises at least one of: number of erases, number of writes, number of reads. In a specific example, the wear parameter comprises the number of writes, and the number of writes is taken as the wear value. In another specific example, the wear parameter comprises the number of writes and the number of reads, and the number of read / writes cycles is taken as the wear value. In yet another specific example, the wear parameter comprises the number of erases and the number of writes, and the number of erase / writes cycles is taken as the wear value. One erase / write cycle comprises one write operation and one erase operation of the memory device.

[0046] Figure 3 An example diagram of wear parameter, read voltage and preset size is shown according to some aspects of the present disclosure. It is noted that, Figure 3 Take the number of writes as an example of the wear parameter. As shown in Figure 3 The read voltage decreases as the wear parameter increases. For example, when the wear parameter is in the interval of [0, 20K], the read voltage can be Vread_1; when the wear parameter is in the interval of [0.2K, 4K], the read voltage can be Vread_2; and when the wear parameter is in the interval of [2K, 10K], the read voltage can be Vread_3. Here, Vread_3 has a voltage offset ΔV compared to Vread_2, and Vread_2 has a voltage offset ΔV compared to Vread_1. The voltage offset ΔV can be a fixed value of -50mV. In some embodiments, Vread_1 can be the default read voltage (Default Vread).

[0047] In some embodiments, the larger the preset size, the larger the corresponding wear parameter. As shown in Figure 3 When the preset size is 128B, the wear parameter can be set to [0, 20K]; when the preset size is 256B, the wear parameter can be set to [0.2K, 4K]; and when the preset size is 1kB, the wear parameter can be set to [2K, 10K]. In some embodiments, the maximum value of the wear parameter can be taken as the preset wear threshold. Here, the wear parameter of the memory device can be used to represent the endurance of the memory device.

[0048] In some embodiments, the smaller the read voltage, the larger the corresponding preset wear threshold. In other words, as the read voltage is reduced, the preset wear threshold becomes larger.

[0049] In a specific example, wear values ​​are statistically analyzed in units of 128 bytes; it is determined whether the wear value of a subset of 128-byte memory cells in the storage device exceeds 20,000; in response to the wear value exceeding 20,000, Vread_1 is adjusted to Vread_2. In this embodiment of the disclosure, in response to the wear value of a subset of memory cells with a preset size exceeding a preset wear threshold, the read voltage of the storage device is adjusted, which can effectively reduce read errors caused by threshold voltage deviation.

[0050] In some embodiments, when the voltage offset ΔV is a fixed value, the adjustment of the read voltage can specifically be achieved by adding a voltage offset ΔV to the previous read voltage Vread_n-1 to obtain the adjusted read voltage Vread_n. Specifically, the voltage offset ΔV can be -50mV.

[0051] In some embodiments, the larger the preset size, the smaller the corresponding read voltage. For example... Figure 3 As shown, when the preset size is 128B, the read voltage can be Vread_1; when the preset size is 256B, the read voltage can be Vread_2; and when the preset size is 1kB, the read voltage can be Vread_3. Here, Vread_3 has a voltage offset ΔV relative to Vread_2, and Vread_2 has a voltage offset ΔV relative to Vread_1. The voltage offset ΔV can be a fixed value of -50mV. In some embodiments, Vread_1 can be the default read voltage (Default Vread).

[0052] In some embodiments, the preset size is negatively correlated with the read voltage; specifically, the preset size increases as the read voltage decreases. In a specific example, when reading the memory device with Vread_1, the wear value is calculated in units of 128 bytes; when reading the memory device with Vread_2, the wear value is calculated in units of 256 bytes; and when reading the memory device with Vread_3, the wear value is calculated in units of 1 kB.

[0053] In some embodiments, the memory controller is configured to: adjust the preset size in response to the wear value meeting the preset wear condition. In response to the wear value meeting the preset wear condition, the read voltage of the memory device is adjusted, and the preset size is also adjusted, so that subsequent wear value statistics are performed using the adjusted preset size as the unit.

[0054] In some embodiments, the memory controller is configured to increase the preset size in response to the wear value satisfying the preset wear condition, the preset wear threshold being positively correlated with the preset size. In response to the wear value satisfying the preset wear condition, the read voltage for read operations on the memory device is decreased and the preset size is increased, so that subsequent statistics of wear values are performed in units of the increased preset size. In some embodiments, the preset wear threshold is greater as the preset size is increased.

[0055] In a specific example, in response to the wear value of the subset of storage units of 128B size in the memory device exceeding 20,000, the preset size is adjusted from 128B to 256B; in response to the wear value of the subset of storage units of 256B size in the memory device exceeding 40,000, the preset size is adjusted from 256B to 1kB.

[0056] In a specific example, when the preset size is 128B, the preset wear threshold can be 20,000; when the preset size is 256B, the preset wear threshold can be 40,000; and when the preset size is 1kB, the preset wear threshold can be 100,000.

[0057] Figure 4 A flowchart illustrating a method of operating a storage system according to some aspects of the present disclosure is shown, in some embodiments, the memory device can be any appropriate memory device disclosed herein. The method of operation can be partially or entirely implemented by the memory controller 204 as Figure 2 shown in FIG. 2. It should be understood that the operations shown in the method of operation are not exhaustive and that other operations can be performed before, after, or between any of the operations shown. Furthermore, some operations can be performed concurrently, or in a different order than shown. Figure 4

[0058] As shown in FIG. 4, at step 402, a read operation is performed on the memory device using a read voltage. The read voltage here can be Vread l, which can be a default read voltage (Default Vread). Figure 4

[0059] At step 404, statistics of wear values are performed in units of a preset size. In some embodiments, the preset size can be negatively correlated with the read voltage. In a specific example, when the read voltage is Vread l, the preset size is 128B.

[0060] At step 406, it is determined whether a wear value of a subset of storage units of the preset size in the memory device satisfies a preset wear condition.

[0061] ​​In some embodiments, step 406 comprises determining that the wear-out value of the subset of memory cells with the preset size in the memory device exceeds a preset wear-out threshold; the preset wear-out threshold is related to the preset size. In a specific example, when the preset size is 128B, the preset wear-out threshold is 20,000.

[0062] In some embodiments, step 406 further comprises determining that the wear-out value of the subset of memory cells with the preset size in the memory device does not exceed a preset wear-out threshold; then step 402 is continued to be performed with Vread_1 as the read voltage.

[0063] At step 408, in response to the wear-out value satisfying the preset wear-out condition, a read voltage for performing a read operation on the memory device is adjusted.

[0064] In some embodiments, step 408 comprises decreasing the read voltage for performing a read operation on the memory device in response to the wear-out value of the subset of memory cells with the preset size in the memory device exceeding a preset wear-out threshold. Step 402 is continued to be performed with the adjusted (decreased) read voltage. In a specific example, in response to the wear-out value of the subset of memory cells with the preset size in the memory device exceeding 20,000, the read voltage Vread_1 is decreased to Vread_2. Vread_2 has a voltage offset ΔV compared to Vread_1, and the voltage offset ΔV can be a fixed value of -50mV. Subsequently, the read operation on the memory device is performed with Vread_2.

[0065] In some embodiments, the method further comprises increasing the preset size in response to the wear-out value of the subset of memory cells with the preset size in the memory device exceeding a preset wear-out threshold, and step 404 is continued to be performed with the adjusted (increased) preset size. In a specific example, in response to the wear-out value of the subset of memory cells with the preset size in the memory device exceeding 20,000, the preset size is increased from 128B to 256B. Subsequently, the wear-out value is counted in units of 256B.

[0066] In the embodiments of the present disclosure, the read voltage of the memory device is adjusted in response to the wear-out value of the subset of memory cells with the preset size exceeding the preset wear-out threshold, which can effectively reduce read errors caused by threshold voltage offset.

[0067] In the embodiments of the present disclosure, in response to the wear value of the subset of storage units with the preset size exceeding the preset wear threshold, the preset size is adjusted, and the wear value is subsequently counted in units of the adjusted preset size, so that the statistical granularity adopted by the storage device at different life periods is different to adapt to the system power consumption and performance requirements at different life periods of the storage device. In particular, the statistical granularity is adjusted to reduce the power consumption of the system in the later period of the life of the storage device, thereby ensuring the performance of the system.

[0068] According to an aspect of the present disclosure, an operating method of a storage system is provided, the storage system comprising a storage device, the storage device comprising a plurality of storage units, the method comprising:

[0069] counting the wear value in units of a preset size;

[0070] determining whether the wear value of a subset of storage units with the preset size in the storage device meets a preset wear condition;

[0071] in response to the wear value meeting the preset wear condition, adjusting a read voltage for a read operation on the storage device.

[0072] In some embodiments, the method further comprises:

[0073] in response to the wear value meeting the preset wear condition, adjusting the preset size.

[0074] In some embodiments, the preset wear condition is that the wear value of the subset of storage units with the preset size in the storage device exceeds a preset wear threshold.

[0075] In some embodiments, in response to the wear value meeting the preset wear condition, adjusting the read voltage for the read operation on the storage device comprises:

[0076] in response to the wear value meeting the preset wear condition, reducing the read voltage for the read operation on the storage device; the preset wear threshold is negatively correlated with the read voltage.

[0077] In some embodiments, in response to the wear value meeting the preset wear condition, adjusting the preset size comprises:

[0078] in response to the wear value meeting the preset wear condition, increasing the preset size; the preset wear threshold is positively correlated with the preset size.

[0079] In some embodiments, the method further comprises determining the wear value based on a wear parameter; the wear parameter comprises at least one of the following: number of erasures, number of writes, number of reads.

[0080] In some embodiments, the memory device comprises a phase change memory (PCM) device, each of the plurality of memory cells comprises a PCM cell.

[0081] It should be noted that the above description of the operation method embodiments of the storage system is similar to the description of the above storage system embodiments, and has similar beneficial effects as the storage system embodiments. For technical details not disclosed in the operation method embodiments of the storage system of the present disclosure, please refer to the description of the storage system embodiments of the present disclosure for understanding.

[0082] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the execution order, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0083] The above description is only the preferred embodiments of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made according to the disclosure content of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A storage system, characterized by, The storage system comprises a memory device comprising a plurality of memory cells, and a memory controller coupled to the memory device and configured to: statistically count a wear value in a preset size unit; the memory device is divided into a plurality of groups of memory cell subsets, and the preset size is a capacity of an address space of the memory cell subset; determine whether the wear value of the memory cell subset with the preset size in the memory device exceeds a preset wear threshold value; in response to the wear value exceeding the preset wear threshold value, adjust the preset size and adjust a read voltage for a read operation on the memory device; the preset wear threshold value is positively correlated with the preset size, and the preset wear threshold value is negatively correlated with the read voltage. The memory controller is configured to: in response to the wear value exceeding the preset wear threshold value, decrease the read voltage for the read operation on the memory device. The memory controller is configured to:

2. The storage system of claim 1, wherein, in response to the wear value exceeding the preset wear threshold value, increase the preset size. The memory controller is configured to:

3. The storage system of claim 1, wherein, determine the wear value based on a wear parameter; the wear parameter comprises at least one of the following: number of erasures, number of writes, number of reads.

5. The storage system of claim 1, wherein:

4. The storage system of claim 1, wherein, the memory device comprises a phase change memory (PCM) device, and each of the plurality of memory cells comprises a PCM cell. The storage system comprises a memory device comprising a plurality of memory cells, and a memory controller coupled to the memory device and configured to: statistically count a wear value in a preset size unit; the memory device is divided into a plurality of groups of memory cell subsets, and the preset size is a capacity of an address space of the memory cell subset; determine whether the wear value of the memory cell subset with the preset size in the memory device exceeds a preset wear threshold value; 6. A storage system, characterized by in response to the wear value exceeding the preset wear threshold value, adjust the preset size; the preset wear threshold value is positively correlated with the preset size. The storage system comprises a memory device comprising a plurality of memory cells, and the method comprises: statistically count a wear value in a preset size unit; the memory device is divided into a plurality of groups of memory cell subsets, and the preset size is a capacity of an address space of the memory cell subset; determine whether the wear value of the memory cell subset with the preset size in the memory device exceeds a preset wear threshold value; in response to the wear value exceeding the preset wear threshold value, adjust the preset size; the preset wear threshold value is positively correlated with the preset size. The method further comprises: in response to the wear value exceeding the preset wear threshold value, adjust a read voltage for a read operation on the memory device; the preset wear threshold value is negatively correlated with the read voltage.

7. An operating method of a storage system characterized by, ​ ​ ​ ​ 8. The method of claim 7, wherein, ​ ​

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