Memory system and operating method thereof

Abstract

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0153351, filed on November 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory system and a method of operating the same. Background Technology

[0004] Memory systems include data storage devices that store data based on requests from a host such as a computer, server, smartphone, tablet PC, or other electronic device. Examples of memory systems range from conventional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory devices (UFS), or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory devices. The memory controller can receive commands from a host and, based on the received commands, can execute those commands or control read / write / erase operations on the memory devices in the memory system. The memory controller can be used to run firmware operations for performing logical operations to control these operations.

[0006] When a memory system writes data to a memory device, it can write a parity check corresponding to the data to be written to the memory device along with the data to verify that the written data is error-free. Summary of the Invention

[0007] Embodiments of this disclosure may provide a memory system and a method of operation thereof capable of preventing performance degradation when writing data and parity associated with the data to a memory device due to the simultaneous writing of unnecessary virtual data, the memory system including a memory device.

[0008] On one hand, embodiments of this disclosure may provide a memory system including a memory device having a plurality of memory blocks and a memory controller for communicating with and controlling the memory device.

[0009] In one embodiment, the memory controller may be configured to: upon receiving a clear command from the host instructing the memory device to clear data cached in a data cache to the memory device, clear first data to the memory device, the data cache being configured to cache data to be written to the memory device, the first data being cached in the data cache and the size of the first data being smaller than the size of a reference write unit, the reference write unit being a reference for writing data to the memory device together with parity.

[0010] The memory controller can write the first parity associated with the first data into a parity storage block among multiple storage blocks, the parity storage block storing parity data smaller than the size of the reference write unit.

[0011] The memory controller can update the value of the parity location pointer to the location where the first parity was written. The parity location pointer indicates the location of the most recently written parity among a plurality of parities associated with data smaller than the size of the reference write unit.

[0012] The memory controller can set a parity write flag, which indicates whether the parity check indicated or pointed to by the parity position pointer is valid.

[0013] On the other hand, embodiments of this disclosure may provide a method of operating a memory system, the memory system including a memory device having a plurality of memory blocks.

[0014] Methods of operating a memory system may include: receiving a clear command from a host, the clear command instructing the memory device to clear data cached in a data cache to the memory device, the data cache being used to cache data to be written to the memory device.

[0015] A method of operating a memory system may include: clearing first data to a memory device, the first data being cached in a data cache and the size of the first data being smaller than the size of a reference write unit, the reference write unit being a reference for writing data together with parity to the memory device.

[0016] The method of operating the memory system may further include: writing a first parity associated with the first data into a parity storage block among a plurality of storage blocks, the parity storage block being configured to store parity data smaller than the size of a reference write unit.

[0017] The method of operating the memory system may further include updating the value of a parity location pointer to the location where a first parity was written, the parity location pointer indicating the location of the most recently written parity among a plurality of parities associated with data smaller than a reference write unit.

[0018] The method of operating the memory system may further include setting a parity write flag that indicates whether the parity check indicated by the parity position pointer is valid.

[0019] On the other hand, embodiments of this disclosure may provide a memory system including a memory device having a plurality of memory blocks and a memory controller for communicating with and controlling the memory device.

[0020] The memory controller can write the first data to the location of the memory device.

[0021] The memory controller can write the second data from the location where the first data has already been written.

[0022] The memory controller can calculate the first parity check associated with the first data.

[0023] The memory controller can determine the value of the parity location pointer, which indicates the location where the first parity check has been written.

[0024] The memory controller can set a parity write flag.

[0025] Embodiments of this disclosure provide memory systems and methods that can effectively prevent performance degradation caused by writing unnecessary virtual data along with data and data parity checks when writing data to a memory device. Attached Figure Description

[0026] Figure 1 This is a schematic diagram illustrating the configuration of a memory system according to an embodiment of the disclosed technology.

[0027] Figure 2 This is a block diagram schematically illustrating a memory device according to an embodiment of the disclosed technology.

[0028] Figure 3 This is a diagram illustrating the structure of word lines and bit lines of a memory device according to an embodiment of the disclosed technology.

[0029] Figure 4 This is a diagram illustrating the operation of a memory system processing a clear command received from a host according to an embodiment of the present disclosure.

[0030] Figure 5This is a diagram illustrating an example of the operation of a memory system writing data and parity to a memory device according to an embodiment of the present disclosure.

[0031] Figure 6 This is a diagram illustrating another example of the operation of a memory system writing data and parity to a memory device according to an embodiment of the present disclosure.

[0032] Figure 7 This is a diagram illustrating an example of the operation of a memory system writing first data and a first parity check to a memory device according to an embodiment of the present disclosure.

[0033] Figure 8 This is a diagram illustrating an example of a parity position pointer and a parity write flag according to an embodiment of the present disclosure.

[0034] Figure 9 This is a diagram illustrating an example of an operation in which a memory system writes second data after the first data has been written, according to an embodiment of the present disclosure.

[0035] Figure 10 This is a diagram illustrating an example of an operation that writes a parity check associated with the sum of first data and second data according to an embodiment of the present disclosure.

[0036] Figure 11 This is a diagram illustrating an example of an operation that writes a parity check associated with the sum of first data and second data according to an embodiment of the present disclosure.

[0037] Figure 12 This is a diagram illustrating another example of the operation of writing a parity check associated with the sum of the first data and the second data according to an embodiment of the present disclosure.

[0038] Figure 13 This is a flowchart illustrating an example of operations performed by the memory system during a power-on reset according to an embodiment of the present disclosure.

[0039] Figure 14 This is a diagram illustrating a method of operating a memory system according to an embodiment of the present disclosure.

[0040] Figure 15 This is a diagram illustrating the configuration of a computing system based on some embodiments of the disclosed technology. Detailed Implementation

[0041] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily limited to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. The term "various embodiments" as used herein does not necessarily refer to all embodiments.

[0042] Figure 1 This is a schematic diagram illustrating the configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0043] In some embodiments, memory system 100 may include memory device 110 configured to store data and memory controller 120 configured to control memory device 110.

[0044] Memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. Operation of memory device 110 may include, for example, read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0045] The memory cells in memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in a memory cell can be erased at the block level.

[0046] In some implementations, the memory device 110 can be implemented as various types, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM).

[0047] The memory device 110 can be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology can be applied to any type of flash memory device with a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, which may be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device may be referred to as charge-fetch flash (CTF).

[0048] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 to access a region of the memory cell array selected using that address. In other words, the memory device 110 can perform operations corresponding to the received commands on a memory region within the memory device that has a physical address corresponding to the address received from the memory controller 120.

[0049] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an address-selected region. During a reading operation, the memory device 110 can read data from an address-selected memory region. During an erasing operation, the memory device 110 can erase data stored in an address-selected memory region.

[0050] The memory controller 120 can control write operations (programming operations), read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0051] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs background operations on the memory device, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0052] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, by way of non-limiting example, the memory controller 120 and the host will be discussed as separate devices.

[0053] Reference Figure 1 The memory controller 120 may include a memory interface 122, a control circuit 123, and a host interface 121.

[0054] Host interface 121 can be configured to provide an interface for communicating with a host.

[0055] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and can perform an operation in response to the received command.

[0056] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120 so that the memory controller 120 can perform memory operations in the memory device 110 based on control signals and instructions from the control circuit 123.

[0057] The control circuit 123 can be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126 configured to detect and correct one or more errors, etc.

[0058] Processor 124 can control all operations of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0059] Processor 124 can be configured to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations in memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and translate them into PBAs using a mapping table.

[0060] Based on the mapping unit, there are various address mapping methods that can be adopted by the FTL. Typical address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0061] Processor 124 can be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, processor 124 can randomize data received from the host using a randomization seed. The randomized data is provided to memory device 110 and written into the memory cell array.

[0062] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 using a derandomization seed. The derandomized data can then be output to the host.

[0063] The processor 124 can run firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 can control all operations of the memory controller 120, and in order to perform logical operations, it can run (drive) the firmware loaded into the working memory 125 during startup.

[0064] The term "firmware" refers to a program or software stored in a non-volatile memory and executed by a processor 124 inside the memory system 100.

[0065] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to translate a logical address in a host request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret commands issued by the host to a data storage device such as the memory system 100 and pass the commands to the FTL, and the flash interface layer (FIL) is configured to pass commands issued by the FTL to the memory device 110.

[0066] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0067] The working memory 125 may store firmware, program code, commands, or multiple data entries necessary for operating the memory controller 120. The working memory 125 may include at least one of, for example, static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memory.

[0068] Error detection / correction circuit 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the data for error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0069] Error detection / correction circuit 126 can be implemented to decode data using error correction codes. Error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0070] In some implementations, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each read data entry can include multiple sectors. In this disclosure, a sector can refer to a data unit smaller than a read unit of flash memory (e.g., a page). The sectors constituting each read data entry can be mapped based on addresses.

[0071] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) sector by sector and determine whether the number of erroneous bits in the data is within error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is less than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or can mark the corresponding sector as "passed".

[0072] Error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector in the read data is correctable, error detection / correction circuit 126 can proceed to the next sector to check if error correction is required for that sector. After completing error detection and correction operations on all read data in this way, error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0073] The memory system 100 may also include a bus 127 to provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 (i.e., host interface 121, memory interface 122, processor 124, working memory 125, and error detection / correction circuitry 126). Bus 127 may include, for example, a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0074] As an example, Figure 1 The aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of those elements shown in the figures may be omitted, or some of the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0075] Figure 2This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0076] In some implementations, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0077] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0078] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged.

[0079] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuitry 230 via multiple bit lines BL.

[0080] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells are non-volatile memory cells. In some embodiments, such non-volatile memory cells may be arranged in a vertical channel configuration.

[0081] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0082] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. As yet another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. As yet another example, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell.

[0083] Reference Figure 2The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuits configured to drive the memory cell array 210.

[0084] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0085] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0086] Address decoder 220 can receive addresses through input / output buffers within memory device 110. Address decoder 220 can be configured to decode block addresses from the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0087] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0088] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL inside the selected memory block, and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0089] During the programming verification operation, the address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL inside the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0090] Address decoder 220 can be configured to decode column addresses from received addresses. Address decoder 220 can then transmit the decoded column addresses to read / write circuitry 230.

[0091] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0092] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0093] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0094] The read / write circuit 230 may include multiple page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 can operate as a "read circuit", and when the memory cell array 210 performs a write operation, the read / write circuit 230 can operate as a "write circuit".

[0095] The aforementioned read / write circuit 230 is also referred to as a page buffer circuit or data register circuit. The page buffer circuit includes multiple page buffers PB. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, may further include cache buffers for data caching.

[0096] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the amount of current that varies according to the programming state of the corresponding memory cell at the sensing node, and the corresponding voltage can be stored or latched as sensing data.

[0097] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0098] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0099] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0100] Control logic 240 can be configured to control all operations of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals to adjust the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0101] Control logic 240 can control read / write circuitry 230 to perform read operations in memory cell array 210. Voltage generation circuitry 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to a voltage generation circuitry control signal output from control logic 240.

[0102] The memory block BLK disposed in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, and multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is connected to one of the word lines WL, and each of the memory cell strings STR is connected to one of the bit lines BL.

[0103] In a storage block BLK, multiple word lines (WLs) and multiple bit lines (BLs) can be arranged in rows and columns. For example, each of the multiple word lines (WLs) can be arranged along the row direction, and each of the multiple bit lines (BLs) can be arranged along the column direction. Alternatively, each of the multiple word lines (WLs) can be arranged along the column direction, and each of the multiple bit lines (BLs) can be arranged along the row direction.

[0104] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other and be electrically isolated from each other, thereby enabling addressing of individual memory cells within an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR) comprising a layer of material capable of retaining charge.

[0105] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of transistor TR may be connected directly or via another transistor TR to the source line (which may be ground). The gate of transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0106] In each of the multiple memory blocks BLK1 to BLKz, a first select line (also referred to as a source select line or drain select line) may be arranged outside the first outermost word line closer to the read / write circuit 230 among the two outermost word lines, and a second select line (also referred to as a drain select line or source select line) may be arranged outside the other second outermost word line.

[0107] In some implementations, at least one additional dummy character line may be arranged between the first outermost character line and the first selection line. Additionally, at least one additional dummy character line may be arranged between the second outermost character line and the second selection line.

[0108] It can perform read and write operations on storage blocks one page at a time, and it can also perform erase operations on storage blocks one by one.

[0109] Figure 3 This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device 110 based on an embodiment of the disclosed technology.

[0110] Reference Figure 3 The memory device 110 has a core region where memory cells MC are arranged, and an auxiliary region (the remaining region other than the core region) including circuitry for performing operations on the memory cell array 210.

[0111] In the kernel region, a certain number of memory cells arranged in one direction can be called a "page" (PG), and a certain number of memory cells connected in series can be called a "memory cell string" (STR).

[0112] Word lines WL1 to WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. (Corresponding to...) Figure 2 The data register 330 of the read / write circuit 230 can exist between multiple bit lines BL and column decoder 320.

[0113] Multiple word lines WL1 to WL9 can correspond to multiple pages PG.

[0114] For example, such as Figure 3 As shown, each of the multiple word lines WL1 to WL9 can correspond to a page PG. When each of the multiple word lines WL1 to WL9 has a larger size, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and when programming and reading operations are performed, all memory cells MC within the same page PG can be operated on simultaneously.

[0115] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd-numbered bit lines BL and even-numbered bit lines BL, such that a pair of odd-numbered bit lines and even-numbered bit lines are connected together to column decoder 320.

[0116] When accessing a memory cell MC, row decoder 310 and column decoder 320 can be used to locate the desired memory cell based on its address.

[0117] In some implementations, the data register 330 plays a crucial role because all data processing performed by the memory device 110, including programming and reading operations, occurs via the data register 330. If data processing performed by the data register 330 is delayed, all other areas must wait until the data register 330 has completed its data processing, which degrades the overall performance of the memory device 110.

[0118] Reference Figure 3 In the example shown, in a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9, respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0119] The multiple word lines WL1 to WL9 include two outermost word lines, WL1 and WL9. A first select line DSL can be additionally arranged outside the first outermost word line WL1. Compared to the other outermost word line WL9, this first outermost word line WL1 is closer to the data register 330 and has a shorter signal path. A second select line SSL can be additionally arranged outside the other second outermost word line WL9.

[0120] The first selection transistor D-TR, controlled by the first selection line DSL to be turned on / off, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL to be turned on / off, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0121] The first selection transistor D-TR serves as a switching circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switching circuit to connect the corresponding memory cell string STR to the source line SL. In other words, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0122] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR to turn on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR to turn off the second selection transistor S-TR.

[0123] During a read or verify operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and to the source line SL corresponding to ground, allowing the voltage level of the bit line BL to be measured. However, during a read operation, there may be a time difference between the on / off timing of the first selection transistor D-TR and the second selection transistor S-TR.

[0124] During the erase operation, the memory system 100 can apply a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 applies a voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0125] Figure 4 This is a diagram illustrating the operation of a memory system 100, including a memory device 110 and a memory controller 120, processing a clear command FLUSH_CMD received from a host according to an embodiment of the present disclosure.

[0126] When data to be written to memory device 110 is received from the host, the memory controller 120 of memory system 100 can cache the received data in a data cache DATA_CACHE. The data cache DATA_CACHE can be located in volatile memory storing the data to be written to memory device 110. For example, the data cache DATA_CACHE can be located in the above-mentioned reference... Figure 1 The working memory 125 is described.

[0127] When certain conditions are met, the memory controller 120 of the memory system 100 can clear data cached in the data cache DATA_CACHE to the memory device 110. Clearing data from the data cache DATA_CACHE to the memory device 110 performed by the memory controller 120 can mean that the memory controller 120 writes the corresponding data to the memory device 110 and deletes the data from the data cache DATA_CACHE. In this case, the data cached in the data cache DATA_CACHE can be stored in any one of the multiple memory blocks BLK disposed in the memory device 110, or distributed and stored across one or more memory blocks.

[0128] When the memory controller 120 receives a clear command FLUSH_CMD from the host, it can clear the data cached in the data cache DATA_CACHE to the memory device 110. The clear command FLUSH_CMD can be a command that instructs that data cached in the data cache DATA_CACHE be cleared to the memory device 110 regardless of whether the conditions for clearing data cached in the data cache DATA_CACHE to the memory device 110 are met.

[0129] When receiving a clear command FLUSH_CMD from the host, the memory controller 120 can simultaneously clear the data cached in the data cache DATA_CACHE and write the parity check associated with the data written to the memory device 110. In this case, the memory controller 120 can generate the parity check corresponding to the data, for example, by performing a specific operation (e.g., an XOR operation) on each bit of the data. As another example, the memory controller 120 can generate the parity check corresponding to the data by inputting the data into a separate parity calculation circuit.

[0130] exist Figure 4 As an example, the case of writing data and the parity check associated with that data into the same memory block BLK (e.g., memory block 410) in memory device 110 has been described. However, the data and the corresponding parity check can be distributed and stored in different memory blocks BLK in memory device 110.

[0131] The following will describe in detail an example of the operation by which the memory system 100 writes data and the parity associated therewith to the memory device 110.

[0132] Figure 5 This is a diagram illustrating an example of the operation of a memory system 100 writing data and parity data into a memory device 110 according to an embodiment of the present disclosure.

[0133] Reference Figure 5 The memory controller 120 of the memory system 100 can determine whether to write data to the memory device 110 by comparing the size 510 of the data to be cached in the data cache DATA_CACHE with the size 520 of the reference write unit REF_WR_UNIT.

[0134] The reference write unit REF_WR_UNIT can be a reference used by the memory controller 120 to write data cached in the data cache DATA_CACHE, along with the parity associated with that data, to the memory device 110. For example, the reference write unit REF_WR_UNIT can be a stripe unit, which is a unit of data written at one time in a superblock of at least one of a word line WL, the memory device 110, or a superblock logically bundled with at least one of a plurality of memory blocks BLK included in the memory device 110.

[0135] When the size 510 of the data cached in the data cache DATA_CACHE is less than the size 520 of the reference write unit REF_WR_UNIT, the memory controller 120 can cache the data to be written in the data cache DATA_CACHE.

[0136] If the size 510 of the data cached in the data cache DATA_CACHE exceeds or is greater than the size 520 of the reference write unit REF_WR_UNIT, the memory controller 120 may write the data of the size of the reference write unit REF_WR_UNIT, along with the parity associated with the corresponding data, to the memory device 110. For example, the data and parity may be written to the memory device 110 sequentially or consecutively. In this case, the sequential writing of the data and parity may not mean that the data and parity are written to physically adjacent regions, but rather that the data and parity are written to logically adjacent addresses within the reference write unit REF_WR_UNIT.

[0137] Figure 6 This is a diagram illustrating another example of the operation of the memory system 100 writing data and parity to the memory device 110 according to an embodiment of the present disclosure.

[0138] Reference Figure 6 When the size 610 of the data cached in the data cache DATA_CACHE is less than the size 620 of the reference write unit REF_WR_UNIT, the memory controller 120 of the memory system 100 may continue to cache the data to be written in the data cache DATA_CACHE.

[0139] In this situation, if the size of the data cached in the data cache DATA_CACHE is smaller than the size of the reference write unit REF_WR_UNIT, the memory controller 120 may receive a clear command FLUSH_CMD from the host.

[0140] Because the FLUSH_CMD clear command has been received from the host, the memory controller 120 will clear the data cached in the DATA_CACHE to the memory device 110. However, at this time, the size of the data cached in the DATA_CACHE is smaller than the size of the reference write unit REF_WR_UNIT.

[0141] Therefore, the memory controller 120 can then write virtual data to the data cached in the data cache DATA_CACHE. In this case, the sum of the size of the data cached in the data cache DATA_CACHE and the size of the virtual data can reach the size of the reference write unit REF_WR_UNIT.

[0142] Furthermore, the memory controller 120 can calculate the parity check associated with the sum of the data cached in the data cache DATA_CACHE and the virtual data, and write the data cached in the data cache DATA_CACHE, the virtual data, and the parity check together into the memory device 110. Therefore, even when the size of the data cached in the data cache DATA_CACHE is less than the reference write unit REF_WR_UNIT, the memory controller 120 can still process the clear command FLUSH_CMD received from the host.

[0143] However, the alternative method of writing virtual data as described above may have the following problems. Because virtual data that the host has not requested to be written is written to the memory device 110, the ratio of (amount of data written to the memory device) to (amount of data requested to be written by the host) may increase. In addition, the number of free memory blocks among the multiple memory blocks (BLKs) included in the memory device 110 may decrease. Therefore, the storage capacity of the memory device 110 may decrease, and the frequency of garbage collection (GC) to obtain free memory blocks may increase, resulting in a decrease in the performance of the memory system 100.

[0144] In the following, embodiments of the present disclosure describe novel operations by which the memory system 100 can solve the aforementioned performance degradation problem.

[0145] Figure 7 This is a diagram illustrating an example of the operation of a memory system 100 writing first data DATA_1 and first parity PARITY_1 into a memory device 110 according to an embodiment of the present disclosure.

[0146] Reference Figure 7When the first data DATA_1 is cached in the data cache DATA_CACHE, the memory controller 120 of the memory system 100 may receive a clear command FLUSH_CMD from the host. In this case, the size 710 of the first data DATA_1 is smaller than the size 720 of the reference write unit REF_WR_UNIT. Alternatively, the size 710 of the first data DATA_1 can be variable.

[0147] In this scenario, the memory controller 120 can clear the first data DATA_1 to the memory device 110 without adding virtual data, and can write the first parity check PARITY_1, which is the parity check of the first data DATA_1, into the parity storage block PARITY_BLK among the multiple storage blocks BLK included in the memory device 110. The parity storage block PARITY_BLK is a parity storage block among the multiple storage blocks BLK included in the memory device 110 that stores data smaller than the size of the reference write unit REF_WR_UNIT. Furthermore, even after writing the first parity check PARITY_1 into the parity storage block PARITY_BLK, the memory controller 120 can store the first parity check PARITY_1 therein without deleting it.

[0148] Therefore, the memory controller 120 can process the clear command FLUSH_CMD received from the host without writing virtual data to the memory device 110, thereby solving the performance degradation problem caused by writing virtual data.

[0149] In this configuration, the memory controller 120 is configured to use the reference write unit REF_WR_UNIT to manage the first data DATA_1 and the first parity PARITY_1, in order to combine the first data DATA_1 to be written to the memory device 110 with the data to be written again and write it to the memory device 110.

[0150] In the following description, the parity position pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG will be used to manage information for the first data DATA_1 and the first parity PARITY_1.

[0151] Figure 8This is a diagram illustrating an example of the parity location pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG according to an embodiment of this disclosure.

[0152] Reference Figure 8 The memory controller 120 can update the value of the parity location pointer PARITY_LOC_PTR to the location where the first parity PARITY_1 is stored.

[0153] The parity position pointer PARITY_LOC_PTR is a value that indicates the position of the parity most recently written to memory device 110 among multiple parities associated with multiple corresponding data of a size smaller than the reference write unit REF_WR_UNIT.

[0154] In embodiments of this disclosure, because parity checks for data having a reference write unit (REF_WR_UNIT) size can be written along with the data, the memory system 100 may not need to separately indicate the location. However, because parity checks associated with data smaller than the reference write unit (REF_WR_UNIT) size are written to a separate parity memory block (PARITY_BLK), a pointer indicating the location where the parity check was written may be required.

[0155] Before writing the first parity PARITY_1 to the parity memory block PARITY_BLK, the memory controller 120 can check the location to be written to the first parity PARITY_1 by using the value of the existing parity position pointer PARITY_LOC_PTR. Alternatively, the memory controller 120 can write the first parity PARITY_1 immediately after or following the location indicated by the existing parity position pointer PARITY_LOC_PTR, and can update the value of the parity position pointer PARITY_LOC_PTR to the location where the first parity PARITY_1 has already been written.

[0156] In addition, the memory controller 120 can set the parity write flag PARITY_WR_FLG, which is a flag indicating whether the parity check is valid at the location indicated (pointed to or identified) by the parity position pointer PARITY_LOC_PTR.

[0157] With the parity write flag PARITY_WR_FLG set, it indicates that parity is valid at the location pointed to by the parity position pointer PARITY_LOC_PTR. Conversely, if the parity write flag PARITY_WR_FLG is reset, it indicates that parity is invalid at the location pointed to by the parity position pointer PARITY_LOC_PTR.

[0158] The memory controller 120 can set the parity write flag PARITY_WR_FLG by setting its value to a first value (e.g., 1). Alternatively, the memory controller 120 can reset the parity write flag PARITY_WR_FLG by setting its value to a second value (e.g., 0), which is different from the first value.

[0159] Meanwhile, the positions of the parity location pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG can vary depending on the implementation scheme.

[0160] In an exemplary embodiment, the parity location pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG may be included in the metadata used to manage the data stored in the memory device 110.

[0161] In another exemplary embodiment, the parity position pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG can be stored in separate storage blocks allocated among a plurality of storage blocks BLK included in the memory device 110 to store the parity position pointer PARITY_LOC_PTR and the parity write flag PARITY_WR_FLG.

[0162] The exemplary embodiments described above have described the operation of the memory system 100 writing the first data DATA_1 into the memory device 110.

[0163] In the following, embodiments of the present disclosure will describe the operation of the memory system 100 writing a second data DATA_2 immediately after writing the first data DATA_1 to the memory device 110.

[0164] Figure 9This is a diagram illustrating an example of an operation in which the memory system 100 writes a second data DATA_2 after the first data DATA_1 has been written, according to an embodiment of the present disclosure.

[0165] Reference Figure 9 When the first data DATA_1 is written to the memory device 110 and the second data DATA_2 is written, the memory controller 120 of the memory system 100 can write the second data DATA_2 immediately after or in the same position in the memory device 110 where the first data DATA_1 was written. In this case, the size of the second data DATA_2 can be changed during operation.

[0166] Figure 10 This is a diagram illustrating an example of an operation in which a memory system 100 according to an embodiment of the present disclosure writes a parity check associated with the sum of first data DATA_1 and second data DATA_2.

[0167] Reference Figure 10 The memory controller 120 of the memory system 100 can write a parity check associated with the sum of the first data DATA_1 and the second data DATA_2 into the memory device 110.

[0168] In this scenario, the parity check operation associated with the sum of the first data DATA_1 and the second data DATA_2 written by the memory controller 120 can vary depending on the size of the first data DATA_1 and the sum of the sizes of the second data DATA_2. Referring below... Figure 11 and Figure 12 A detailed description of the parity check write operation according to embodiments of the present disclosure is provided.

[0169] Reference Figure 11 and Figure 12 The parity write flag PARITY_WR_FLG and memory device 110 are shown separately to indicate whether the parity write flag PARITY_WR_FLG has changed, but it is understood that this is not limited to the case where the parity write flag PARITY_WR_FLG exists outside the memory device 110.

[0170] In addition, Figure 11 and Figure 12 In the parity write flag, a "V" mark on the parity write flag PARITY_WR_FLG indicates that the parity write flag PARITY_WR_FLG has been set, and the absence of a "V" mark on the parity write flag PARITY_WR_FLG indicates that the parity write flag PARITY_WR_FLG has been reset.

[0171] Figure 11 This is a diagram illustrating an example of a parity check operation performed by a memory system 100 according to an embodiment of the present disclosure, where the sum of first data DATA_1 and second data DATA_2 is written.

[0172] exist Figure 11 In this context, the sum of the size 1101 of the first data DATA_1 and the size 1102 of the second data DATA_2 has a size 1103, which is equal to the size 1104 of the reference write unit REF_WR_UNIT. Additionally, the parity position pointer PARITY_LOC_PTR indicates the location 1105 where the first parity PARITY_1 associated with the first data DATA_1 is written, and the parity write flag PARITY_WR_FLG is in the setting state 1106 indicated by the V flag.

[0173] In this scenario, the memory controller 120 can reset the parity write flag PARITY_WR_FLG (changing the parity write flag PARITY_WR_FLG to the reset state 1107 indicated by the "Unmarked" box), and then write the second data DATA_2 to the parity of the sum of the first data DATA_1 and the second data DATA_2. The reason the memory controller 120 resets the parity write flag PARITY_WR_FLG is that the parity 1109 of the sum of the first data DATA_1 and the second data DATA_2 has already been written to the memory device 110, so the memory controller 120 does not need to manage the first parity PARITY_1.

[0174] Meanwhile, the memory controller 120 can maintain the parity location pointer PARITY_LOC_PTR without changing its value. Subsequently, when a new parity is written to the parity memory block PARITY_BLK, the location of the new parity to be written can be determined based on the value of the parity location pointer PARITY_LOC_PTR.

[0175] Figure 12 This is a diagram illustrating another example of the parity check operation of writing the sum of first data DATA_1 and second data DATA_2 according to an embodiment of the present disclosure.

[0176] Reference Figure 12 The sum of the size of the first data DATA_1 (1201) and the size of the second data DATA_2 (1202) (1203) is less than the size of the reference write unit REF_WR_UNIT (1204).

[0177] In this scenario, the memory controller 120 can reset the parity write flag PARITY_WR_FLG and write the parity of the sum of the first data DATA_1 and the second data DATA_2 (associated with the sum of the first data DATA_1 and the second data DATA_2) to the parity memory block PARITY_BLK at location 1205. This is because the sum 1203 of the size 1201 of the first data DATA_1 and the size 1202 of the second data DATA_2 is less than the size 1204 of the reference write unit REF_WR_UNIT.

[0178] Because the parity of the sum of the first data DATA_1 and the second data DATA_2 is a valid parity, the memory controller 120 can set, for example, the parity write flag PARITY_WR_FLG indicated by the V flag 1206.

[0179] In addition, since the parity check of the sum of the first data DATA_1 and the second data DATA_2 is the most recently written parity check, the memory controller 120 can update the value of the parity location pointer PARITY_LOC_PTR to the location 1208 where the parity check of the sum of the first data DATA_1 and the second data DATA_2 was written.

[0180] Figure 13 This is a flowchart illustrating an example of operations performed by the memory system 100 during a power-on reset according to an embodiment of the present disclosure.

[0181] Reference Figure 13 The memory controller 120 of the memory system 100 can check the parity write flag PARITY_WR_FLG (S1310) during power-on reset (POR).

[0182] The memory controller 120 can determine whether the parity write flag PARITY_WR_FLG is set (S1320). In this case, the setting of the parity write flag PARITY_WR_FLG can mean that data smaller than the size of the reference write unit REF_WR_UNIT is written to the memory device 110, so the memory controller 120 needs to verify whether an error has occurred in the data.

[0183] When the parity write flag PARITY_WR_FLG is set (S1320 - Yes), the memory controller 120 can verify the first data DATA_1 written to the memory device 110 based on the first parity PARITY_1 written to the position indicated by the parity position pointer PARITY_LOC_PTR (S1330). In this case, the memory controller 120 can calculate the parity based on the first data DATA_1 written to the memory device 110, and verify the first data DATA_1 by determining whether the calculated parity is the same as the first parity PARITY_1, and can terminate the operation (end). When the parity write flag PARITY_WR_FLG is not set (S1320 - No), the memory controller 120 does not perform any action (end).

[0184] Simultaneously, the memory controller 120 can search for the first data DATA_1 in an open memory block among the multiple memory blocks BLK disposed in the memory device 110. This is because: after the first data DATA_1, which is smaller than the size of the reference write unit REF_WR_UNIT, has been written to an open memory block of the memory device 110, a power-on reset is performed before the memory block where the first data DATA_1 was written has been closed.

[0185] Figure 14 This is a flowchart illustrating a method of operating a memory system 100 according to an exemplary embodiment of the present disclosure.

[0186] Reference Figure 14 The method of operating the memory system 100 may include receiving a clear command FLUSH_CMD from a host, the clear command FLUSH_CMD instructing the memory system 100 to clear data cached in the data cache DATA_CACHE to the memory device 110 (S1410). See also... Figure 4 The memory system 100 receives the clear command FLUSH_CMD from the host.

[0187] Additionally, the operation method of the memory system 100 may include clearing the first data DATA_1 to the memory device 110 (S1420). In this case, the first data DATA_1 is in a state where it is cached in the data cache DATA_CACHE and has a size smaller than the reference write unit REF_WR_UNIT, wherein the data cache DATA_CACHE is used to cache data to be written to the memory device 110, and the reference write unit REF_WR_UNIT is a reference used to write the data to the memory device 110 together with parity.

[0188] Further, the method of operating the memory system 100 may include writing a first parity PARITY_1, which is a parity check associated with the first data DATA_1, into the parity storage block PARITY_BLK (S1430). The parity storage block PARITY_BLK is a storage block among a plurality of storage blocks BLK included in the memory device 110 for storing parity checks of data blocks, wherein the size of each data block is smaller than the size of the reference write unit REF_WR_UNIT. (Refer to...) Figure 12 The parity_1 associated with the first data DATA_1 is stored at position 1205 of the parity storage block PARITY_BLK, and the parity of (DATA_1+DATA_2) is stored at position 1208 of the parity storage block PARITY_BLK.

[0189] Additionally, the operation method of the memory system 100 may include updating the value of the parity location pointer PARITY_LOC_PTR to the location where the first parity PARITY_1 was written, the value of which indicates the location of the parity most recently written to the memory device 110 among the parities of a data block whose size is smaller than the reference write unit REF_WR_UNIT (S1440).

[0190] The operation method of the memory system 100 may include setting a parity write flag PARITY_WR_FLG, which is a flag indicating whether the parity check indicated by the parity position pointer PARITY_LOC_PTR is valid (S1450).

[0191] In this case, the parity write flag PARITY_WR_FLG and the parity location pointer PARITY_LOC_PTR can be included in the metadata used to manage the data stored in the memory device 110.

[0192] The method of operating the memory system 100 may further include writing a second data DATA_2 at the location where the first data DATA_1 is written in the memory device 110, the second data DATA_2 being the data to be written immediately after the first data DATA_1.

[0193] The operation method of the memory system 100 may further include writing the parity check of the sum of the first data DATA_1 and the second data DATA_2 into the memory device 110.

[0194] In this scenario, for example, when the sum of the sizes of the first data DATA_1 and the second data DATA_2 equals the size of the reference write unit REF_WR_UNIT, the parity write flag PARITY_WR_FLG can be reset. Parity can then be checked by writing the sum of the first data DATA_1 and the second data DATA_2 using the second data DATA_2. (See reference...) Figure 11 Then, or following the second data DATA_2, write the parity check 1109 associated with DATA_1 and DATA_2.

[0195] In another exemplary embodiment, if the sum of the sizes of the first data DATA_1 and the second data DATA_2 is less than the size of the reference write unit REF_WR_UNIT, the parity write flag PARITY_WR_FLG can be set, and the parity of the sum of the first data DATA_1 and the second data DATA_2 can be written to the parity storage block PARITY_BLK. Furthermore, the value of the parity position pointer PARITY_LOC_PTR can be updated to the position where the parity of the sum of the first data DATA_1 and the second data DATA_2 was written. (Refer to...) Figure 12 The parity position pointer PARITY_LOC_PTR can be updated to position 1208, where the parity of the sum of the first data DATA_1 and the second data DATA_2 is written.

[0196] The method of operating the memory system 100 may further include checking the parity write flag PARITY_WR_FLG during power-on reset, and, if the parity write flag PARITY_WR_FLG is set, verifying the first data DATA_1 written to the memory device 110 based on the first parity PARITY_1 written to the location indicated by the parity position pointer PARITY_LOC_PTR.

[0197] In some implementations, the operation of the memory controller 120 described above can be controlled by the control circuit 123 and can be executed by the processor 124 running (driving) firmware or program instructions in the working memory 125 that are programmed with all the operations of the memory controller 120.

[0198] Figure 15 This is a diagram illustrating the configuration of a computing system 1500 according to an embodiment of the disclosed technology.

[0199] Reference Figure 15The computing system 1500 according to embodiments of the disclosed technology may include: a memory system 100 electrically connected to a system bus 1560; a CPU 1510 configured to control all operations of the computing system 1500; RAM 1520 configured to store data and information associated with the operation of the computing system 1500; a user interface / user experience (UI / UX) module 1530 configured to provide a user environment to a user; a communication module 1540 configured to communicate with external devices in a wired and / or wireless manner; and a power management module 1550 configured to manage the power used by the computing system 1500.

[0200] The computing system 1500 may be a personal computer (PC), or any one or more mobile terminals such as smartphones, tablets, or various electronic devices.

[0201] The computing system 1500 may further include a battery for supplying operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0202] The memory system 100 may include not only devices configured to store data on disks, such as hard disk drives (HDDs), but also devices configured to store data in non-volatile memory, such as solid-state drives (SSDs), general-purpose flash memory devices, or embedded MMC (eMMC) devices. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, the memory system 100 can be implemented as various types of storage devices and installed inside various electronic devices.

[0203] Based on the embodiments of the disclosed technology, the operation latency of the memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead incurred in processes that call specific functions can be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described with specific details and different specifications for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on what is disclosed or shown in this disclosure.

Claims

1. A memory system comprising: a memory device including a plurality of memory blocks; and a memory controller in communication with and controlling the memory device; wherein, upon receiving a flush command from a host instructing the memory device to flush data to be cached in a data cache to the memory device: flushing first data to be cached in the data cache to the memory device, a size of the first data being smaller than a size of a reference write unit, the reference write unit being a reference to write data with parity to the memory device, and writing first parity associated with the first data to a parity storage block among the plurality of memory blocks, the parity storage block storing parity of data blocks, each of the data blocks having a size smaller than the size of the reference write unit.

2. The memory system of claim 1, wherein the memory controller updates a value of a parity location pointer to a location where the first parity is written, the value of the parity location pointer indicating a location of a parity among the parity of the data blocks that is most recently written to the memory device, and setting a parity write flag indicating whether the first parity at the location indicated by the parity location pointer is valid.

3. The memory system of claim 1, wherein the memory controller writes second data to be written immediately after the first data following a location in the memory device where the first data is written.

4. The memory system of claim 3, wherein the memory controller writes parity of a sum of the first data and the second data to the memory device. when a sum of the size of the first data and the size of the second data is the size of the reference write unit, the memory controller resets a parity write flag and writes parity of the sum of the first data and the second data following the second data.

5. The memory system of claim 4, wherein, when the sum of the size of the first data and the size of the second data is smaller than the size of the reference write unit, the memory controller sets the parity write flag, writes parity of the sum of the first data and the second data to the parity storage block, and updates a value of a parity location pointer to a location where parity of the sum of the first data and the second data is written.

6. The memory system of claim 4, wherein, 7. The memory system of claim 1, wherein the memory controller checks a parity write flag upon power-on reset, and in a case where the parity write flag is set, verifies the first data written to the memory device based on the first parity written to a location indicated by a parity location pointer.

8. A method of operating a memory system including a memory device having a plurality of memory blocks, the method comprising: ​ receiving, by a memory controller from a host, a flush command instructing the memory device to flush data cached in a data cache to the memory device, flushing first data to be cached in the data cache to the memory device, a size of the first data being smaller than a size of a reference write unit, the reference write unit being a reference to write data with parity to the memory device, and writing first parity associated with the first data to a parity storage block among the plurality of storage blocks, the parity storage block storing parity of data blocks, each of the data blocks being smaller in size than the reference write unit.

9. The method of claim 8, further comprising: updating a value of a parity location pointer to a location where the first parity is written, the value of the parity location pointer indicating a location of a parity among the parity of the data blocks that is most recently written to the memory device, and setting a parity write flag indicating whether the first parity at the location indicated by the parity location pointer is valid.

10. The method of claim 9, further comprising: a location in the memory device where the first data is written next writes second data written next to the first data.

11. The method of claim 10, further comprising: writing parity of a sum of the first data and the second data to the memory device.

12. The method of claim 11, further comprising: when a sum of a size of the first data and a size of the second data is equal to a size of the reference write unit: resetting the parity write flag; and next to the second data, parity of a sum of the first data and the second data is written. when the sum of the size of the first data and the size of the second data is smaller than the size of the reference write unit:

13. The method of claim 11, further comprising: setting, by the memory controller, the parity write flag; writing parity of a sum of the first data and the second data to the parity storage block; and updating a value of a parity location pointer to a location where parity of a sum of the first data and the second data is written.

14. The method of claim 9, further comprising: checking the parity write flag at power-on reset; and in a case where the parity write flag is set, verifying the first data written to the memory device based on the first parity written to the location indicated by the parity location pointer.

15. A memory system, comprising: a memory device including a plurality of storage blocks; and a memory controller in communication with the memory device and controlling the memory device, wherein the memory controller: receives, from a host, a flush command instructing the memory device to flush data cached in a data cache to the memory device; writes first data to be cached in the data cache to a location of the memory device, a size of the first data being smaller than a size of a reference write unit, the reference write unit being a reference to write data with parity to the memory device; ​ ​ ​ the location where the first data has been written; calculating a first parity associated with the first data; determining a value of a parity location pointer, the value of the parity location pointer indicating a location where the first parity has been written; and setting a parity write flag.

16. The memory system of claim 15, wherein the memory controller further: determining that a sum of a size of the first data and a size of the second data is equal to a size of a reference write unit; in a case where the sum of the size of the first data and the size of the second data is equal to the size of the reference write unit: resetting the parity write flag; calculating a parity associated with the sum of the first data and the second data; and subsequently the second data writes the calculated parity.

17. The memory system of claim 15, wherein the memory controller further: determining that a sum of a size of the first data and a size of the second data is less than a size of a reference write unit; in a case where the sum of the size of the first data and the size of the second data is less than the size of the reference write unit: calculating a sum parity associated with the sum of the first data and the second data; and writing the calculated sum parity to a parity storage block in the memory device.

18. The memory system of claim 17, wherein the memory controller further: updating a value of a second parity location pointer to a location where the calculated sum parity has been written.

19. The memory system of claim 15, wherein the parity write flag is set in the memory device.

20. The memory system of claim 15, wherein the parity write flag is set outside of the memory device.

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