Method and device for implementing processor front-end instruction reading queue

Abstract

The present invention proposes a method for implementing a processor front-end instruction read queue, which relates to the field of computer technology. The method includes: the processor front-end includes an instruction prediction component, an instruction read queue, and an instruction read component. When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction read queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component to the instruction read queue in the form of an instruction block; and the instruction block is stored in a storage structure preset by the instruction read queue to wait for the instruction read component to extract it. When an instruction fetch request prediction instruction prediction error is detected, a self-flushing operation is performed to re-sequence the instruction fetch request prediction instruction. As a result, the instruction read queue acts as a buffer queue between the instruction prediction component and the instruction read component, mutually hiding the pipeline blockage of instruction prediction and instruction read and the cavitation caused by self-flushing, thereby realizing a high-performance, high-frequency processor front-end.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, electronic device and storage medium for implementing a processor front-end instruction reading queue. Background Art

[0002] High-performance processors use pipeline technology, and the problem that comes with it is the cycle loss caused by branch instruction misprediction, which is more obvious for high-performance processors with deep pipeline structures. With the improvement of chip manufacturing process, the technology is gradually approaching the physical limit. High-performance processors can no longer rely solely on process advancement to implement more complex architectures on chips year by year. The main frequency of modern processors is gradually increasing. At the same time, in order to achieve high branch instruction prediction accuracy, the branch instruction prediction strategy has become increasingly complex, making it difficult to complete complex branch instruction prediction tasks within an increasingly limited clock cycle. In related technologies, branch instruction prediction tasks will have mispredictions, which will produce mispredicted branch instruction prediction bubbles, affecting the processing efficiency of high-performance processors. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] To this end, the first purpose of the present invention is to propose a method for implementing a processor front-end instruction read queue, wherein the instruction read queue serves as a buffer queue between an instruction prediction component and an instruction read component, hiding the pipeline blockage and cavitation caused by self-flushing of instruction prediction and instruction reading from each other, thereby realizing a high-performance, high-frequency processor front-end.

[0005] The second objective of the present invention is to provide a device for implementing a processor front-end instruction read queue.

[0006] A third objective of the present invention is to provide an electronic device.

[0007] A fourth object of the present invention is to provide a non-transitory computer-readable storage medium storing computer instructions.

[0008] To achieve the above-mentioned purpose, the first aspect of the present invention proposes a method for implementing a processor front-end instruction read queue, wherein the processor front-end includes an instruction prediction component, an instruction read queue, and an instruction read component, and each pipeline stage of the instruction prediction component is connected to the instruction read queue, and the method includes:

[0009] When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction read queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component predicting the instruction fetch request to the instruction read queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction read queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block;

[0010] Based on the instruction information of the instruction fetch request predicting the instruction, the instruction block is stored in a storage structure preset in the instruction fetch queue to wait for the instruction fetch component to fetch it;

[0011] After the instruction reading component extracts the instruction block, the instruction fetch request prediction instruction in the instruction block is pre-decoded based on the instruction decoder in the instruction reading component, and the pre-decoded information is transmitted back to the instruction reading queue, so that when the instruction decoder detects that the instruction fetch request prediction instruction is wrong according to the pre-decoded information, a self-flush operation is performed to re-sequence the instruction fetch request prediction instructions corresponding to the instruction block in the instruction reading queue.

[0012] To achieve the above-mentioned purpose, the second aspect of the present invention proposes a device for implementing a processor front-end instruction read queue, wherein the processor front-end includes an instruction prediction component, an instruction read queue, and an instruction read component, and each pipeline stage of the instruction prediction component is connected to the instruction read queue, and the device includes:

[0013] A transfer module, used for, when the instruction prediction unit is running, the instruction prediction unit shakes hands with the instruction reading queue to transfer the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction unit predicting the instruction fetch request to the instruction reading queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction reading queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block;

[0014] A storage module, used for storing the instruction block in a storage structure preset in the instruction read queue based on the instruction information of the instruction fetch request prediction instruction, so as to wait for the instruction read component to extract it;

[0015] A reordering module is used to pre-decode the instruction fetch request prediction instructions in the instruction block based on the instruction decoder in the instruction fetch component after the instruction fetch component extracts the instruction block, and transmit the pre-decoding information back to the instruction fetch queue, so as to perform a self-flush operation and reorder the instruction fetch request prediction instructions corresponding to the instruction block in the instruction fetch queue when the instruction decoder detects that the instruction fetch request prediction instruction is wrong based on the pre-decoding information.

[0016] To achieve the above-mentioned purpose, the third aspect of the present invention proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the first aspect.

[0017] In order to achieve the above-mentioned purpose, the fourth aspect of the present invention proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to enable the computer to execute the method described in the first aspect.

[0018] The implementation method, device, electronic device and storage medium of the processor front-end instruction read queue provided by the embodiment of the present invention, the processor front-end includes an instruction prediction component, an instruction read queue, and an instruction read component. When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction read queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component to the instruction read queue in the form of an instruction block; based on the instruction information of the instruction fetch request prediction instruction, the instruction block is stored in the storage structure preset by the instruction read queue to wait for the instruction read component to extract it, and when the instruction fetch request prediction instruction prediction error is detected, a self-flush operation is performed to re-sequence the instruction fetch request prediction instruction. As a result, the instruction read queue acts as a buffer queue between the instruction prediction component and the instruction read component, mutually hiding the pipeline blockage of instruction prediction and instruction read and the cavitation caused by self-flush, so as to realize a high-performance, high-frequency processor front-end.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A flowchart of a method for implementing a processor front-end instruction reading queue provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of an operation flow of a target instruction block in an instruction reading queue provided by an embodiment of the present invention;

[0023] Figure 3 An exemplary diagram of another implementation method of a processor front-end instruction read queue provided by an embodiment of the present invention;

[0024] Figure 4A schematic diagram of the structure of a device for implementing a processor front-end instruction read queue provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0026] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of the present invention are in compliance with the relevant provisions of national laws and regulations.

[0027] The following describes a method and device for implementing a processor front-end instruction read queue according to an embodiment of the present invention with reference to the accompanying drawings.

[0028] Figure 1 A flowchart of a method for implementing a processor front-end instruction reading queue provided by an embodiment of the present invention.

[0029] like Figure 1 As shown, the method comprises the following steps:

[0030] Step 101, when the instruction prediction component is running, the instruction prediction component shakes hands with the instruction read queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component to the instruction read queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction read queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block.

[0031] In some embodiments, an instruction block is a range of instruction fetch requests that the instruction prediction unit sends to the instruction fetch queue each time.

[0032] Optionally, the instruction read queue is a buffer queue between the instruction prediction unit and the instruction read unit, and its main function is to temporarily store instruction blocks of the instruction prediction unit and send instruction fetch requests to the instruction read unit according to these instruction blocks. Another important function is to temporarily store instruction fetch request prediction instructions obtained by predicting instruction fetch requests by each branch predictor of the instruction prediction unit.

[0033] The predicted width of the instruction block is the maximum instruction stream width predicted and provided to the instruction fetching unit each time, which is the same as the instruction fetch width. If the instruction fetch width is 32 bytes, the predicted width is also 32 bytes.

[0034] Instruction block partitioning strategies include:

[0035] Indexed by the starting address, which is generated in the prediction pipeline of the pipeline stage. The starting address includes one of two cases:

[0036] The starting address is the ending address of the previous instruction block;

[0037] The start address is the target address of the re-fetched instruction from outside the instruction prediction unit;

[0038] Among them, the instruction block contains at most two branch instructions, and the first one must be a conditional branch instruction;

[0039] The end address of the instruction block satisfies one of the three conditions, where the three conditions are:

[0040] The difference between the end address and the start address is the predicted width;

[0041] The ending address is the PC of the third branch instruction within the predicted width range starting from the starting address;

[0042] The end address is the PC (Program Counter) of the next instruction of an unconditional jump branch, and the end address is within the predicted width range starting from the start address.

[0043] Among them, the instruction life cycle of the instruction fetch request prediction instruction in the instruction block will involve four pointers in the instruction read queue, namely the enqueue pointer, the instruction fetch pointer, the write back pointer and the dequeue pointer. The enqueue pointer is at the front and the dequeue pointer is at the end. When the enqueue pointer starts to point to the next instruction block of the instruction read queue, the instruction fetch request prediction instruction in the instruction block enters the instruction life cycle. When the dequeue pointer points to the next instruction block of the instruction read queue, the instruction fetch request prediction instruction in the instruction block completes the instruction life cycle. The position of the prefetch pointer is between the enqueue pointer and the instruction fetch pointer.

[0044] Step 102 , based on the instruction information of the instruction predicted by the instruction fetch request, the instruction block is stored in a storage structure preset in the instruction fetch queue to wait for being fetched by the instruction fetch component.

[0045] In this embodiment, the instruction information may include information such as the address and address width of the instruction, but is not limited thereto.

[0046] Optionally, the storage structure is determined based on the instruction information of the instruction block corresponding to the instruction fetch request prediction instruction stored in the instruction read queue, and is implemented through registers and / or register files and / or static random access memory to achieve high performance and high main frequency, and reduce area and cost.

[0047] Furthermore, the instruction read queue mainly includes the following storage structures:

[0048] ftq_pc_regfile: implemented using register stack, stores instruction information related to the instruction address predicted by the instruction fetch request, including the following fields:

[0049] startAddr instruction block starting address;

[0050] nextLineAddr is the starting address of the next cache line of the instruction block;

[0051] IsNextMask determines whether the starting position of each possible instruction fetch request prediction instruction in the instruction block is within the next region aligned with the predicted width;

[0052] fallThruError predicts whether the next sequential instruction fetch request predicted instruction address is wrong.

[0053] ftq_pd_regfile: implemented with register stack, stores the decoding information of each instruction fetch request prediction instruction in the instruction block returned by the instruction fetch component, including the following fields:

[0054] brMask predicts whether each instruction fetch request is a conditional branch instruction;

[0055] jmpInfo Information about the unconditional jump instruction at the end of the instruction block, including whether it exists, whether it is a jal (jump and link) or jalr (jump and link register), and whether it is a call (call instruction) or ret (return) instruction;

[0056] jmpOffset The position of the unconditional jump instruction at the end of the instruction block;

[0057] The jump address of jal at the end of the jalTarget instruction block;

[0058] rvcMask predicts whether each instruction fetch request is a compressed instruction;

[0059] ftq_redirect_sram: implemented with static random-access memory (SRAM), it stores prediction information that needs to be restored when re-fetching instructions, mainly including information related to the return address stack (RAS) and the branch instruction history.

[0060] ftq_meta_1r_sram: implemented with static random access memory, stores the remaining instruction prediction unit prediction information.

[0061] ftb_entry_regfile: implemented with register file, stores necessary information of instruction fetch target buffer entries during prediction, and is used to train new instruction fetch target buffer entries after submission.

[0062] Step 103, after the instruction reading component extracts the instruction block, the instruction fetch request prediction instruction in the instruction block is pre-decoded based on the instruction decoder in the instruction reading component, and the pre-decoded information is returned to the instruction reading queue, so that when the instruction decoder detects that the instruction fetch request prediction instruction is predicted incorrectly based on the pre-decoded information, a self-flush operation is performed to reorder the instruction fetch request prediction instructions corresponding to the instruction block in the instruction reading queue.

[0063] Wherein, all subsequent spare instruction fetch request prediction instructions after the instruction fetch request prediction instruction in the instruction block is mispredicted are cancelled.

[0064] Furthermore, the instruction fetch request prediction instruction needs to be executed in the instruction reading unit like other instructions, but its result bus additionally contains branch results. After execution, the instruction reading unit will update the execution information and write it back to the branch queue. These results include the target address of the JALR instruction and the branch direction of the conditional branch instruction. These results can be used to determine whether the prediction of this instruction fetch request prediction instruction is accurate. Similarly, if the prediction is wrong, a self-flush operation is performed. Regardless of whether the prediction of the instruction fetch request prediction instruction is successful or not, the execution result of the instruction fetch request prediction instruction will be fed back to the instruction reading unit to correct the relevant branch predictor to help the prediction of subsequent instruction fetch request prediction instructions.

[0065] The implementation method of the processor front-end instruction reading queue provided by the embodiment of the present invention, the processor front-end includes an instruction prediction component, an instruction reading queue, and an instruction reading component. When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction reading queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component to the instruction reading queue in the form of an instruction block; based on the instruction information of the instruction fetch request prediction instruction, the instruction block is stored in the storage structure preset by the instruction reading queue to wait for the instruction reading component to extract it, and when the instruction fetch request prediction instruction prediction error is detected, a self-flushing operation is performed to re-sequence the instruction fetch request prediction instruction. As a result, the instruction reading queue acts as a buffer queue between the instruction prediction component and the instruction reading component, mutually hiding the pipeline blockage of instruction prediction and instruction reading and the cavitation caused by self-flushing, so as to realize a high-performance, high-frequency processor front-end.

[0066] Figure 2 A schematic diagram of the operation flow of a target instruction block in an instruction reading queue provided by an embodiment of the present invention.

[0067] like Figure 2As shown, the method comprises the following steps:

[0068] Step 201, when any target instruction block in the corresponding instruction block is issued from the instruction prediction unit when the instruction prediction unit shakes hands with the instruction read queue, it enters the instruction read queue, and the enqueue pointer corresponding to the instruction read queue points to the next instruction block of the instruction read queue, initializes the instruction fetch request prediction instruction in the instruction read queue item corresponding to the target instruction block, and writes the instruction fetch request prediction instruction into the storage structure of the instruction read queue; if the target instruction block comes from the branch predictor of the instruction prediction unit, restore the enqueue pointer and instruction fetch pointer corresponding to the instruction read queue.

[0069] In some embodiments, the instruction life cycle of the instructions in instruction block n (target instruction block) will involve four pointers in the instruction read queue, namely, the enqueue pointer, the instruction fetch pointer, the write back pointer and the dequeue pointer. The enqueue pointer is at the front and the dequeue pointer is at the end. When the enqueue pointer starts to point to the next instruction block in the instruction read queue, the instruction fetch request prediction instruction in the instruction block enters the instruction life cycle. When the dequeue pointer points to the next instruction block in the instruction read queue, the instruction fetch request prediction instruction in the instruction block completes the instruction life cycle.

[0070] Among them, the four pointers, namely, the queue entry pointer, the instruction fetch pointer, the write-back pointer and the queue exit pointer, all have an initialization state, and the initialization state points to the first instruction block of the instruction read queue.

[0071] The status information of each instruction read queue item in the instruction read queue (instruction fetch request prediction instruction) is implemented using registers.

[0072] Optionally, the branch predictor is organized in the form of multiple predictors with different delays. The predictor with larger delay and relatively more accuracy is placed in the later pipeline stage. The instruction fetch request prediction instruction generated by it will be compared with the previous predictor. If they are different, the pipeline will be flushed. The overall prediction result is based on the most accurate predictor.

[0073] Among them, the branch predictor adopts a multi-level hybrid prediction architecture, mainly including the next line predictor (Next Line Predictor, NLP) and the accurate predictor (Accurate Predictor, APD). NLP provides bubble-free prediction, and the prediction result can be obtained in the next beat of the predicted instruction fetch request. The delay of each component of APD is between 2 and 3 beats. A predicted instruction fetch request will go through three pipeline stages, and each pipeline stage will produce a new prediction result. These predictors distributed in different pipeline stages form a branch predictor (Overriding Predictor).

[0074] Step 202, when the instruction fetch queue sends an instruction fetch request to the instruction fetch unit, the instruction fetch pointer points to the next instruction block of the instruction fetch queue and waits for the instruction decoder in the instruction fetch unit to write back the pre-decoding information of the instruction predicted by the instruction fetch request.

[0075] Step 203, when the instruction decoder in the instruction reading unit writes back the pre-decoding information, the write-back pointer corresponding to the instruction reading queue points to the next instruction block of the instruction reading queue. If the instruction decoder detects that the instruction fetch request predicts an instruction prediction error based on the pre-decoding information, a corresponding first re-instruction fetch request is sent to the instruction prediction unit to restore the queue entry pointer and the instruction fetch pointer.

[0076] In this embodiment, each pipeline stage of the instruction prediction unit is connected to the instruction read queue. Once the first prediction pipeline stage has a valid prediction result (the instruction fetch request prediction instruction prediction is correct), or the subsequent prediction pipeline stage produces a different prediction result, it will handshake with the instruction read queue and pass the handshake information to the instruction read queue. After the instruction read unit prediction is completed, the global history information used in the current prediction will be stored in the instruction read queue. In the case that the pre-decoding information corresponds to the instruction fetch request prediction instruction prediction error, it is read out and sent back to the instruction prediction unit.

[0077] Step 204, when the instruction decoder detects that the instruction fetch request prediction instruction is correct based on the pre-decoding information, the instruction fetch request prediction instruction corresponding to the pre-decoding information is input into the processor back end for execution. If the processor back end detects that the instruction fetch request prediction instruction is wrong, the instruction read queue is notified, and a second re-instruction fetch request is sent to the instruction read component and the instruction prediction component to restore the enqueue pointer, the instruction fetch pointer and the write back pointer.

[0078] Optionally, the processor backend can be a pipeline for processor scheduling, emission, execution, writeback, submission, etc.

[0079] Step 205, when the processor back end detects that the instruction fetch request prediction instruction is correctly predicted, the instruction fetch request prediction instruction corresponding to the pre-decoding information is submitted at the processor back end, and the instruction read queue is notified until all the instruction fetch request prediction instructions in the instruction read queue items have been submitted, the dequeue pointer corresponding to the instruction read queue points to the next instruction block of the instruction read queue, and the instruction read queue completely releases the instruction read queue item corresponding to the target instruction block in the storage structure.

[0080] Optionally, after all the instruction fetch request prediction instructions in the instruction fetch queue items have been submitted, the target instruction fetch request prediction instruction temporarily stored in the instruction fetch queue is sent back to the instruction prediction unit for training of the branch predictor.

[0081] In some embodiments, after the prefetch pointer reads the target address of the instruction block (if jumping, it is the jump target, if not jumping, it is the starting address of the next instruction block in sequence), and sends a prefetch request to a preset instruction prefetcher, the instruction prefetcher completes the address translation of the target address (accesses ITLB) and accesses the tag address storage body (TAG SRAM) of the instruction cache corresponding to the instruction prefetcher. If the target address exists in the tag address storage body, the prefetch request is canceled. If the target address does not exist in the tag address storage body, an application is made to allocate a prefetch request item to the prefetch queue item of the instruction prefetcher, and a prefetch request is sent to the lower storage system of the instruction cache (such as the second-level cache (L2 Cache)) to prefetch the target instruction cache line corresponding to the prefetch request item to the lower storage system (such as the second-level cache L2Cache); wherein the instruction prefetcher records the physical address of the prefetch request that has been sent, and the uniqueness of all prefetch requests in the prefetch queue item is determined according to the physical address of the prefetch request.

[0082] Furthermore, before any prefetch request applies for a prefetch queue entry, the prefetcher will check the physical address record of the prefetch request that has been issued. If it is found that the cache block address is the same as the prefetch request that has been sent, the current prefetch request will be cancelled.

[0083] Furthermore, the instruction reading component fetches the instruction fetch request prediction instruction from the instruction cache according to the target address of the target instruction block passed by the instruction reading component pointer item in the instruction reading queue, and performs a hit check on the instruction fetch request prediction instruction translation buffer (Instruction Translation Lookaside Buffer, ITLB) and the instruction cache (Instruction Cache, ICache). When a hit occurs, the instruction fetch request prediction instruction is taken out from the ICache Data (the tag address storage body of the instruction cache) and transmitted to the pipeline stage of the processor back end.

[0084] Optionally, the instruction read queue stores the program counter PC (Program Counter). Since the processor backend has a large overhead for storing PC, when the processor backend needs to read the PC, it will also read it from the instruction read queue. The processor backend is mainly responsible for the scheduling, transmission, execution, write back, submission, etc. of instructions.

[0085] Optionally, the branch predictor is trained based on the instruction fetch request prediction instructions of the instruction block, the pre-decoding information corresponding to the instruction fetch request prediction instructions, and the execution results of the instruction fetch request prediction instructions on the back end of the processor to obtain a trained branch predictor, thereby continuously updating the branch predictor and improving the reliability of the branch predictor.

[0086] Furthermore, when the instruction prediction unit receives a re-instruction fetch request from outside it, it will restore the elements that have been speculatively updated (global history information, RAS stack top items, etc.).

[0087] In addition, based on the processing information of the processor front end in the instruction read queue, the instruction read queue is used as a processor front-end performance counter for performance analysis of the processor front end; wherein the processing information includes the number of re-fetched instructions of instruction fetch requests, the number of various re-fetched instruction requests of the instruction read queue, the number of instruction prediction errors predicted by instruction fetch requests, the number of instruction prediction errors predicted by various types of instruction fetch requests, the number of prediction errors of each branch instruction prediction pipeline stage, and the number of prediction errors of each type of branch instruction in the instruction block.

[0088] The implementation method of the processor front-end instruction reading queue of the embodiment of the present invention, the processor front-end includes an instruction prediction component, an instruction reading queue, and an instruction reading component. When the instruction prediction component is running, the instruction fetch request prediction instructions predicted by the branch predictor corresponding to each instruction prediction component are sent in the form of instruction blocks and stored in the instruction reading queue to wait for the instruction reading component to extract, wherein the instruction fetch request prediction instructions are sent to the instruction reading queue after the instruction prediction component predicts, until all the instruction fetch request prediction instructions in the target instruction block where the instruction fetch request is located are submitted and completed in the processor back-end, and the instruction reading queue completely releases the instruction reading queue items corresponding to the target instruction block in the storage structure. Therefore, the instruction reading queue acts as a buffer queue between the instruction prediction component and the instruction reading component, hiding the pipeline blockage and cavitation caused by self-flushing of instruction prediction and instruction reading from each other, and realizing a high-performance, high-frequency processor front-end.

[0089] In order to clearly explain the above embodiment, Figure 3The present invention is an implementation example diagram of another implementation method of a processor front-end instruction read queue provided by an embodiment of the present invention. Specifically, the processor front-end (referred to as "front-end") includes an instruction prediction unit, an instruction read queue, and an instruction read unit. The processor front-end communicates with the processor back-end (referred to as "back-end") through the instruction read queue. When the instruction prediction unit and the instruction read queue shake hands, any target instruction block in the corresponding instruction block is issued from the instruction prediction unit, and enters the instruction read queue. The instruction fetch request prediction instructions predicted by the branch predictor of each instruction prediction unit are sent in the form of instruction blocks and stored in the instruction read queue (data stored in the instruction read queue). When the instruction read queue issues an instruction fetch request (instruction fetch request) to the instruction read unit, the instruction read unit pre-decodes the instruction fetch request prediction instruction to obtain pre-decoding information, returns the pre-decoding information as branch prediction information to the instruction read queue, and submits the instruction fetch request prediction instruction corresponding to the pre-decoding information at the processor back-end until all the instruction fetch request prediction instructions in the instruction read queue items have been submitted, and returns the processor back-end execution result to the instruction read queue.

[0090] Among them, Figure 3 As shown, another important function of the instruction read queue is to temporarily store the instruction fetch request prediction instructions of each branch predictor of the instruction prediction unit. After the instruction fetch request prediction instructions corresponding to the pre-decoding information are submitted to the processor back end, the execution results of these submitted instruction fetch request prediction instructions are sent back to the instruction prediction unit as branch predictor training information for branch predictor training; the instruction read queue stores the program counter PC, and when the processor back end needs to read the instruction PC, it will also read it from the instruction read queue; between the instruction prediction unit and the instruction read queue, there are all re-instruction fetch requests in the case of instruction fetch request prediction instruction prediction errors, and between the instruction read queue and the instruction read unit, there is also processor back end re-instruction fetching and re-instruction fetching information. In addition, as Figure 3 As shown, the instruction read queue also includes a pre-fetch function, which sends a pre-fetch request to a preset instruction pre-fetcher through a pre-fetch pointer.

[0091] In order to implement the above embodiment, the present invention also proposes a device for implementing a processor front-end instruction reading queue.

[0092] Figure 4 A schematic diagram of the structure of a device for implementing a processor front-end instruction read queue provided by an embodiment of the present invention.

[0093] like Figure 4 As shown, the implementation device 40 of the processor front-end instruction reading queue includes: a transmission module 41, a storage module 42 and a reordering module 43.

[0094] A transfer module 41 is used for, when the instruction prediction unit is running, the instruction prediction unit shakes hands with the instruction reading queue to transfer the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction unit predicting the instruction fetch request to the instruction reading queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction reading queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block;

[0095] A storage module 42, for storing the instruction block in a storage structure preset in the instruction fetch queue based on the instruction information of the instruction fetch request prediction instruction, to wait for the instruction fetch component to fetch it;

[0096] The reordering module 43 is used to pre-decode the instruction fetch request prediction instructions in the instruction block based on the instruction decoder in the instruction fetch component after the instruction fetch component extracts the instruction block, and transmit the pre-decoding information back to the instruction fetch queue, so as to perform a self-flush operation and reorder the instruction fetch request prediction instructions corresponding to the instruction block in the instruction read queue when the instruction decoder detects that the instruction fetch request prediction instruction is wrong according to the pre-decoding information.

[0097] Furthermore, in a possible implementation manner of the embodiment of the present invention, the instruction block is a range of an instruction fetch request that the instruction prediction component gives to the instruction read queue each time.

[0098] Furthermore, in a possible implementation of the embodiment of the present invention, the instruction block division strategy includes:

[0099] Indexed by the starting address, which is generated in the prediction pipeline of the pipeline stage. The starting address includes one of two cases:

[0100] The starting address is the ending address of the previous instruction block;

[0101] The start address is the target address of the re-fetched instruction from outside the instruction prediction unit;

[0102] Among them, the instruction block contains at most two branch instructions, and the first one must be a conditional branch instruction;

[0103] The end address of the instruction block satisfies one of the three conditions, where the three conditions are:

[0104] The difference between the end address and the start address is the predicted width;

[0105] The ending address is the PC of the third branch instruction within the predicted width range starting from the starting address;

[0106] The ending address is the program counter PC of the next instruction of an unconditional jump branch, and the ending address is within the predicted width range starting from the starting address.

[0107] Furthermore, in a possible implementation of the embodiment of the present invention, the device further includes:

[0108] A training module is used to train the branch predictor based on the instruction fetch request prediction instruction of the instruction block, the pre-decoding information corresponding to the instruction fetch request prediction instruction, and the execution result of the instruction fetch request prediction instruction in the processor back end to obtain a trained branch predictor.

[0109] Furthermore, in a possible implementation of an embodiment of the present invention, the storage structure is determined based on instruction information of an instruction block corresponding to an instruction fetch request prediction instruction stored in an instruction read queue, and is implemented through registers and / or register files and / or static random access memory.

[0110] Furthermore, in a possible implementation manner of the embodiment of the present invention, all spare instruction fetch request prediction instructions after the instruction fetch request prediction instruction in the instruction block is mispredicted are cancelled.

[0111] Further, in a possible implementation of an embodiment of the present invention, the instruction life cycle of the instruction fetch request prediction instruction in the instruction block will involve four pointers in the instruction read queue, namely, the enqueue pointer, the instruction fetch pointer, the write-back pointer and the dequeue pointer, wherein the enqueue pointer is at the front and the dequeue pointer is at the end. When the enqueue pointer starts to point to the next instruction block of the instruction read queue, the instruction fetch request prediction instruction in the instruction block enters the instruction life cycle. When the dequeue pointer points to the next instruction block of the instruction read queue, the instruction fetch request prediction instruction in the instruction block completes the instruction life cycle. The position of the prefetch pointer is between the enqueue pointer and the instruction fetch pointer. Further, in a possible implementation of an embodiment of the present invention, the device also includes:

[0112] A prefetch module, for completing the address translation of the target address through the instruction prefetcher and accessing the tag address storage body of the instruction cache corresponding to the instruction prefetcher after the prefetch pointer reads the target address of the instruction block and sends a prefetch request to a preset instruction prefetcher, and if the target address exists in the tag address storage body, canceling the prefetch request, and if the target address does not exist in the tag address storage body, applying to the prefetch queue item of the instruction prefetcher for allocation of a prefetch request item, and sending a prefetch request to the lower storage system of the instruction cache, so as to prefetch the target instruction cache line corresponding to the prefetch request item to the lower storage system;

[0113] The instruction prefetcher records the physical addresses of the prefetch requests that have been sent, and determines the uniqueness of all prefetch requests in the prefetch queue items according to the physical addresses of the prefetch requests.

[0114] Furthermore, in a possible implementation of the embodiment of the present invention, the device further includes:

[0115] A processing module, configured to use the instruction read queue as a processor front-end performance counter based on the processing information of the processor front-end in the instruction read queue, so as to be used for performance analysis of the processor front-end;

[0116] Among them, the processing information includes the number of re-fetched instructions for instruction fetch requests, the number of various re-fetched instruction requests for the instruction read queue, the number of prediction errors of instruction fetch request predictions, the number of prediction errors of various types of instruction fetch requests predictions, the number of prediction errors of each branch instruction prediction pipeline stage, and the number of prediction errors of each type of branch instruction in the instruction block.

[0117] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and will not be repeated here.

[0118] The implementation device of the processor front-end instruction reading queue of the embodiment of the present invention, the processor front-end includes an instruction prediction component, an instruction reading queue, and an instruction reading component. When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction reading queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component to the instruction reading queue in the form of an instruction block; based on the instruction information of the instruction fetch request prediction instruction, the instruction block is stored in the storage structure preset by the instruction reading queue to wait for the instruction reading component to extract it, and when the instruction fetch request prediction instruction prediction error is detected, a self-flush operation is performed to re-sequence the instruction fetch request prediction instruction. As a result, the instruction reading queue acts as a buffer queue between the instruction prediction component and the instruction reading component, mutually hiding the pipeline blockage of instruction prediction and instruction reading and the cavitation caused by self-flush, so as to realize a high-performance, high-frequency processor front-end.

[0119] In order to implement the above embodiment, the present invention further provides an electronic device, including:

[0120] at least one processor; and

[0121] a memory communicatively connected to the at least one processor; wherein,

[0122] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the aforementioned method.

[0123] In order to implement the above embodiment, the present invention further proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to enable the computer to execute the above method.

[0124] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0125] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0126] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0127] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0128] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0129] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0130] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0131] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for implementing a processor front-end instruction reading queue, characterized in that: in, The processor front end includes an instruction prediction component, an instruction reading queue, and an instruction reading component, and each pipeline stage of the instruction prediction component is connected to the instruction reading queue. The method includes: When the instruction prediction component is running, the instruction prediction component shakes hands with the instruction read queue to pass the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction component predicting the instruction fetch request to the instruction read queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction read queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block; Based on the instruction information of the instruction fetch request predicting the instruction, the instruction block is stored in a storage structure preset in the instruction fetch queue to wait for the instruction fetch component to fetch it; After the instruction reading component extracts the instruction block, the instruction fetch request prediction instruction in the instruction block is pre-decoded based on the instruction decoder in the instruction reading component, and the pre-decoded information is returned to the instruction reading queue, so that when the instruction decoder detects that the instruction fetch request prediction instruction is wrong according to the pre-decoded information, a self-flushing operation is performed to re-order the instruction fetch request prediction instructions corresponding to the instruction block in the instruction reading queue; The method further comprises: Based on the processing information of the processor front end in the instruction read queue, the instruction read queue is used as a processor front end performance counter for performance analysis of the processor front end; Among them, the processing information includes the number of re-fetched instructions for instruction fetch requests, the number of various re-fetched instruction requests for the instruction read queue, the number of prediction errors of instruction fetch request predictions, the number of prediction errors of various types of instruction fetch requests predictions, the number of prediction errors of each branch instruction prediction pipeline stage, and the number of prediction errors of each type of branch instruction in the instruction block.

2. The method according to claim 1, characterized in that in, The instruction block is a range of an instruction fetch request that the instruction prediction unit gives to the instruction read queue each time.

3. The method according to claim 1, characterized in that The instruction block division strategy includes: Indexed by the starting address, which is generated in the prediction pipeline of the pipeline stage. The starting address includes one of two cases: The starting address is the ending address of the previous instruction block; The start address is the target address of the re-fetched instruction from outside the instruction prediction unit; Among them, the instruction block contains at most two branch instructions, and the first one must be a conditional branch instruction; The end address of the instruction block satisfies one of the three conditions, where the three conditions are: The difference between the end address and the start address is the predicted width; The end address is the program counter PC of the third branch instruction within the predicted width range starting from the start address; The ending address is the PC of the next instruction of an unconditional jump branch, and the ending address is within the predicted width range starting from the starting address.

4. The method according to claim 1, characterized in that: The method further comprises: Based on the instruction fetch request prediction instruction of the instruction block, the pre-decoding information corresponding to the instruction fetch request prediction instruction, and the execution result of the instruction fetch request prediction instruction in the processor back end, the branch predictor is trained to obtain a trained branch predictor.

5. The method according to claim 1, characterized in that The storage structure is determined based on instruction information of the instruction block corresponding to the instruction fetch request prediction instruction stored in the instruction read queue, and is implemented through registers and / or register files and / or static random access memory.

6. The method according to claim 1, characterized in that in, All subsequent spare instruction fetch request prediction instructions after the instruction fetch request prediction instruction in the instruction block is mispredicted are cancelled.

7. The method according to claim 1, characterized in that in, The instruction life cycle of the instruction fetch request prediction instruction in the instruction block involves four pointers in the instruction read queue, namely the enqueue pointer, instruction fetch pointer, write back pointer and dequeue pointer. The enqueue pointer is at the front and the dequeue pointer is at the end. When the enqueue pointer starts to point to the next instruction block in the instruction read queue, the instruction fetch request prediction instruction in the instruction block enters the instruction life cycle. When the dequeue pointer points to the next instruction block in the instruction read queue, the instruction fetch request prediction instruction in the instruction block completes the instruction life cycle. The position of the prefetch pointer is between the enqueue pointer and the instruction fetch pointer.

8. The method according to claim 6, characterized in that The method further comprises: After the prefetch pointer reads the target address of the instruction block and sends a prefetch request to a preset instruction prefetcher, the instruction prefetcher completes the address translation of the target address and accesses the tag address storage body of the instruction cache corresponding to the instruction prefetcher. If the target address exists in the tag address storage body, the prefetch request is canceled. If the target address does not exist in the tag address storage body, an application is made to the prefetch queue item of the instruction prefetcher to allocate a prefetch request item, and a prefetch request is sent to the lower storage system of the instruction cache to prefetch the target instruction cache line corresponding to the prefetch request item to the lower storage system. The instruction prefetcher records the physical addresses of the prefetch requests that have been sent, and determines the uniqueness of all prefetch requests in the prefetch queue items according to the physical addresses of the prefetch requests.

9. A device for implementing a processor front-end instruction reading queue, characterized in that: in, The processor front end includes an instruction prediction component, an instruction reading queue, and an instruction reading component. Each pipeline stage of the instruction prediction component is connected to the instruction reading queue. The device includes: A transfer module, used for, when the instruction prediction unit is running, the instruction prediction unit shakes hands with the instruction reading queue to transfer the instruction fetch request prediction instruction obtained by the branch predictor in the instruction prediction unit predicting the instruction fetch request to the instruction reading queue in the form of an instruction block, wherein there is a prefetch pointer in the instruction reading queue to send a prefetch request to a preset instruction prefetcher after the prefetch pointer reads the target address of the instruction block; A storage module, used for storing the instruction block in a storage structure preset in the instruction read queue based on the instruction information of the instruction fetch request prediction instruction, so as to wait for the instruction read component to extract it; a reordering module, for pre-decoding the instruction fetch request prediction instruction in the instruction block based on the instruction decoder in the instruction fetching unit after the instruction fetching unit extracts the instruction block, and transmitting the pre-decoding information back to the instruction fetching queue, so as to perform a self-flushing operation and reorder the instruction fetch request prediction instruction corresponding to the instruction block in the instruction fetching queue when the instruction decoder detects that the instruction fetch request prediction instruction is wrong according to the pre-decoding information; The device also includes: Based on the processing information of the processor front end in the instruction read queue, the instruction read queue is used as a processor front end performance counter for performance analysis of the processor front end; Among them, the processing information includes the number of re-fetched instructions for instruction fetch requests, the number of various re-fetched instruction requests for the instruction read queue, the number of prediction errors of instruction fetch request predictions, the number of prediction errors of various types of instruction fetch requests predictions, the number of prediction errors of each branch instruction prediction pipeline stage, and the number of prediction errors of each type of branch instruction in the instruction block.

10. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

Images