A very low bit rate Turbo coding structure and design method

Abstract

The present application relates to a very low code rate Turbo coding structure and design method. The method comprises: in the Turbo coding structure, each component encoder uses more than three shift registers to construct a generator matrix of a codeword set; wherein the output of the transfer function corresponding to the generator matrix corresponds to the output of the component encoder, and each bit output is represented as a function of the state of the shift register; in the interleaving matrix design, an interleaver of the Mersenne Twister algorithm is used to generate the interleaving matrix; in the puncturing matrix design, according to the preset code rate, a fixed check bit output by each component encoder is selected, and a specific position is selected in the remaining check bits for puncturing and puncturing. The use of this method can flexibly implement encoding of different code rates so as to better provide services for the terminal.

Description

Technical Field

[0001] The present application relates to the field of satellite communication and navigation technology, and in particular to a very low bit rate Turbo coding structure and design method. Background Art

[0002] In order to meet the needs of mobile short message communication in the next generation satellite system, it is important to design a more flexible, reliable and simpler channel coding method to realize direct information transmission between user terminals and satellites. Among them, Turbo code has excellent performance under the condition of short code length and low code rate. However, the code rate used by the channel coding standard in the existing communication system is not suitable for the transmission of satellite communication signals under long-distance and low signal-to-noise ratio conditions. In addition, user terminals have different transmission requirements for short message signals. Designing a coding structure that can flexibly realize different code rates can better provide services for the terminals. Summary of the invention

[0003] Based on this, it is necessary to provide a very low bit rate Turbo coding structure and design method to address the above technical issues.

[0004] A very low bit rate Turbo coding structure and design method, the method comprising:

[0005] In the Turbo coding structure, each component encoder uses three shift registers to construct a generator matrix of the codeword set; wherein the output of the transfer function corresponding to the generator matrix corresponds to the output of the component encoder, and each bit output is represented as a function of the state of the shift register;

[0006] In the interleaving matrix design, an interleaver using the Mersenne Twister algorithm is used to generate the interleaving matrix;

[0007] In the puncturing matrix design, a fixed check bit output by each component encoder is selected according to a preset code rate, and a specific position is selected in the remaining check bits for puncturing and puncturing, wherein after puncturing, one component encoder outputs a check bit and the other component encoder outputs an information bit.

[0008] In one embodiment, it further includes: each component encoder uses more than three shift registers to construct a generator matrix of the codeword set, and the transfer function corresponding to the generator matrix is:

[0009]

[0010] Where G(D) represents the transfer function, D represents the state of the shift register, d(D) represents the feedback input related to the state of all registers, and d(D) = 1+D+D 3 , n0(D)=1+D2 +D 3 , n1(D)=1+D+D 2 +D 3 , n2(D)=1+D 3 , n3(D)=1+D+D 2 , n4(D)=1+D, n5(D)=1+D 2 , n6(D)=1, n7(D)=D+D 3 , n0, n1, .., n7 correspond to the 8 check bits output of each component encoder.

[0011] In one embodiment, the method further includes: generating a sequence S from 1 to N i ,i∈[1,N];

[0012] Generate a random number sequence R of length N using the Mersenne Twister algorithm i ,i∈[1,N];

[0013] The sequence S i With the random number sequence R i Interleaving sequence I i ,i∈[1,N].

[0014] In one embodiment, the preset code rate is 1 / 16 code rate; further comprising: selecting the first component encoder to output the check bit Y 10 ~Y 16 , the second component encoder outputs the check bit Y 20 ~Y 26 , the remaining 1 check bit is punctured, and the two component encoders alternately output the check bit [Y 17 ,Y 27 ], thereby achieving 1 / 16 Turbo coding.

[0015] In one embodiment, the pre-set code rate is a 1 / 12 code rate; it also includes: selecting fixed 5-bit check bits output by two component encoders, selecting specific positions in the remaining 3-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders alternately output the check bits, thereby obtaining 11-bit check bit output and 1-bit information bit output.

[0016] In one of the embodiments, the pre-set code rate is a 1 / 8 code rate; it also includes: selecting fixed 3-bit check bits output by two component encoders, selecting specific positions in the remaining 5-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders alternately output the check bits, thereby obtaining 7-bit check bit output and 1-bit information bit output.

[0017] In one of the embodiments, the pre-set code rate is a 1 / 6 code rate; it also includes: selecting fixed 2-bit check bits output by two component encoders, selecting specific positions in the remaining 6-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders alternately output the check bits, thereby obtaining a 5-bit check bit output and a 1-bit information bit output.

[0018] In one embodiment, the method further comprises: generating a codeword set {C ij}, represents the generator matrix of the jth codeword under the i-th puncturing condition;

[0019] According to the principle of maximizing the Hamming distance, the puncturing matrix is ​​selected as:

[0020]

[0021] [D h ,C]=max(D i )

[0022] Among them, D i is the Hamming distance under the i-th punctured matrix, D h and C is the maximum Hamming distance and the corresponding generator matrix.

[0023] The above-mentioned extremely low code rate Turbo coding structure and design method, by constructing a generator matrix of a codeword set, can realize Turbo codes of different code rates under the same encoder structure by simply adjusting the construction of the puncturing matrix, thereby being able to flexibly realize coding structures of different code rates to better provide services for the terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 1 is a flow chart of a very low bit rate Turbo coding structure and design method in one embodiment;

[0025] Figure 2 A schematic diagram of the structure of an extremely low turbo encoder in one embodiment;

[0026] Figure 3 A schematic diagram of the structure of a component encoder in one embodiment;

[0027] Figure 4 is a codeword generation matrix of a very low turbo encoder in one embodiment;

[0028] Figure 5 is an interleaving matrix with a sequence length of 222 bits in an embodiment;

[0029] Figure 6 is a puncturing matrix with a code rate of 1 / 16 in one embodiment;

[0030] Figure 7 The bit error rate performance of 1 / 16 code rate at different code lengths in one embodiment;

[0031] Figure 8 The bit error rate performance of 1 / 12 code rate in different code length information in one embodiment;

[0032] Fig. 9 The bit error rate performance of 1 / 8 code rate in different code lengths in one embodiment; wherein (a) is the bit error rate performance of 222 bits, and (b) is the bit error rate performance of 444 bits. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] In one embodiment, Figure 1 As shown in FIG. , a very low bit rate Turbo coding structure and design method are provided, such as Figure 2 As shown, the Turbo coding structure adopted by the present invention includes three parts: two component encoders, an inner interleaver, and puncturing and multiplexing. One information bit is input and the check bits generated by the two component encoders are output according to the code rate requirement. The component encoder part realizes the generation of the check bits, and the interleaver is used to reduce the correlation between the two component encoders as the input of the second component encoder. The method includes the following steps:

[0035] Step 102: In the Turbo coding structure, each component encoder uses three shift registers to construct a generator matrix of the codeword set.

[0036] The output of the transfer function corresponding to the generator matrix corresponds to the output of the component encoder, and each bit output is represented as a function of the state of the shift register.

[0037] Step 104: In the interleaving matrix design, a random interleaver generated by the Mersenne Twister algorithm is used to generate an interleaving matrix.

[0038] Step 106, in the design of the puncturing matrix, according to the preset code rate, select the fixed check bits output by each component encoder, and select specific positions in the remaining check bits for puncturing.

[0039] The two component encoders after puncturing output parity bits, which together with the direct output information bits, form Turbo coded information with a specific low code rate.

[0040] In the above-mentioned extremely low bit rate Turbo coding structure and design method, by constructing a generator matrix of a codeword set, Turbo codes with different bit rates can be realized under the same encoder structure simply by adjusting the construction of the puncturing matrix, thereby being able to flexibly realize coding structures with different bit rates to better provide services for the terminal.

[0041] In one embodiment, each component encoder uses three shift registers to construct a generator matrix of the codeword set, and the transfer function corresponding to the generator matrix is:

[0042]

[0043] Where G(D) represents the transfer function, D represents the state of the shift register, d(D) represents the feedback input related to the state of all registers, and d(D) = 1+D+D 3 , n0(D)=1+D 2 +D 3 , n1(D)=1+D+D 2 +D 3 , n2(D)=1+D 3 , n3(D)=1+D+D 2 , n4(D)=1+D, n5(D)=1+D 2 , n6(D)=1, n7(D)=D+D 3 , n0, n1, .., n7 correspond to the 8 check bits output of each component encoder.

[0044] In this embodiment, based on the framework of the Turbo coding structure in the 3GPP standard, a Turbo encoder is formed by using two parallel cascade convolutional code structures with 8 states, including: output information bits and check bits output by two parallel component encoders, wherein the input of the second component encoder is realized by interleaving the information bits; for each component encoder, three shift registers are used to construct a generator matrix of the codeword set. In this embodiment, if Figure 2 As shown, the input information bit is X k , the first component encoder corresponds to the output of 8-bit check bit Y 10 ,Y 11 ,...,Y 17 , the second component encoder outputs 8-bit check bit Y 20 ,Y 21 ,...,Y 27 (The structure is the same as the first component encoder, not shown in the figure.) Turbo coding with a very low bit rate of 1 / 16 can be achieved. At the same time, Turbo coding with bit rates of 1 / 12, 1 / 8 and 1 / 6 can be achieved by designing different puncturing matrices.

[0045] In one embodiment, a sequence S from 1 to N is generated. i ,i∈[1,N]; Generate a random number sequence R of length N through the Mersenne Twister algorithm i ,i∈[1,N]; the sequence S i With the random number sequence R i Interleaving sequence I i ,i∈[1,N].

[0046] In this embodiment, an interleaving matrix is ​​designed for information sequences with length N of 128, 256, 512 bits and 222, 444 bits, in order to reduce the correlation between the check bits of the two component encoders, thereby reducing the bit error rate in the iterative decoding process. The performance of the interleaver can be improved by increasing the length and randomness of the interleaver. Since the present invention is aimed at Turbo coding with extremely low code rate and short code length, an interleaver based on the Mersenne Twister random number generation algorithm is used to generate the interleaving matrix.

[0047] In one embodiment, for Turbo coding with a code rate of 1 / 16, it is necessary to output corresponding 15 check bits and 1 information bit. Therefore, the first component encoder is selected to output the check bit Y 10 ~Y 16 , the second component encoder outputs the check bit Y 20 ~Y 26 , the remaining 1 check bit is punctured, and the two component encoders alternately output the check bit [Y 17 ,Y 27 ], thereby achieving 1 / 16 Turbo coding.

[0048] In another embodiment, for Turbo coding with a code rate of 1 / 12, a fixed 5-bit check bit is selected from the outputs of the two component encoders, and specific positions are selected from the remaining 3 check bits for puncturing and deletion. After puncturing, the two component encoders alternately output the check bits, thereby obtaining an 11-bit check bit output and a 1-bit information bit output.

[0049] Specifically, the first component encoder can output 5 check bits Y 11 ,Y 12 ,Y 13 ,Y 14 ,Y 16 , in the second component encoder, 5 check bits Y are output 21 ,Y 22 ,Y 23 ,Y 24 ,Y 26Then, the remaining check bits in each component encoder are punctured and the output is alternating [Y 15 ,Y 25 ] Finally, the 11-bit check bits and information bits output by the two component encoders are output together to achieve 1 / 12 Turbo coding.

[0050] In another embodiment, for Turbo coding with a code rate of 1 / 8, fixed 3-bit check bits are selected from the outputs of two component encoders, and specific positions are selected from the remaining 5-bit check bits for puncturing and deletion. After puncturing, the two component encoders alternately output the check bits, thereby obtaining a 7-bit check bit output and a 1-bit information bit output.

[0051] Specifically, in the first component encoder, 3 check bits Y are output 11 ,Y 12 ,Y 15 , in the second component encoder, output 3 check bits Y 21 ,Y 22 ,Y 25 Then, the remaining check bits in each component encoder are punctured and the output is alternating [Y 13 ,Y 23 ] Finally, the 7-bit check bits output by the two component encoders are output together with the information bits to achieve 1 / 8 Turbo coding.

[0052] In one of the embodiments, for Turbo coding with a code rate of 1 / 6, a fixed 2-bit check bit is selected from the outputs of two component encoders, and specific positions are selected from the remaining 6-bit check bits for puncturing and deletion. After puncturing, the two component encoders alternately output the check bits, thereby obtaining a 5-bit check bit output and a 1-bit information bit output.

[0053] Specifically, in the first component encoder, the 2-bit check bit Y is output 10 ,Y 11 , in the second component encoder, output 2 check bits Y 20 ,Y 21 Then, the remaining check bits in each component encoder are punctured and the output is alternating [Y 12 ,Y 22 ] Finally, the 5-bit check bits output by the two component encoders are output together with the information bits to achieve 1 / 6 Turbo coding.

[0054] In another embodiment, since it is necessary to select one of the multiple check bits as output and delete the rest, it is necessary to design and optimize the puncturing matrix. The specific steps are as follows: ij}, represents the generator matrix of the jth codeword under the i-th puncturing condition; the puncturing matrix is ​​selected according to the principle of maximizing the Hamming distance as follows:

[0055]

[0056] [D h ,C]=max(D i )

[0057] Among them, D i is the Hamming distance under the i-th punctured matrix, D h and C is the maximum Hamming distance and the corresponding generator matrix.

[0058] For the above embodiments, please refer to Figure 2 and 3 , taking a 222-bit information sequence to implement 1 / 16 code rate Turbo coding as an example, the specific process is as follows:

[0059] First, all registers of the two component encoders are initially set to zero. One path of the input information sequence is directly output as information bits, and the other path is used to generate 15-bit check bits. For component encoder 1, the information bits are directly input, and then, according to Figure 4 The provided interleaving matrix outputs the interleaved information bits in order of rows and then columns as the input of the component encoder 2.

[0060] Then, according to Figure 5 The provided puncturing matrix punctures the output check bits. When the input information bits are odd, the output check bits Y 17 , when the input information bit is an even number, the output check bit Y 27 By multiplexing the parity bits and information bits output by the two component registers, 1 / 16 code rate Turbo coding is realized. Finally, the performance simulation analysis of this coding case is carried out in the AWGN channel.

[0061] Figure 6 and Figure 7 The bit error rate performance of information sequence lengths of 222 bits and 444 bits is given when the code rate is 1 / 16 and 1 / 12 respectively. It can be seen that at the same code rate, the longer the information sequence length, the longer the corresponding interleaving matrix length, so the bit error rate will be lower. For the same information sequence length, a lower code rate will have better bit error rate performance.

[0062] Figure 8The bit error rate performance of information sequence lengths of 128, 256 and 512 bits is given when the code rate is 1 / 8. As can be seen from the figure, when the signal-to-noise ratio is low, the bit error rate performance of information sequence lengths of 128 and 256 bits is similar, and both are better than the performance of 512 bits. However, as the signal-to-noise ratio increases, the performance differences of different lengths become increasingly obvious.

[0063] Fig. 9 The bit error rate performance of information sequence lengths of 222 bits and 444 bits when the code rate is 1 / 6 is given, and compared with the 1 / 6 code rate performance achievable by the Turbo structure of the CCSDS standard. The results show that compared with the Turbo coding performance under this standard, there is a certain gain in both sequence lengths. In addition, as the sequence length increases, the gain brought by the coding structure proposed in this invention is more obvious.

[0064] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0065] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0066] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A very low bit rate Turbo coding structure and design method, characterized in that: The method comprises: In the Turbo coding structure, each component encoder uses three shift registers to construct a generator matrix of the codeword set; wherein the output of the transfer function corresponding to the generator matrix corresponds to the output of each component encoder, and each bit output is represented as a function of the state of the shift register; In the design of the inner interleaving matrix, a random interleaver generated by the Mersenne Twister algorithm is used to generate the interleaving matrix; In the puncturing matrix design, according to the preset code rate, a fixed check bit output by each component encoder is selected, and a specific position is selected in the remaining check bits for puncturing and puncturing. The two component encoders after puncturing output the check bits, and the check bits are combined with the directly output information bits to form a specific low-code-rate Turbo coding information; Each component encoder uses three shift registers to construct a generator matrix of a codeword set, including: Each component encoder uses three shift registers to construct a generator matrix of the codeword set. The transfer function corresponding to the generator matrix is: Where G(D) represents the transfer function, D represents the state of the shift register, d(D) represents the feedback input related to the state of all registers, and d(D) = 1+D+D 3 , n0(D)=1+D 2 +D 3 , n1(D)=1+D+D 2 +D 3 , n2(D)=1+D 3 , n3(D)=1+D+D 2 , n4(D)=1+D, n5(D)=1+D 2 , n6(D)=1, n7(D)=D+D 3 , n0, n1, .., n7 correspond to the 8 check bits output of each component encoder; Select specific locations for puncturing, including: Generate codeword set {C ij }, represents the generator matrix of the jth codeword under the i-th puncturing condition; According to the principle of maximizing the Hamming distance, the puncturing matrix is ​​selected as: [D h ,C]=max(D i ) Among them, D i is the Hamming distance under the i-th punctured matrix, D h and C is the maximum Hamming distance and the corresponding generator matrix.

2. The method according to claim 1, characterized in that The interleaver using the Mersenne Twister algorithm generates an interleaving matrix, comprising: Generate a sequence S from 1 to N i ,i∈[1,N]; Generate a random number sequence R of length N using the Mersenne Twister algorithm i ,i∈[1,N]; The sequence S i With the random number sequence R i Interleaving sequence I i ,i∈[1,N].

3. The method according to claim 1, characterized in that The preset bit rate is 1 / 16 bit rate; According to the preset code rate, a fixed check bit output by each component encoder is selected, and puncturing is performed at a specific position of the output check bit, wherein the two component encoders after puncturing output the check bits, and the check bits are directly output to form a specific low code rate Turbo coding information, including: Select the first component encoder to output the check bit Y 10 ~Y 16 , the second component encoder outputs the check bit Y 20 ~Y 26 , the remaining 1 check bit is punctured, and the two component encoders alternately output the check bit [Y 17 ,Y 27 ], thereby achieving 1 / 16 Turbo coding.

4. The method according to claim 1, characterized in that: The preset bit rate is 1 / 12 bit rate; According to the preset code rate, a fixed check bit output by each component encoder is selected, and a specific position is selected in the remaining check bits for puncturing and puncturing, wherein the two component encoders after puncturing output the check bits, and the check bits are directly output to form a specific low code rate Turbo coding information, including: Select the fixed 5-bit check bits output by the two component encoders, select specific positions in the remaining 3-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders alternately output the check bits, thereby obtaining 11-bit check bit output and 1-bit information bit output.

5. The method according to claim 1, characterized in that The preset bit rate is 1 / 8 bit rate; According to the preset code rate, a fixed check bit output by each component encoder is selected, and a specific position is selected in the remaining check bits for puncturing and puncturing, wherein the two component encoders after puncturing output the check bits, and the check bits are directly output to form a specific low code rate Turbo coding information, including: Select the fixed 3-bit check bits output by the two component encoders, select specific positions in the remaining 5-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders output the check bits alternately, so as to obtain 7-bit check bit output and 1-bit information bit output.

6. The method according to claim 1, characterized in that The preset bit rate is 1 / 6 bit rate; According to the preset code rate, a fixed check bit output by each component encoder is selected, and a specific position is selected in the remaining check bits for puncturing and puncturing, wherein the two component encoders after puncturing output the check bits, and the check bits are directly output to form a specific low code rate Turbo coding information, including: Select the fixed 2-bit check bits output by the two component encoders, select specific positions in the remaining 6-bit check bits for puncturing and puncturing, and after puncturing, the two component encoders alternately output the check bits, thereby obtaining a 5-bit check bit output and a 1-bit information bit output.

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