Data transmission methods, devices and systems

Abstract

The present application provides a data transmission method, apparatus and system. In the solution provided by the present application, the sending end multiplexes a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a, any one of the b data streams includes multiple symbol groups, any one symbol group includes multiple symbols from different codewords, and any one symbol includes multiple bits; the sending end transmits the b data streams. Based on the solution provided by the present application, the sending end multiplexes based on symbol groups including symbols. Even if there are consecutive multiple-bit burst errors during the transmission process, after the receiving end demultiplexes based on symbol groups, the number of symbols affected by consecutive multiple-bit burst errors in the data stream multiplexed based on symbol groups is much smaller than the number of symbols affected by consecutive multiple-bit burst errors in the data stream multiplexed based on bits, improving the error correction performance and the reliability of the system.

Description

Technical Field

[0001] This application belongs to the field of communication technologies, and particularly relates to a data transmission method, apparatus, and system. Background Art

[0002] In the architecture of a high-speed interface of traditional Ethernet, there is a Physical Medium Attachment (PMA) layer. The PMA layer is used for data transmission rate conversion. The traditional PMA layer processes data in a bit multiplexing (Bit Mux) manner. Taking the sending end as an example, the PMA layer multiplexes m data streams obtained based on symbol interleaving into n data streams in units of bits, and the n data streams are output through the PMA channel. During the process of data transmission from the sending end to the receiving end, if there are burst errors in the transmitted data, for example, there are consecutive multiple-bit burst error data in a certain data stream among the n data streams, when the receiving end demultiplexes the n data streams, the above-mentioned consecutive multiple-bit burst error data will be demultiplexed into multiple symbols of multiple streams, resulting in a large spread of burst errors, increasing the difficulty of error correction at the receiving end and reducing the system reliability. Summary of the Invention

[0003] Embodiments of this application provide a data transmission method, apparatus, and system, which can reduce the difficulty of error correction and improve the system reliability.

[0004] In a first aspect, a data transmission method is provided, including: multiplexing a data streams based on symbol group multiplexing to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a, and any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; transmitting the b data streams. In the above method, through symbol group-based multiplexing at the sending end, it is possible to prevent consecutive multiple-bit burst error data generated during transmission from being demultiplexed into multiple symbols of multiple streams, which helps reduce the spread of burst errors, reduces the difficulty of error correction, and improves the system reliability.

[0005] In a possible implementation, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0006] In one possible implementation, the a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols. The length of the RS symbol is 10 bits.

[0007] In one possible implementation, 'a' equals 8, 'b' equals 1, the symbol group includes 2 symbols, and any 8 consecutive symbol groups in the 'b' data streams originate from the 8 data streams. This implementation belongs to 200GBASE-R technology, where the two symbols in a symbol group come from different codewords within the same codeword group.

[0008] In one possible implementation, before multiplexing *a* data streams based on symbol groups to obtain *b* data streams, the method further includes: delaying the transmission of the data stream output by the channel with odd sequence numbers in the *a* data streams by L symbols, where L equals 136*N+1, and N is an integer greater than or equal to 1. In this implementation, the order of codewords belonging to consecutive symbols output by the channel with any even sequence number in the *a* data streams before the delay is different from the order of codewords belonging to consecutive symbols output by the channel with any odd sequence number in the *a* data streams before the delay. After the delay, the order of codewords belonging to consecutive symbols output by any two channels in the *a* data streams is the same.

[0009] In one possible implementation, 'a' equals 16, 'b' equals 2, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the 'b' data streams come from the 8 data streams in the 'a' data streams. This implementation belongs to the 400GBASE-R technology, where the two symbols in a symbol group come from different codewords in the same codeword group.

[0010] In one possible implementation, before multiplexing *a* data streams based on symbol groups to obtain *b* data streams, the method further includes: delaying the transmission of the data stream output by the channel with odd sequence numbers in the *a* data streams by L symbols, where L equals 68*N+1, and N is an integer greater than or equal to 1. In this implementation, before the delay, the order of the codewords to which consecutive symbols belong in the channel output by any even sequence number in the *a* data streams belong is different from the order of the codewords to which consecutive symbols belong in the channel output by any odd sequence number in the *a* data streams belong. After the delay, the order of the codewords to which consecutive symbols belong in the output by any two channels in the *a* data streams belong is the same.

[0011] In one possible implementation, 'a' equals 16, 'b' equals 8, and the symbol group comprises 4 symbols. Any two consecutive symbol groups in any of the 'b' data streams originate from two data streams in the 'a' data streams. This implementation belongs to the 1.6TBASE-R technology, where the two symbols in a symbol group originate from different codewords within the same codeword group. The order of the codewords belonging to consecutive symbols output from any even-numbered sequence channel in the 'a' data streams is the same as the order of the codewords belonging to consecutive symbols output from any odd-numbered sequence channel in the 'a' data streams.

[0012] In one possible implementation, 'a' equals 32, 'b' equals 4, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the 'b' data streams originate from the 8 data streams in the 'a' data streams. The 8 data streams in the 'a' data streams include 4 data streams from a first codeword group and 4 data streams from a second codeword group. The first codeword group includes 2 codewords, and the second codeword group includes 2 codewords. The 2 codewords in the first codeword group are different from the 2 codewords in the second codeword group. This implementation belongs to 800GBASE-R technology.

[0013] In one possible implementation, before multiplexing *a* data streams based on symbol groups to obtain *b* data streams, the method further includes: delaying the transmission of the data stream output from the channel with each odd sequence number in the *a* data streams by L symbols, where L equals 2*N+1, and N is an integer greater than or equal to 0. In this implementation, before the delay, the order of codewords belonging to consecutive symbols from the same codeword group output from the channel with any even sequence number in the *a* data streams is different from the order of codewords belonging to consecutive symbols from the same codeword group output from the channel with any odd sequence number in the *a* data streams. After the delay, the order of codewords belonging to consecutive symbols from the same codeword group output from the channel with any even sequence number in the *a* data streams is the same as the order of codewords belonging to consecutive symbols from the same codeword group output from the channel with any odd sequence number in the *a* data streams.

[0014] In one possible implementation, the method further includes: encoding the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; interleaving the codewords included in the K codeword groups based on the symbols to obtain the a data stream.

[0015] In one possible implementation, the encoding includes feedforward error correction (FEC) encoding.

[0016] In a possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0017] In a possible implementation, the rate of any one of the b data streams is 200 gigabits per second (Gbps).

[0018] In a second aspect, a data transmission method is provided, including: receiving b data streams, where b is an integer greater than or equal to 1, and any one of the b data streams includes a plurality of symbol groups, any symbol group includes a plurality of symbols from different codewords, and any symbol includes a plurality of bits; demultiplexing the b data streams based on the symbol groups to obtain a data streams, where a is an integer greater than or equal to 2 and a > b.

[0019] In a possible implementation, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the plurality of symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0020] In a possible implementation, the a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

[0021] In a possible implementation, the length of the RS symbol is 10 bits.

[0022] In a third aspect, a data transmission device is provided, the device includes a processor and a transmitter coupled to the processor; the processor is used to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a, and any one of the b data streams includes a plurality of symbol groups, any symbol group includes a plurality of symbols from different codewords, and any symbol includes a plurality of bits; the transmitter is used to transmit the b data streams.

[0023] In a possible implementation, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the plurality of symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0024] In one possible implementation, the a data stream is based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

[0025] In one possible implementation, the RS symbol is 10 bits long.

[0026] In one possible implementation, a equals 8, b equals 1, the symbol group includes 2 symbols, and any 8 consecutive symbol groups included in the b data streams come from the 8 data streams respectively.

[0027] In one possible implementation, the processor is further configured to delay the transmission of the data stream output by the channel of each odd sequence number in the a data stream by L symbols, where L equals 136*N+1 and N is an integer greater than or equal to 1.

[0028] In one possible implementation, a equals 16, b equals 2, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the b data streams are respectively derived from the 8 data streams in the a data stream.

[0029] In one possible implementation, the processor further delays the transmission of the data stream output by the channel for each odd sequence number in the a data stream by L symbols, where L equals 68*N+1 and N is an integer greater than or equal to 1.

[0030] In one possible implementation, a equals 16, b equals 8, the symbol group includes 4 symbols, and any two consecutive symbol groups in any of the b data streams come from two data streams in the a data streams respectively.

[0031] In one possible implementation, the order of the codewords to which the consecutive symbols output by the channel of any even-numbered sequence number in the a data stream belong is the same as the order of the codewords to which the consecutive symbols output by the channel of any odd-numbered sequence number in the a data stream belong.

[0032] In one possible implementation, a equals 32, b equals 4, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the b data streams are respectively from the 8 data streams in the a data stream. The 8 data streams in the a data stream include 4 data streams from the first codeword group and 4 data streams from the second codeword group. The first codeword group includes 2 codewords, and the second codeword group includes 2 codewords. The 2 codewords in the first codeword group are different from the 2 codewords in the second codeword group.

[0033] In one possible implementation, the processor is further configured to delay the transmission of the data stream output by the channel of each odd sequence number in the a data stream by L symbols, where L equals 2*N+1 and N is an integer greater than or equal to 0.

[0034] In one possible implementation, the processor is further configured to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword group in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data stream.

[0035] In one possible implementation, the encoding includes feedforward error correction (FEC) encoding.

[0036] In one possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0037] In one possible implementation, the rate of any one of the b data streams is 200 Gbps.

[0038] Fourthly, a data receiving apparatus is provided, the apparatus comprising a processor and a receiver coupled to the processor: the receiver is configured to receive b data streams, where b is an integer greater than or equal to 1, any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; the processor is configured to demultiplex the b data streams based on the symbol groups to obtain a data streams, where a is an integer greater than or equal to 2 and a>b.

[0039] In one possible implementation, the a data stream includes a first data stream and a second data stream, the b data stream includes a third data stream, the plurality of symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0040] In one possible implementation, the a data stream is based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

[0041] In one possible implementation, the RS symbol is 10 bits long.

[0042] Fifthly, a data processing apparatus is provided, the apparatus comprising a unit for performing the method provided by the first aspect and any possible implementation thereof, or a unit for performing the method provided by the second aspect and any possible implementation thereof.

[0043] In a sixth aspect, a data processing apparatus is provided, the apparatus comprising a processor configured to implement the method provided by the first aspect and any possible implementation thereof, or the method provided by any possible implementation thereof.

[0044] In one possible implementation, the apparatus further includes a memory for storing computer execution instructions, wherein when the processor executes the computer execution instructions in the memory, the apparatus is triggered to implement the method provided by the first aspect and any possible implementation of the first aspect, or the method provided by any possible implementation of the second aspect.

[0045] In a seventh aspect, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the method provided by the first aspect and any possible implementation thereof, or the method provided by any possible implementation thereof.

[0046] Eighthly, a computer program product is provided, the computer program product storing instructions that, when the instructions are executed on a computer, cause the computer to perform the method provided by the first aspect and any possible implementation thereof, or the method provided by any possible implementation thereof.

[0047] Ninth aspect, a chip is provided, the chip may include processing circuitry or interface circuitry, which, when the chip is running, is used to implement the method provided by the first aspect and any possible implementation of the first aspect, or the method provided by any possible implementation of the second aspect and the second aspect.

[0048] A tenth aspect provides a system comprising a transmitter and a receiver, the transmitter comprising the apparatus provided in the third aspect or any possible implementation thereof, and the receiver comprising the apparatus provided in the fourth aspect or any possible implementation thereof. Wherein, both the transmitter and receiver comprise a main chip; or both the transmitter and receiver comprise a main chip, a clock and data recovery (CDR) chip, and an optical module; or both the transmitter and receiver comprise a main chip and an optical module; or the transmitter comprises a main chip, a CDR chip, and an optical module, and the receiver comprises a main chip and an optical module; or the transmitter comprises a main chip and an optical module, and the receiver comprises a main chip, a CDR chip, and an optical module.

[0049] Eleventhly, a data processing method is provided, the method comprising:

[0050] Perform first data processing on the received first data to obtain second data;

[0051] The second data is distributed based on data blocks to obtain a first data stream and a second data stream;

[0052] FEC encoding is performed on the first data stream to obtain the first codeword and the second codeword;

[0053] FEC encoding is performed on the second data stream to obtain the third and fourth codewords;

[0054] Based on symbols, the first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed to obtain a data streams, where a is an integer greater than 1.

[0055] In one possible implementation, after obtaining a data stream, the method further includes the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0056] In one possible implementation, the method provided by the first aspect or any possible implementation of the first aspect is implemented by the PMA.

[0057] In one possible implementation, the steps of obtaining the second data stream to obtaining the a data stream are implemented by the Physical Coding Sublayer (PCS).

[0058] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, where the first data is data obtained after 64B / 66B encoding. Here, B represents a bit block.

[0059] In one possible implementation, the first codeword and the second codeword come from the same encoder, and the third codeword and the fourth codeword come from the same encoder.

[0060] In one possible implementation, 'a' is 16, and in any one of the 'a' data streams, four consecutive symbols come from the first codeword, the second codeword, the third codeword, and the fourth codeword, respectively.

[0061] In one possible implementation, 'a' is 16, and the rate of any one of the 'a' data streams is 100Gbps.

[0062] In one possible implementation, the codewords in the codeword group are obtained by encoding the same encoder.

[0063] In one possible implementation, the method is implemented by a chip or optical module at the transmitting end.

[0064] In one possible implementation, the data block is 257 bits (b).

[0065] In the twelfth aspect, a data processing method is provided, which is the method obtained by reversing the method provided in the eleventh aspect. This method is implemented by a chip or optical module at the receiving end.

[0066] In a thirteenth aspect, a data transmission apparatus is provided, the apparatus including a processor, the processor being configured to:

[0067] Perform first data processing on the received first data to obtain second data;

[0068] The second data is distributed based on data blocks to obtain a first data stream and a second data stream;

[0069] FEC encoding is performed on the first data stream to obtain the first codeword and the second codeword;

[0070] FEC encoding is performed on the second data stream to obtain the third and fourth codewords;

[0071] Based on symbols, the first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed to obtain a data streams, where a is an integer greater than 1.

[0072] In one possible implementation, the processor is further configured to perform the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0073] In one possible implementation, the method provided by the first aspect or any possible implementation of the first aspect is implemented by the PMA included in the processor.

[0074] In one possible implementation, the steps of obtaining the second data stream and obtaining the a data stream are implemented by a physical coding sublayer (PCS) included in the processor.

[0075] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, where the first data is data obtained after 64B / 66B encoding. Here, B represents a bit block.

[0076] In one possible implementation, the first codeword and the second codeword come from the same encoder included in the processor, and the third codeword and the fourth codeword come from the same encoder included in the processor.

[0077] In one possible implementation, 'a' is 16, and in any one of the 'a' data streams, four consecutive symbols come from the first codeword, the second codeword, the third codeword, and the fourth codeword, respectively.

[0078] In one possible implementation, 'a' is 16, and the rate of any one of the 'a' data streams is 100Gbps.

[0079] In one possible implementation, the codewords included in the codeword group are obtained by encoding the same encoder included in the processor.

[0080] In one possible implementation, the processor is located in the chip or optical module at the transmitting end.

[0081] In one possible implementation, the data block is 257 bits (b).

[0082] In a fourteenth aspect, a data receiving apparatus is provided, comprising a processor configured to execute a method obtained by reversing the method provided in the eleventh aspect. The processor is located at a receiving end chip or optical module.

[0083] In a fifteenth aspect, a data processing method is provided, the method comprising:

[0084] The received first data is encoded to obtain the second data;

[0085] The second data is distributed based on data blocks to obtain a first data stream and a second data stream;

[0086] Perform first data processing and FEC encoding on the first data stream to obtain the first codeword and the second codeword;

[0087] The second data stream is processed by the first data processing and FEC encoding to obtain the third and fourth codewords;

[0088] Based on symbols, the first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed to obtain a data streams, where a is an integer greater than 1.

[0089] In one possible implementation, after obtaining a data stream, the method further includes the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0090] In one possible implementation, the method provided by the first aspect or any possible implementation of the first aspect is implemented by the PMA.

[0091] In one possible implementation, the steps of obtaining the second data stream to obtaining the a data stream are implemented by the Physical Coding Sublayer (PCS).

[0092] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the second data is the data obtained after 64B / 66B encoding. Here, B represents a bit block.

[0093] In one possible implementation, the first codeword and the second codeword come from the same encoder, and the third codeword and the fourth codeword come from the same encoder.

[0094] In one possible implementation, 'a' is 32, and in any one of the 'a' data streams, two consecutive symbols come from the same codeword group, where the codeword group includes the first codeword and the second codeword, or the codeword group includes the third codeword and the fourth codeword.

[0095] In one possible implementation, 'a' is 32, and the rate of any one of the 'a' data streams is 25 Gbps.

[0096] In one possible implementation, the codewords in the codeword group are obtained by encoding the same encoder.

[0097] In one possible implementation, the method is implemented by a chip or optical module at the transmitting end.

[0098] In one possible implementation, the data block is 66 bits (b).

[0099] In a sixteenth aspect, a data processing method is provided, which is the method obtained by reversing the method provided in the fifteenth aspect. This method is implemented by a chip or optical module at the receiving end.

[0100] In a seventeenth aspect, a data transmission apparatus is provided, the apparatus including a processor, the processor being configured to:

[0101] The received first data is encoded to obtain the second data;

[0102] The second data is distributed based on data blocks to obtain a first data stream and a second data stream;

[0103] Perform first data processing and FEC encoding on the first data stream to obtain the first codeword and the second codeword;

[0104] The second data stream is processed by the first data processing and FEC encoding to obtain the third and fourth codewords;

[0105] Based on symbols, the first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed to obtain a data streams, where a is an integer greater than 1.

[0106] In one possible implementation, the processor is further configured to perform the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0107] In one possible implementation, the method provided by the first aspect or any possible implementation of the first aspect is implemented by the PMA included in the processor.

[0108] In one possible implementation, the steps of obtaining the second data stream and obtaining the a data stream are implemented by a physical coding sublayer (PCS) included in the processor.

[0109] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the second data is the data obtained after 64B / 66B encoding. Here, B represents a bit block.

[0110] In one possible implementation, the first codeword and the second codeword come from the same encoder included in the processor, and the third codeword and the fourth codeword come from the same encoder.

[0111] In one possible implementation, 'a' is 32, and in any one of the 'a' data streams, two consecutive symbols come from the same codeword group, where the codeword group includes the first codeword and the second codeword, or the codeword group includes the third codeword and the fourth codeword.

[0112] In one possible implementation, 'a' is 32, and the rate of any one of the 'a' data streams is 25 Gbps.

[0113] In one possible implementation, the codewords included in the codeword group are obtained by encoding the same encoder included in the processor.

[0114] In one possible implementation, the processor is located on the chip or optical module at the transmitting end.

[0115] In one possible implementation, the data block is 66 bits (b).

[0116] Eighteenthly, a data receiving apparatus is provided, including a processor for executing a method obtained by reversing the method provided in the fifteenth aspect. The processor is located at a receiving end chip or optical module. Attached Figure Description

[0117] Figure 1(a) is a schematic diagram of data processing at the sending end.

[0118] Figure 1(b) is a schematic diagram of data processing at the receiving end.

[0119] Figure 2 This is a flowchart illustrating the data processing method provided in an embodiment of this application.

[0120] Figure 3(a) is a schematic diagram of interleaving and offsetting two codewords in a codeword group provided in an embodiment of this application.

[0121] Figure 3(b) is a schematic diagram of multiplexing the offset data stream in Figure 3(a) to obtain a data stream according to an embodiment of this application.

[0122] Figure 4(a) is a schematic diagram of interleaving and offsetting two codewords in a codeword group provided in an embodiment of this application.

[0123] Figure 4(b) is a schematic diagram of multiplexing the offset data stream in Figure 4(a) to obtain two data streams according to an embodiment of this application.

[0124] Figure 5(a) is a schematic diagram of interleaving and offsetting multiple codewords included in two codeword groups according to an embodiment of this application.

[0125] Figure 5(b) is a schematic diagram of multiplexing the offset data stream in Figure 5(a) to obtain 4 data streams according to an embodiment of this application.

[0126] Figure 6 This is a schematic diagram illustrating the reuse of four codewords in a codeword group, as provided in an embodiment of this application.

[0127] Figure 7 This is a flowchart illustrating another data processing method provided in an embodiment of this application.

[0128] Figure 8(a) is a schematic diagram of demultiplexing a multiplexed data stream provided in an embodiment of this application.

[0129] Figure 8(b) is a schematic diagram of offsetting the demultiplexed data stream in Figure 8(a) according to an embodiment of this application.

[0130] Figure 9(a) is a schematic diagram of demultiplexing two multiplexed data streams provided in an embodiment of this application.

[0131] Figure 9(b) is a schematic diagram of offsetting the demultiplexed data stream in Figure 9(a) according to an embodiment of this application.

[0132] Figure 10(a) is a schematic diagram of demultiplexing four multiplexed data streams provided in an embodiment of this application.

[0133] Figure 10(b) is a schematic diagram of offsetting the demultiplexed data stream in Figure 10(a) according to an embodiment of this application.

[0134] Figure 11 This is a schematic diagram illustrating the demultiplexing of eight multiplexed data streams, provided as an embodiment of this application.

[0135] Figure 12(a) is a schematic diagram of the structure of a hardware provided in an embodiment of this application.

[0136] Figure 12(b) is a schematic diagram of another hardware structure provided in an embodiment of this application.

[0137] Figure 13(a) is a schematic diagram of the data processing method provided in the embodiment of this application implemented by a chip.

[0138] Figure 13(b) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by a chip.

[0139] Figure 13(c) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by a chip.

[0140] Figure 14(a) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0141] Figure 14(b) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0142] Figure 14(c) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0143] Figure 14(d) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0144] Figure 14(e) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0145] Figure 14(f) is a schematic diagram of the data processing method provided in the embodiments of this application implemented by multiple chips.

[0146] Figure 15(a) is a schematic diagram of the structure of a data transmission device provided in an embodiment of this application.

[0147] Figure 15(b) is a schematic diagram of the structure of a data receiving device provided in an embodiment of this application.

[0148] Figure 16(a) is a schematic diagram of another data transmission device provided in an embodiment of this application.

[0149] Figure 16(b) is a schematic diagram of another data receiving device provided in an embodiment of this application.

[0150] Figure 17 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application.

[0151] Figure 18 This is a schematic diagram of the structure of a data processing system provided in an embodiment of this application. Detailed Implementation

[0152] To facilitate data processing or reduce costs, chips, units, or modules typically process multiple lower-rate data streams to obtain one or more higher-rate data streams. This data processing may include mapping, multiplexing, interleaving, or merging. These one or more higher-rate data streams can be transmitted via optical fiber or other media. Figure 1(a) illustrates a data processing method at the transmitting end. In Figure 1(a), the transmitting end employs a multiplexing data processing method, that is, multiplexing at the bit level. The transmitting end merges multiple lower-rate data streams into a single higher-rate data stream. In Figure 1(a), each cell represents 1 bit of data from a specific data stream at the transmitting end, and the XY marking in each cell indicates that X comes from data stream X, and Y represents the Y-th bit. Figure 1(a) illustrates this using n+1 bits in each data stream as an example, where n is an integer greater than or equal to 0. As shown in Figure 1(a), data stream 0, data stream 1, data stream 2, and data stream 3 are all low-rate data streams, for example, 25 gigabits per second (Gbps). The sending end reads the Y-th bit of data from each low-rate data stream in the order of data stream 0 -> data stream 1 -> data stream 2 -> data stream 3, and uses it as the 4 bits output sequentially in the acquired high-rate data stream (the muxed stream shown in Figure 1(a)). The sending end processes the data in a loop as described above to acquire 4*(n+1) bits of data in the muxed stream. The muxed stream in Figure 1(a) may experience burst errors during transmission, i.e., multiple consecutive bit errors. As shown in Figure 1(b), the muxed stream received by the receiver includes 10 bits of burst errors (the lines in Figure 1(b)), specifically bits 3.0, 0.1, 1.1, 2.1, 3.1, 0.2, 1.2, 2.2, 3.2, and 0.3, which experience burst errors during transmission. Based on the muxed stream containing these 10-bit burst errors, the receiver acquires four low-rate data streams, such as data stream 0', data stream 1', data stream 2', and data stream 3'.The aforementioned 10-bit burst error is propagated at the receiver to multiple symbols within data streams 0', 1', 2', and 3'. For example, 0.1, 0.2, and 0.3 belong to symbols within data stream 0', 1.1 and 1.2 to symbols within data stream 1', 2.1 and 2.2 to symbols within data stream 2', and 3.0, 3.1, and 3.2 to symbols within data stream 3'. The bit mux-based processing at the transmitter leads to a significant propagation of burst errors across multiple symbols in multiple data streams during transmission. Since feedforward error correction (FEC) codewords can only correct a limited number of symbol errors—for example, when using Reed-Solomon (RS) (544, 514) FEC codewords—a maximum of 15 symbol errors can be corrected. If the number of symbol errors caused by burst error data generated during transmission based on bit multiplexing exceeds the number of correctable symbol errors, such as more than 15 symbol errors, it will cause FEC codeword error correction processing to fail, reduce error correction performance, reduce the accuracy of subsequent data transmission, and thus reduce the reliability of the system.

[0153] Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of this application. Figure 2 The method shown is executed by a transmitting end, which can be a module or chip that acts as a transmitter. The module or chip can be located in a host or optical module. The host can be a router, switch, or server, etc.

[0154] 201, The sending end obtains the input data stream.

[0155] In the first possible implementation, the input data stream is a data stream obtained by interleaving M codeword groups based on symbols, where M is an integer greater than or equal to 1. Each codeword group includes multiple codewords. These codewords can be different codewords output by different encoders, or different codewords output successively by the same encoder. All symbols in any interleaved data stream come from one codeword group. Any two consecutive symbols in any interleaved data stream come from different codewords, i.e., two adjacent codewords come from different codewords within the same codeword group. In this embodiment, "adjacent" refers to bits or symbols that are adjacent in position and not separated by other codewords. The length of the symbol is multiple bits, for example, the length of the symbol can be an integer multiple of 10 bits, specifically 10 bits, 20 bits, etc., which will not be listed here. The symbol can be an RS symbol, in which case the length of the RS symbol is 10 bits. In this embodiment, "bit" can also be called a bit or bit segment, and this application does not limit this. Interleaving can be symbol-based multi-mix-one interleaving, symbol-based multi-mix-multi interleaving, or symbol-based single-mix-interleaving. Multiple-to-one interleaving means that multiple data streams are interleaved into a single data stream. Multiple-to-multiple interleaving means that multiple data streams are interleaved into multiple data streams. Single-to-multiple interleaving means that a single data stream remains a single data stream after interleaving. The changes in the data stream after interleaving compared to the data stream before interleaving include: a regular adjustment in the order of the smallest data units output, measured in symbols. For example, the first and second data units in the data stream before interleaving may be swapped in their transmission order to form the data stream after interleaving.

[0156] In the second possible implementation, the input data stream is the data stream obtained after interleaving and offsetting. The interleaving is the same as the symbol-based interleaving of M codeword groups in the first possible implementation, which will not be elaborated further here. The offset is an N-bit delay on one or more data streams from the same codeword group in the interleaved data stream, so that symbols at the same position in any two data streams from the same codeword group come from the same codeword. N is an integer greater than or equal to 1; for example, N bits can be one or more symbol lengths. From the perspective of channel sequence numbers, the specific operation of the offset can be to delay the transmission of data streams transmitted by channels with even sequence numbers in the multiple channels transmitting the input data stream by N bits, or to delay the transmission of data streams transmitted by channels with odd sequence numbers in the multiple channels transmitting the input data stream by N bits. From the perspective of codeword groups, if the input data flows through multiple channels and the data streams originate from the same codeword group, the specific operation of the offset can be to delay the transmission of one or more channels containing data streams with the same symbol order; if the input data flows through multiple channels and the data streams originate from different codeword groups, the specific operation of the offset can be to delay the transmission of one or more channels containing data streams with the same codeword group and the same symbol order, or the specific operation of the offset can be to delay the transmission of one or more channels containing data streams with the same symbol order from the same codeword group.

[0157] In the third possible implementation, the input data stream is a data stream obtained after encoding and interleaving. The encoding code can be Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Hamming code, low-density parity check (LDPC) code, polar code, convolutional code, turbo code, turboproduct code (TPC), staircase code, fire code, Reed Muller (RM) code, or oFEC code. When the encoding code is RS code, the resulting codewords include RS symbols, as detailed in the relevant description in the first possible implementation. The interleaving is based on symbols and involves interleaving M codeword groups as in the first possible implementation, and will not be elaborated further here.

[0158] In the fourth possible implementation, the input data stream is obtained after encoding, interleaving, and offsetting. The encoding method is the same as in the third possible implementation. The interleaving method is the symbol-based interleaving of M codeword groups, as in the first possible implementation. The offset method is the same as in the second possible implementation. These methods will not be elaborated upon further here.

[0159] 202. The sending end multiplexes the input data stream based on symbol groups, obtains the output data stream, and outputs it.

[0160] For example, any symbol group in the input data stream includes multiple symbols, and these symbols come from multiple codewords. The codewords from which the symbols within a symbol group originate are in the same order. For 200GBASE-R and 400GBASE-R, any symbol group in the input data stream includes two symbols, and these two symbols come from different codewords within the same codeword group. Symbols output through odd-numbered channels have the same codeword order, symbols output through even-numbered channels have the same codeword order, and symbols output through any odd-numbered channel have a different codeword order than those output through any even-numbered channel. For 800GBASE-R, any symbol group in the input data stream includes two symbols, and these two symbols come from different codewords within the same codeword group. The input data stream outputs symbols from the first codeword group through multiple channels and symbols from the second codeword group through multiple other channels. In the multiple channels outputting symbols from the first codeword group, the codewords from which the odd-numbered channels output symbols are in the same order. In the multiple channels outputting symbols from the first codeword group, the codewords from which the even-numbered channels output symbols are in the same order. In the multiple channels outputting symbols from the first codeword group, the codewords from which the odd-numbered channels output symbols are in a different order than those from any even-numbered channel. In the multiple channels outputting symbols from the second codeword group, the codewords from which the odd-numbered channels output symbols are in the same order. In the multiple channels outputting symbols from the second codeword group, the codewords from which the even-numbered channels output symbols are in the same order. In the multiple channels outputting symbols from the second codeword group, the codewords from which the odd-numbered channels output symbols are in a different order than those from any even-numbered channel. For 1.6TBASE-R, any group of symbols in the input data stream consists of 4 symbols, and the 4 symbols come from different codewords in the same codeword group. The symbols output from any two channels of the input data stream come from codewords with the same order.

[0161] For example, the sending end can obtain the output data stream by means of polling. The input data stream can be transmitted through multiple channels, such as output through a channels, and the output data stream can also be transmitted through one or more channels, such as b channels, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1, and b < a. The sum of the data rates output by the a channels is the same as the sum of the data rates output by the b channels. For example, for 200GBASE-R, 400GBASE-R or 800GBASE-R, the exact value of the data rate output by each of the a channels is 26.5625Gbps. Then the sum of the rates of 8 data streams of 26.5625Gbps is 212.5Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 212.5Gbps. Usually, the data rate output by each of the a channels is roughly estimated to be 25Gbps. Then the sum of the rates of 8 data streams of 25Gbps is 200Gbps. After multiplexing into 1 channel, the rate of the data output by this 1 channel is 200Gbps. For 1.6TBASE-R, 2 data streams in the data streams output by the a channels are merged into one data stream output by the b channels. The exact value of the data rate output by each of the a channels is 106.25Gbps. Then the sum of the rates of 2 data streams of 106.25Gbps is 212.5Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 212.5Gbps. Usually, the data rate output by each of the a channels is roughly estimated to be 100Gbps. Then the sum of the rates of 2 data streams of 100Gbps is 200Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 200. The above a channels or b channels can be logically divided logical channels or physical channels, such as physical channels corresponding to the pins of the chip. The sending end can obtain consecutive multiple symbols on each of the multiple channels for transmitting the input data stream based on the polling order, and map the consecutive multiple symbols obtained on each channel as a symbol group to one channel for transmitting the output data stream. Among them, any two adjacent symbol groups in the data stream transmitted through any one of the one or more channels of the output data stream come from different channels of the input data stream. When the sending end performs polling, each time the multiple channels of the input data stream are polled once, it is counted as one cycle, and in each cycle, the symbol groups at the same position in the data stream transmitted through each channel are polled.

[0162] For example, the polling order can satisfy any one of the following:

[0163] Poll the data stream transmitted through the channels with even serial numbers first, and then poll the data stream transmitted through the channels with odd serial numbers; or

[0164] First poll the data stream transmitted through channels with odd sequence numbers, then poll the data stream transmitted through channels with even sequence numbers; or

[0165] Poll the data stream transmitted through the channel in ascending or descending order of sequence number; or

[0166] The channels are divided into two parts according to their sequence numbers. The first and second parts contain the same number of channels. First, the data streams transmitted by the even-numbered channels in the first part and the odd-numbered channels in the second part are polled in a round-robin fashion. Then, the data streams transmitted by the odd-numbered channels in the first part and the even-numbered channels in the second part are polled in a round-robin fashion.

[0167] The channel is divided into two parts according to the sequence number. The first part and the second part contain the same number of channels. First, the data stream transmitted by the odd-numbered channels in the first part and the data stream transmitted by the even-numbered channels in the second part are polled. Then, the data stream transmitted by the even-numbered channels in the first part and the data stream transmitted by the odd-numbered channels in the second part are polled.

[0168] In the possible implementations of the above polling order, when polling the data streams transmitted through a portion of the channels in the first part and the portion of the channels in the second part, one can first poll the data streams transmitted through the portion of the channels in the first part, and then poll the data streams transmitted through the portion of the channels in the second part. Alternatively, when polling the data streams transmitted through the portion of the channels in the first part and the portion of the channels in the second part, one can first poll the data stream transmitted through one channel in the first part, then poll the data stream transmitted through one channel in the second part, continue polling the data stream transmitted through the other channel in the first part, and then poll the other channel in the second part, until both the data streams transmitted through the portion of the channels in the first part and the portion of the channels in the second part have been polled.

[0169] In the method provided in this application embodiment, the transmitting end performs multiplexing based on symbol groups including symbols. In this way, even if a burst error of multiple consecutive bits occurs in the output data stream during transmission, the receiving end will only affect a small number of symbols after performing demultiplexing based on symbol groups. That is, the number of symbols affected by burst errors of multiple consecutive bits in the data stream multiplexed based on symbol groups is much smaller than the number of symbols affected by burst errors of multiple consecutive bits in the data stream multiplexed based on bits, thereby improving error correction performance and system reliability.

[0170] Figures 3(a) and 3(b) illustrate an embodiment where the codeword group comprises two different codewords, the input data stream has 8 channels, and the output data stream has 1 channel. This embodiment can also be used for other scenarios where the ratio of the number of input data stream channels to the number of output data stream channels is 8:1, and will not be illustrated further here.

[0171] Figure 3(a) is a schematic diagram of interleaving and offsetting multiple codewords included in a codeword group. The codeword group in Figure 3(a) includes codeword A and codeword B, which come from different encoders. The smallest data unit included in codeword A and codeword B is a symbol. After symbol-based interleaving, codeword A and codeword B are output through 8 channels. This interleaving is a multi-mix multi-interleaving, meaning multiple codewords are interleaved to obtain multiple interleaved data streams. In Figure 3(a), the identifier Opq in each box indicates that the current symbol belongs to codeword O, and its transmission sequence number in the channel with sequence number p is q. In this embodiment, the data continuously output through the channels is the data stream. For all symbols included in the codewords in the codeword group, for example, codeword A and codeword B both include 544 symbols, any two adjacent symbols in any channel from lane 0 to lane 7 come from different codewords in the same codeword group, that is, any two consecutive symbols in any channel come from different codewords in the same codeword group. In this embodiment, adjacent reference positions are adjacent and there is no gap. For example, the two symbols A.1.0 and B.1.0 output through lane 1 originate from codewords A and B, respectively. On lane 1, A.1.0 and B.1.0 are adjacent without any gap; that is, A.1.0 and B.1.0 are adjacent. When data from codewords A and B is output through lane 1, these two consecutive symbols, A.1.0 and B.1.0, originate from codewords A and B, respectively. After encoding, codewords A and B each contain L1*544 symbols, where L1 is an integer greater than or equal to 1. The symbols in each codeword are interleaved and output through eight channels (lanes 0 to 7), with each channel outputting L1*136 symbols. Of these, L1*68 symbols come from codeword A, and L1*68 symbols come from codeword B. In lanes 0 to 7, the even-numbered channels output the symbols from different codewords in the codeword group in the same order, while the odd-numbered channels output the symbols from different codewords in the same order. The symbols output by the even-numbered channels are different from those output by the odd-numbered channels.For example, taking any two even-numbered channels as an example, the symbols included in lane 4 and lane 6 both come from codeword A and codeword B. After interleaving codeword A and codeword B, the symbols output through lane 4 can be represented as A.4.0->B.4.0->A.4.1->B.4.1->A.4.2->B.4.2->A.4.3->…->A.4.67->B.4.67. After interleaving codeword A and codeword B, the symbols output through lane 6 can be represented as A.6.0->B.6.0->A.6.1->B.6.1->A.6.2->B.6.2->A.6.3->…->A.6.67->B.6.67. The order of the symbols output through lane 4 and lane 6 after interleaving codeword A and codeword B is ABABAB. Taking any two channels with odd-numbered sequence numbers as an example, the symbols included in lane 1 and lane 3 both come from codeword A and codeword B. The symbols output through lane 1 after interleaving codeword A and codeword B can be represented as B.1.0->A.1.0->B.1.1->A.1.1->B.1.2->A.1.2->B.1.3->…->B.1.67->A.1.67. Similarly, the symbols output through lane 3 after interleaving codeword A and codeword B can be represented as B.3.0->A.3.0->B.3.1->A.3.1->B.3.2->A.3.2->B.3.3->…->B.3.67->A.3.67. The order of the symbols output through lane 1 and lane 3 after interleaving codeword A and codeword B is the BABABA sequence. This application uses a subset of symbols as examples for illustration, and will not provide examples of more symbols than those shown in the figure. Based on Figure 3(a) and the above content, the symbols output by the even-numbered sequence number channel and the odd-numbered sequence number channel come from the same codeword group, but the order of the symbols is different.

[0172] The transmitter can offset the interleaved data stream. For example, as shown in Figure 3(a), the data output from each of the four channels (lane 1, lane 3, lane 5, and lane 7) is delayed by an odd number of symbols, such as 137 symbols. When the RS symbol length is 10 bits, the data output from each of the four lanes (lane 1, lane 3, lane 5, and lane 7) is delayed by 10 bits. Alternatively, if the RS symbol length is 10 bits, the data output from each of the four lanes (lane 1, lane 3, lane 5, and lane 7) is delayed by 1370 bits. The transmitter can also delay the data output from channels with even sequence numbers, but this will not be illustrated further here. By delaying the data transmission by an odd number of symbols, it is possible not only to ensure that the output symbols in any two channels are in the same order, but also to increase the interleaving depth to enhance the error correction capability against burst errors. For example, if the transmission of each odd-numbered sequence number channel is delayed by 137 symbols, the original multiplexing of 2*RS symbols can be converted into multiplexing of 4*RS symbols. That is, the four symbols used to transmit the output data stream come from four different codewords, instead of four different codewords. Taking a codeword with 544 symbols encoded by the same encoder each time as an example, in the four consecutive symbols B.0.68, A.0.69, B.1.0, and A.1.0 in the muxed lane after the delay, A.1.0 and A.0.69 are obtained from two encoding outputs of the same encoder, and B.1.0 and B.0.68 are obtained from two encoding outputs of the same encoder. That is, the four symbols come from four different codewords. Taking a channel with an odd sequence number and a 137-symbol delay as an example, the boundary of the symbol identified by B.1.0 in lane 1 is aligned with the boundary of the symbol identified by B.0.68 in lane 0, and the boundary of the symbol identified by A.1.0 in lane 1 is aligned with the boundary of the symbol identified by A.0.69 in lane 0. Similarly, the boundary of the symbol identified by B.3.0 in lane 3 is aligned with the boundary of the symbol identified by B.6.68 in lane 6, and the boundary of the symbol identified by A.3.0 in lane 3 is aligned with the boundary of the symbol identified by A.6.69 in lane 6. Furthermore, the boundary of the symbol identified by B.5.0 in lane 5 is aligned with the boundary of the symbol identified by B.2.68 in lane 2, and the boundary of the symbol identified by A.5.0 in lane 5 is aligned with the boundary of the symbol identified by A.2.69 in lane 2.The boundary of the symbol identified by B.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by B.4.68 in lane 4, and the boundary of the symbol identified by A.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by A.4.69 in lane 4. The order of symbols output from any channel after the offset is BABABABA. The alignment of the remaining symbols will not be explained in detail here.

[0173] In other possible implementations, if the even-numbered channels in lanes 0 to 7 are delayed in transmission, the order of the symbols output by any channel in lanes 0 to 7 after the offset will be ABABAB. The rule for delaying the transmission of even-numbered channels is similar to that for delaying the transmission of odd-numbered channels, as detailed in Figure 3(a) above, and will not be repeated here.

[0174] Figure 3(b) is a schematic diagram of multiplexing the offset data stream in Figure 3(a) to obtain a single data stream. Figure 3(b) illustrates this using a symbol group containing two symbols as an example, where the two symbols in the symbol group come from codeword B and codeword A, respectively. In this embodiment, a symbol group containing two symbols can also be called a symbol pair, or two symbols from different codewords can be called a symbol pair. In any symbol group in Figure 3(b), the codewords from which the symbols come are ordered in the same order, which is BA. That is, taking a symbol group as an example, the symbols from codeword B are followed by symbols from codeword A in a consecutive sequence within the symbol group. During the process of polling lanes 0 to 7 to obtain symbol groups, the sending end polls each of the eight channels in ascending order of sequence number in each cycle to obtain the symbol groups at the same position in each channel. The eight symbol groups obtained in one cycle are continuously output to the muxedlane according to the sequence number of their respective channels. Each cycle follows the polling pattern described above for one cycle, until all symbol groups output by the codeword group have been polled. The following example of two cycles illustrates the specific polling method: Lane 0 includes symbol groups B.0.68 and A.0.69; Lane 1 includes symbol groups B.1.0 and A.1.0; Lane 2 includes symbol groups B.2.68 and A.2.69; Lane 3 includes symbol groups B.3.0 and A.3.0; Lane 4 includes symbol groups B.4.68 and A.4.69; Lane 5 includes symbol groups B.5.0 and A.5.0; Lane 6 includes symbol groups B.6.68 and A.6.69; and Lane 7 includes symbol groups B.7.0 and A.7.0. These are the symbol groups in the same position within the symbol groups of lanes 0 through 7. The above 8 symbol groups are output sequentially through the mixed lane according to the order of the lane numbers they output. For example, the symbols output in the mixed lane in sequence can be represented as: B.0.68->A.0.69->B.1.0->A.1.0->B.2.68->A.2.69->B.3.0->A.3.0->B.4.68->A.4.69->B.5.0->A.5.0->B.6.68->A.6.69->B.7.0->A.7.0.The symbol groups B.0.69 and A.0.70 in lane 0, B.1.1 and A.1.1 in lane 1, B.2.69 and A.2.70 in lane 2, B.3.1 and A.3.1 in lane 3, B.4.69 and A.4.70 in lane 4, B.5.1 and A.5.1 in lane 5, B.6.69 and A.6.70 in lane 6, and B.7.1 and A.7.1 in lane 7 are the symbol groups in the same position among the symbol groups output from lane 0 to lane 7. In a muxed lane, the eight consecutive symbols output after the symbol at position A.7.0 can be represented as follows: B.0.69->A.0.70->B.1.1->A.1.1->B.2.69->A.2.70->B.3.1->A.3.1->B.4.69->A.4.70->B.5.1->A.5.1->B.6.69->A.6.70->B.7.1->A.7.1. Any eight consecutive symbols in the muxed lane output come from eight different lanes.

[0175] Figures 4(a) and 4(b) illustrate an embodiment where the codeword group comprises two different codewords, the input data stream has 16 channels, and the output data stream has 2 channels. This embodiment can also be used for other scenarios where the ratio of the number of input data stream channels to the number of output data stream channels is 16:2, and will not be illustrated further here.

[0176] Figure 4(a) is a schematic diagram of interleaving and offsetting multiple codewords included in a codeword group. The meanings of the codeword group, symbols, and labels within each box in Figure 4(a) can be found in the relevant explanations in Figure 3(a). Any two adjacent symbols in any channel from lane 0 to lane 15 come from different codewords within the same codeword group; that is, any two consecutive symbols in any channel come from different codewords within the same codeword group. The meanings of adjacent and consecutive symbols in Figure 4(a) can be found in the relevant explanations in Figure 3(a). Codeword A and codeword B in Figure 4(a) contain L2*544 symbols, where L2 is an integer greater than or equal to 1. After interleaving, the symbols included in each codeword are output through the 16 channels from lane 0 to lane 15. Each channel outputs L2*68 symbols, of which L2*34 symbols come from codeword A and L2*34 symbols come from codeword B. This interleaving is a multi-mix multi-interleaving, meaning multiple codewords are interleaved to obtain multiple data streams. In lanes 0 to 15, the even-numbered channels output symbols from different codeword groups in the same order, while the odd-numbered channels output symbols from different codeword groups in the same order. The order of symbols output from even-numbered channels differs from that of odd-numbered channels. For example, after interleaving codeword A and codeword B, the symbols output through even-numbered channels are both in the order ABABAB. After interleaving codeword A and codeword B, the symbols output through odd-numbered channels are both in the order BABABA. This application uses a subset of symbols as examples for illustration; examples of more symbols than illustrated are not provided.

[0177] The transmitter can offset the interleaved stream, for example, by delaying the transmission of data output from each of the eight channels (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) by an odd number of symbol lengths, such as 69 symbols. If the RS symbol length is 10 bits, then the data output from each of the eight lanes (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) will be delayed by 10 bits. Alternatively, if the RS symbol length is 10 bits, then the data output from each of the eight lanes (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) will be delayed by 690 bits. By delaying the transmission of data by an odd number of symbols, it is possible not only to ensure that the output symbols in any two channels are in the same order, but also to increase the interleaving depth and enhance the error correction capability for burst errors. For example, delaying the transmission of each odd-numbered sequence number channel by 69 symbols can convert the multiplexing of 2*RS symbols into the multiplexing of 4*RS symbols. That is, the four symbols used to transmit the output data stream come from four different codewords, instead of four different codewords. Taking a codeword with 544 symbols encoded by the same encoder each time as an example, in the four consecutive symbols B.0.34, A.0.35, B.1.0, and A.1.0 in the muxed lane 0 after the delay, A.1.0 and A.0.35 are obtained from two encoding outputs of the same encoder, and B.1.0 and B.0.35 are obtained from two encoding outputs of the same encoder. That is, the four symbols come from four different codewords. Taking a channel with an odd sequence number and a 69-symbol delay as an example, the boundary of the symbol identified by B.1.0 in lane 1 is aligned with the boundary of the symbol identified by B.0.34 in lane 0, and the boundary of the symbol identified by A.1.0 in lane 1 is aligned with the boundary of the symbol identified by A.0.35 in lane 0. Similarly, the boundary of the symbol identified by B.3.0 in lane 3 is aligned with the boundary of the symbol identified by B.6.34 in lane 6, and the boundary of the symbol identified by A.3.0 in lane 3 is aligned with the boundary of the symbol identified by A.6.35 in lane 6. Finally, the boundary of the symbol identified by B.5.0 in lane 5 is aligned with the boundary of the symbol identified by B.2.34 in lane 2, and the boundary of the symbol identified by A.5.0 in lane 5 is aligned with the boundary of the symbol identified by A.2.35 in lane 2.The boundary of the symbol identified by B.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by B.12.34 in lane 12, and the boundary of the symbol identified by A.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by A.12.35 in lane 12. The boundary of the symbol identified by B.11.0 in lane 11 (delayed transmission) is aligned with the boundary of the symbol identified by B.4.34 in lane 4, and the boundary of the symbol identified by A.11.0 in lane 11 (delayed transmission) is aligned with the boundary of the symbol identified by A.4.35 in lane 4. The boundary of the symbol identified by B.13.0 in lane 13 (delayed transmission) is aligned with the boundary of the symbol identified by B.10.34 in lane 10, and the boundary of the symbol identified by A.13.0 in lane 13 (delayed transmission) is aligned with the boundary of the symbol identified by A.10.35 in lane 10. The boundary of the symbol identified by B.15.0 in lane 15 (delayed transmission) is aligned with the boundary of the symbol identified by B.8.34 in lane 8, and the boundary of the symbol identified by A.15.0 in lane 15 (delayed transmission) is aligned with the boundary of the symbol identified by A.8.35 in lane 8. The boundary of the symbol identified by B.9.0 in lane 9 (delayed transmission) is aligned with the boundary of the symbol identified by B.14.34 in lane 14, and the boundary of the symbol identified by A.9.0 in lane 9 (delayed transmission) is aligned with the boundary of the symbol identified by A.14.35 in lane 14. The order of the symbols output from any channel after the offset is BABABABA. The alignment of the remaining symbols will not be illustrated further here.

[0178] In other possible implementations, if the even-numbered channels in lanes 0 to 15 are delayed in transmission, the order of symbols output by any channel in lanes 0 to 15 after the offset will be ABABAB. The rule for delaying the transmission of even-numbered channels is similar to that for delaying the transmission of odd-numbered channels, as detailed in Figure 4(a) above, and will not be repeated here.

[0179] Figure 4(b) is a schematic diagram of multiplexing the offset data stream in Figure 4(a) to obtain two data streams. Figure 4(b) illustrates this using a symbol group containing two symbols, which come from codeword B and codeword A, respectively. In Figure 4(b), the symbols in any symbol group are ordered in the same order, namely BA, meaning that symbols from codeword B are followed by symbols from codeword A. During the process of polling lanes 0 to 15 to obtain symbol groups, the transmitter can divide lanes 0 to 15 into two parts: lanes 0 to 7 and lanes 8 to 15. For each part, each cycle polls each of the eight channels in ascending order of sequence number to obtain the symbol group at the same position in each channel. The eight symbol groups acquired in a cycle are sequentially output to a mixed lane according to their channel sequence numbers. For example, symbol groups from lane 0 to lane 7 are output through mixed lane 0, and symbol groups from lane 8 to lane 15 are output through mixed lane 1. Each cycle follows the same polling method until all symbol groups in that section have been polled.

[0180] The following example, using two cycles, illustrates the polling method: For the symbol groups output through lanes 0 to 7, the symbol groups in lane 0 (including B.0.34 and A.0.35), lane 1 (including B.1.0 and A.1.0), lane 2 (including B.2.34 and A.2.35), lane 3 (including B.3.0 and A.3.0), lane 4 (including B.4.34 and A.4.35), lane 5 (including B.5.0 and A.5.0), lane 6 (including B.6.34 and A.6.35), and lane 7 (including B.7.0 and A.7.0) are the symbol groups in the same position among the symbol groups output from lanes 0 to 7. The above 8 symbol groups are output sequentially through mixed lane 0 according to the order of the lane numbers they output. For example, the symbols output in mixed lane 0 in sequence can be represented as: B.0.34->A.0.35->B.1.0->A.1.0->B.2.34->A.2.35->B.3.0->A.3.0->B.4.34->A.4.35->B.5.0->A.5.0->B.6.34->A.6.35->B.7.0->A.7.0. The symbol groups B.0.35 and A.0.36 in lane 0, B.1.1 and A.1.1 in lane 1, B.2.35 and A.2.36 in lane 2, B.3.1 and A.3.1 in lane 3, B.4.35 and A.4.36 in lane 4, B.5.1 and A.5.1 in lane 5, B.6.35 and A.6.36 in lane 6, and B.7.1 and A.7.1 in lane 7 are the symbol groups in the same position among the symbol groups output from lane 0 to lane 7. In muxed lane 0, the eight consecutive symbol groups output after the symbol at position A.7.0 can be represented as follows: B.0.35->A.0.36->B.1.1->A.1.1->B.2.35->A.2.36->B.3.1->A.3.1->B.4.35->A.4.36->B.5.1->A.5.1->B.6.35->A.6.36->B.7.1->A.7.1. Any eight consecutive symbol groups output by muxed lane 0 come from eight different lanes, from lane 0 to lane 7.For the symbol groups output through lanes 8 to 15, the symbol groups B.8.34 and A.8.35 in lane 8, B.9.0 and A.9.0 in lane 9, B.10.34 and A.10.35 in lane 10, B.11.0 and A.11.0 in lane 11, B.12.34 and A.12.35 in lane 12, B.13.0 and A.13.0 in lane 13, B.14.34 and A.14.35 in lane 14, and B.15.0 and A.15.0 in lane 15 are the symbol groups in the same position among the symbol groups output through lanes 8 to 15. The above 8 symbol groups are output sequentially through mixed lane 1 according to the order of the lane numbers they output. For example, the symbols output in mixed lane 1 in sequence can be represented as: B.8.34->A.8.35->B.9.0->A.9.0->B.10.34->A.10.35->B.11.0->A.11.0->B.12.34->A.12.35->B.13.0->A.13.0->B.14.34->A.14.35->B.15.0->A.15.0. The symbol groups B.8.35 and A.8.36 in lane 8, B.9.1 and A.9.1 in lane 9, B.10.35 and A.10.36 in lane 10, B.11.1 and A.11.1 in lane 11, B.12.35 and A.12.36 in lane 12, B.13.1 and A.13.1 in lane 13, B.14.35 and A.14.36 in lane 14, and B.15.1 and A.15.1 in lane 15 are the symbol groups in the same position among the symbol groups output from lanes 8 to 15. In muxed lane 1, the eight consecutive symbol groups output after the symbol at position A.15.0 can be represented as: B.8.35->A.8.36->B.9.1->A.9.1->B.10.35->A.10.36->B.11.1->A.11.1->B.12.35->A.12.36->B.13.1->A.13.1->B.14.35->A.14.36->B.15.1->A.15.1. Any eight consecutive symbol groups output by muxed lane 1 come from eight different lanes.

[0181] Figures 5(a) and 5(b) illustrate an embodiment with two codeword groups, each containing two different codewords, 32 channels in the input data stream, and 4 channels in the output data stream. For scenarios with multiple codeword groups where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 8:1, the method described in this embodiment can be referenced, and will not be illustrated further here.

[0182] Figure 5(a) is a schematic diagram illustrating the interleaving and offset of multiple codewords within two codeword groups. In this embodiment, the first codeword group includes codeword A and codeword B, and the second codeword group includes codeword C and codeword D. After interleaving, codewords A and B in the first codeword group are output as multiple symbols through lanes 0 to 15. After interleaving, codewords C and D in the second codeword group are output as multiple symbols through lanes 16 to 31. Taking the first codeword group including codewords A and B as an example, the symbols output through even-numbered channels after interleaving are in the order of ABABAB, and the symbols output through odd-numbered channels are in the order of BABABA. The meanings of the labels in each box in Figure 5(a), the meanings of adjacent labels, and the meanings of consecutive labels can be found in the corresponding content of Figure 3(a). The specific method by which codewords A and B, after interleaving, output multiple symbols through lanes 0 to 15 can be found in the corresponding content of Figure 4(a). In Figure 5(a), codewords A and B contain L3*544 symbols, where L3 is an integer greater than or equal to 1. Each codeword in the first codeword group, after interleaving, is output through the 16 channels from lane 0 to lane 15. Each channel outputs L3*68 symbols, where L3*34 symbols come from codeword A and L3*34 symbols come from codeword B. In Figure 5(a), codewords C and D contain L4*544 symbols, where L4 is an integer greater than 0. Each codeword in the second codeword group consists of symbols that are interleaved and output through 16 channels from lane 16 to lane 31. Each channel outputs L4*68 symbols, of which L4*34 symbols come from codeword C and L4*34 symbols come from codeword D. The interleaving shown in Figure 5(a) is a multi-mix multi-interleaving, as detailed in the corresponding content of Figure 3(a). Taking codeword C and codeword D in the second codeword group as examples, after interleaving, the symbols output through even-numbered channels of codeword C and codeword D are in the order of CDCDCD, and the symbols output through odd-numbered channels of codeword C and codeword D are in the order of DCCDCDC.This application uses a partial representation of symbols obtained after interleaving multiple codewords in the second codeword group as an example for illustration, and will not exemplify the number of symbols exceeding those shown in the figure. For example, taking any two even-numbered channels, lane16 and lane28, from lane 16 to lane 31 as an example, the symbols included in lane 16 and lane28 both come from codeword C and codeword D included in the codeword group. The symbols output from lane 16 after interleaving codeword C and codeword D can be represented as: C.16.0->D.16.0->C.16.1->D.16.1->C.16.2->D.16.2->C.16.3->…D.16.33->C.16.33. Similarly, the symbols output from lane 28 after interleaving codeword C and codeword D can be represented as: C.28.0->D.28.0->C.28.1->D.28.1->C.28.2->D.28.2->C.28.3->…C.28.33->D.28.33. Taking any two channels with odd-numbered sequence numbers as an example, the symbols included in lanes 19 and 27 both come from codewords C and D within the codeword group. The symbols output through lane 19 after interleaving codeword C and codeword D can be represented as D.19.0->C.19.0->D.19.1->C.19.1->D.19.2->C.19.2->D.19.3->…->D.19.33->C.19.33. Similarly, the symbols output through lane 27 after interleaving codeword C and codeword D can be represented as D.27.0->C.27.0->D.27.1->C.27.1->D.27.2->C.27.2->D.27.3->…->D.27.33->C.27.33. For any codeword group output through 16 channels, the order of symbols output by odd-numbered channels differs from the order of symbols output by even-numbered channels.

[0183] The transmitter can offset the interleaved stream, for example, by delaying the transmission of symbols output from one or more channels from lane 0 to lane 31. The delay depth is an odd number of symbol lengths. For example, if the RS symbol length is 10 bits, then the data output from each lane in lanes 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, and 31 will be delayed by 10 bits. This will ensure that the boundaries of the symbols output from codeword A, codeword B, codeword C, and codeword D in lanes 0 to 31 are aligned, as shown by the dashed lines in Figure 5(a). By delaying data transmission by an odd number of symbols, it is possible to ensure that the order of symbols in any two channels output after interleaving symbols from the same codeword group is the same. Taking the channels with odd sequence numbers in lanes 0 to 15 delayed by one symbol as an example, the boundary of the symbol identified by B.1.0 in lane 1 is aligned with the boundary of the symbol identified by B.0.0 in lane 0, and the boundary of the symbol identified by A.1.0 in lane 1 is aligned with the boundary of the symbol identified by A.0.1 in lane 0. Similarly, the boundary of the symbol identified by B.3.0 in lane 3 is aligned with the boundary of the symbol identified by B.6.0 in lane 6, and the boundary of the symbol identified by A.3.0 in lane 3 is aligned with the boundary of the symbol identified by A.6.1 in lane 6. The boundary of the symbol identified by B.5.0 in lane 5 (delayed transmission) is aligned with the boundary of the symbol identified by B.2.0 in lane 2; the boundary of the symbol identified by A.5.0 in lane 5 (delayed transmission) is aligned with the boundary of the symbol identified by A.2.1 in lane 2. The boundary of the symbol identified by B.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by B.12.0 in lane 12; the boundary of the symbol identified by A.7.0 in lane 7 (delayed transmission) is aligned with the boundary of the symbol identified by A.12.1 in lane 12. The boundary of the symbol identified by B.11.0 in lane 11 (delayed transmission) is aligned with the boundary of the symbol identified by B.4.0 in lane 4; the boundary of the symbol identified by A.11.0 in lane 11 (delayed transmission) is aligned with the boundary of the symbol identified by A.4.1 in lane 4.The boundary of the symbol identified by B.13.0 in lane 13 (delayed transmission) is aligned with the boundary of the symbol identified by B.10.0 in lane 10, and the boundary of the symbol identified by A.13.0 in lane 13 (delayed transmission) is aligned with the boundary of the symbol identified by A.10.1 in lane 10. The boundary of the symbol identified by B.15.0 in lane 15 (delayed transmission) is aligned with the boundary of the symbol identified by B.8.0 in lane 8, and the boundary of the symbol identified by A.15.0 in lane 15 (delayed transmission) is aligned with the boundary of the symbol identified by A.8.1 in lane 8. The boundary of the symbol identified by B.9.0 in lane 9 (delayed transmission) is aligned with the boundary of the symbol identified by B.14.0 in lane 14, and the boundary of the symbol identified by A.9.0 in lane 9 (delayed transmission) is aligned with the boundary of the symbol identified by A.14.1 in lane 14. Taking the transmission of odd-numbered channels in lanes 16 to 31 with a one-symbol delay as an example, the boundary of the symbol identified by D.17.0 in lane 17, which is transmitted with a delay, is aligned with the boundary of the symbol identified by D.16.0 in lane 16; the boundary of the symbol identified by C.17.0 in lane 17, which is transmitted with a delay, is aligned with the boundary of the symbol identified by C.16.1 in lane 16. Similarly, the boundary of the symbol identified by D.19.0 in lane 19, which is transmitted with a delay, is aligned with the boundary of the symbol identified by D.22.0 in lane 22; and the boundary of the symbol identified by C.19.0 in lane 19, which is transmitted with a delay, is aligned with the boundary of the symbol identified by C.22.1 in lane 22. The boundary of the symbol identified by D.21.0 in lane 21 (delayed transmission) is aligned with the boundary of the symbol identified by D.18.0 in lane 18, and the boundary of the symbol identified by C.21.0 in lane 21 (delayed transmission) is aligned with the boundary of the symbol identified by C.18.1 in lane 18. The boundary of the symbol identified by D.23.0 in lane 23 (delayed transmission) is aligned with the boundary of the symbol identified by D.28.0 in lane 28, and the boundary of the symbol identified by C.23.0 in lane 23 (delayed transmission) is aligned with the boundary of the symbol identified by C.28.1 in lane 28. The boundary of the symbol identified by D.27.0 in lane 27 (delayed transmission) is aligned with the boundary of the symbol identified by D.20.0 in lane 20, and the boundary of the symbol identified by C.27.0 in lane 27 (delayed transmission) is aligned with the boundary of the symbol identified by C.20.1 in lane 20.The boundary of the symbol identified by D.29.0 in lane 29 (delayed transmission) is aligned with the boundary of the symbol identified by D.26.0 in lane 26, and the boundary of the symbol identified by C.29.0 in lane 29 (delayed transmission) is aligned with the boundary of the symbol identified by C.26.1 in lane 26. The boundary of the symbol identified by D.31.0 in lane 31 (delayed transmission) is aligned with the boundary of the symbol identified by D.24.0 in lane 24, and the boundary of the symbol identified by C.31.0 in lane 31 (delayed transmission) is aligned with the boundary of the symbol identified by C.24.1 in lane 24. The boundary of the symbol identified by D.25.0 in lane 25 (delayed transmission) is aligned with the boundary of the symbol identified by D.30.0 in lane 30, and the boundary of the symbol identified by C.25.0 in lane 25 (delayed transmission) is aligned with the boundary of the symbol identified by C.30.1 in lane 30. The order of symbols output from any channel in lane 16 to lane 31 after offset is the same as the order of DCDCDC.

[0184] Figure 5(b) is a schematic diagram of multiplexing the offset data stream in Figure 5(a) to obtain four data streams. The offset data streams output from lanes 0 to 31 in Figure 5(b) include symbols from the first codeword group output through lanes 0 to 15 and symbols from the second codeword group output through lanes 16 to 31. The four data streams obtained after multiplexing at the transmitting end are output through mixed lane 0, mixed lane 1, mixed lane 2, and mixed lane 3, respectively. The multiplexing method based on the multiplexed data streams output from any of the above mixed lanes 0, mixed lane 1, mixed lane 2, and mixed lane 3 is the same. The method for obtaining the data stream output through mixed lane 1 will be explained below as an example. The transmitting end polls the symbol groups output by four channels in lanes 0 to 15 and four channels in lanes 16 to 31 to obtain the data stream output through any of the mixed lanes. Taking the data stream output by mixed lane 1 as an example, the polling method for two cycles includes: obtaining the symbol groups output by the above eight channels in the order of lane 4->lane 20->lane 5->lane 21->lane 6->lane 22->lane 7->lane 23. The symbol groups in lane 4 (including B.4.0 and A.4.1), lane 20 (including D.20.0 and C.20.1), lane 5 (including B.5.0 and A.5.0), lane 21 (including D.21.0 and C.21.0), lane 6 (including B.6.0 and A.6.1), lane 22 (including D.22.0 and C.22.1), lane 7 (including B.7.0 and A.7.0), and lane 23 (including D.23.0 and C.23.0) are the same symbol groups in the same position among the eight channels selected above.The above 8 symbol groups are first output through mixed lane 1 in the order of lane 4->lane20->lane 5->lane 21->lane 6->lane 22->lane 7->lane 23 (the order of the lanes to which the 8 symbol groups output by mixed lane 1 in the first cycle is shown in Figure 5(b)). For example, the 16 symbols output in mixed lane 1 from the above 8 channels can be represented as: B.4.0->A.4.1->D.20.0->C.20.1->B.5.0->A.5.0->D.21.0->C.21.0->B.6.0->A.6.1->D.22.0->C.22.1->B.7.0->A.7.0->D.23.0->C.23.0. The symbol groups B.4.1 and A.4.2 in lane 4, D.20.1 and C.20.2 in lane 20, B.5.1 and A.5.1 in lane 5, D.21.1 and C.21.1 in lane 21, B.6.1 and A.6.2 in lane 6, D.22.1 and C.22.2 in lane 22, B.7.1 and A.7.1 in lane 7, and D.23.1 and C.23.1 in lane 23 are another symbol group in the same position among the eight channels selected above. In Muxed lane 1, after symbol C.23.1, the output sequence consists of 16 symbols from the 8 consecutive symbol groups acquired in the second cycle and located at the same position. Specifically, this can be represented as: B.4.1->A.4.2->D.20.1->C.20.2->B.5.1->A.5.1->D.21.1->C.21.1->B.6.1->A.6.2->D.22.1->C.22.2->B.7.1->A.7.1->D.23.1->C.23.1. Any 8 consecutive symbol groups output by Muxed lane 1 come from 8 different lanes: lane 4, lane 20, lane 5, lane 21, lane 6, lane 22, lane 7, and lane 23. For the multiplexing methods of symbols output by other muxed lanes, please refer to the multiplexing methods of symbols output by muxed 1, which will not be repeated here.Due to the offset, the data streams from the same codeword group have the same symbol order when outputting symbols. Based on the symbol group, the symbols output from any 4 channels from the first codeword group and the symbols output from any channel from the second codeword group are multiplexed to obtain the symbols output from any muxed lane channel. In this way, the interval between the symbols output from any codeword in the muxed lane channel is 3. For example, the symbols output from any muxed lane channel are ordered in the order of BADCBADC.

[0185] In other possible implementations, if the even-numbered channels in lanes 0 to 15 are delayed in transmission, the output symbols of any channel in lanes 0 to 15 after the offset will be in the order of ABABAB, and the output symbols of any channel in lanes 16 to 31 after the offset will be in the order of CDCDCD. The pattern of delaying the transmission of even-numbered channels is similar to that of delaying the transmission of odd-numbered channels, as detailed in Figure 5(a). After delaying the transmission of even-numbered channels, the output symbols of any mixed lane will be in the order of ABCDABCD. The specific method of multiplexing can be found in Figure 5(b).

[0186] Figure 6 This example illustrates a codeword group comprising four distinct codewords, with 16 channels in the input data stream and 8 channels in the output data stream. For other scenarios involving a codeword group with four codewords, where the ratio of input data stream channels to output data stream channels is 2:1, the method described in this example can be referenced, and will not be elaborated upon further here. Figure 6 For the meanings of adjacent, consecutive, symbol group, symbol, and codeword group, please refer to the corresponding content in Figure 3(a). Figure 6 The symbol group in this application includes four symbols, and these four symbols come from different codewords. The symbol group comprising four symbols in this embodiment can also be called a symbol quartet, or four symbols from different codewords can be called a symbol quartet. The multiplexing of a symbol group comprising four symbols can also be called RS symbol quartet multiplexing. Figure 6Lanes 0 through 15 output the interleaved data stream of codewords A, B, C, and D. The symbols output from lanes 0 through 15 are ordered in the sequence ABCDABCD. Each symbol group consists of four symbols from different codewords. The order of the codewords from which the symbols in any symbol group originate can be expressed as ABCD. The transmitter multiplexes the interleaved symbols output from lanes 0 through 15 based on the symbol groups to obtain the data stream output through mixed lanes 0 through 7. That is, the data stream obtained after multiplexing any two lanes from lanes 0 to 15 is output through a single mixed lane. Figure 6Taking the multiplexing of symbols output from an odd-numbered channel and symbols output from an even-numbered channel to obtain a mixed lane as an example, since the symbols in any lane are ordered in the sequence ABCDABCD, any two lanes can be selected, such as symbols output from one odd-numbered channel and symbols output from another odd-numbered channel, or symbols output from one even-numbered channel and symbols output from another even-numbered channel. The following explanation uses the example of obtaining the symbols output from mixed lane 4 by multiplexing symbols output from lane 8 and lane 9. The symbol group A.8.0, B.8.0, C.8.0, and D.8.0 in lane 8 is in the same position as the symbol group A.9.0, B.9.0, C.9.0, and D.9.0 in lane 9. The transmitter acquires these two symbol groups in the first cycle and outputs them to the mixed lane 4 in the order of lane8->lane9, which can be represented as: A.8.0->B.8.0->C.8.0->D.8.0->A.9.0->B.9.0->C.9.0->D.9.0. The symbol group A.8.1, B.8.1, C.8.1, and D.8.1 in lane 8 and the symbol group A.9.1, B.9.1, C.9.1, and D.9.1 in lane 9 are in the same position. The transmitter acquires these two symbol groups in the second cycle and, after outputting symbol D.9.0 from the first cycle, outputs them to the mixed lane 4 in the order of lane 8 -> lane 9, specifically: A.8.1 -> B.8.1 -> C.8.1 -> D.8.1 -> A.9.1 -> B.9.1 -> C.9.1 -> D.9.1. Following this polling order, each cycle polls the symbol groups in the same position in the two lanes and passes them sequentially through the mixed lane. This polling continues for multiple cycles until all symbols in the output codeword group are included. Two consecutive symbol groups output from any mixed lane originate from different lanes. The codewords to which the symbols output by any muxed lane belong are ordered in the sequence ABCDABCD.

[0187] Figure 7 This is a flowchart illustrating another data processing method provided in an embodiment of this application. Figure 7 The method shown is executed by a receiving end, which can be a module or chip acting as a transmitter. This module or chip can be located in a host computer or optical module. In this embodiment, the data processing performed by the receiving end can be... Figure 2 And the inverse process of data processing performed by the sending end in related embodiments.

[0188] 701, The receiving end acquires the input data stream.

[0189] For example, the input data stream acquired by the receiving end is the output data stream acquired by the sending end. The input data stream acquired by the receiving end can be the data stream output by the sending end through b channels, where b is an integer greater than or equal to 1. The receiving end can also use the data stream transmitted through b channels as its input data stream. For example, the input data stream acquired by the receiving end can be the data stream transmitted through the mixed lane in Figure 3(b), the data stream transmitted through mixed lane 0 and mixed lane 1 in Figure 4(b), or the data stream transmitted through mixed lane 0 to mixed lane 3 in Figure 5(b). Figure 6 The data stream transmitted in muxed lanes 0 to 7. For the specific meanings of symbols, symbol groups, codewords, and codeword groups in the input data stream acquired by the receiving end, please refer to [link to relevant documentation]. Figures 2-6 The relevant content in the related embodiments will not be repeated here.

[0190] 702, the receiving end demultiplexes the input data stream based on symbol groups to obtain the output data stream.

[0191] For example, the symbol group on which the receiver demultiplexes is based has the same meaning as the symbol group on which the transmitter multiplexes. See [link to documentation] for details. Figures 2-6 The relevant content in the related embodiments will not be repeated here. The output data stream acquired by the receiving end can be output through 'a' channels, where 'a' is an integer greater than or equal to 2, and 'a>b'. The symbol group includes multiple symbols, and the data included in the multiple symbols comes from different codewords of the sending end. The output data stream acquired by the receiving end is used to obtain codewords that are the same as those of the sending end. Specifically, the receiving end deinterleaves the output data stream to obtain codewords that are the same as those of the sending end, or the receiving end offsets and deinterleaves the output data stream to obtain codewords that are the same as those of the sending end. The above deinterleaving process is the reverse process of the interleaving process of the sending end. Both deinterleaving and interleaving at the sending end are symbol-level, and will not be repeated here. After acquiring codewords that are the same as those of the sending end, the receiving end can further decode the codewords. The specific decoding code type is the same as the encoding code type used by the sending end, and will not be repeated here.

[0192] For example, for 200GBASE-R and 400GBASE-R, the symbols in the data stream transmitted through the same channel are from different codewords in the same codeword group, and adjacent symbols come from different codewords; the symbols from different codewords within the symbol group are ordered in the same order, and the number of symbols in the symbol group is the same as the number of codewords, for example, a symbol group includes 2 symbols. For 800GBASE-R, the symbols in the data stream transmitted through the same channel are from different codewords in two codeword groups, and adjacent symbols come from different codewords; adjacent symbol groups within the data stream transmitted through the same channel come from different codeword groups, and for symbol groups from the same codeword group, the symbols from different codewords within that symbol group are ordered in the same order, for example, a symbol group includes 2 symbols. For 1.6TGBASE-R, the input data stream transmitted through the same channel includes symbols from different codewords within the same codeword group, and adjacent symbols come from different codewords; the symbols from different codewords within the symbol group of the input data stream transmitted through the same channel have the same order, and the number of symbols in the symbol group is the same as the number of codewords, for example, a symbol group includes 4 symbols. The meanings of "continuous" and "adjacent" in this embodiment can be found in [reference needed]. Figure 2 The corresponding content in the corresponding embodiments.

[0193] Taking one of the b channels used by the receiving end to acquire the input data stream as an example, the receiving end sequentially acquires a1 symbol groups from the data stream output from this channel and distributes them to the a1 channels of the b channels used to acquire the output data stream, where a1 is an integer less than or equal to a. After completing the previous round of distribution, the receiving end acquires a2 symbol groups following the aforementioned a1 symbol groups from the data stream output from this channel and distributes them to the aforementioned a1 channels, where a2 has the same value as a1. For all channels in the b channels, the distribution principle for each channel is the same as that for the single channel mentioned above, and will not be repeated here.

[0194] Optionally, the receiving end can perform an offset operation on the *a* data streams obtained after demultiplexing to restore the same *a* data streams obtained after interleaving at the sending end. The specific method of the offset operation at the receiving end can be found in the offset operation method used at the sending end, i.e., delayed transmission. The difference between the offset operation at the receiving end and the offset operation at the sending end is that the channel in which the data offset at the receiving end is located is different from the channel in which the data offset at the sending end is located. For example, if the sending end delays the transmission of data transmitted through channels with odd sequence numbers by N bits, where N is an integer greater than or equal to 1, then the receiving end delays the transmission of data transmitted through channels with even sequence numbers by N bits. Conversely, if the sending end delays the transmission of data transmitted through channels with even sequence numbers by N bits, then the receiving end delays the transmission of data transmitted through channels with odd sequence numbers by N bits.

[0195] In the method provided in this application embodiment, the transmitting end performs multiplexing based on symbol groups including symbols. In this way, even if a burst error of multiple consecutive bits occurs in the output data stream during transmission, the receiving end will only affect a small number of symbols after performing demultiplexing based on symbol groups. That is, the number of symbols affected by burst errors of multiple consecutive bits in the data stream multiplexed based on symbol groups is much smaller than the number of symbols affected by burst errors of multiple consecutive bits in the data stream multiplexed based on bits, thereby improving error correction performance and system reliability.

[0196] Figures 8(a) and 8(b) illustrate an embodiment where a codeword group comprises two different codewords, and the symbols of one codeword group are demultiplexed, with one channel in the input data stream and eight channels in the output data stream. This method can also be used for other scenarios where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 1:8, and will not be illustrated further here. The receiver in Figures 8(a) and 8(b) can be a host or chip based on 200GBASE-R.

[0197] The input data stream in Figure 8(a) is the output data stream in Figure 3(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 8(a) can be found in the corresponding content of Figures 3(b) and 3(a). In this embodiment, the meanings of consecutive and adjacent are the same as... Figure 2The corresponding content in the corresponding embodiments is the same, and will not be repeated here. The symbols in Figure 8(a) come from the codeword group including codeword A and codeword B. The receiver retrieves eight consecutive symbol groups from the mixed lane, in units of two-symbol groups, and outputs them sequentially to lanes 0 through 7. For example, the symbol group containing B.0.68 and A.0.69 is output through lane 0, the symbol group containing B.1.0 and A.1.0 is output through lane 1, the symbol group containing B.2.68 and A.2.69 is output through lane 2, the symbol group containing B.3.0 and A.3.0 is output through lane 3, the symbol group containing B.4.68 and A.4.69 is output through lane 4, the symbol group containing B.5.0 and A.5.0 is output through lane 5, the symbol group containing B.6.68 and A.6.69 is output through lane 6, and the symbol group containing B.7.0 and A.7.0 is output through lane 7. After demultiplexing the aforementioned 8 symbol groups, the receiving end continues to obtain 8 consecutive symbol groups from the muxed lane, including the symbol groups B.7.0 and A.7.0, and outputs them sequentially to lanes 0 to 7. This process of outputting 8 consecutive symbol groups sequentially to lanes 0 to 7 continues until all symbols from codeword A and codeword B output from the muxed lane have been demultiplexed to lanes 0 to 7.

[0198] The receiving end delays the data stream output from the even-numbered sequence number channel in Figure 8(a) by 137 symbols, as shown in Figure 8(b). After delaying the transmission of lanes 0, 2, 4, and 6 in lanes 0 to 7 by 137 symbols, the symbols B.0.68 in lane 0, A.1.68 in lane 1, B.2.68 in lane 2, A.3.68 in lane 3, B.4.68 in lane 4, A.5.68 in lane 5, B.6.68 in lane 6, and A.7.68 in lane 7 are symbols in the same position in lanes 0 to 7, that is, the symbol boundaries of the above 8 symbols are aligned. The following symbol groups are located in the same positions within lanes 0 through 7: lane 0 includes B.0.68 and A.0.69; lane 1 includes B.1.69 and A.1.68; lane 2 includes B.2.68 and A.2.69; lane 3 includes B.3.69 and A.3.68; lane 4 includes B.4.68 and A.4.69; lane 5 includes B.5.69 and A.5.68; lane 6 includes B.6.68 and A.6.69; and lane 7 includes B.7.69 and A.7.68. In Figure 8(b), the dashed boxes represent the symbols received by the receiver from codeword A and codeword B. Specifically, after the receiver has acquired L1*544 symbols starting from A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, and B.7.0, where L1 is an integer greater than or equal to 1, as shown in the order of the symbols in the solid and dashed boxes in Figure 8(b), the receiver can perform deinterleaving and decoding. Through delayed transmission, symbols at the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. Through this delayed transmission, the receiver reconstructs the same symbol order as the transmitter, enabling the subsequent decoder to complete the decoding operation.

[0199] Figures 9(a) and 9(b) illustrate an embodiment where a codeword group comprises two different codewords, and the symbols of one codeword group are demultiplexed. The number of input data stream channels is 2, and the number of output data stream channels is 16. This method can also be used for other scenarios where the ratio of the number of input data stream channels to the number of output data stream channels is 2:16, and will not be illustrated further here. The receiving end in Figures 9(a) and 9(b) can be a host or chip based on 400GBASE-R.

[0200] The input data stream in Figure 9(a) is the output data stream in Figure 4(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 9(a) can be found in the corresponding content of Figures 4(b) and 4(a). In this embodiment, the meanings of consecutive and adjacent are the same as... Figure 2The corresponding content in the corresponding embodiments is the same, and will not be repeated here. The symbols in Figure 9(a) come from codeword groups including codeword A and codeword B. The receiving end obtains eight consecutive symbol groups, each consisting of two symbols, from both mixed lane 0 and mixed lane 1, and outputs them sequentially to lanes 0 to 15. Specifically, the receiving end obtains eight consecutive symbol groups, each consisting of two symbols, from mixed lane 0 and outputs them sequentially to lanes 0 to 7; the receiving end obtains eight consecutive symbol groups, each consisting of two symbols, from mixed lane 1 and outputs them sequentially to lanes 8 to 15. The above 16 symbol groups are demultiplexed to the same positions in the corresponding channels of lanes 0 to 15. For example: the symbol group including B.0.34 and A.0.35 is output through lane 0; the symbol group including B.1.0 and A.1.0 is output through lane 1; the symbol group including B.2.34 and A.2.35 is output through lane 2; the symbol group including B.3.0 and A.3.0 is output through lane 3; the symbol group including B.4.34 and A.4.35 is output through lane 4; the symbol group including B.5.0 and A.5.0 is output through lane 5; the symbol group including B.6.34 and A.6.35 is output through lane 6; and the symbol group including B.7.0 and A.7.0 is output through lane 7. After demultiplexing the above 8 consecutive symbol groups from mixed lane 0, the receiving end continues to obtain 8 consecutive symbol groups from mixed lane 1 and demultiplex them. Symbol groups including B.8.34 and A.8.35 are output via lane 8; symbol groups including B.9.0 and A.9.0 are output via lane 9; symbol groups including B.10.34 and A.10.35 are output via lane 10; symbol groups including B.11.0 and A.11.0 are output via lane 11; symbol groups including B.12.34 and A.12.35 are output via lane 12; symbol groups including B.13.0 and A.13.0 are output via lane 13; symbol groups including B.14.34 and A.14.35 are output via lane 14; and symbol groups including B.15.0 and A.15.0 are output via lane 15.After demultiplexing the aforementioned 16 symbol groups, the receiving end will handle the following symbol groups: B.0.34 and A.0.35; B.1.0 and A.1.0; B.2.34 and A.2.35; B.3.0 and A.3.0; B.4.34 and A.4.35; B.5.0 and A.5.0; B.6.34 and A.6.35; and B.7.0 and A.7.0. The following symbol groups are included: B.8.34 and A.8.35; B.9.0 and A.9.0; B.10.34 and A.10.35; B.11.0 and A.11.0; B.12.34 and A.12.35; B.13.0 and A.13.0; B.14.34 and A.14.35; and B.15.0 and A.15.0. These are the symbol groups with the same position in the corresponding channels of lane 0 to lane 15. The receiving end continues to acquire the eight consecutive symbol groups following A.7.0 of muxed lane 0 and the eight consecutive symbol groups following A.15.0 of muxed lane 1, and demultiplexes them according to the above method until all symbols from codeword A and codeword B output by muxed lane 0 and muxed lane 1 are demultiplexed to lane 0 to lane 15.

[0201] The receiving end delays the data stream output from the even-numbered sequence number channel in Figure 9(a) by 69 symbols, as shown in Figure 9(b). After a 69-symbol delay, lanes 0, 2, 4, 6, 8, 10, 12, and 14 in lanes 0 through 15 are sent. The following signals are then sent: B.0.34 in lane 0, A.1.34 in lane 1, B.2.34 in lane 2, A.3.34 in lane 3, B.4.34 in lane 4, A.5.34 in lane 5, B.6.34 in lane 6, A.7.34 in lane 7, B.8.34 in lane 8, A.9.34 in lane 9, B.10.34 in lane 10, A.11.34 in lane 11, B.12.34 in lane 12, and A.13.34 in lane 13. B.14.34 in lane 14 and A.15.34 in lane 15 are symbols in the same position in lane 0 to lane 15, that is, the symbol boundaries of the above 16 symbols are aligned. Lane 0 includes the symbol group B.0.34 and A.0.35; Lane 1 includes the symbol group B.1.35 and A.1.34; Lane 2 includes the symbol group B.2.34 and A.2.35; Lane 3 includes the symbol group B.3.35 and A.3.34; Lane 4 includes the symbol group B.4.34 and A.4.35; Lane 5 includes the symbol group B.5.35 and A.5.34; Lane 6 includes the symbol group B.6.34 and A.6.35; Lane 7 includes the symbol group B.7.35 and A.7.34; Lane 8 includes the symbol group B.8.34 and A.8.35; Lane 9 includes the symbol group B.9.35 and A.9.34 ... The symbol groups in lane 10 (including B.10.34 and A.10.35), lane 11 (including B.11.35 and A.11.34), lane 12 (including B.12.34 and A.12.35), lane 13 (including B.13.35 and A.13.34), lane 14 (including B.14.34 and A.14.35), and lane 15 (including B.15.35 and A.15.34) are the symbol groups in the same position in lanes 0 to 15.In Figure 9(b), the dashed boxes represent the symbols received by the receiver from codeword A and codeword B. Specifically, after the receiver has acquired L2*544 symbols starting from A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, B.7.0, A.8.0, B.9.0, A.10.0, B.11.0, A.12.0, B.13.0, A.14.0, and B.15.0, where L2 is an integer greater than or equal to 1, as shown in the order of the symbols in the solid and dashed boxes in Figure 9(b), the receiver can perform deinterleaving and decoding. Through delayed transmission, symbols at the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. Through this delayed transmission, the receiver reconstructs the same symbol order as the transmitter, enabling the subsequent decoder to complete the decoding operation.

[0202] Figures 10(a) and 10(b) illustrate an embodiment where a codeword group comprises two different codewords, and the symbols of the two codeword groups are demultiplexed. The number of channels in the input data stream is 4, and the number of channels in the output data stream is 32. This method can also be used for scenarios with multiple codeword groups where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 4:32; however, these scenarios will not be illustrated individually here. The receiving end in Figures 10(a) and 10(b) can be a host or chip based on 800GBASE-R.

[0203] The input data stream in Figure 10(a) is the output data stream in Figure 5(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 10(a) can be found in the corresponding content of Figures 5(b) and 5(a). In this embodiment, the meanings of consecutive and adjacent are the same as... Figure 2The corresponding content in the corresponding embodiments is the same, and will not be repeated here. The symbols in Figure 10(a) come from two codeword groups. The first codeword group includes codeword A and codeword B, and the second codeword group includes codeword C and codeword D. The receiving end acquires eight consecutive symbol groups (each consisting of two symbols) from each of the mixed lanes 0 to 3 and outputs them sequentially to lanes 0 to 31. Specifically, the receiving end acquires eight consecutive symbol groups (each consisting of two symbols) from mixed lane 0 and outputs them sequentially to four channels in lanes 0 to 15 and four channels in lanes 16 to 31; the receiving end acquires eight consecutive symbol groups (each consisting of two symbols) from mixed lane 1 and outputs them sequentially to four channels in lanes 0 to 15 and four channels in lanes 16 to 31; the receiving end acquires eight consecutive symbol groups (each consisting of two symbols) from mixed lane 2 and outputs them sequentially to four channels in lanes 0 to 15 and four channels in lanes 16 to 31. The receiver acquires eight consecutive symbol groups (each consisting of two symbols) from mixed lane 3 and outputs them sequentially to four channels in lanes 0-15 and four channels in lanes 16-31. These 32 symbol groups are demultiplexed to the same positions in the corresponding channels of lanes 0-31, and any lane from mixed lane 0 to mixed lane 3 is demultiplexed to eight completely different channels.For example: the symbol group including B.0.0 and A.0.0 is output through lane 0; the symbol group including B.1.0 and A.1.0 is output through lane 1; the symbol group including B.2.0 and A.2.0 is output through lane 2; the symbol group including B.3.0 and A.3.0 is output through lane 3; the symbol group including B.4.0 and A.4.0 is output through lane 4; the symbol group including B.5.0 and A.5.0 is output through lane 5; the symbol group including B.6.0 and A.6.0 is output through lane 6; the symbol group including B.7.0 and A.7.0 is output through lane 7; the symbol group including B.8.0 and A.8.0 is output through lane 8; the symbol group including B.9.0 and A.9.0 is output through lane 9; and the symbol group including B.10.0 and A.10.0 is output through lane 1. The outputs are as follows: symbol groups B.11.0 and A.11.0 are output through lane 11; symbol groups B.12.0 and A.12.0 are output through lane 12; symbol groups B.13.0 and A.13.0 are output through lane 13; symbol groups B.14.0 and A.14.0 are output through lane 14; and symbol groups B.15.0 and A.15.0 are output through lane 15. These 16 symbol groups, including symbols from the first codeword group, are located at the same position in each channel from lane 0 to lane 15, meaning the boundaries of the symbols in these 16 symbol groups are aligned. The demultiplexing process for symbols from the second codeword group is the same as the demultiplexing process for symbols from the first codeword group, and will not be described again here. The receiving end performs demultiplexing according to the above method until all symbols from the first codeword group and the second codeword group output from muxe lane 0 to muxed lane 3 are demultiplexed to lane 0 to lane 31.

[0204] The receiving end delays the data stream output by the channel with even sequence number in Figure 10(a) by 1 symbol, as shown in Figure 10(b). Lanes 0 through 31, including lanes 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, and 30, are sent with a one-symbol delay. The following lanes are then sent with a one-symbol delay: lane 0 (B.0.0), lane 1 (A.1.0), lane 2 (B.2.0), lane 3 (A.3.0), lane 4 (B.4.0), lane 5 (A.5.0), lane 6 (B.6.0), lane 7 (A.7.0), lane 8 (B.8.0), lane 9 (A.9.0), lane 10 (B.10.0), and lane 11 (A.11.0). Lane 12, B.12.0; Lane 13, A.13.0; Lane 14, B.14.0; Lane 15, A.15.0; Lane 16, D.16.0; Lane 17, C.17.0; Lane 18, D.18.0; Lane 19, C.19.0; Lane 20, D.20.0; Lane 21, C.21.0; Lane 22, D.22.0; Lane 23, C.23.0; Lane 24, D.24.0; Lane 25, C.25.0; Lane 26, D.26.0; Lane C, C.27.0; Lane 28, C.28.0; Lane 29, C.29.0; Lane 30, D.30.0; Lane C.31.0 in 31 refers to the symbols in the same position in lane 0 to lane 31, that is, the symbol boundaries of the above 32 symbols are aligned. The symbol group including the above 32 symbols is the symbol group in the same position in each channel in lane 0 to lane 31.In Figure 10(b), the dashed boxes represent the symbols received by the receiver from codeword A, codeword B, codeword C, and codeword D, i.e., from A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, B.7.0, A.8.0, B.9.0, A.10.0, B.11.0, A.12.0, B.13.0, A.14.0, B.15.0, C.16.0, D.17.0, C.18.0, D.19.0, C.20.0, and D.21. After the receiver acquires the first L3*544 symbols (C.22.0, D.23.0, C.24.0, D.25.0, C.26.0, D.27.0, C.28.0, D.29.0, C.30.0, and D.31.0), L3 is an integer greater than or equal to 1, as shown in the order of symbols in the solid and dashed boxes in Figure 10(b). The receiver can then perform deinterleaving and decoding. Through delayed transmission, symbols at the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. Through this delayed transmission, the receiver reconstructs the same symbol order as the transmitter, enabling the subsequent decoder to complete the decoding operation.

[0205] Figure 11 This embodiment describes a codeword group consisting of 4 different codewords, demultiplexing the symbols of one codeword group, with 8 channels in the input data stream and 16 channels in the output data stream. This method can also be used for other scenarios where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 8:16, and will not be illustrated further here. Figure 11 The receiving end can be a host or chip based on 1.6TGBASE-R.

[0206] Figure 11 The input data stream is Figure 6 Output data stream, Figure 11 The meanings of the identifiers, symbols, symbol groups, and codeword groups in the box can be found in [reference needed]. Figure 6 The corresponding content. In this embodiment, the meanings of "continuous" and "adjacent" are... Figure 2 The corresponding content in the corresponding embodiments is the same, and will not be repeated here. Figure 11The symbols in the code come from a codeword group consisting of four codewords: codeword A, codeword B, codeword C, and codeword D. The receiver retrieves two consecutive symbol groups (each containing four symbols) from each of the mixed lanes 0 to 7 and outputs them sequentially to lanes 0 to 15. Specifically, the receiver retrieves two consecutive symbol groups (each containing four symbols) from mixed lane 0 and outputs them sequentially to lanes 0 and 1; the receiver retrieves two consecutive symbol groups (each containing four symbols) from mixed lane 1 and outputs them sequentially to lanes 2 and 3; the receiver retrieves two consecutive symbol groups (each containing four symbols) from mixed lane 2 and outputs them sequentially to lanes 4 and 5; and the receiver retrieves two consecutive symbol groups (each containing four symbols) from mixed lane 3 and outputs them sequentially to lanes 6 and 7. The receiving end demultiplexes mixed lanes 4 to 7 into lanes 8 to 15 using the same method as demultiplexing mixed lanes 0 to 3 into lanes 0 to 7. After this demultiplexing, the codewords from which the symbols in any symbol group in lanes 0 to 15 originate have the same order, ABCD. The receiving end reconstructs the same symbol order as that obtained by the transmitting end, enabling the subsequent decoder to complete the decoding operation.

[0207] The hardware structure shown in Figure 12(a) includes, in sequence, a reconciliation sublayer (RS), a physical coding sublayer (PCS), two physical medium attachment (PMA) layers, an inner forward error correction (Inner FEC) layer, a physical medium dependent (PMD) layer, and a medium. A medium-independent interface (MII) is provided between the RS and PCS, and an attachment unit interface (AUI) is provided between the two PMA layers. A medium-dependent interface (MDI) is provided between the PMD layer and the medium. The medium can be coaxial cable, fiber optic cable, or twisted-pair cable, etc. Figures 2 to 11 In the corresponding embodiment, the data processing method can be implemented by the PMA layer between the PCS and AUI in Figure 12(a). In this case, the AUI transmits 200G / lane data, and the PMA layer between the AUI and the Inner FEC can transparently transmit the data transmitted by the AUI. Alternatively, the PMA layer between the AUI and the Inner FEC layer in Figure 12(a) can use... Figures 2 to 11In the corresponding embodiment, the AUI transmits 100G / lane data. The PMA layer between the AUI and the Inner FEC can use bit-level multiplexing or pass-through of PCS data. The RS is used to provide mapping processing for the data transmitted between the Media Access Control (MAC) layer and the PCS. The PCS is used to encode or decode the transmitted data according to a certain encoding method. The PCS can also deploy the FEC layer functionality. The FEC layer is used to implement FEC processing. The PMD layer is used to realize the mutual conversion between the data signal of the PAM layer and the signal transmitted on a specific media medium. The AUI can be used to transmit data at different rates between PMAs. The MII is used to transmit data at different rates between the RS and the PCS, which can include various data types such as 50GMII, 100GMII, and 200G / 400GMII. The transmitted data passes through RS->PCS->PMA layer->PMA layer->Inner FEC layer->PMD layer->media medium output; the received data passes through media medium->PMD layer->Inner FEC layer->PMA layer->PMA layer->PCS->RS output. The hardware structure shown in Figure 12(b) includes RS, PCS, PMA layer, Inner FEC layer, PMD layer, and media medium arranged sequentially. An MII is provided between RS and PCS. An MDI is provided between the PMD layer and the media medium. The media medium can be coaxial cable, fiber optic cable, or twisted-pair cable, etc. Figures 2 to 11 The data processing method in the corresponding embodiment can be implemented by the PMA layer in Figure 12(b). The functions of RS, PCS, PMA layer, Inner FEC layer, PMD layer, medium media, and MII are shown in Figure 12(a). Transmitted data passes through RS->PCS->PMA layer->Inner FEC layer->PMD layer->medium media for output; received data passes through medium media->PMD layer->Inner FEC layer->PMA layer->PCS->RS for output. Figure 12(a) or Figure 12(b) can be applied to hosts or chips employing 200GBASE-R, 400GBASE-R, 800GBASE-R, and 1.6TBASE-R.

[0208] Figures 13(a) to 13(c) This refers to deployment in a chip-based scenario. Figures 2 to 11 Possible implementations of the data processing method in the corresponding embodiments. Figures 13(a) to 13(c)In this context, FEC encoding or FEC1 encoding refers to the first FEC encoding (e.g., FEC encoding in PCS), FEC2 encoding refers to the second FEC encoding (e.g., Inner FEC encoding), and symbol combination refers to multiplexing based on symbol groups. Figures 2-6 The corresponding data processing method in the embodiments), symbol group splitting refers to demultiplexing based on symbol groups ( Figures 7-11 In the corresponding embodiment of the data processing method, FEC decoding or FEC1 decoding refers to the first FEC decoding (e.g., FEC decoding in PCS), and FEC2 decoding refers to the second FEC decoding (e.g., Inner FEC decoding). The symbol combination may also include... Figures 2-6 The offset in the corresponding embodiment; symbol group splitting may also include Figures 7-11 The offset in the corresponding embodiment. TX represents the transmitting side, and RX represents the transmitting side. Figures 14(a) to 14(f) It is used for deployment in multiple chip scenarios. Figures 2 to 11 Possible implementations of the data processing method in the corresponding embodiments. Figures 14(a) to 14(f) In this context, FEC encoding or FEC1 encoding refers to the first FEC encoding (e.g., FEC encoding in PCS), FEC2 encoding refers to the second FEC encoding (e.g., Inner FEC encoding), and symbol combination, symbol combination 1, or symbol combination 2 refers to multiplexing based on symbol groups. Figures 2-6 The corresponding data processing method in the embodiments), symbol group splitting, symbol group splitting 1 or symbol group splitting 2 refers to demultiplexing based on symbol groups ( Figures 7-11 In the corresponding embodiment of the data processing method, FEC decoding or FEC1 decoding refers to the first FEC decoding (e.g., FEC decoding in PCS), and FEC2 decoding refers to the second FEC decoding (e.g., Inner FEC decoding). The symbol combination, symbol combination 1, or symbol combination 2 may further include... Figures 2-6 The offset in the corresponding embodiment; symbol group splitting, symbol group splitting 1 or symbol group splitting 2 may also include Figures 7-11 The offset in the corresponding embodiment. TX represents the transmitting side, and RX represents the transmitting side. Figures 14(a) to 14(f) If a clock and data recovery (CDR) chip exists between the main chip and the optical module, the symbol combination, symbol combination 1 or symbol combination 2 on the TX side is implemented in the CDR chip, and the symbol group splitting, symbol group splitting 1 or symbol group splitting 2 on the RX side is implemented in the CDR chip. This application will not provide specific examples for each of these implementations.

[0209] As shown in FIG. 15(a), a data sending device 1500 provided by an embodiment of the present application includes a processing unit 1502 and an output unit 1503. Optionally, the data sending device 1500 further includes an acquisition unit 1501. The processing unit 1502 is used to implement Figure 2 the method of obtaining an output data stream in the corresponding embodiment 202. The output unit 1503 is used to implement Figure 2 the output method included in the corresponding embodiment 202. The acquisition unit 1501 is used to implement Figure 2 the method of 201 in the corresponding embodiment. When the data sending device 1500 is used to implement the method executed by the sending end in FIGS. 3 to Figure 6 when, the processing unit 1502 is used to implement the multiplexing method in the corresponding embodiment in FIGS. 3 to Figure 6 when, the output unit 1503 is used to implement the method of outputting a data stream through a muxed lane in the corresponding embodiment in FIGS. 3 to Figure 6 when, the acquisition unit 1501 is used to implement one or more methods of offset and interleaving in the corresponding embodiment in FIGS. 3 to Figure 6 when. The data sending device 1500 may be a router, a switch, a server, etc.

[0210] For example, the processing unit 1502 is used to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among the b data streams, any one of the data streams includes multiple symbol groups, any one symbol group includes multiple symbols from different codewords, and any one symbol includes multiple bits. The output unit 1503 is used to transmit the b data streams.

[0211] Among them, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0212] For example, the a data streams are based on coding, and the symbol is an RS symbol. The length of the RS symbol is 10 bits.

[0213] In the 200GBASE-R implementation, a equals 8, b equals 1, the symbol group includes 2 symbols, and any 8 consecutive symbol groups in the b data streams come from the 8 data streams respectively. The processing unit 1502 is also used to delay the transmission of the data stream output by the channel with each odd sequence number in the a data stream by 136*N+1 symbols, where N is an integer greater than or equal to 1.

[0214] In the 400GBASE-R implementation, 'a' equals 16, 'b' equals 2, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the 'b' data streams originate from the 8 data streams in the 'a' data streams. The processing unit 1502 is further configured to delay the transmission of the data stream output from each odd-numbered channel in the 'a' data streams by 68*N+1 symbols, where N is an integer greater than or equal to 1.

[0215] In the 1.6TBASE-R implementation, a equals 16, b equals 8, the symbol group includes 4 symbols, and any two consecutive symbol groups in any of the b data streams come from the two data streams in the a data streams respectively.

[0216] Based on any of the above implementation methods, the order of the codewords to which the consecutive symbols output by the channel of any even-numbered sequence number in the a data stream belong is the same as the order of the codewords to which the consecutive symbols output by the channel of any odd-numbered sequence number in the a data stream belong.

[0217] In the 800GBASE-R implementation, 'a' equals 32, 'b' equals 4, and the symbol group comprises 2 symbols. Any consecutive 8 symbol groups in any of the 'b' data streams originate from the 8 data streams in the 'a' data streams. The 8 data streams in the 'a' data streams include 4 data streams from a first codeword group and 4 data streams from a second codeword group. The first codeword group comprises 2 codewords, and the second codeword group comprises 2 codewords. The 2 codewords in the first codeword group are different from the 2 codewords in the second codeword group. The processing unit 1502 is further configured to delay the transmission of the data stream output from each odd-numbered sequence number channel in the 'a' data streams by 2*N+1 symbols, where N is an integer greater than or equal to 0.

[0218] In one implementation, the acquisition unit 1501 is further configured to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword group in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data streams. The encoding includes feedforward error correction (FEC) coding.

[0219] In one implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams. Each of the b data streams has a rate of 200 Gbps.

[0220] As shown in Figure 15(b), a data receiving device 1510 provided in this embodiment includes an acquisition unit 1511 and a processing unit 1512. The acquisition unit 1511 is used to implement... Figure 7 The method of 701 in the corresponding embodiment. Processing unit 1512 is used to implement Figure 7 The method of 702 in the corresponding embodiment. The data receiving device 1510 is used to implement Figure 8 to... Figure 11 When the receiving end executes the method, the acquisition unit 15 is used to implement Figure 8 to... Figure 11 In the corresponding embodiment, the input data stream is obtained through a muxe lane, and the processing unit 1513 is used to implement Figure 8 to... Figure 11 The demultiplexing method in the corresponding embodiment. Further, the processing unit 1513 is used to implement the methods shown in Figures 8 to 9. Figure 11 The method of offsetting in the corresponding embodiment. The function performed by the unit included in the receiving device is the reverse process of the method performed by the unit included in the transmitting device, and will not be described again here. The data receiving device 1510 may be a router, switch, or server, etc.

[0221] For example, the acquisition unit 1511 is used to receive b data streams, where b is an integer greater than or equal to 1. Each of the b data streams includes multiple symbol groups, each symbol group includes multiple symbols from different codewords, and each symbol includes multiple bits. The processing unit 1512 is used to demultiplex the b data streams based on the symbol groups to obtain a data streams, where a is an integer greater than or equal to 2 and a>b.

[0222] As shown in Figure 16(a), another data transmission device 1600 provided in the application embodiment includes a processor 1601 and a transmitter 1602 coupled to the processor 1601. The processor 1601 is used to implement... Figure 2 In the corresponding embodiments, 201 and 202 include methods for acquiring the output data stream. Transmitter 1602 is used to implement... Figure 2The method for the output included in the corresponding embodiment. The data sending device 1600 is used to implement the method executed by the sending end in FIGS. 3 to Figure 6 When implementing the method, the processor 1601 is used to implement the method executed by the sending end in FIGS. 3 to Figure 6 The multiplexing method in the corresponding embodiment, and the transmitter 1602 is used to implement the method for outputting the data stream through the muxed lane in FIGS. 3 to Figure 6 The method for outputting the data stream through the muxed lane in the corresponding embodiment. Optionally, the processor 1601 is further used to implement one or more of the offset and interleaving in the corresponding embodiment in FIGS. 3 to Figure 6 The processor 1601 may adopt the structure of FIG. 12(a) or FIG. 12(b). The transmitter 1602 may specifically be a sending circuit or a sending interface. The data sending device 1600 may be a router, a switch or an optical module. When the data sending device 1600 is a router or a switch, the processor 1601 may be a physical layer (PHY) chip, such as the TX main chip in FIGS. 13 to 14, and the transmitter 1602 may be an optical module, such as the TX optical module in FIGS. 13 to 14. When the data sending device 1600 is an optical module, such as the TX optical module in FIGS. 13 to 14, the processor 1601 may be a processing circuit, and the transmitter 1602 may be a sending circuit. The data sending device 1600 may be a router, a switch or a server, etc.

[0223] For example, the processor 1601 is used to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, and b is an integer greater than or equal to 1 and b < a. Any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; the transmitter 1602 is used to transmit the b data streams.

[0224] In a possible implementation manner, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0225] In a possible implementation manner, the a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

[0226] In a possible implementation manner, the length of the RS symbol is 10 bits.

[0227] In one possible implementation, a equals 8, b equals 1, the symbol group includes 2 symbols, and any 8 consecutive symbol groups included in the b data streams come from the 8 data streams respectively.

[0228] In one possible implementation, the processor is further configured to delay the transmission of the data stream output by the channel of each odd sequence number in the a data stream by L symbols, where L equals 136*N+1 and N is an integer greater than or equal to 1.

[0229] In one possible implementation, a equals 16, b equals 2, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the b data streams are respectively derived from the 8 data streams in the a data stream.

[0230] In one possible implementation, the processor further delays the transmission of the data stream output by the channel for each odd sequence number in the a data stream by L symbols, where L equals 68*N+1 and N is an integer greater than or equal to 1.

[0231] In one possible implementation, a equals 16, b equals 8, the symbol group includes 4 symbols, and any two consecutive symbol groups in any of the b data streams come from two data streams in the a data streams respectively.

[0232] In one possible implementation, the order of the codewords to which the consecutive symbols output by the channel of any even-numbered sequence number in the a data stream belong is the same as the order of the codewords to which the consecutive symbols output by the channel of any odd-numbered sequence number in the a data stream belong.

[0233] In one possible implementation, a equals 32, b equals 4, the symbol group includes 2 symbols, and any consecutive 8 symbol groups in any of the b data streams are respectively from the 8 data streams in the a data stream. The 8 data streams in the a data stream include 4 data streams from the first codeword group and 4 data streams from the second codeword group. The first codeword group includes 2 codewords, and the second codeword group includes 2 codewords. The 2 codewords in the first codeword group are different from the 2 codewords in the second codeword group.

[0234] In one possible implementation, the processor is further configured to delay the transmission of the data stream output by the channel of each odd sequence number in the a data stream by L symbols, where L equals 2*N+1 and N is an integer greater than or equal to 0.

[0235] In one possible implementation, the processor is further configured to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword group in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data stream.

[0236] In one possible implementation, the encoding includes feedforward error correction (FEC) encoding.

[0237] In one possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0238] In one possible implementation, the rate of any one of the b data streams is 200 Gbps.

[0239] As shown in Figure 16(b), another data receiving device 1610 provided in this embodiment includes a receiver 1611 and a processor 1612 coupled to the receiver 1611. The receiver 1611 is used to implement... Figure 7 The method of 701 in the corresponding embodiment. Processor 1612 is used to implement Figure 7 The method of 702 in the corresponding embodiment. The data receiving device 1610 is used to implement Figure 8 to... Figure 11 When the receiving end executes the method, the receiver 1611 is used to implement Figure 8 to... Figure 11 In the corresponding embodiment, the input data stream is obtained through a muxelane, and the processor 1612 is used to implement Figure 8 to... Figure 11 The demultiplexing method in the corresponding embodiment. Further, the processor 1612 is used to implement Figures 8 to... Figure 11 The offset method in the corresponding embodiment. The processor 1611 can adopt the structure of Figure 12(a) or Figure 12(b). The receiver 1611 can specifically be a receiving circuit or a receiving interface. The data receiving device 1610 can be a router, a switch, or an optical module. When the data receiving device 1610 is a router or a switch, the processor 1611 can be a physical layer (PHY) chip, such as the RX main chip in Figures 13 and 14, and the receiver 1612 can be an optical module, such as the RX optical module in Figures 13 and 14. When the data receiving device 1610 is an optical module, such as the RX optical module in Figures 13 and 14, the processor 1611 can be a processing circuit, and the receiver 1611 can be a receiving circuit. The data receiving device 1610 can be a router, a switch, or a server, etc.

[0240] For example, the receiver 1611 is used to receive b data streams, where b is an integer greater than or equal to 1. Each of the b data streams includes multiple symbol groups, each symbol group includes multiple symbols from different codewords, and each symbol includes multiple bits. The processor 1612 is used to demultiplex the b data streams based on the symbol groups to obtain a data streams, where a is an integer greater than or equal to 2 and a>b. The a data streams include a first data stream and a second data stream, the b data streams include a third data stream, and the multiple symbol groups include a first symbol group and a second symbol group. The first symbol group and the second symbol group are consecutive in the third data stream. All symbols in the first symbol group originate from and are consecutive in the first data stream, and all symbols in the second symbol group originate from and are consecutive in the second data stream.

[0241] In one possible implementation, the a data streams are RS encoded, and the symbols are RS symbols. The length of the RS symbol is 10 bits.

[0242] Figure 17This is a schematic diagram of a data processing apparatus provided in an embodiment of this application. The apparatus is either the sending end or the receiving end provided in an embodiment of this application. The apparatus includes a processor 1701, a memory 1702, a network interface 1703, and a bus 1704. The memory 1702 stores a computer program 1705, which is used to implement various application functions. The processor 1701 executes the computer program 1705 to implement the data processing method provided in any of the above-described method embodiments. For example, the processor 1701 can execute the computer program 1705 to implement the functions of the various units or structures shown in any of Figures 15 and 16. The processor 1701 can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), ASICs, FPGAs, graphics processing units (GPUs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The memory 1702 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).There can be multiple network interfaces 1703, and these interfaces are used to establish communication connections with other devices (which can be wired or wireless). These other devices can be optical modules, hosts, routers, switches, etc. Figure 17 The data processing device shown can be a router, switch, or server, etc.

[0243] This application also provides a computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the steps performed by the sending end or the receiving end as described in the above method embodiments.

[0244] This application also provides a computer program product containing instructions that, when executed on a processor, cause the processor to perform the steps performed by the sending end or the receiving end as described in the above method embodiments.

[0245] This application also provides a system including a transmitter and a receiver. The transmitter may be the data transmission device shown in FIG15(a) or FIG16(a) above, or the transmitter may be used to perform... Figures 2 to 6 The corresponding embodiment describes the method used by the transmitting end. The receiving end can be the data receiving device shown in Figure 15(b) or Figure 16(b) above, or the receiving end is used to perform... Figures 7 to 11 The corresponding embodiment uses the method employed by the receiving end.

[0246] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In the embodiments of this application, the term "at least one" refers to one or more, and "multiple" refers to two or more. In the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0247] The above description is merely an optional implementation of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method, characterized in that: The method includes: Delaying the data streams output from channels with odd serial numbers in the a data streams by L symbols for transmission, where L is an integer greater than or equal to 1. The sorting of the consecutive symbols belonging to the codeword in the output of any channel with an even serial number in the a data streams is the same as the sorting of the consecutive symbols belonging to the codeword in the output of any channel with an odd serial number in the a data streams; Based on symbol groups, multiplexing the a data streams to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among them, any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; Transmitting the b data streams.

2. The method according to claim 1, characterized in that: The a data streams include a first data stream and a second data stream. The b data streams include a third data stream. The multiple symbol groups include a first symbol group and a second symbol group. The first symbol group and the second symbol group are consecutive in the third data stream. All symbols in the first symbol group come from the first data stream and are consecutive in the first data stream. All symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

3. The method according to claim 1 or 2, characterized in that: The a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

4. The method according to claim 3, characterized in that The length of the RS symbol is 10 bits.

5. The method according to any one of claims 1 to 4, characterized in that: a is equal to 8, b is equal to 1, the number of symbols included in the symbol group is 2. Any consecutive 8 symbol groups included in any one of the b data streams come from the 8 data streams among the a data streams respectively. L is equal to 136*N + 1, where N is an integer greater than or equal to 1.

6. The method according to any one of claims 1 to 4, characterized in that: a is equal to 16, b is equal to 2, the number of symbols included in the symbol group is 2. Any consecutive 8 symbol groups included in any one of the b data streams come from the 8 data streams among the a data streams respectively. L is equal to 68*N + 1, where N is an integer greater than or equal to 1.

7. The method according to any one of claims 1 to 4, characterized in that: a is equal to 16, b is equal to 8, the number of symbols included in the symbol group is 4. Any consecutive 2 symbol groups included in any one of the b data streams come from 2 data streams among the a data streams respectively.

8. The method according to any one of claims 1 to 4, characterized in that: a is equal to 32, b is equal to 4, the number of symbols included in the symbol group is 2. Any consecutive 8 symbol groups included in any one of the b data streams come from the 8 data streams among the a data streams respectively. The 8 data streams among the a data streams include 4 data streams from a first codeword group and 4 data streams from a second codeword group. The first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group. L is equal to 2*N + 1, where N is an integer greater than or equal to 0.

9. The method according to any one of claims 1 to 8, characterized in that: The method further includes: Encoding the received data to obtain K codeword groups, where K is an integer greater than or equal to 1. The number of symbols included in any one of the codewords in the K codeword groups is a positive integer multiple of 544; The codewords included in the K codeword groups are interleaved based on symbols to obtain the a data streams.

10. The method according to claim 9, characterized in that The encoding includes feed-forward error correction (FEC) encoding.

11. The method according to any one of claims 1 to 10, characterized in that: The sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

12. The method according to any one of claims 1 to 11, characterized in that: The rate of any one of the b data flows is 200 Gbps.

13. A data transmission method, characterized in that: The method comprises: Receive b data streams, where b is an integer greater than or equal to 1, any data stream among the b data streams includes a plurality of symbol groups, any symbol group includes a plurality of symbols from different codewords, and any symbol includes a plurality of bits; Demultiplexing the b data streams based on symbol groups to obtain a data stream, where a is an integer greater than or equal to 2 and a>b, and the order of codewords to which consecutive symbols output by a channel with an even sequence number in the a data streams belong is the same as the order of codewords to which consecutive symbols output by a channel with an odd sequence number in the a data streams belong; The data stream output by each channel with an even sequence number among the a data streams is delayed by L symbols and sent, where L is an integer greater than or equal to 1.

14. The method according to claim 13, characterized in that The a data stream includes a first data stream and a second data stream, the b data stream includes a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are continuous in the third data stream, all symbols in the first symbol group come from the first data stream and are continuous in the first data stream, and all symbols in the second symbol group come from the second data stream and are continuous in the second data stream.

15. The method according to claim 13 or 14, characterized in that The a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

16. The method according to claim 15, characterized in that The length of the RS symbol is 10 bits.

17. A data processing device, characterized in that: The device comprises a unit for executing the method of any one of claims 1 to 12 or a unit for executing the method of any one of claims 13 to 16.

18. A computer program product, characterized in that The computer program product stores instructions, and when the instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 12 or the method according to any one of claims 13 to 16.

19. A chip, characterized in that: The chip may include a processing circuit and an interface circuit, and the processing circuit and the interface circuit are used to implement the method of any one of claims 1 to 12 or any one of claims 13 to 16.

20. A system, characterized in that: The system includes a transmitting end and a receiving end, wherein the transmitting end is used to implement the method described in any one of claims 1 to 12, and the receiving end is used to implement the method described in any one of claims 13 to 16.

Images