Voltage regulator circuits, chip systems and electronic devices

Abstract

The embodiments of the present application provide a voltage stabilizing circuit, a chip system and an electronic device, which relate to the field of integrated circuit technology, and are used to improve the power-on and power-off speed of the voltage stabilizing circuit while avoiding overshoot. The voltage stabilizing circuit includes an input end, an output end, an LDO circuit, a slow start module and a switch circuit; the input end of the voltage stabilizing circuit is coupled to the input end of the slow start module and the voltage input end of the LDO circuit, the output end of the slow start module is coupled to the control end of the LDO circuit, the voltage output end of the LDO circuit is coupled to the voltage input end of the switch circuit, and the voltage output end of the switch circuit is coupled to the output end of the voltage stabilizing circuit; the slow start module is used to slow down the rise of the output voltage of the voltage output end of the LDO circuit; when the output voltage of the voltage output end of the LDO circuit no longer rises, the output end of the voltage stabilizing circuit supplies power to the load when the switch circuit is turned on, and stops supplying power to the load when the switch circuit is turned off.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a voltage stabilizing circuit, a chip system and an electronic device. Background Art

[0002] Currently, many electronic devices use low dropout regulator (LDO) circuits to power loads. One performance requirement for LDO circuits is that they can be powered on and off quickly so as to achieve a fast response to load power supply. However, fast power on and off of LDO circuits can cause overshoot problems in the output voltage and current of the LDO circuit, which has a negative impact on the power supply to the load. Summary of the invention

[0003] Embodiments of the present application provide a voltage stabilizing circuit, a chip system, and an electronic device, which are used to increase the power-on and power-off speeds of the voltage stabilizing circuit while avoiding overshoot.

[0004] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0005] In a first aspect, a voltage stabilizing circuit is provided, comprising: an input end, an output end, an LDO circuit, a slow start module and a switch circuit; the input end of the voltage stabilizing circuit is coupled to the input end of the slow start module and the voltage input end of the LDO circuit, and the input end of the voltage stabilizing circuit is used to input a power supply voltage; the output end of the slow start module is coupled to the control end of the LDO circuit, the voltage output end of the LDO circuit is coupled to the voltage input end of the switch circuit, and the voltage output end of the switch circuit is coupled to the output end of the voltage stabilizing circuit; the slow start module is used to slow down the rise of the output voltage of the voltage output end of the LDO circuit by slowing down the rise of the output voltage of the slow start module when the input end of the voltage stabilizing circuit inputs the power supply voltage; when the output voltage of the voltage output end of the LDO circuit no longer rises, the output end of the voltage stabilizing circuit supplies power to the load when the switch circuit is turned on, and stops supplying power to the load when the switch circuit is turned off.

[0006] In the voltage stabilizing circuit provided in the embodiment of the present application, the slow start module causes the LDO circuit to power on slowly while solving the overshoot problem. When the LDO circuit is continuously powered, the output voltage of the voltage stabilizing circuit is controlled by the switch circuit. When the switch circuit is turned on, the voltage stabilizing circuit supplies power to the load, and when the switch circuit is turned off, the voltage stabilizing circuit stops supplying power to the load. Since the voltage difference between the input and output ends of the switch circuit is smaller, the overshoot is smaller when it is turned on and off quickly, thereby achieving fast power on and off of the voltage stabilizing circuit while solving the overshoot problem.

[0007] In a possible implementation, the switch circuit includes a second switch tube; the control end of the second switch tube is used to input the first enable signal, the first controlled end of the second switch tube is the voltage input end of the switch circuit, and the second controlled end of the second switch tube is the voltage output end of the switch circuit. The first enable signal is generated by the controller, which is independent of the LDO circuit and the soft start module, and can flexibly control the conduction or shutdown of the second switch tube, thereby controlling the output voltage of the voltage stabilization circuit.

[0008] In a possible implementation, the second switch tube is a P-channel metal oxide semiconductor field effect transistor (PMOS tube). The gate of the PMOS tube is the control end of the second switch tube, the source of the PMOS tube is the first controlled end of the second switch tube, and the drain of the PMOS tube is the first controlled end of the second switch tube.

[0009] In a possible implementation, the slow-start module includes a capacitor, which can slow down the rise of the output voltage of the slow-start module, thereby making the output voltage of the LDO circuit rise smoothly and avoiding the occurrence of spike pulses.

[0010] In a possible implementation, the LDO circuit includes a bandgap reference module, a differential amplifier, a first switch tube and a voltage divider circuit; the differential amplifier includes a first input terminal, a second input terminal, an output terminal and a control terminal; the voltage divider circuit includes a voltage divider node; the voltage input terminal of the bandgap reference module is coupled to the input terminal of the voltage stabilization circuit, and the enable terminal of the bandgap reference module is used to input a second enable signal; the first input terminal of the differential amplifier is coupled to the voltage output terminal of the bandgap reference module, the second input terminal of the differential amplifier is coupled to the voltage divider node of the voltage divider circuit, the output terminal of the differential amplifier is coupled to the control terminal of the first switch tube, the first controlled terminal of the first switch tube is coupled to the voltage input terminal of the LDO circuit, and the second controlled terminal of the first switch tube is coupled to the voltage output terminal of the LDO circuit; the control terminal of the differential amplifier is coupled to the output terminal of the slow start module; and the voltage divider circuit is coupled to the voltage output terminal of the LDO circuit.

[0011] The differential amplifier is used to improve the stability of the output voltage of the LDO circuit while deepening the feedback effect. The differential amplifier amplifies the small error signal between the feedback voltage and the reference voltage, and then outputs it to the output end of the LDO circuit through the first switch tube. Negative feedback is formed through the voltage divider circuit, ensuring that the output voltage of the LDO circuit is stable at the specified value.

[0012] In a possible implementation, the first switch tube is a PMOS tube. The gate of the PMOS tube is the control end of the first switch tube, the source of the PMOS tube is the first controlled end of the first switch tube, and the drain of the PMOS tube is the second controlled end of the first switch tube. When the gate voltage is lower than the source voltage, the PMOS tube is turned on, and when the gate voltage is higher than the source voltage, the PMOS tube is turned off.

[0013] In a possible implementation, the voltage divider circuit includes a first resistor and a second resistor; a first end of the first resistor is coupled to a voltage output end of the LDO circuit, a second end of the second resistor is grounded, and a second end of the first resistor and a first end of the second resistor are coupled to a voltage divider node. The voltage divider circuit is used to divide the output voltage of the LDO circuit to obtain a feedback voltage.

[0014] In a possible implementation, the voltage stabilizing circuit further includes an AND gate; the control signal output end of the soft start module is coupled to the first input end of the AND gate, the second input end of the AND gate is used to input a second enable signal, and the output end of the AND gate is coupled to the enable end of the differential amplifier.

[0015] In a second aspect, a chip system is provided, which includes the voltage stabilizing circuit of the first aspect and any embodiment thereof.

[0016] In a third aspect, a chip system is provided, which includes the LDO circuit and the soft start module in the voltage stabilizing circuit of the first aspect and any embodiment thereof, and the chip system is coupled to the switch circuit in the voltage stabilizing circuit.

[0017] In a fourth aspect, an electronic device is provided. The electronic device includes the voltage stabilizing circuit of the first aspect and any embodiment thereof and a load, wherein the voltage stabilizing circuit is used to supply power to the load.

[0018] The technical effects of the second to fourth aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of a first voltage stabilizing circuit provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of the upper and lower power waveforms of the first voltage stabilizing circuit provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of a second voltage stabilizing circuit provided in an embodiment of the present application;

[0023] Figure 5A schematic diagram of the upper and lower power waveforms of the second voltage stabilizing circuit provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a third voltage stabilizing circuit provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the upper and lower power waveforms of the third voltage stabilizing circuit provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the structure of the first chip system provided in the embodiment of the present application;

[0027] Fig. 9 A schematic diagram of the structure of the second chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] First, some concepts involved in this application are described.

[0029] The terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0030] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the related concepts in a specific way.

[0031] The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0032] The electronic device provided in the embodiment of the present application may be an electronic device including a voltage stabilizing circuit, and the electronic device may be mobile or fixed. The electronic device may be deployed on land (e.g., indoors or outdoors, handheld or vehicle-mounted, etc.), on water (e.g., ships, etc.), or in the air (e.g., airplanes, balloons, and satellites, etc.). The electronic device may be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device, etc. For example, the electronic device may be a mobile phone, tablet computer, laptop computer, smart bracelet, smart watch, power bank, new energy vehicle, or other electronic device. The embodiment of the present application does not limit the specific type and structure of the electronic device, and a possible structure of the electronic device is described below.

[0033] Taking a mobile phone as an example, Figure 1 A possible structure of an electronic device 1 is shown. Exemplarily, the electronic device 1 may include a voltage stabilizing circuit 10, a power management chip 11, a controller 12, and a load 13. The voltage output terminal of the power management chip 11 is coupled to the input terminal of the voltage stabilizing circuit 10. When the power adapter 2 is connected to the power management chip 11 (via wired or wireless means), the power management chip 11 converts the output voltage of the power adapter 2 into the input voltage of the voltage stabilizing circuit 10, which is then converted into the supply voltage of the load by the voltage stabilizing circuit 10. The enable signal output terminal of the controller 12 is coupled to the enable terminal of the voltage stabilizing circuit 10, and is used to output an enable signal to control the power on and off of the voltage stabilizing circuit 10.

[0034] Figure 2 The schematic diagram of the structure of a voltage stabilizing circuit 10 provided in an embodiment of the present application is shown, and the voltage stabilizing circuit 10 includes an LDO circuit 101. It should be noted that the voltage input end of the LDO circuit 101 is the input end of the voltage stabilizing circuit 10; the voltage output end of the LDO circuit 101 is the output end of the voltage stabilizing circuit 10. The LDO circuit 101 can realize the conversion of the power supply voltage, has the advantages of low cost, low noise and small quiescent current, and is usually used in the field of voltage reduction.

[0035] The LDO circuit 101 includes a bandgap reference module BR, a differential amplifier AMP, a switch tube Q1 (eg, a PMOS tube) and a voltage divider circuit F.

[0036] The enable terminal CON1 of the voltage stabilizing circuit 10 is coupled to the enable terminal of the bandgap reference module BR and the enable terminal of the differential amplifier AMP; the voltage input terminal of the bandgap reference module BR is coupled to the input terminal of the voltage stabilizing circuit 10, the first input terminal (e.g., the negative phase input terminal) of the differential amplifier AMP is coupled to the voltage output terminal of the bandgap reference module BR, the second input terminal (e.g., the positive phase input terminal) of the differential amplifier AMP is coupled to the voltage dividing node of the voltage dividing circuit F, the output terminal of the differential amplifier AMP is coupled to the control terminal of the switch tube Q1, the first controlled terminal of the switch tube Q1 is coupled to the voltage input terminal of the LDO circuit 101, and the second controlled terminal of the switch tube Q1 is coupled to the voltage output terminal of the LDO circuit 101; the voltage dividing circuit F is coupled to the voltage output terminal of the LDO circuit 101.

[0037] The voltage input terminal of the bandgap reference module BR is used to input the supply voltage Vin, and the enable terminal of the bandgap reference module BR is used to input the power supply voltage Vin from the controller (for example Figure 1 The controller 12 in the circuit 10 receives an enable signal EN1, and the voltage output terminal of the bandgap reference module BR is used to output a reference voltage Vref. The first input terminal (e.g., the negative input terminal) of the differential amplifier AMP is used to input the reference voltage Vref, the enable terminal of the differential amplifier AMP is used to input the enable signal EN1, and the output terminal of the differential amplifier AMP is coupled to the control terminal of the switch tube Q1. The first controlled terminal of the switch tube Q1 is the voltage input terminal of the LDO circuit 101 (also the input terminal IN of the voltage stabilizing circuit 10), and the second controlled terminal of the switch tube Q1 is the voltage output terminal of the LDO circuit 101 (also the output terminal OUT of the voltage stabilizing circuit 10). The first terminal of the voltage divider circuit F is coupled to the voltage output terminal of the LDO circuit 101, and the second terminal of the voltage divider circuit F is grounded GND.

[0038] The voltage divider circuit F includes a first resistor R1 and a second resistor R2, which are coupled in series between the voltage output terminal of the LDO circuit 101 and the ground GND, and the second end of the first resistor R1 and the first end of the second resistor R2 are coupled to the voltage divider node, that is, the first end of the first resistor R1 is coupled to the second controlled end of the switch tube Q1, the second end of the first resistor R1 is coupled to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The first resistor R1 and the second resistor R2 are used to divide the output voltage Vout1 of the LDO circuit 101 to obtain the feedback voltage Vf:

[0039] Vf=Vout1*R2 / (R1+R2)

[0040] The differential amplifier AMP amplifies the small error signal between the feedback voltage Vf and the reference voltage Vref. Taking the first input terminal as the negative phase input terminal and the second input terminal as the positive phase input terminal as an example, when the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP outputs a low level, and when the reference voltage Vref is less than the feedback voltage Vf, the differential amplifier AMP outputs a high level.

[0041] Taking the switch tube Q1 as a PMOS tube as an example, the gate of the PMOS tube is the control end of the switch tube Q1, the source of the PMOS tube is the first controlled end of the switch tube Q1, and the drain of the PMOS tube is the second controlled end of the switch tube Q1. When the gate voltage is lower than the source voltage, the PMOS tube is turned on, and when the gate voltage is higher than the source voltage, the PMOS tube is turned off.

[0042] The differential amplifier AMP, the voltage divider circuit F, and the switch tube Q1 constitute a negative feedback circuit, so that the output voltage Vout1 of the LDO circuit 101 is stabilized at a specified value. Specifically, Figure 2 The working process of the voltage stabilizing circuit 10 shown is:

[0043] In the initial state, although the LDO circuit 101 inputs the supply voltage Vin, and the first input terminal of the differential amplifier AMP inputs the reference voltage Vref, the enable signal EN1 is at a low level, and the differential amplifier AMP is in a high impedance state because it is disabled, and does not output voltage, the switch tube Q1 is turned off, and the output voltage Vout1 of the LDO circuit 101 is 0, so that the feedback voltage Vf is 0.

[0044] When the enable signal EN1 is at a high level, since the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP outputs a low level, the switch tube Q1 is turned on, and the output voltage Vout1 of the LDO circuit 101 rises rapidly, causing the feedback voltage Vf to rise rapidly. When the feedback voltage Vf rises to a level greater than the reference voltage Vref, the differential amplifier AMP outputs a high level, the switch tube Q1 is turned off, the output voltage Vout1 of the LDO circuit 101 begins to drop, and the feedback voltage Vf on the second resistor R2 also drops accordingly, until the reference voltage Vref is greater than the feedback voltage Vf, and the above process is repeated. Therefore, the output voltage Vout1 is stabilized at a preset value, which is equal to K times the reference voltage Vref.

[0045] Table 1 shows the above Figure 2 The truth table of the output voltage Vout1 of the voltage regulator circuit 10 (ie, the output voltage Vout1 of the LDO circuit 101) is shown in Table 1. As can be seen from Table 1, the output voltage Vout1 of the voltage regulator circuit 10 can be high only when the power supply voltage Vin is high and the enable signal EN1 is high.

[0046] Table 1

[0047]

[0048] Figure 3 Shown above Figure 2 The upper and lower electrical waveforms of the voltage stabilizing circuit 10 are as follows. After the supply voltage Vin is input, when the enable signal EN1 starts to rise from zero in a stepwise manner, it can be seen from 31 and 32 that Figure 2 When the output current I of the voltage regulator circuit 10 (ie, the output current I of the LDO circuit 101 ) rises rapidly, a surge current is generated; as can be seen from 33 and 34 , when the output voltage Vout1 of the voltage regulator circuit 10 rises rapidly, a peak voltage is generated.

[0049] In electronic devices, the surge current generated at the moment of power-on may cause breakdown damage to the load; in chip systems, the uncertain value of the spike voltage sometimes affects the functional judgment of the chip at the moment of power-on, and sometimes may even cause the chip to fail.

[0050] To solve the overshoot problem, Figure 2 The voltage stabilizing circuit 10 shown in the figure is improved, for example, Figure 2 Based on the voltage regulator circuit 10 shown, Figure 4 The voltage stabilizing circuit 10 shown further includes a soft start module 102 and an AND gate AND.

[0051] The signal output terminal of the slow start module 102 is coupled to the first input terminal of the AND gate AND, the enable terminal CON1 of the voltage stabilizing circuit 10 is coupled to the second input terminal of the AND gate AND, and the output terminal of the AND gate AND is coupled to the enable terminal of the differential amplifier AMP.

[0052] The voltage input terminal of the slow start module 102 is used to input the supply voltage Vin, the first input terminal of the AND gate AND is used to input the output voltage of the slow start module 102, and the second input terminal of the AND gate AND is used to input the output voltage from the controller (for example Figure 1 The enable signal EN1 of the controller 12 in the controller 100, the output signal of the soft start module 102 and the enable signal EN1 together enable the differential amplifier AMP through the AND gate AND.

[0053] Exemplarily, the slow start module 102 includes a capacitor C, a first end of the capacitor C is coupled to the input terminal IN of the voltage stabilizing circuit 10, and a second end of the capacitor C is coupled to the first input terminal of the AND gate AND. After the slow start module 102 inputs the supply voltage Vin, since the charge on the electrode of the capacitor C is gradually accumulated, the output voltage of the slow start module 102 rises slowly.

[0054] In addition to the slow start module 102 and the AND gate AND, Figure 4The structure of the voltage stabilizing circuit 10 shown is similar to Figure 2 The structure of the voltage stabilizing circuit 10 shown is the same as that of the Figure 2 The voltage stabilizing circuit 10 shown is the same as that shown in FIG. Figure 2 The voltage stabilizing circuit 10 shown is not described in detail here.

[0055] Figure 4 The working process of the voltage stabilizing circuit 10 shown is similar to Figure 2 The working process of the voltage stabilizing circuit 10 shown is similar, except that the output voltage of the slow start module 102 rises slowly, so when the enable signal EN1 is at a high level, the voltage at the first input terminal of the AND gate AND slowly rises to a high level, and is ANDed with the enable signal EN1, the AND gate AND will output a high level, and can jointly enable the differential amplifier AMP, so that the differential amplifier AMP starts to output voltage. When the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP slowly outputs a low level, the switch tube Q1 is gradually turned on, and the output voltage Vout1 of the LDO circuit 101 can slowly rise.

[0056] Table 2 shows Figure 4 The truth table of the output voltage Vout1 of the voltage regulator circuit 10 (ie, the output voltage Vout1 of the LDO circuit 101 ) is shown. Figure 4 The voltage stabilizing circuit 10 shown in FIG. Figure 2 Compared with the voltage stabilizing circuit 10 shown in FIG. Figure 4 The voltage stabilizing circuit 10 shown in the figure slows down the power-on speed of the output voltage Vout1 of the LDO circuit 101. Its truth table is similar to Figure 2 The voltage stabilizing circuit 10 shown is the same, and the output voltage Vout1 of the voltage stabilizing circuit 10 can be high only when the supply voltage Vin is at a high level and the enable signal EN1 is at a high level.

[0057] Table 2

[0058]

[0059] Figure 5 Shows Figure 4 The upper and lower power waveforms of the voltage stabilizing circuit 10 shown in FIG. 1 are shown. After the slow start module 102 is added, when the enable signal EN1 rises in a step, it can be seen from 51 and 52 that Figure 4 The output current I of the voltage regulator circuit 10 (ie, the output current I of the LDO circuit 101 ) has no impact current; as can be seen from 53 and 54 , the output voltage Vout1 of the voltage regulator circuit 10 has no peak voltage, but the power-on speed is slow.

[0060] Although the overshoot problem is solved by adding the slow start module 102 , the output voltage Vout1 of the voltage regulator circuit 10 is powered on slowly, which makes it difficult to meet the response speed requirements of certain loads in practical applications and sometimes even causes hardware circuit timing errors.

[0061] To solve the problem of slow power-on, Figure 4 The voltage stabilizing circuit 10 shown in the figure is improved, for example, Figure 4 Based on the voltage regulator circuit 10 shown, Figure 6 The voltage stabilizing circuit 10 shown also includes a switch circuit 103. The switch circuit 103 is coupled to the output end of the LDO circuit 101. When the LDO circuit 101 is continuously powered, the switch circuit 103 is controlled to be turned on or off to control whether the voltage stabilizing circuit 10 supplies power to a load (e.g. Figure 1 Since the voltage difference between the input and output ends of the switch circuit 103 is smaller when the LDO circuit 101 is continuously powered, the overshoot is smaller when it is quickly turned on and off, thereby achieving rapid power on and off of the voltage stabilizing circuit 10 while solving the overshoot problem.

[0062] Specifically, the output end of the LDO circuit 101 is coupled to the voltage input end of the switch circuit 103, and the voltage output end of the switch circuit 103 is used to supply power to the load 13. When the LDO circuit 101 is in a continuous power supply state, the controller (e.g. Figure 1 The controller 12 in the circuit 100 outputs an enable signal EN2 to the control terminal of the switch circuit 103 (which is also the enable terminal CON2 of the voltage stabilizing circuit 10) to control the switch circuit 103 to be turned on. At this time, the switch circuit 103 supplies power to the load. The controller 12 stops outputting the enable signal EN2 to the control terminal of the switch circuit 103 to control the switch circuit 103 to be turned off. At this time, the switch circuit 103 stops supplying power to the load. The switch circuit 103 can be implemented by a transistor, a switch tube, etc.

[0063] In a possible implementation, the switch circuit 103 includes a switch tube Q2. The control end of the switch tube Q2 is used to input an enable signal EN2, the first controlled end of the switch tube Q2 is the voltage input end of the switch circuit 103, and the second controlled end of the switch tube Q2 is the voltage output end of the switch circuit 103 (also the output end OUT of the voltage stabilizing circuit 10).

[0064] Exemplarily, when the switch tube Q2 is a PMOS tube, the gate of the PMOS tube is the control end of the switch tube Q2, the source of the PMOS tube is the first controlled end of the switch tube Q2, and the drain of the PMOS tube is the second controlled end of the switch tube Q2. When the gate voltage is lower than the source voltage, the PMOS tube is turned on, and when the gate voltage is higher than the source voltage, the PMOS tube is turned off. Therefore, when the enable signal EN2 is at a low level, the PMOS tube is turned on, and when the enable signal EN2 is at a high level, the PMOS tube is turned off.

[0065] In the embodiment of the present application, the connection relationship, structure and function of the LDO circuit 101 and the slow start module 102 can be referred to Figure 4 The relevant description of the voltage stabilizing circuit 10 is not repeated here.

[0066] In the embodiment of the present application, the working process of the voltage stabilizing circuit 10 is as follows:

[0067] After the power supply voltage Vin is input, when the enable signal EN1 is at a high level, the output voltage of the slow start module 102 rises slowly, the switch tube Q1 is gradually turned on, and the output voltage Vout1 of the LDO circuit 101 rises slowly. At this time, when the enable signal EN2 is at a low level, the switch tube Q2 is turned on, and the output voltage Vout2 of the voltage stabilizing circuit 10 rises slowly; when the enable signal EN2 is at a high level, the switch tube Q2 is turned off, and the output voltage Vout2 of the voltage stabilizing circuit 10 is at a low level.

[0068] The enable signal EN1 maintains a high level, and the output voltage Vout1 of the LDO circuit 101 maintains a high level. At this time, when the enable signal EN2 is at a low level, the switch tube Q2 is turned on, and the output voltage Vout2 of the voltage regulator circuit 10 is quickly powered on; when the enable signal EN2 is at a high level, the switch tube Q2 is turned off, and the output voltage Vout2 of the voltage regulator circuit 10 is quickly powered off.

[0069] Table 3 shows the above Figure 6 The truth table of the output voltage Vout2 of the voltage stabilizing circuit 10 is shown in FIG. 1 . Since the switch circuit 103 is coupled in series to the voltage output terminal of the LDO circuit 101, the circuit logic is in an AND relationship. When the enable signal EN1 is at a high level, the switch tube Q1 is turned on; when the enable signal EN2 is at a low level, the switch tube Q2 is turned on. Therefore, the output voltage Vout2 of the voltage stabilizing circuit 10 can be high only when the power supply voltage Vin is at a high level, the enable signal EN1 is at a high level, and the enable signal EN2 is at a low level.

[0070] Table 3

[0071]

[0072] Figure 7 Shown above Figure 6 The power-on and power-off waveforms of the voltage stabilizing circuit 10. As shown in 71, when the enable signal EN1 is at a high level and the enable signal EN2 is at a low level for the first time, the output voltage Vout2 of the voltage stabilizing circuit 10 is powered on slowly; as shown in 72 and 73, in the subsequent process, when the enable signal EN1 is at a high level and the enable signal EN2 is at a low level, the output voltage Vout2 of the voltage stabilizing circuit 10 can be powered on quickly.

[0073] To summarize, the voltage stabilizing circuit, chip system and electronic device provided in the embodiments of the present application can flexibly control the output voltage of the voltage stabilizing circuit by adding a switching circuit, thereby solving the overshoot problem and achieving fast power-on to meet the power-on timing requirements of the hardware circuit in practical applications.

[0074] like Figure 8 As shown, an embodiment of the present application provides a first chip system 80 , and the chip system 80 includes a voltage stabilizing circuit 10 .

[0075] like Fig. 9 As shown, the embodiment of the present application provides a second chip system 80. The chip system 80 includes an LDO circuit 101 and a slow start module 102 in the voltage stabilizing circuit 10, and the chip system is coupled to a switch circuit 103 in the voltage stabilizing circuit 10.

[0076] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and apparatuses can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0077] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one device or distributed on multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0078] In addition, each functional module in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0079] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with the medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0080] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A voltage stabilizing circuit, characterized in that: include: Input end, output end, low dropout linear regulator LDO circuit, slow start module and switch circuit; The input end of the voltage stabilizing circuit is coupled to the input end of the slow start module and the voltage input end of the LDO circuit, and the input end of the voltage stabilizing circuit is used to input the supply voltage; the output end of the slow start module is coupled to the control end of the LDO circuit, the voltage output end of the LDO circuit is coupled to the voltage input end of the switch circuit, and the voltage output end of the switch circuit is coupled to the output end of the voltage stabilizing circuit; The LDO circuit includes a bandgap reference module, a differential amplifier, a first switch tube and a voltage divider circuit; the differential amplifier includes a first input terminal, a second input terminal, an output terminal and a control terminal; the voltage divider circuit includes a voltage divider node; The voltage input terminal of the bandgap reference module is coupled to the input terminal of the voltage stabilizing circuit, and the enable terminal of the bandgap reference module is used to input a second enable signal; The first input end of the differential amplifier is coupled to the voltage output end of the bandgap reference module, the second input end of the differential amplifier is coupled to the voltage dividing node of the voltage dividing circuit, the output end of the differential amplifier is coupled to the control end of the first switch tube, the first controlled end of the first switch tube is coupled to the voltage input end of the LDO circuit, and the second controlled end of the first switch tube is coupled to the voltage output end of the LDO circuit; the control end of the differential amplifier is coupled to the output end of the slow start module; The voltage divider circuit is coupled to a voltage output terminal of the LDO circuit; The voltage stabilizing circuit also includes an AND gate; The signal output end of the slow start module is coupled to the first input end of the AND gate, the second input end of the AND gate is used to input a second enable signal, and the output end of the AND gate is coupled to the enable end of the differential amplifier; The slow start module is used to slow down the rise of the output voltage of the voltage output end of the LDO circuit by slowing down the rise of the output voltage of the slow start module when the input end of the voltage stabilizing circuit inputs the supply voltage; When the output voltage of the voltage output end of the LDO circuit no longer rises, the output end of the voltage stabilizing circuit supplies power to the load when the switch circuit is turned on, and stops supplying power to the load when the switch circuit is turned off.

2. The voltage stabilizing circuit according to claim 1, characterized in that: The switch circuit includes a second switch tube; The control end of the second switch tube is used to input a first enable signal, the first controlled end of the second switch tube is a voltage input end of the switch circuit, and the second controlled end of the second switch tube is a voltage output end of the switch circuit.

3. The voltage stabilizing circuit according to claim 2, characterized in that: The second switch tube is a P-type metal oxide semiconductor field effect transistor (PMOS) tube.

4. The voltage stabilizing circuit according to claim 1, characterized in that: The soft start module includes a capacitor.

5. The voltage stabilizing circuit according to any one of claims 1 to 4, characterized in that: The first switch tube is a PMOS tube.

6. The voltage stabilizing circuit according to any one of claims 1 to 4, characterized in that: The voltage divider circuit includes a first resistor and a second resistor; A first end of the first resistor is coupled to a voltage output end of the LDO circuit, a second end of the second resistor is grounded, and a second end of the first resistor and a first end of the second resistor are coupled to the voltage division node.

7. A chip system, characterized in that: Comprising the voltage stabilizing circuit as described in any one of claims 1 to 6.

8. A chip system, characterized in that: It comprises an LDO circuit and a soft start module in the voltage stabilizing circuit as described in any one of claims 1 to 6, and the chip system is coupled to a switch circuit in the voltage stabilizing circuit.

9. An electronic device, characterized in that: It comprises a voltage stabilizing circuit and a controller as described in any one of claims 1 to 6, wherein the controller is used to control the voltage stabilizing circuit to supply power to a load.

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