A method and apparatus for intelligent data plane reasoning

Abstract

This application proposes an intelligent data plane inference method and apparatus, comprising: receiving unprocessed data packets through a programmable switch; creating a feature header for the data packets when a preset inference point is met; writing feature information extracted from the data packets into the feature header; and sending the written data packets to an FPGA; performing inference based on the feature header using an inference model deployed on the FPGA; writing the inference result into the feature header; and sending the processed data packets to the programmable switch; performing custom traffic processing on the data packets based on the inference result carried in the feature header using the programmable switch; and removing the feature header from the data packets after processing. This invention, employing the above scheme, can achieve high-speed, high-precision data packet inference tasks, thereby enabling the classification and identification of different types of traffic in the data plane, and can be deployed and applied in ultra-high-speed networks with high-speed, complex traffic processing requirements.

Description

Technical Field

[0001] This application relates to the fields of next-generation Internet architecture, network intelligence, and ultra-high-speed programmable data plane technology, and in particular to intelligent data plane inference methods and devices. Background Technology

[0002] The diversification of internet applications and the increasing complexity of cybersecurity threats have placed higher demands on internet architecture. With the rapid development of technologies such as cloud computing, big data analytics, and artificial intelligence, more and more application scenarios require high-speed, reliable, and low-latency data transmission and processing capabilities. Traditional network architectures and data plane technologies face a series of challenges when dealing with these new application types, including high latency, low throughput, and a lack of adaptability and flexibility. In recent years, programmable data planes (PDPs) have emerged as a new technology that allows for flexible configuration and programming of data plane functions in network devices, enabling networks to quickly adapt to different application scenarios and needs. Furthermore, PDP technology, by introducing high-speed switching chips and programmable chips into network devices, achieves high-speed data packet processing and forwarding, providing network devices with higher performance and throughput. However, due to the limited hardware resources of current programmable switching chips, it is extremely difficult to achieve intelligent processing of network traffic on the data plane using only programmable switches. On the one hand, the number of static random access memory (SRAM) and register resources in programmable switches is limited, making it impossible to store neural network inference models for processing network traffic; on the other hand, programmable switches support a limited range of computational types, making it difficult to perform high-precision neural network inference model calculations. Therefore, the mainstream approach to analyzing and processing network traffic at the data plane currently involves experts using their professional knowledge and existing network traffic information to pre-label and process network traffic to meet different application scenarios and needs. This approach has three drawbacks: 1) Experts responsible for a portion of the network may have limitations in their professional knowledge; 2) Traffic patterns of some network switching devices may change over time; 3) Experts cannot effectively handle unknown traffic, including potentially malicious traffic. In fact, different network traffic types possess certain characteristics in their packet header information and flow distribution. However, relying solely on experts' prior knowledge to manually process this information is insufficient to meet the demands of today's complex traffic processing needs. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first objective of this application is to propose an intelligent data plane inference method that solves the technical problem that existing methods cannot meet the current complex traffic processing needs, and realizes high-speed and high-precision packet inference tasks. This enables the classification and identification of different types of traffic in the data plane, and is very suitable for deployment and application in ultra-high-speed networks with high-speed and complex traffic processing needs.

[0005] The second objective of this application is to propose an intelligent data plane reasoning device.

[0006] To achieve the above objectives, the first aspect of this application proposes an intelligent data plane inference method, comprising: receiving unprocessed data packets through a programmable switch; when the data packets meet a preset inference point, creating a feature header for the data packets, extracting feature information from the data packets, and writing the extracted feature information into the feature header to obtain a data packet with added features; and sending the data packet with added features to a field-programmable gate array (FPGA); receiving the data packet with added features through the FPGA, performing inference based on the feature header using an inference model deployed on the FPGA, writing the inference result into the feature header to obtain a processed data packet, and sending the processed data packet to the programmable switch; receiving the processed data packet through the programmable switch, performing custom traffic processing on the data packets based on the inference result carried in the feature header, and removing the feature header from the data packets after processing.

[0007] The intelligent data plane inference method of this application uses a field-programmable gate array (FPGA) chip to deploy a neural network inference model for traffic analysis. The FPGA chip provides highly parallel computing capabilities, exhibiting low latency and high throughput. Furthermore, due to its programmable logic units, traffic analysis models meeting different needs can be deployed simply by writing programs without replacing hardware. During the model training phase, appropriate flow-level and packet-level features are selected from network traffic data over a period of time as input data for the neural network model when processing traffic information. This data acquisition method not only improves the accuracy of traffic processing but also reduces the pressure of designing complex heuristic methods to process traffic with limited information. During model deployment, the trained model is quantized, allowing the neural network inference model deployed on the FPGA to be larger in scale and faster inference, better meeting the high throughput and low latency requirements of ultra-high-speed networks. Simultaneously, to fully utilize the existing programmable data plane hardware resources, the packet parsing capability of the programmable switching chip is used to extract feature information on the programmable switch. This application has the advantages of high accuracy, fast processing speed and strong scalability in network traffic processing and analysis in ultra-high-speed network scenarios. It can adapt to different traffic processing and analysis tasks and is very suitable for deployment and application in ultra-high-speed network scenarios with complex traffic processing requirements.

[0008] Optionally, in one embodiment of this application, the method further includes:

[0009] The programmable switch receives data packets and determines whether the data packet is unprocessed or processed based on its flag bits.

[0010] Optionally, in one embodiment of this application, before feature extraction from the unprocessed data packets, the method further includes:

[0011] Determine whether the data packet belongs to the stream data that has been recorded by the FPGA. If it does not belong, hash the five-tuple of the data packet and allocate register resources for the data packet.

[0012] Features include packet-level features and flow-level features. Extracting packet-level features from data packets includes reading the corresponding fields from the packet header.

[0013] Extracting flow-level features of data packets includes: statistically analyzing the flow feature information of each traffic stream using at least one register array;

[0014] Write the extracted feature information into the feature packet header, including writing the extracted feature information into a specified field of the feature packet header.

[0015] Optionally, in one embodiment of this application, before performing inference based on the feature packet header through the inference model deployed on the FPGA, the method further includes:

[0016] Build an inference model and deploy it on the FPGA;

[0017] Capture the characteristic header of data packets using FPGA;

[0018] Inference is performed based on the truncated feature packet header using an inference model, including:

[0019] The results of matrix multiplication are calculated simultaneously using at least one multiplier, and the calculated multiplication result vectors are grouped and added together to obtain the final result vector.

[0020] Optionally, in one embodiment of this application, constructing a reasoning model includes:

[0021] Data streams in ultra-high-speed network scenarios are collected, features of the data streams are extracted, and result vectors of the data streams are obtained. A training dataset is then constructed based on the features of the data streams and the result vectors.

[0022] The inference model is trained using a training dataset. During training, the features of the data stream are taken as input and the result vector is taken as output to obtain the trained inference model.

[0023] The trained inference model is quantized based on the Power-of-two method.

[0024] Optionally, in one embodiment of this application, before extracting the features of the data stream, the following steps are further included:

[0025] Construct a data set based on the collected data stream;

[0026] The data streams in the dataset are divided according to their respective business types to obtain a set of business types.

[0027] Optionally, in one embodiment of this application, the data set is represented as:

[0028] T = {T1,T2,...,T} n}

[0029] Among them, T n This represents the data stream with index n, where n represents the number of data streams.

[0030] The set of business types is represented as follows:

[0031] C = {C1,C2,...,C} n}

[0032] Among them, C nThis represents the business type with index n, where n represents the number of business types, and C1∪C2∪...∪C n =T,

[0033] Optionally, in one embodiment of this application, extracting features of the data stream includes:

[0034] Determine the flow characteristics and packet characteristics of the data stream;

[0035] For each data packet in each data stream, a feature vector is constructed based on the selected stream features and packet features, and the feature vector is decomposed into a fixed-point numerical decomposition to obtain a fixed-point feature vector. The number of fixed points decomposed in the fixed-point numerical decomposition is the same as the number of bits of the fixed-point number used in the quantization of the inference model.

[0036] Optionally, in one embodiment of this application, the feature vector is represented as:

[0037] F = [F1, F2, ..., F w ]

[0038] Among them, F w This indicates the feature information with index w, where w is the number of feature information.

[0039] The fixed-point eigenvector is represented as:

[0040] f = [f1, f2, ..., f w′ ]

[0041] Among them, f w′ This indicates the feature information with index w′, where w′ is the number of feature information after definite-point numerical decomposition.

[0042] Training the inference model includes:

[0043] Taking the feature vector f of the data packet as input, and the result vector R = [R1, R2, ..., R] as input, m The output is ], where m is the number of business types, and j = argmax. i (R i ), i∈[1,m.

[0044] To achieve the above objectives, a second aspect of the present invention provides an intelligent data plane inference device, comprising a programmable switch and a field-programmable gate array (FPGA), wherein,

[0045] The programmable switch is used to receive unprocessed data packets. When the data packet meets the preset inference point, it creates a feature header for the data packet, extracts the feature information of the data packet, writes the extracted feature information into the feature header, obtains a data packet with added features, and sends the data packet with added features to the field programmable gate array (FPGA).

[0046] The FPGA is used to receive data packets with added features, perform inference based on the feature packet header using its own deployed inference model, write the inference result into the feature packet header to obtain the processed data packet, and send the processed data packet to the programmable switch.

[0047] Programmable switches are also used to receive processed data packets, perform custom traffic processing on the data packets based on the inference results carried in the feature packet header, and remove the feature packet header from the data packets after processing.

[0048] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0049] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0050] Figure 1 This is a flowchart illustrating an intelligent data plane reasoning method provided in Embodiment 1 of this application;

[0051] Figure 2 This is a structural diagram of the intelligent data plane inference system according to an embodiment of this application;

[0052] Figure 3 This is a schematic diagram of the structure of an intelligent data plane inference device provided in an embodiment of this application. Detailed Implementation

[0053] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0054] The intelligent data plane reasoning method and apparatus of this application are described below with reference to the accompanying drawings.

[0055] Figure 1 This is a flowchart illustrating an intelligent data plane reasoning method provided in Embodiment 1 of this application.

[0056] like Figure 1As shown, the intelligent data plane reasoning method includes the following steps:

[0057] Step 101: Receive unprocessed data packets through a programmable switch. When the data packet meets the preset inference point, create a feature header for the data packet, extract the feature information of the data packet, and write the extracted feature information into the feature header to obtain a data packet with added features. Then, send the data packet with added features to the field programmable gate array (FPGA).

[0058] Step 102: Receive the data packet with added features through the FPGA, perform inference based on the feature packet header through the inference model deployed on the FPGA, write the inference result into the feature packet header to obtain the processed data packet, and send the processed data packet to the programmable switch.

[0059] Step 103: Receive the processed data packet through the programmable switch, perform custom traffic processing on the data packet based on the inference result carried in the feature packet header, and remove the feature packet header from the data packet after processing.

[0060] The intelligent data plane inference method of this application uses a field-programmable gate array (FPGA) chip to deploy a neural network inference model for traffic analysis. The FPGA chip provides highly parallel computing capabilities, exhibiting low latency and high throughput. Furthermore, due to its programmable logic units, traffic analysis models meeting different needs can be deployed simply by writing programs without replacing hardware. During the model training phase, appropriate flow-level and packet-level features are selected from network traffic data over a period of time as input data for the neural network model when processing traffic information. This data acquisition method not only improves the accuracy of traffic processing but also reduces the pressure of designing complex heuristic methods to process traffic with limited information. During model deployment, the trained model is quantized, allowing the neural network inference model deployed on the FPGA to be larger in scale and faster inference, better meeting the high throughput and low latency requirements of ultra-high-speed networks. Simultaneously, to fully utilize the existing programmable data plane hardware resources, the packet parsing capability of the programmable switching chip is used to extract feature information on the programmable switch. This application has the advantages of high accuracy, fast processing speed and strong scalability in network traffic processing and analysis in ultra-high-speed network scenarios. It can adapt to different traffic processing and analysis tasks and is very suitable for deployment and application in ultra-high-speed network scenarios with complex traffic processing requirements.

[0061] Optionally, in one embodiment of this application, traffic information is first collected in an ultra-high-speed network scenario. Specifically,

[0062] Suppose that n data streams are collected in the ultra-high-speed network of the neural network inference model to be deployed, forming a set T = {T1, T2, ..., T...} n}. Among them, T i ∈T refers to the data stream with index i in the data stream set. Each data stream is represented by a unique 5-tuple (source IP address, destination IP address, source port number, destination port number, and transport protocol).

[0063] Optionally, in one embodiment of this application, before extracting the features of the data stream, the collected traffic information is further divided; specifically,

[0064] For the collected data stream set T, the traffic is manually filtered and labeled according to its service type. Assume the collected data stream set contains m service types, and all service types form a set C = {C1, C2, ..., Cn}. n}. Among them, C j ∈C refers to the business type with index j in the set of business types. Each business type is a set of data streams T. i The set. Each business type contains no duplicate data streams, and all business types contain all data streams in T, that is...

[0065] (when j≠j′)

[0066] Optionally, in one embodiment of this application, feature extraction and numerical decomposition of the segmented traffic information are performed, including:

[0067] For the segmented traffic information, this embodiment extracts traffic feature information. Traffic feature information is divided into packet-level feature information and flow-level feature information. Packet-level feature information mainly refers to feature information that can be directly obtained from the packet header, while flow-level feature information mainly refers to statistical information that needs to be analyzed from the traffic packets, such as the average packet length of the data flow, the total number of packets contained in the data flow, and the number of bytes contained in the data flow. The selection of feature information can be changed according to different traffic processing tasks. For each packet of each data flow, a feature vector F = [F1, F2, ..., F] is constructed based on the selected flow feature information and packet feature information. w ], where F k ∈F refers to the feature information at index k in the feature vector, and w is the number of feature information. Since feature information cannot be represented using floating-point numbers on a programmable switching chip, the feature information here is rounded to integers. Because 8-bit fixed-point numbers are used during model quantization, during the feature extraction stage, for each feature information F within each feature vector...i According to F i The theoretical scope of F k The value is decomposed into t 8-bit fixed-point numbers. For example, F k From 0 to 2 8·j If the given number of unsigned integers is in the range -1, then use t integers f in the range 0 to 255. i F represents i ,Right now

[0068]

[0069] Thus, the new fixed-point eigenvector f = [f1, f2, ..., f w′ ], where f k′ ∈f refers to the index k in the fixed-point eigenvector. ′ The feature information is w′, where w′ is the number of feature information after fixed-point numerical decomposition.

[0070] Optionally, in one embodiment of this application, traffic characteristic information in the ultra-high-speed network for which the neural network inference model is to be deployed is obtained. This embodiment can train and quantize the neural network model for this network. Specifically, the training process includes:

[0071] Training a neural network model for traffic processing based on neural networks such as multilayer perceptrons or Transformers. Using the aforementioned feature extraction methods, each data packet in each data stream possesses a feature information vector f, and for each data packet belonging to the data stream T... i There is T i Business type C j This embodiment constructs a multilayer perceptron network or a Transformer network, taking f as input, and the result vector R = [R1, R2, ..., R...]. m As the output of the traffic processing neural network model, m is the number of service types, and for vector R, j = argmax. i (R i ), i∈[1,m]. In this embodiment, a supervised training method is used to train the multilayer perceptron model. In the traffic processing neural network model, this embodiment selects the linear rectified function as the activation function and the cross-entropy function as the loss function.

[0072] Optionally, in one embodiment of this application, the trained neural network model is quantized based on the Power-of-two method. Specifically,

[0073] This neural network model contains multiple floating-point matrices, and the inference process involves multiplying vectors and matrices. For one of these matrices M, if a simpler matrix M′ can be found such that for most vectors k·M≈k·M... ′ Then matrix M′ is the quantized result of matrix M. This quantization process is performed by the function Q(M), which is a quantization function based on the Power-of-two matrix quantization method, capable of mapping continuous values ​​to discrete power-law levels. For the quantized matrix M′, each number is represented by an 8-bit fixed-point number, and the range of the representation is determined by the data range of the input matrix during quantization.

[0074] Optionally, in one embodiment of this application, after obtaining a traffic processing neural network model trained based on traffic characteristic information in the current ultra-high-speed network and performing quantization, the traffic processing neural network model can be better deployed on a field-programmable gate array (FPGA). By deploying traffic feature extraction on a programmable switching chip and deploying the traffic processing neural network model on an FPGA, the parallel computing capabilities of the FPGA and the packet parsing capabilities of the programmable switching chip can be better utilized.

[0075] Figure 2 This embodiment describes an intelligent data plane inference system, which includes a programmable switch and an FPGA, such as... Figure 2 As shown, the system's processing steps include:

[0076] (1) Creating feature header information for neural network inference. Data packets exchange information between the programmable switch and the field-programmable gate array (FPGA) chip by carrying headers containing feature information and result information. The length of the header can be configured according to the length of the feature information. The feature header is assembled onto the data packet by the programmable switch chip when the data packet first enters the programmable switch, and is removed from the data packet when the data packet is finally forwarded out of the programmable switch.

[0077] (2) A high-speed data plane feature extraction method based on a programmable switching chip. On the programmable switching chip, for packet-level features, the corresponding fields can be directly read from the packet header and written to the corresponding positions in the feature header. Since the position of packet feature information in the data packet differs for different protocol types, it is necessary to uniformly write the packet feature information in the data packet to the specified fields in the feature header. For flow-level feature information, multiple register arrays are used in the programmable switch to statistically analyze the flow feature information of each flow, and after the statistics are compiled, the feature information is written to the specified fields in the feature header of the data packet. On the programmable switching chip, the hash value of the five-tuple of the flow to which the data packet belongs is used as the index value of the register array.

[0078] (3) Neural Network Model Inference for Flow Processing Based on Field-Programmable Gate Array (FPGA) Chips. Utilizing the parallel processing capability of FPGAs, multiple multipliers are used to simultaneously calculate the matrix multiplication results. After obtaining the multiplication results, the resulting vectors are grouped and added together to obtain a final result vector. The number of iterations increases with the number of layers in the multilayer perceptron.

[0079] (4) Processing method of data packets received by the programmable switch. After receiving a data packet, the programmable switch will use the flag bit to determine whether the data packet comes from the chip processed by the field-programmable gate array (FPGA). If the data packet comes from the FPGA chip, it will perform custom traffic processing based on the inference result information carried in the feature information packet header. After processing, the feature packet header will be removed from the data packet in step (1). If the data packet does not come from the FPGA chip, it will check whether the data packet belongs to the flow that has been recorded by the programmable switch chip. If it does, the data packet will be processed in step (5). If it does not, the five-tuple of the data packet will be hashed first, and register resources will be allocated for this new data flow. Then, the data packet will be processed in step (5).

[0080] (5) Method for processing data streams by a programmable switch. Since not all data packets in a data stream need to be inferred by the traffic processing neural network model, this embodiment configures inference points for the data stream. That is, when a specified number of data packets are received from the data stream, the data packets are forwarded to the field-programmable gate array (FPGA) chip for inference. The inference points of the data stream are configured as a set and sent to the programmable switch chip. When the programmable switch chip determines that the current data packet is located at an inference point, it creates a feature header for the data packet in step (1) and writes the feature information into the feature header in step (2). The data packet after writing is then forwarded to the FPGA chip for processing in steps (6) and (3).

[0081] (6) Processing method of data packets received by the field-programmable gate array (FPGA) chip. After receiving a data packet, the FPGA chip needs to extract the feature header portion and input it into the neural network model because the data packet contains headers and payload fields other than the feature information header. The extracted fields are processed in step (3), and the result is written into the result field in the feature header before the complete data packet is forwarded to the programmable switch.

[0082] To implement the above embodiments, this application also proposes an intelligent data plane inference device.

[0083] Figure 3 This is a schematic diagram of the structure of an intelligent data plane inference device provided in an embodiment of this application.

[0084] like Figure 3 As shown, the intelligent data plane inference device includes a programmable switch and a field-programmable gate array (FPGA), wherein,

[0085] The programmable switch is used to receive unprocessed data packets. When the data packet meets the preset inference point, it creates a feature header for the data packet, extracts the feature information of the data packet, writes the extracted feature information into the feature header, obtains a data packet with added features, and sends the data packet with added features to the field programmable gate array (FPGA).

[0086] The FPGA is used to receive data packets with added features, perform inference based on the feature packet header using its own deployed inference model, write the inference result into the feature packet header to obtain the processed data packet, and send the processed data packet to the programmable switch.

[0087] Programmable switches are also used to receive processed data packets, perform custom traffic processing on the data packets based on the inference results carried in the feature packet header, and remove the feature packet header from the data packets after processing.

[0088] It should be noted that the foregoing explanation of the intelligent data plane reasoning method embodiment also applies to the intelligent data plane reasoning device of this embodiment, and will not be repeated here.

[0089] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0091] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0092] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0093] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0094] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0095] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0096] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. An intelligent data plane inference method, characterized in that, The method comprises the following steps: receiving an unprocessed data packet by a programmable switch, creating a feature packet header for the data packet when the data packet meets a preset inference point, extracting feature information of the data packet, and writing the extracted feature information into the feature packet header to obtain a feature-added data packet, and sending the feature-added data packet to a field programmable gate array (FPGA); receiving the feature-added data packet by the FPGA, performing inference based on the feature packet header by an inference model deployed on the FPGA, writing an inference result into the feature packet header to obtain a processed data packet, and sending the processed data packet to the programmable switch; receiving the processed data packet by the programmable switch, performing self-defined traffic processing on the data packet based on the inference result carried on the feature packet header, and removing the feature packet header from the data packet after processing.

2. The method of claim 1, wherein, The method further comprises: receiving a data packet by the programmable switch, and judging whether the data packet is an unprocessed data packet or a processed data packet based on a flag bit of the data packet.

3. The method of claim 1, wherein, Before extracting features of the unprocessed data packet, the method further comprises: judging whether the data packet belongs to flow data that has been recorded by the FPGA, and if not, performing hashing on five-tuple of the data packet, and allocating register resources for the data packet; the features include packet-level features and flow-level features, the packet-level features of the data packet are extracted by reading corresponding fields from a packet header; the flow-level features of the data packet are extracted by performing statistics on flow feature information of each piece of traffic by at least one register array; the extracted feature information is written into the feature packet header by writing the extracted feature information into designated fields of the feature packet header.

4. The method according to any one of claims 1 to 3, characterized in that, Before performing inference based on the feature packet header by the inference model deployed on the FPGA, the method further comprises: constructing the inference model, and deploying the constructed inference model on the FPGA; intercepting the feature packet header of the data packet by the FPGA; performing inference based on the intercepted feature packet header by the inference model, comprising: using at least one multiplier to simultaneously calculate a result of matrix multiplication, and performing grouped addition on a calculated multiplication result vector to obtain a result vector.

5. The method of claim 1, wherein, The inference model is constructed by: collecting data flows in a super-high-speed network scenario, extracting features of the data flows, and obtaining a result vector of the data flows, and constructing a training data set based on the features and the result vector of the data flows; training the inference model using the training data set, taking the features of the data flows as input and taking the result vector as output during the training to obtain a trained inference model; quantizing the trained inference model based on a Power-of-two method.

6. The method of claim 5, wherein, Before extracting the features of the data flows, the method further comprises: constructing a data set based on the collected data flows; dividing the data flows in the data set according to their business types to obtain a business type set.

7. The method of claim 6, wherein, The data set is represented as: wherein, denotes a data stream with index n, n denotes the number of data streams; The business type set is represented as: wherein represents a service type with index n, n representing a number of service types, , .

8. The method of claim 7, wherein, The features of the data flows are extracted by: determining flow features and packet features of the data flows; For each data packet of each data stream, a feature vector is constructed based on the selected stream features and packet features, and a fixed-point numerical decomposition is performed on the feature vector to obtain a fixed-point feature vector, wherein the fixed-point numbers decomposed in the fixed-point numerical decomposition have the same number of bits as the fixed-point numbers used in the quantization of the inference model.

9. The method of claim 8, wherein, The feature vector is represented as: wherein represents the characteristic information with the index is the number of characteristic information;​ The fixed-point feature vector is represented as: wherein, represents the index of the characteristic information, is the number of characteristic information after the fixed-point numerical resolution; The inference model is trained, including: The feature vector f of the data packet is taken as input, and the result vector is taken as output for training, wherein is the number of service types, .

10. An intelligent data plane inference apparatus, characterized in that, The programmable switch and the field programmable gate array (FPGA) are included, wherein, The programmable switch is configured to receive an unprocessed data packet, create a feature packet header for the data packet when the data packet meets a preset inference point, extract feature information of the data packet, write the extracted feature information into the feature packet header to obtain a data packet with added features, and send the data packet with added features to the field programmable gate array (FPGA); The FPGA is configured to receive the data packet with added features, perform inference based on the feature packet header through a deployed inference model, write the inference result into the feature packet header to obtain a processed data packet, and send the processed data packet to the programmable switch; The programmable switch is further configured to receive the processed data packet, perform custom traffic processing on the data packet based on the inference result carried on the feature packet header, and remove the feature packet header from the data packet after processing.

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