Intra prediction method and device, chip, electronic equipment and storage medium

Abstract

The present disclosure provides an intra prediction method and device, a chip, an electronic device and a storage medium. The intra prediction method comprises: reordering a plurality of prediction blocks in a coding unit; reading reference side information of a next prediction block adjacent to a current prediction block after reordering; and after intra prediction of the current prediction block is completed, processing the reference side information of the next prediction block to obtain an intra prediction result of the next prediction block. The present disclosure adopts a general pipeline architecture, adapts to multiple video coding standards and future formats, has high freedom and strong adaptability. The reordering strategy adopted optimizes the prediction timing, can prepare the reference side information of the next prediction block in advance, realizes seamless prediction starting, allows parallel execution of dependency judgment and address calculation, and improves the intra prediction efficiency.

Description

Technical Field

[0001] This disclosure belongs to the field of video decoding technology and relates to intra-frame prediction methods and apparatus, chips, electronic devices and storage media. Background Technology

[0002] During video decoding, intra-frame prediction requires using reference edge information of the current prediction block, such as the pixel values ​​to the left, bottom left, top left, top, and top right, to predict the pixel values ​​of the current prediction block. To achieve this, the hardware architecture needs to allocate sufficient storage space to store this reference edge information. However, as video resolution increases, the size of both decoding and prediction blocks also increases, meaning that even more reference edge information needs to be stored.

[0003] In existing technologies, a large amount of reference side information may be directly stored in registers. The numerous multiplexers (MUX) generated by each register result in extensive wiring during placement and routing, consuming significant chip area, increasing hardware costs, and exacerbating the AOI (AND-OR-Invert) problem. Furthermore, existing video decoding methods require waiting for all reference side information to be ready before prediction calculations can be performed, which significantly reduces decoding speed and limits system performance improvements. Summary of the Invention

[0004] This disclosure provides intra-frame prediction methods and apparatus, chips, electronic devices, and storage media, which can optimize the processing timing of prediction block reference edge information and improve the efficiency of intra-frame prediction.

[0005] In a first aspect, embodiments of this disclosure provide an intra-frame prediction method. The intra-frame prediction method includes: reordering multiple prediction blocks within a coding unit; reading reference edge information of the next prediction block adjacent to the current prediction block after reordering; and, after the intra-frame prediction of the current prediction block is completed, processing the reference edge information of the next prediction block to obtain the intra-frame prediction result of the next prediction block.

[0006] In one implementation of the first aspect, the intra-frame prediction method further includes: acquiring syntax elements decoded from the bitstream information by the decoder, and parsing the syntax elements into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction; wherein reordering multiple prediction blocks within a coding unit includes: reordering multiple prediction blocks within the received coding unit based on the first instruction; wherein reading reference edge information of the next prediction block adjacent to the current prediction block after reordering includes: reading reference edge information of the next prediction block adjacent to the current prediction block after reordering from a memory based on the second instruction and the third instruction; and wherein processing the reference edge information of the next prediction block to obtain an intra-frame prediction result of the next prediction block includes: after completing the intra-frame prediction of the current prediction block, processing the reference edge information of the next prediction block based on the fourth instruction to obtain an intra-frame prediction result of the next prediction block.

[0007] In one implementation of the first aspect, reordering multiple prediction blocks within a coding unit includes: determining the dependency relationship between a first prediction block, a second prediction block, and a third prediction block; if there is a dependency relationship between the first prediction block and the second prediction block, and the third prediction block does not have a dependency relationship with the first prediction block and the second prediction block, then the third prediction block is inserted between the first prediction block and the second prediction block to reorder the multiple prediction blocks.

[0008] In one implementation of the first aspect, reordering multiple prediction blocks within an encoding unit includes: obtaining the color space components of each prediction block, the color space components including chroma components or luminance components, a prediction block containing the chroma component being defined as a chroma prediction block, and a prediction block containing the luminance component being defined as a luminance prediction block; performing an initial sorting of the multiple prediction blocks within the encoding unit according to a rule of considering the luminance component first and then the chroma component; and placing the chroma prediction block between two adjacent luminance prediction blocks to complete the reordering of the multiple prediction blocks within the encoding unit.

[0009] In one implementation of the first aspect, reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering, based on the second instruction and the third instruction, includes: loading the reference edge information of the prediction blocks from the memory according to the reordered order of the prediction blocks, based on the second instruction; temporarily storing the reference edge information of the prediction blocks and allocating a specific storage address for each reference edge information of the prediction blocks; determining whether there is a dependency relationship between the next prediction block and the current prediction block; if there is no dependency relationship, passing the third instruction downstream; otherwise, waiting for the current prediction block to complete intra-frame prediction before passing the third instruction downstream; calculating the storage address of the reference edge information of the next prediction block; and preloading the reference edge information of the next prediction block from the storage address based on the third instruction.

[0010] In one implementation of the first aspect, determining whether there is a dependency relationship between the next prediction block and the current prediction block and calculating the storage address of the reference edge information of the next prediction block are performed in parallel.

[0011] In one implementation of the first aspect, determining whether there is a dependency relationship between the next prediction block and the current prediction block includes: recording the maintenance area defined by the right preset column and the bottom preset row of the current prediction block; sampling the left preset column and the top preset row of the next prediction block according to a preset sampling interval to obtain a number of reference edge sampling points; determining whether at least one of the reference edge sampling points falls within the maintenance area; if so, determining that there is a dependency relationship between the next prediction block and the current prediction block; and otherwise, determining that there is no dependency relationship between the next prediction block and the current prediction block.

[0012] In one implementation of the first aspect, processing the reference edge information of the next prediction block to obtain the intra-prediction result of the next prediction block includes: calculating the filtering parameters and prediction parameters required for intra-prediction of the next prediction block; filling and filtering the reference edge information of the next prediction block based on the filtering parameters to obtain filtered reference edge information; and predicting and reconstructing the filtered reference edge information based on the prediction parameters to obtain the intra-prediction result of the next prediction block.

[0013] In one implementation of the first aspect, the intra-prediction method further includes: temporarily storing the intra-prediction result of the next prediction block to iteratively update the reference edge information of the temporarily stored prediction block.

[0014] In one implementation of the first aspect, the intra-frame prediction method further includes: determining whether the current prediction block is located at the last line at the bottom of the coding unit; if so, after completing the intra-frame prediction of the current prediction block, backing up the intra-frame prediction result of the current prediction block to the memory for use when the prediction blocks of subsequent coding units perform intra-frame prediction; otherwise, no backup processing is performed.

[0015] Secondly, embodiments of this disclosure provide an intra-prediction apparatus. The intra-prediction apparatus includes: a sequence adjustment module configured to reorder multiple prediction blocks within a coding unit; a reference edge information reading module configured to read reference edge information of the next prediction block adjacent to the current prediction block after reordering; and a reference edge information processing module configured to process the reference edge information of the next prediction block after the intra-prediction of the current prediction block is completed, to obtain the intra-prediction result of the next prediction block.

[0016] In one implementation of the second aspect, the intra-prediction apparatus further includes: an instruction parsing module configured to acquire syntax elements decoded from the bitstream information by the decoder, and parse the syntax elements into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction; wherein the order adjustment module is configured to reorder multiple prediction blocks within the received coding unit based on the first instruction; wherein the reference side information reading module is configured to read reference side information of the next prediction block adjacent to the current prediction block after reordering from the memory based on the second instruction and the third instruction; and wherein the reference side information processing module is configured to process the reference side information of the next prediction block based on the fourth instruction after completing the intra-prediction of the current prediction block to obtain the intra-prediction result of the next prediction block.

[0017] In one implementation of the second aspect, the reference edge information reading module includes: a reference edge loading module configured to load the reference edge information of the prediction blocks from the memory according to the reordered order of the prediction blocks based on the second instruction; a temporary storage module configured to temporarily store the reference edge information of the prediction blocks and allocate a specific storage address for each reference edge information of the prediction blocks; a dependency judgment module configured to determine whether there is a dependency relationship between the next prediction block and the current prediction block; if there is no dependency relationship, the third instruction is passed downstream; otherwise, the third instruction is passed downstream only after the current prediction block completes intra-frame prediction; a data fetch address calculation module configured to calculate the storage address of the reference edge information of the next prediction block in the temporary storage module; and a reference edge preloading module configured to preload the reference edge information of the next prediction block from the storage address in the temporary storage module based on the third instruction.

[0018] In one implementation of the second aspect, the dependency judgment module and the data retrieval address calculation module work in parallel.

[0019] In one implementation of the second aspect, the temporary storage module includes a random access memory unit and a cache unit.

[0020] In one implementation of the second aspect, the reference edge preloading module is configured to: search for reference edge information of the next prediction block in the cache unit based on the third instruction; if the search is successful, directly obtain the reference edge information of the next prediction block from the cache unit; otherwise, obtain the reference edge information of the next prediction block from the random storage unit based on the storage address, and update the reference edge information of the next prediction block in the cache unit.

[0021] Thirdly, embodiments of this disclosure provide a chip. The chip includes: a decoder configured to decode syntax elements from bitstream information; a memory configured to store reference side information of a plurality of prediction blocks within a coding unit, and to store intra-frame prediction results of the prediction blocks in the bottom last row of the coding unit; and an intra-frame prediction apparatus according to any one of the preceding claims.

[0022] Fourthly, embodiments of this disclosure provide an electronic device. The electronic device includes: a memory configured to store an executable program; and a processor configured to execute the program to cause the electronic device to perform the intra-frame prediction method according to any one of the preceding claims.

[0023] Fifthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon. When executed, the program implements the intra-frame prediction method according to any of the preceding claims.

[0024] As described above, the intra-frame prediction method, apparatus, chip, electronic device, and storage medium according to the embodiments of this disclosure adopt a general-purpose pipeline architecture, which is compatible with multiple video coding standards such as H.265, H.264, VP9, ​​AVS2, and AV1, and is easily expandable to support future video formats. It allows for flexible addition and removal of modules, offering high freedom and adaptability. Simultaneously, by integrating random access memory and cache units in the storage structure, it effectively avoids the hardware resource consumption and AOI problems caused by using a large number of multiplexers in traditional designs. The reordering strategy deeply considers the dependencies between different color components, optimizes the prediction timing, and improves decoding speed. The dependency pre-judgment mechanism allows the reference edge information of the next prediction block to be prepared in advance, without waiting for the current prediction block to empty the prediction path, thus achieving seamless prediction startup. It allows dependency judgment and data fetching address calculation to be executed in parallel, improving the efficiency of intra-frame prediction and demonstrating economy in resource utilization. Attached Figure Description

[0025] Figure 1 The diagram shown is a structural schematic of the prediction calculation unit and prediction block described in an embodiment of the present disclosure.

[0026] Figure 2 The diagram shown is a schematic representation of the division of the coding units described in this disclosure in one embodiment.

[0027] Figure 3 The flowchart shown is an embodiment of the intra-frame prediction method described in this disclosure.

[0028] Figure 4 The diagram shown is a structural schematic of the chip described in one embodiment of the present disclosure.

[0029] Figure 5a The diagram shown is a structural schematic of an intra-frame prediction apparatus according to an embodiment of the present disclosure.

[0030] Figure 5b The diagram shown is a structural schematic of the intra-frame prediction apparatus described in this disclosure in another embodiment.

[0031] Figure 6a The diagram shows the initial arrangement of the six PUs described in this embodiment.

[0032] Figure 6b The diagram shows a reordering of the six PUs described in this embodiment.

[0033] Figure 7 The diagram shown is a structural schematic of the maintenance area described in one embodiment of the present disclosure.

[0034] Figure 8a The diagram shown is a structural schematic of a reference edge sampling point as described in an embodiment of this disclosure.

[0035] Figure 8b The diagram shown is a structural schematic of the reference edge sampling point described in an embodiment of this disclosure in another embodiment.

[0036] Figure 9a The diagram shows a reference edge preloading process for the six PUs described in one embodiment of the present disclosure.

[0037] Figure 9b The diagram shows a reference edge preloading process for the six PUs described in this embodiment of the present disclosure in another embodiment.

[0038] Figure 10 The diagram shown is a structural schematic of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0039] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0040] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this disclosure.

[0042] To facilitate understanding of the technical solutions provided in the embodiments of this disclosure, the key terms that may be involved in the embodiments of this disclosure will first be explained in detail.

[0043] The basic unit of intra-frame prediction is the prediction block (PU). Each PU uses the values ​​of adjacent reconstructed pixels within the same video frame as reference edge information to perform pixel prediction. The reference edge information includes the pixels to the left, lower left, upper left, above, and upper right of the prediction block currently being predicted (hereinafter referred to as the current prediction block).

[0044] It should be noted that the selection of reference edge information is related to the prediction mode. For example, in some prediction modes, the reference edge information for intra-frame prediction may only include the left, upper left, and upper pixels, but regardless of the selection, the range of reference pixels will not exceed the range of left, lower left, upper left, upper, and upper right.

[0045] The PU will be further divided into smaller predictive computing units (PCUs). Figure 1 This is a schematic diagram illustrating the structure of a prediction computation unit and a prediction block according to an embodiment of the present disclosure in one embodiment. In existing prediction modes, a large amount of reference edge information is typically stored in registers. When performing prediction computation for each PCU, a selection needs to be made from this large amount of reference edge information. As the number of selectable reference information increases, the complexity of the hardware implementation also increases, which may lead to an increase in chip area, thereby affecting area utilization and exacerbating AOI problems.

[0046] The dependencies between different functional units (PUs) have a significant impact on decoding efficiency. These dependencies refer to the fact that the prediction calculation process of one PU may need to wait for the prediction tasks of its neighboring PUs to complete before it can begin. Figure 2 This is a schematic diagram illustrating the partitioning of coding units according to embodiments of the present disclosure in one embodiment, revealing potential dependencies between PUs. For example... Figure 2 As shown, a particular PU may depend on its neighboring PUs. For example, PU4 may depend on PU1, PU2, and PU3.

[0047] It should be noted that a PU is not necessarily dependent on all its neighboring PUs. The dependency between PUs depends on the location of each PU, the prediction mode used, and the color space components present.

[0048] The following will describe in detail, with reference to the accompanying drawings, the principles and implementation methods of an intra-frame prediction method and apparatus, chip, electronic device and storage medium of this embodiment, so that those skilled in the art can understand the technical solution of this disclosure without creative effort.

[0049] Figure 3 This is a flowchart illustrating an embodiment of the intra-frame prediction method according to an embodiment of the present disclosure. For example... Figure 3 As shown, this embodiment provides an intra-frame prediction method. The intra-frame prediction method includes the following steps S100 to S300.

[0050] In step S100, multiple prediction blocks within the coding unit are reordered.

[0051] In step S200, the reference edge information of the next prediction block adjacent to the current prediction block after reordering is read.

[0052] In step S300, after the intra-prediction of the current prediction block is completed, the reference edge information of the next prediction block is processed to obtain the intra-prediction result of the next prediction block.

[0053] In one embodiment of this disclosure, the intra-frame prediction method provided in this embodiment further includes step S400: obtaining the syntax elements decoded by the decoder from the bitstream information, and parsing the syntax elements into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction.

[0054] In some embodiments, reordering multiple prediction blocks within a coding unit includes: reordering the received multiple prediction blocks within the coding unit based on the first instruction. Reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering includes: reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering from memory based on the second instruction and the third instruction. Processing the reference edge information of the next prediction block to obtain the intra-prediction result of the next prediction block includes: after completing the intra-prediction of the current prediction block, processing the reference edge information of the next prediction block based on the fourth instruction to obtain the intra-prediction result of the next prediction block.

[0055] In one embodiment of this disclosure, step S100 of reordering multiple prediction blocks within a coding unit may include: determining the dependency relationship between a first prediction block, a second prediction block, and a third prediction block. If there is a dependency relationship between the first prediction block and the second prediction block, and the third prediction block does not have a dependency relationship with either the first or the second prediction block, then the third prediction block is inserted between the first and the second prediction blocks to reorder the multiple prediction blocks.

[0056] In another embodiment of this disclosure, the step S100 of reordering multiple prediction blocks within a coding unit may include steps S101 to S103.

[0057] In step S101, the color space components of each prediction block are obtained. The color space components include chroma components or luminance components. A prediction block with chroma components is defined as a chroma prediction block, and a prediction block with luminance components is defined as a luminance prediction block.

[0058] In step S102, the multiple prediction blocks within the coding unit are initially sorted according to the rule of considering the luminance component first and then the chrominance component.

[0059] In step S103, the chroma prediction block is placed between two adjacent luminance prediction blocks to complete the reordering of several prediction blocks within the coding unit.

[0060] In one embodiment of this disclosure, reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering from the memory based on the second instruction and the third instruction may include the following steps S201 to S205.

[0061] In step S201, based on the second instruction, the reference edge information of the prediction blocks is loaded from the memory according to the reordered order of the prediction blocks.

[0062] In step S202, the reference edge information of the prediction block is temporarily stored, and a specific storage address is allocated for the reference edge information of each prediction block.

[0063] In step S203, it is determined whether there is a dependency relationship between the next prediction block and the current prediction block. If there is no dependency relationship, the third instruction is passed downstream. Otherwise, the third instruction is passed downstream only after the current prediction block completes intra-frame prediction.

[0064] Specifically, determining whether there is a dependency between the next prediction block and the current prediction block includes: recording the maintenance area defined by the right preset column and the bottom preset row of the current prediction block; sampling the left preset column and the top preset row of the next prediction block according to a preset sampling interval to obtain several reference edge sampling points; determining whether at least one of the reference edge sampling points falls within the maintenance area; if so, determining that there is a dependency between the next prediction block and the current prediction block; otherwise, determining that there is no dependency between the next prediction block and the current prediction block.

[0065] In step S204, the storage address of the reference edge information of the next prediction block is calculated.

[0066] In step S205, based on the third instruction, the reference edge information of the next prediction block is preloaded from the storage address.

[0067] In this embodiment of the disclosure, determining whether there is a dependency relationship between the next prediction block and the current prediction block and calculating the storage address of the reference edge information of the next prediction block are performed in parallel.

[0068] In one embodiment of this disclosure, step S300, which processes the reference edge information of the next prediction block to obtain the intra-prediction result of the next prediction block, may include steps S301 to S303.

[0069] In step S301, the filtering parameters and prediction parameters required for intra-frame prediction of the next prediction block are calculated.

[0070] In step S302, based on the filtering parameters, the reference edge information of the next prediction block is filled and filtered to obtain the filtered reference edge information.

[0071] In step S303, based on the prediction parameters, the filtered reference edge information is predicted and reconstructed to obtain the intra-frame prediction result of the next prediction block.

[0072] In one embodiment of this disclosure, the intra-frame prediction method provided in this embodiment further includes step S500: temporarily storing the intra-frame prediction result of the next prediction block, so as to iteratively update the reference edge information of the temporarily stored prediction block.

[0073] In one embodiment of this disclosure, the intra-frame prediction method provided in this embodiment further includes step S600: determining whether the current prediction block is located in the last row at the bottom of the coding unit. If so, after completing the intra-frame prediction of the current prediction block, the intra-frame prediction result of the current prediction block is backed up to the memory for use when the prediction blocks of subsequent coding units perform intra-frame prediction; otherwise, no backup processing is performed.

[0074] It should be noted that the scope of protection of the intra-frame prediction method described in this disclosure is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this disclosure is included within the scope of protection of this disclosure.

[0075] Figure 4 This is a schematic diagram illustrating the structure of a chip according to an embodiment of the present disclosure in one embodiment. For example... Figure 4 As shown, this embodiment provides a chip. The chip includes a decoder 10, a memory 20, and an intra-frame prediction device 30.

[0076] In one embodiment of this disclosure, the decoder 10 is configured to decode syntax elements from the bitstream information.

[0077] In some embodiments, Cabac is used as the decoder 10. Specifically, the bitstream information to be decoded is input into Cabac, which decodes the syntax elements from the bitstream information. The syntax elements are generated during the encoding process and contain important information from the video images. Further, Cabac seamlessly concatenates the decoded syntax elements and sends the concatenated syntax elements to the intra-frame prediction device 30.

[0078] In one embodiment of this disclosure, the memory 20 is configured to store reference edge information of a plurality of prediction blocks within a coding unit, and to store the intra-frame prediction results of the prediction blocks in the bottom last row of the coding unit.

[0079] In some embodiments, the memory 20 is a double-rate synchronous dynamic random access memory (DDR). DDR is a high-performance memory technology with high transfer rates and bandwidth, suitable for storing pixel values ​​of a large number of encoded prediction blocks.

[0080] When performing intra-frame prediction, the intra-frame prediction device 30 can access the memory 20 to obtain the pixel values ​​of the encoded prediction block as reference information in order to provide accurate prediction for the current prediction block.

[0081] Figure 5a This is a schematic diagram illustrating the structure of an intra-frame prediction apparatus according to an embodiment of the present disclosure in one embodiment. For example... Figure 5aAs shown, this embodiment provides an intra-frame prediction device 30. The intra-frame prediction device 30 includes an order adjustment module 31, a reference edge information reading module 32, and a reference edge information processing module 33.

[0082] The order adjustment module 31 is configured to reorder multiple prediction blocks within the coding unit.

[0083] The reference edge information reading module 32 is configured to read the reference edge information of the next prediction block that is adjacent to the current prediction block after reordering.

[0084] The reference edge information processing module 33 is configured to process the reference edge information of the next prediction block after the intra-prediction of the current prediction block is completed, so as to obtain the intra-prediction result of the next prediction block.

[0085] Figure 5b This is a schematic diagram showing the structure of the intra-frame prediction apparatus according to an embodiment of the present disclosure in another embodiment.

[0086] In one embodiment of this disclosure, the intra-prediction apparatus further includes an instruction parsing module 34. The instruction parsing module 34 is configured to acquire syntax elements decoded from the bitstream information by the decoder 10, and parse the syntax elements into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction. The order adjustment module 31 is configured to reorder multiple prediction blocks within the received coding unit based on the first instruction. The reference side information reading module 32 is configured to read the reference side information of the next prediction block adjacent to the current prediction block after reordering from the memory 20 based on the second instruction and the third instruction. The reference side information processing module 33 is configured to, after completing the intra-prediction of the current prediction block, process the reference side information of the next prediction block based on the fourth instruction to obtain the intra-prediction result of the next prediction block.

[0087] In one embodiment of this disclosure, the order adjustment module 31 is configured to determine the dependencies between the first prediction block, the second prediction block, and the third prediction block. If there is a dependency between the first prediction block and the second prediction block, and the third prediction block does not have a dependency between the first prediction block and the second prediction block, then the third prediction block is inserted between the first prediction block and the second prediction block to reorder the multiple prediction blocks.

[0088] In another embodiment of this disclosure, the order adjustment module 31 is configured to acquire the color space components of each prediction block, wherein the color space components include chroma components or luminance components. A prediction block containing the chroma component is defined as a chroma prediction block, and a prediction block containing the luminance component is defined as a luminance prediction block. Based on the rule of considering the luminance component first and then the chroma component, the multiple prediction blocks within the coding unit are initially ordered. The chroma prediction block is placed between two adjacent luminance prediction blocks to complete the reordering of the multiple prediction blocks within the coding unit.

[0089] In existing video coding standards, such as H.265 / HEVC, a CU typically contains multiple PUs, and each PU corresponds to a specific color space component. Taking the YUV420 image format CU as an example, a CU consists of 6 PUs, from PU0 to PU5. Among them, PU0 to PU3 correspond to the luma component (i.e., luminance information), while PU4 corresponds to the cb component, and PU5 corresponds to the cr component. Both the cb and cr components are chrominance information.

[0090] Assume that PU0 depends on PU1, PU2 depends on PU1, and PU3 depends on PU2. Figure 6a This is a schematic diagram illustrating the initial arrangement of the six PUs according to an embodiment of the present disclosure in one embodiment. For example... Figure 6a As shown, the initial sorted PU sequence is: PU0(luma)->PU1(luma)->PU2(luma)->PU3(luma)->PU4(cb)->PU5(cr).

[0091] In this embodiment of the disclosure, based on the fact that there is no mutual dependency between the luma component, cb component and cr component, the PU blocks of cb component and cr component are inserted into the PU block sequence of luma component to achieve PU reordering.

[0092] Figure 6b This is a schematic diagram illustrating the reordering of the six PUs according to embodiments of the present disclosure in one embodiment. For example... Figure 6b As shown, in the same Figure 6a Under the same assumptions, the reordered PU sequence is: PU0(luma)->PU4(cb)->PU1(luma)->PU2(luma)->PU5(cr)->PU3(luma).

[0093] Figure 6a and Figure 6bThe empty prediction path shown means that, due to the interdependence of the preceding and following PUs, the next PU can only enter the prediction path and begin its prediction process after the preceding PU has completed all prediction calculations and all relevant data has been emptied from the prediction path.

[0094] Traditional prediction models follow a sequential order from PU0 to PU5 for prediction calculations. That is, each PU must wait for the preceding PU to complete its prediction and reconstruction before initiating its own prediction process. For example... Figure 6a As shown, PU1 needs to wait for PU0 to complete its prediction and reconstruction before it can start. This sequential execution method reduces the overall decoding speed.

[0095] Compared to traditional prediction models, this disclosure proposes to perform prediction calculations based on the reordered PU sequence. For example... Figure 6b As shown, once PU1 prediction is complete, PU2's dependency on PU0 has already been eliminated, and it can immediately begin prediction calculation without waiting for PU0 to be completely depleted. Similarly, once PU4 prediction is complete, PU5 has already been eliminated from its dependency on PU3, and it can seamlessly enter the prediction calculation process.

[0096] In this implementation, the reordering strategy fully considers the dependencies between different color components, optimizes the PU prediction timing, and accelerates the decoding process without sacrificing prediction accuracy or adding extra complexity.

[0097] In one embodiment of this disclosure, the reference edge information reading module 32 includes a reference edge loading module, a temporary storage module, a dependency judgment module, a data retrieval address calculation module, and a reference edge preloading module.

[0098] The reference edge loading module is configured to load the reference edge information of the prediction blocks from the memory 20 according to the second instruction and the reordered order of the prediction blocks.

[0099] Specifically, after the processing order of the PU is determined by reordering, the reference edge loading module will be responsible for controlling the reading of adjacent block information that is processed first.

[0100] It should be noted that some instructions in the instruction set are passed through. For example, the second instruction in this embodiment does not require any modification or parsing and is directly passed through the sequence adjustment module 31 to the reference edge loading module. Similarly, the third instruction is directly passed through the sequence adjustment module 31 to the dependency judgment module, and the fourth instruction is directly passed through the sequence adjustment module 31 to the reference edge information processing module 33.

[0101] The temporary storage module is configured to temporarily store the reference edge information of the prediction block and allocate a specific storage address for the reference edge information of each prediction block.

[0102] Specifically, the temporary storage module includes a random access memory (RAM) unit and a cache unit, wherein the random access memory unit adopts a random access memory (RAM) unit, and the cache unit adopts a register array.

[0103] Due to the limitations of RAM—that only one address can be read per clock cycle—reading data across multiple addresses must be done in multiple steps, potentially degrading performance. Furthermore, reference edge information often overlaps significantly between PCUs within the PU. Therefore, this disclosure employs a combined RAM and cache structure to replace the traditional method of using only registers to store reference edge information. RAM has a fixed connection method and is essentially accessed based on address, thus avoiding address overlap issues. Simultaneously, the presence of cache reduces the number of RAM reads, thereby compensating for RAM's limitations.

[0104] In this implementation, by integrating RAM and cache storage structures, the hardware resource consumption and AOI problems caused by using a large number of multiplexers in traditional designs are effectively avoided.

[0105] The dependency determination module is configured to determine whether there is a dependency relationship between the next prediction block and the current prediction block. If there is no dependency relationship, the third instruction is passed downstream; otherwise, the module waits for the current prediction block to complete intra-frame prediction before passing the third instruction downstream.

[0106] Specifically, the dependency determination module determines whether there is a dependency relationship between the next prediction block and the current prediction block by: recording the maintenance area defined by the right preset column and the bottom preset row of the current prediction block; sampling the left preset column and the top preset row of the next prediction block according to a preset sampling interval to obtain a number of reference edge sampling points; determining whether at least one of the reference edge sampling points falls within the maintenance area; if so, determining that there is a dependency relationship between the next prediction block and the current prediction block; otherwise, determining that there is no dependency relationship between the next prediction block and the current prediction block.

[0107] Figure 7 This is a schematic diagram illustrating the structure of the maintenance area of ​​the present disclosure according to an embodiment of the present disclosure in one example. For example... Figure 7 As shown, the prediction block ready to enter the prediction calculation (i.e., the next prediction block) is PU3, and the prediction blocks currently undergoing prediction calculation are PU0 to PU2. The area defined by the right column and bottom row of PU0 to PU2 is the maintenance area.

[0108] Figure 8a This is a schematic diagram illustrating the structure of a reference edge sampling point according to an embodiment of the present disclosure in one embodiment. Figure 8b This is a schematic diagram illustrating the structure of a reference edge sampling point according to an embodiment of the present disclosure in another embodiment. For example... Figure 8a and Figure 8b As shown, assuming that the reference edge range required by PU3 only includes the left, upper left and top, then sampling at a sampling point distance of 4 on the top and left sides of PU3 (size is 16×16 pixels) can obtain the reference edge sampling points.

[0109] It should be noted that if any of the prediction blocks from PU0 to PU2 has completed its prediction, then the maintenance region defined by its right column and bottom row needs to be released. Once these maintenance regions are released, it is no longer necessary to compare whether the reference edge sampling points fall within these maintenance regions.

[0110] For example, PU0 has completed its prediction, but PU1 and PU2 have not yet completed their predictions. In this case, the maintenance region of PU0 will be released. When PU3 enters the prediction calculation process, it is necessary to check whether each reference edge sampling point of PU3 falls into the maintenance region of PU1 and PU2 respectively. If it is found that any reference edge sampling point of PU3 falls into the maintenance region of PU1, but no reference edge sampling point falls into the maintenance region of PU2, then it can be determined that PU3 depends on PU1, but not on PU2.

[0111] The data retrieval address calculation module is configured to calculate the storage address of the reference edge information of the next prediction block in the temporary storage module.

[0112] Specifically, the data fetch address refers to the address from which reference edge information is read from RAM. Its function is to provide information to the reference edge preloading module, guiding it to extract the reference edge information required for the next prediction block from specific memory spaces and addresses. The data fetch address is pre-calculated by the data fetch address calculation module and stored in a register. This register is a temporary storage space located at the output of the data fetch address calculation module.

[0113] After the dependency between the next prediction block and the current prediction block is removed, the reference edge information of the next prediction block can be directly loaded from the temporary storage module as needed. This means that once the address of the reference edge information of the next prediction block in the temporary storage module is determined and the information is available, the reference edge preloading module can read the required reference edge information from the specified storage location for subsequent processing and prediction.

[0114] In one embodiment of this disclosure, the data retrieval address calculation module calculates the storage address of the reference edge information of the next prediction block in the temporary storage module according to the prediction mode.

[0115] In another embodiment of this disclosure, the data retrieval address calculation module stores the data in the order it arrives and also reads it in the same order. This sequential access method does not require complex prediction algorithms; it assumes that the data processing order is linear and continuous, simplifying the data retrieval address calculation process.

[0116] In one embodiment of this disclosure, the dependency judgment module and the data retrieval address calculation module work in parallel.

[0117] This implementation allows for simultaneous dependency checks and data retrieval address calculations, effectively saving prediction time and improving overall data processing efficiency and performance.

[0118] The reference edge preloading module is configured to preload the reference edge information of the next prediction block from the storage address in the temporary storage module based on the third instruction.

[0119] Specifically, the reference edge preloading module is configured to: search for the reference edge information of the next prediction block in the cache unit based on the third instruction; if the search is successful, directly obtain the reference edge information of the next prediction block from the cache unit; otherwise, obtain the reference edge information of the next prediction block from the random storage unit based on the storage address, and update the reference edge information of the next prediction block to the cache unit.

[0120] This embodiment improves data preloading efficiency by using a cache structure to reduce direct access to RAM. However, whether or not preloading is performed depends on the result of the dependency determination module. Only when the dependency determination module determines that the next predicted block has no dependency on the current predicted block can the reference edge preloading module read data from RAM and cache based on the result of the third instruction and the data fetch address calculation module. If a dependency exists, even if the data fetch address has been calculated, the preloading operation cannot be performed because it is necessary to wait for the dependency to be resolved.

[0121] Assume that PU0 depends on PU1, PU2 does not depend on PU1, and PU3 does not depend on PU2. Figure 9a This is a schematic diagram illustrating the reference edge preloading process of six PUs according to an embodiment of the present disclosure in one embodiment. For example... Figure 9a As shown, each PU needs to load its reference edge information before performing prediction calculations.

[0122] For example, before starting the prediction calculation of PU0, the reference edge information for PU0 needs to be prepared first. Once the reference edge information for PU0 is loaded, the prediction calculation of PU0 is then performed. After the prediction of PU0 is completed, the prediction path of PU0 needs to be cleared. Because there is a dependency between PU0 and PU1, PU1 will not start the prediction calculation process until PU0 has completed its prediction and its prediction path has been cleared. This process will cycle sequentially, that is, from PU0 to the last PU, each PU needs to wait for the previous PU to complete its prediction and clear its prediction path before it can start its own prediction calculation. This serialization process significantly reduces processing speed and efficiency.

[0123] Figure 9b This is a schematic diagram illustrating the reference edge preloading process of the six PUs according to an embodiment of the present disclosure in another embodiment. For example... Figure 9b As shown, in the same Figure 9a Under the same assumptions, the reference edge information of the next PU can be read out in advance before each PU has completed its prediction calculation.

[0124] For example, the reference edge information of PU2 can be read in advance before PU1 has completed its prediction calculation. Once PU1 has completed its prediction, that is, the last PCU inside PU1 enters the loop, the first PCU inside PU2 can immediately enter the loop. This effectively saves the preparation process of reference edge information, thereby achieving an acceleration effect.

[0125] It should be noted that if there is a dependency between the preceding and following PUs, the prediction result of the current PU must be read after the current PU has completed its prediction in order to prepare reference edge information for the next prediction block.

[0126] In this implementation, by determining in advance whether there is a dependency between the preceding and following PUs, reference edge information can be prepared in advance even when there is no dependency, without waiting for the previous PU to empty the prediction path. Once the current PU completes its operation, the next PU can seamlessly begin prediction, thereby improving overall performance.

[0127] In one embodiment of this disclosure, after completing the intra-frame prediction of the current prediction block, the reference edge information processing module 33 processes the reference edge information of the next prediction block based on the fourth instruction to obtain the intra-frame prediction result of the next prediction block, including: calculating the filtering parameters and prediction parameters required for intra-frame prediction of the next prediction block based on the fourth instruction; filling and filtering the reference edge information of the next prediction block based on the filtering parameters to obtain filtered reference edge information; and predicting and reconstructing the filtered reference edge information based on the prediction parameters to obtain the intra-frame prediction result of the next prediction block.

[0128] Specifically, the filtering parameters and prediction parameters are pre-calculated by the reference edge information processing module 33 and stored in two registers respectively. These two registers are temporary storage spaces located at the output of the reference edge information processing module 33.

[0129] Under a specific clock signal, the system reads the pre-calculated filtering and prediction parameters from these two registers and then begins processing the reference edge information for the next prediction block.

[0130] In one embodiment of this disclosure, the intra-frame prediction device 30 further includes an iterative update module.

[0131] The iterative update module is configured to store the intra-frame prediction result of the next prediction block to the temporary storage module, so as to iteratively update the reference edge information of the prediction block stored in the temporary storage module.

[0132] In this embodiment of the disclosure, the intra-frame prediction result of the next prediction block can be used as reference side information for subsequent predictions.

[0133] In one embodiment of this disclosure, the intra-frame prediction device 30 further includes an information backup module.

[0134] The information backup module is configured to determine whether the current prediction block is located at the last row of the bottom of the coding tree unit; if so, after completing the intra-frame prediction of the current prediction block, the intra-frame prediction result of the current prediction block is backed up to the memory 20 for use when the prediction blocks of subsequent coding tree units perform intra-frame prediction; otherwise, no backup processing is performed.

[0135] It should be noted that the embodiments of the intra-prediction device 30 of this disclosure are basically the same as the embodiments of the intra-prediction method described above, therefore, repeated embodiments will not be described again. The intra-prediction device 30 provided in the embodiments of this disclosure can implement the intra-prediction method described in this disclosure, but the implementation device of the intra-prediction method described in this disclosure includes, but is not limited to, the structure of the intra-prediction device 30 listed in this embodiment. All structural modifications and substitutions of the prior art made according to the principles of this disclosure are included within the protection scope of this disclosure.

[0136] like Figure 10 As shown, this embodiment provides an electronic device. The electronic device includes a processor and a memory.

[0137] The memory is configured to store executable programs.

[0138] The processor is configured to execute the program to cause the electronic device to perform the intra-frame prediction method according to any of the preceding claims.

[0139] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0140] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this disclosure, depending on actual needs. For example, the functional modules / units in the various embodiments of this disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0141] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0142] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed, implements the intra-frame prediction method according to any of the preceding embodiments. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium that is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0143] This disclosure also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this disclosure are generated. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0144] When the computer program product is executed by a computer, the computer performs the method described in the foregoing method embodiments. The computer program product can be a software installation package; when the foregoing method is required, the computer program product can be downloaded and executed on the computer.

[0145] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0146] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. An intra-frame prediction method, characterized in that, include: Reorder multiple prediction blocks within a coding unit; Read the reference edge information of the next prediction block that is adjacent to the current prediction block after reordering; as well as After the intra-prediction of the current prediction block is completed, the reference edge information of the next prediction block is processed to obtain the intra-prediction result of the next prediction block. The reordering of multiple prediction blocks within a coding unit includes: determining the dependency relationship between a first prediction block, a second prediction block, and a third prediction block; if there is a dependency relationship between the first prediction block and the second prediction block, and no dependency relationship between the third prediction block and the first and second prediction blocks, then the third prediction block is inserted between the first prediction block and the second prediction block to reorder the multiple prediction blocks.

2. The intra-frame prediction method according to claim 1, characterized in that, Also includes: The syntax elements decoded from the bitstream information by the decoder are obtained, and the syntax elements are parsed into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction. The reordering of multiple prediction blocks within a coding unit includes: reordering the received multiple prediction blocks within the coding unit based on the first instruction. The process of reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering includes: based on the second instruction and the third instruction, reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering from the memory, and... The process of processing the reference edge information of the next prediction block to obtain the intra-prediction result of the next prediction block includes: after completing the intra-prediction of the current prediction block, processing the reference edge information of the next prediction block based on the fourth instruction to obtain the intra-prediction result of the next prediction block.

3. The intra-frame prediction method according to claim 1, characterized in that, Reordering multiple prediction blocks within a coding unit includes: Obtain the color space components of each prediction block, wherein the color space components include chroma components or luminance components. A prediction block containing the chroma components is defined as a chroma prediction block, and a prediction block containing the luminance components is defined as a luminance prediction block. Based on the rule of considering the luminance component first and then the chrominance component, the multiple prediction blocks within the coding unit are initially sorted; and The chroma prediction block is placed between two adjacent luminance prediction blocks to complete the reordering of several prediction blocks within the coding unit.

4. The intra-frame prediction method according to claim 2, characterized in that, Based on the second instruction and the third instruction, reading the reference edge information of the next prediction block adjacent to the current prediction block after reordering from the memory includes: Based on the second instruction, the reference edge information of the prediction blocks is loaded from the memory according to the reordered order of the prediction blocks; The reference edge information of the prediction block is temporarily stored, and a specific storage address is allocated for the reference edge information of each prediction block. Determine whether there is a dependency between the next prediction block and the current prediction block. If there is no dependency, pass the third instruction downstream; otherwise, wait for the current prediction block to complete intra-frame prediction before passing the third instruction downstream. Calculate the storage address of the reference edge information for the next prediction block; and Based on the third instruction, the reference edge information of the next prediction block is preloaded from the storage address.

5. The intra-frame prediction method according to claim 4, characterized in that, The determination of whether there is a dependency relationship between the next prediction block and the current prediction block and the calculation of the storage address of the reference edge information of the next prediction block are performed in parallel.

6. The intra-frame prediction method according to claim 4, characterized in that, Determining whether there is a dependency between the next prediction block and the current prediction block includes: Record the maintenance area defined by the preset column to the right and the preset row below the current prediction block; According to the preset sampling interval, the left preset column and the top preset row of the next prediction block are sampled to obtain a number of reference edge sampling points; Determine whether at least one of the reference edge sampling points falls within the maintenance area; If so, it is determined that there is a dependency between the next prediction block and the current prediction block; and Otherwise, it is determined that there is no dependency between the next prediction block and the current prediction block.

7. The intra-frame prediction method according to claim 1, characterized in that, Processing the reference edge information of the next prediction block to obtain the intra-frame prediction result of the next prediction block includes: Calculate the filtering parameters and prediction parameters required for intra-frame prediction of the next prediction block; Based on the filtering parameters, the reference edge information of the next prediction block is filled and filtered to obtain filtered reference edge information; and Based on the prediction parameters, the filtered reference edge information is predicted and reconstructed to obtain the intra-frame prediction result of the next prediction block.

8. The intra-frame prediction method according to claim 4, characterized in that, Also includes: The intra-frame prediction results of the next prediction block are temporarily stored, and the reference edge information of the temporarily stored prediction block is iteratively updated.

9. The intra-frame prediction method according to claim 1, characterized in that, Also includes: Determine whether the current prediction block is located in the last row at the bottom of the coding unit; If so, after completing the intra-frame prediction of the current prediction block, the intra-frame prediction result of the current prediction block is backed up to the memory so that it can be used when the prediction blocks of subsequent coding units perform intra-frame prediction. Otherwise, no backup will be performed.

10. An intra-frame prediction device, characterized in that, include: The order adjustment module is configured to reorder multiple prediction blocks within a coding unit; The reference edge information reading module is configured to read the reference edge information of the next prediction block that is adjacent to the current prediction block after reordering. as well as The reference edge information processing module is configured to process the reference edge information of the next prediction block after the intra-prediction of the current prediction block is completed, so as to obtain the intra-prediction result of the next prediction block. The order adjustment module is configured to: determine the dependency relationship between the first prediction block, the second prediction block and the third prediction block; if there is a dependency relationship between the first prediction block and the second prediction block, and there is no dependency relationship between the third prediction block and the first prediction block and the second prediction block, then insert the third prediction block between the first prediction block and the second prediction block to reorder multiple prediction blocks.

11. The intra-frame prediction apparatus according to claim 10, characterized in that, Also includes: The instruction parsing module is configured to acquire the syntax elements decoded from the bitstream information by the decoder, and parse the syntax elements into an instruction set including a first instruction, a second instruction, a third instruction, and a fourth instruction. The order adjustment module is configured to reorder multiple prediction blocks within the received encoding unit based on the first instruction. The reference edge information reading module is configured to read the reference edge information of the next prediction block adjacent to the current prediction block after reordering from the memory, based on the second instruction and the third instruction. The reference edge information processing module is configured to process the reference edge information of the next prediction block based on the fourth instruction after completing the intra-prediction of the current prediction block, so as to obtain the intra-prediction result of the next prediction block.

12. The intra-frame prediction apparatus according to claim 11, characterized in that, The reference edge information reading module includes: The reference edge loading module is configured to load the reference edge information of the prediction blocks from the memory according to the reordered order of the prediction blocks, based on the second instruction. A temporary storage module is configured to temporarily store the reference edge information of the prediction block and allocate a specific storage address for the reference edge information of each prediction block. The dependency determination module is configured to determine whether there is a dependency relationship between the next prediction block and the current prediction block. If there is no dependency relationship, the third instruction is passed downstream; otherwise, the module waits for the current prediction block to complete intra-frame prediction before passing the third instruction downstream. The data retrieval address calculation module is configured to calculate the storage address of the reference edge information of the next prediction block in the temporary storage module; and The reference edge preloading module is configured to preload the reference edge information of the next prediction block from the storage address in the temporary storage module based on the third instruction.

13. The intra-frame prediction apparatus according to claim 12, characterized in that, The dependency judgment module and the data retrieval address calculation module work in parallel.

14. The intra-frame prediction apparatus according to claim 12, characterized in that, The temporary storage module includes a random access memory unit and a cache unit.

15. The intra-frame prediction apparatus according to claim 14, characterized in that, The reference edge preload module is configured as follows: Based on the third instruction, the reference edge information of the next prediction block is searched in the cache unit; If the search is successful, the reference edge information of the next prediction block is directly obtained from the cache unit; as well as Otherwise, based on the storage address, the reference edge information of the next prediction block is obtained from the random storage unit, and the reference edge information of the next prediction block is updated in the cache unit.

16. A chip, characterized in that, include: The decoder is configured to decode syntax elements from the bitstream information; The memory is configured to store reference edge information of multiple prediction blocks within the coding unit, and to store the intra-frame prediction results of the prediction blocks in the bottom last row of the coding unit. as well as The intra-frame prediction apparatus according to any one of claims 10 to 15.

17. An electronic device, characterized in that, include: The memory is configured to store executable programs; as well as A processor is configured to execute the program to cause the electronic device to perform the intra-frame prediction method according to any one of claims 1 to 9.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed, it implements the intra-frame prediction method according to any one of claims 1 to 9.

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