Display panel and preparation method thereof

Abstract

Embodiments of the present application disclose a display panel and a preparation method thereof. The display panel is provided with a channel passing through a support member at the junction of a buffer region and a cathode overlap region on a light-emitting device layer, so that the material of the cathode can pass through the channel into the cathode overlap region and overlap on the wire exposed by the first opening. The electronic functional layer is formed by an evaporation process, and the cathode is formed by an evaporation process with a smaller evaporation angle or a sputtering process, and the electronic functional layer and the cathode are formed under the same mask plate. Due to the channel, the material of the cathode and the electronic functional layer can extend to the cathode overlap region through the channel. In addition, the cathode is evaporated by a smaller evaporation angle or a sputtering process, so that the film forming range of the cathode is larger than that of the electronic functional layer, and then the cathode can overlap the wire to realize the light emission of the light-emitting device layer, thereby reducing the preparation cost of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] In related technologies, OLED panels can be produced using inkjet printing (IJP) process and evaporation (EV) process / sputtering (SPT) process. Due to the limited development of inks for electron transport materials (ETM) and electron injection materials (EIM), IJP OLED panels currently use the IJP process to deposit OLED functional layers such as the hole injection layer (HIL), hole transport layer (HTL), and light-emitting layer (EML), and use the EV / SPT process to deposit OLED functional layers such as the electron transport layer (ETL), electron injection layer (EIL), and cathode.

[0003] The cathode of the OLED panel needs to be connected to the metal traces on the driver substrate to realize the circuit control of the OLED light emission. Therefore, the film forming area needs to be larger than the film forming area of ​​​​ETL and EIL, so that the cathode film layer can directly overlap with the metal traces. The EV / SPT process is based on changing the opening design of the mask to achieve different film forming areas. Therefore, the opening size of the mask for cathode film formation needs to be larger than the opening size of the mask for ETL&EIL film formation. In other words, two masks are required to form the OLED functional layer, which greatly increases the preparation cost. Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a method for manufacturing the same, which can reduce the manufacturing cost of the panel.

[0005] An embodiment of the present application provides a display panel, comprising a display area and a non-display area located on at least one side of the display area, wherein the non-display area includes a buffer area and a cathode overlapping area located on a side of the buffer area away from the display area. The display panel includes:

[0006] a thin film transistor structure layer, the thin film transistor structure layer including a wiring and an insulating layer covering the wiring, wherein a first opening is provided on the insulating layer in the cathode overlapping region, and the first opening exposes the wiring;

[0007] a light-emitting device layer, the light-emitting device layer being disposed on the thin-film transistor structure layer, the light-emitting device layer comprising an electronic functional layer and a cathode disposed on a side of the electronic functional layer away from the thin-film transistor structure layer;

[0008] a supporting member, the supporting member being disposed on the insulating layer and located at a junction of the buffer zone and the cathode overlapping zone;

[0009] The light emitting device layer is provided with at least one channel in the buffer area, the channel extends to the cathode overlap area through the support member, and the first opening is located in the extension direction of the channel.

[0010] In the non-display area of the orthographic projection pattern of the display panel, the boundary of the cathode exceeds the boundary of the electronic functional layer, the electronic functional layer covers at least the display area and the buffer area, and the cathode covers the display area and the buffer area and is connected to the trace through the channel at the first opening.

[0011] Optionally, in some embodiments of the present application, the light emitting device layer comprises a planar layer covering the insulating layer and a pixel definition layer covering the planar layer, and the electronic functional layer covers the pixel definition layer.

[0012] Taking the side of the insulating layer close to the planar layer as a reference surface, the bottom surface height of the channel is lower than the side of the pixel definition layer away from the thin film transistor structure layer, and the bottom surface height of the channel is higher than or equal to the reference surface.

[0013] Optionally, in some embodiments of the present application, the channel comprises at least one first hollow opening and a plurality of second hollow openings, one first hollow opening is connected to at least one second hollow opening, the first hollow opening and the second hollow opening both penetrate the planar layer and the pixel definition layer, the first hollow opening is located in the buffer area, and the second hollow opening penetrates the support member.

[0014] In the orthographic projection pattern of the display panel, the extension direction of the second hollow opening intersects the extension direction of the trace.

[0015] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the display panel, the extension direction of the second hollow opening is perpendicular to the extension direction of the trace.

[0016] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the display panel, a plurality of channels are arranged along the extension direction of the trace, and the channels are arranged along the direction perpendicular to the extension direction of the trace.

[0017] Optionally, in some embodiments of the present application, the first opening has at least one, and in the orthographic projection pattern of the display panel, one first opening corresponds to at least one second hollow opening arranged in the extension direction of the second hollow opening.

[0018] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the display panel, a plurality of the first openings are arranged along the extension direction of the trace, and one of the first openings is arranged in the extension direction of one of the second hollows.

[0019] Optionally, in some embodiments of the present application, the first opening is one, and in the orthographic projection pattern of the display panel, the first opening is arranged along the extension direction of the trace, and one of the first openings is arranged in the extension direction of a plurality of the second hollows.

[0020] Optionally, in some embodiments of the present application, the support member is a plurality, and in the orthographic projection pattern of the display panel, a plurality of the support members are arranged along the extension direction of the trace, and the support members are arranged between two adjacent first openings in the extension direction of the second hollow.

[0021] The cathode includes a plurality of overlapping portions arranged in the overlapping region of the cathode, one of the overlapping portions is arranged in the first opening and connected to the trace, and a plurality of the overlapping portions are arranged along the extension direction of the trace.

[0022] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the display panel, the support member overlaps with the two side regions of the first opening along the extension direction of the second hollow.

[0023] Optionally, in some embodiments of the present application, the width of the second hollow is between 10 microns and 500 microns.

[0024] Optionally, in some embodiments of the present application, the width of the support member is greater than or equal to 10 microns.

[0025] Optionally, in some embodiments of the present application, at least one of the flat layer and the pixel definition layer is arranged in the same layer and made of the same material as at least part of the support member.

[0026] Optionally, in some embodiments of the present application, the support member includes a first portion, a second portion and a third portion stacked in sequence on the insulating layer, the first portion is arranged in the same layer and made of the same material as the flat layer, and the second portion is arranged in the same layer and made of the same material as the pixel definition layer.

[0027] Optionally, in some embodiments of the present application, the thickness of the support member is greater than or equal to 4 microns.

[0028] Optionally, in some embodiments of the present application, the electronic functional layer is connected to the exposed part of the trace through the channel at the first opening, and the cathode covers the electronic functional layer in the first opening and is connected to the exposed part of the trace.

[0029] Optionally, in some embodiments of the present application, the electronic functional layer comprises at least one of an electron transport layer and an electron injection layer, the light emitting device layer further comprises an anode, a light emitting layer and a hole functional layer, the anode is arranged on the planar layer, the pixel definition layer is provided with a second opening, the second opening exposes the anode, the hole functional layer and the light emitting layer are sequentially arranged on the anode and located in the second opening, and the electronic functional layer is arranged on the light emitting layer.

[0030] Correspondingly, the present application further provides a preparation method of a display panel, the display panel comprising a display area and a non-display area located at least one side of the display area, the non-display area comprising a buffer area and a cathode overlap area located at a side of the buffer area away from the display area, the preparation method of the display panel comprising the following steps:

[0031] forming a support member on a thin film transistor structure layer, the thin film transistor structure layer comprising a trace and an insulating layer covering the trace, in the cathode overlap area, a first opening is arranged on the insulating layer, the first opening exposes the trace, the support member is arranged on the insulating layer and located at the junction of the buffer area and the cathode overlap area, at least one channel is formed on the support member, the channel communicates the buffer area and the cathode overlap area, and the first opening is located in the extension direction of the channel;

[0032] arranging a mask plate on the support member, an opening area of the mask plate corresponds to the display area and the buffer area, and a shielding area of the mask plate corresponds to the cathode overlap area;

[0033] based on the same mask plate, sequentially forming an electronic functional layer and a cathode on the thin film transistor structure layer, a boundary of the cathode exceeds a boundary of the electronic functional layer, the electronic functional layer covers at least the display area and the buffer area, and the cathode covers the display area and the buffer area and is connected to the trace through the channel at the first opening.

[0034] The display panel of the present application forms a channel through the support member located at the junction of the buffer area and the cathode overlap area on the light emitting device layer, so that the material of the cathode can enter the cathode overlap area through the channel and overlap on the trace exposed by the first opening.

[0035] That is, the electronic functional layer is formed by an evaporation process, the cathode is formed by an evaporation process with a small evaporation angle or a sputtering process, and the electronic functional layer and the cathode are formed under the same mask plate. Due to the arrangement of the through hole, the material of the cathode and the electronic functional layer can extend to the cathode overlap area through the through hole. In addition, due to the evaporation of the cathode by a small evaporation angle or the sputtering process, the film forming range of the cathode is larger than that of the electronic functional layer, and the cathode can overlap the wire to realize the light emission of the light emitting device layer, thereby reducing the preparation cost of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of a front projection of a display panel provided by an embodiment of the present application;

[0037] Figure 2 is Figure 1 is an enlarged view of the Q part in FIG. 8;

[0038] Figure 3 is Figure 2 is a schematic diagram of a cross section along the CC line in FIG. 8;

[0039] Figure 4 is Figure 2 is a schematic diagram of a cross section along the DD line in FIG. 8;

[0040] Figure 5 is a schematic diagram of a front projection of a display panel provided by another embodiment of the present application;

[0041] Figure 6 is a schematic diagram of a curve of different film thicknesses corresponding to different distances of the cathode and the electronic functional layer;

[0042] Figure 7 is a schematic diagram of a front projection of a display panel provided by still another embodiment of the present application;

[0043] Figure 8 is Figure 7 is a schematic diagram of a cross section along the SS line in FIG. 9;

[0044] Figure 9 is a schematic diagram of a cross section structure of a display panel provided by still another embodiment of the present application;

[0045] Figure 10 is a schematic diagram of step B1 of a preparation method of a display panel provided by an embodiment of the present application;

[0046] Figure 11 is a schematic diagram of step B2 of a preparation method of a display panel provided by an embodiment of the present application;

[0047] Figure 12 is a schematic diagram of step B3 of a preparation method of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device; the terms "first", "second", "third" and the like are only used as labels, and do not impose numerical requirements or establish sequences.

[0049] The present application provides a display panel and a preparation method thereof, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0050] Please refer to Figures 1 to 4 The present application provides a display panel 100, which includes a display area AA and a non-display area NA located at least one side of the display area AA. The non-display area NA includes a buffer area NA1 and a cathode overlap area NA2 located at a side of the buffer area NA1 away from the display area AA.

[0051] The display panel 100 includes a thin film transistor structure layer 10, a light emitting device layer 20 and a support member 30.

[0052] The thin film transistor structure layer 10 includes a wire 11 and an insulating layer 12 covering the wire 11. In the cathode overlap area NA2, a first opening k1 is provided on the insulating layer 12, and the first opening k1 exposes the wire 11.

[0053] The light emitting device layer 20 is provided on the thin film transistor structure layer 10. The light emitting device layer 20 includes an electron functional layer 21 and a cathode 22 provided at a side of the electron functional layer 21 away from the thin film transistor structure layer 10.

[0054] The support member 30 is provided on the insulating layer 12 and located at the junction of the buffer area NA1 and the cathode overlap area NA2.

[0055] In the buffer area NA1, the light emitting device layer 20 is provided with at least one channel td. The channel td extends through the support member 30 to the cathode overlap area NA2, and the first opening k1 is located in the extension direction of the channel td.

[0056] In the non-display area NA of the display panel 100, the boundary of the cathode 22 is beyond the boundary of the electron functional layer 21, the electron functional layer 21 covers at least the display area AA and the buffer area NA1, the cathode 22 covers the display area AA and the buffer area NA1 and extends into the cathode overlap area NA2 along the channel td, and the cathode 22 extends into the first opening k1 to connect to the wire 11. That is, the cathode 22 and the channel td are connected to the wire 11 at the first opening k1.

[0057] The display panel 100 of the embodiment of the present application is provided with the channel td passing through the support member 30 at the junction of the buffer area NA1 and the cathode overlap area NA2 on the light emitting device layer 20, so that the material of the cathode 22 can enter the cathode overlap area NA2 through the channel td and overlap on the wire 11 exposed by the first opening k1.

[0058] That is, the electron functional layer 21 is formed by the evaporation process, and the cathode 22 is formed by the evaporation process with a smaller evaporation angle or the sputtering process under the same mask plate. Due to the provision of the channel td, the materials of the cathode 22 and the electron functional layer 21 can extend to the cathode overlap area NA2 through the channel td. In addition, the cathode 22 is evaporated by the evaporation process with a smaller evaporation angle or the sputtering process, so that the film forming range of the cathode 22 is larger than that of the electron functional layer, and thus the cathode can overlap the wire to realize the light emission of the light emitting device layer, thereby reducing the preparation cost of the display panel.

[0059] Optionally, the non-display area NA is arranged at one side of the display area AA, and the wire 11 is arranged only at one side of the display area AA. In some embodiments, the non-display area NA can also be arranged around the display area AA, and the wire 11 is arranged around the outer periphery of the display area AA to form a closed loop structure. In some embodiments, the non-display area NA is arranged at two or three adjacent sides of the display area AA, and the wire 11 is arranged in a zigzag shape around the outer periphery of the display area AA.

[0060] Optionally, the electron functional layer 21 is connected to the part of the wire 11 at the first opening k1 through the channel td. The cathode 22 covers the electron functional layer 21 in the first opening k1 and is connected to the exposed part of the wire 11. Such an arrangement can reduce the width of the non-display area NA.

[0061] In an embodiment, the electron functional layer 21 can also not overlap the wire 11 in the first opening k1, so as to improve the stability of the cathode 22 overlapping the wire 11.

[0062] Optionally, the thin film transistor structure layer 10 can be at least one of a top-gate thin film transistor, a bottom-gate thin film transistor, a double-gate thin film transistor and a vertical thin film transistor. The embodiment is described by taking one of the top-gate thin film transistors as an example, but is not limited thereto.

[0063] Please refer to Figures 3-4 In an embodiment, the thin-film transistor structure layer 10 comprises a substrate 13, a light-blocking layer 14, a buffer layer 15, an active layer 16, a gate insulating layer 17, a gate electrode g, an interlayer dielectric layer 18, a source electrode s and a drain electrode d, which are sequentially stacked. The trace 11 is disposed on the interlayer dielectric layer 18 in the same layer as the source electrode s. The insulating layer 12 further covers the source electrode s, the drain electrode d and the interlayer dielectric layer 18.

[0064] Optionally, the thin-film transistor structure layer 10 further comprises a signal access line 19 disposed in the same layer as the light-blocking layer 14 and spaced apart from the light-blocking layer 14. The trace 11 is connected to the signal access line 19 through a via. The signal access line 19 is configured to access a cathode signal.

[0065] Optionally, the light-emitting device layer 20 comprises a planarization layer 23 covering the insulating layer 12 and a pixel definition layer 24 covering the planarization layer 23. The electron functional layer 21 covers the pixel definition layer 24.

[0066] The light-emitting device layer 20 further comprises an anode 25, a hole functional layer 26 and a light-emitting layer 27. The anode 25 is disposed on the planarization layer 23. The pixel definition layer 24 is provided with a second opening k2 exposing the anode 25. The hole functional layer 26 and the light-emitting layer 27 are sequentially disposed on the anode 25 and located within the second opening k2. The electron functional layer 21 is disposed on the light-emitting layer 27. The anode 25 is connected to the drain electrode d of the thin-film transistor through a via.

[0067] Optionally, the electron functional layer 21 comprises at least one of an electron transport layer and an electron injection layer. The hole functional layer 26 comprises at least one of a hole transport layer and a hole injection layer. In the embodiment, the electron functional layer 21 comprises an electron transport layer and an electron injection layer which are sequentially stacked on the light-emitting layer 27. The hole functional layer 26 comprises a hole injection layer and a hole transport layer which are sequentially stacked on the anode 25.

[0068] Optionally, the support member 30 is used to support a mask plate. That is, when the electron functional layer 21 and the cathode 22 are prepared, the same mask plate is overlapped on the support member 30. The display area AA and the buffer area NA1 are exposed under the opening pattern of the mask plate, and the cathode overlap area NA2 is shielded by the mask plate. By using the diffusion phenomenon of the material in the process, the cathode material and the electron functional layer material pass through the channel td into the cathode overlap area NA2. The part of the material entering the cathode overlap area NA2 is a diffusion part (shadow).

[0069] Optionally, with the side of the insulating layer 12 close to the planarization layer 23 as a reference surface, the bottom surface height of the channel td is lower than the side of the pixel definition layer 24 away from the thin-film transistor structure layer 10 in the display area AA, and the bottom surface height of the channel td is higher than or equal to the reference surface.

[0070] For example, in the buffer area NA1, a hollow opening is formed in the planar layer 23 to expose the insulating layer 12, and the pixel definition layer 24 covers the hollow opening to form a lower-lying recessed portion compared with the display area AA, and the recessed groove (channel td) of the recessed portion extends through the support member 30, so that the material can enter the cathode overlap area NA2 through the recessed groove.

[0071] For another example, in the buffer area NA1, a hollow opening is formed in the pixel definition layer 24 to expose the planar layer 23, and the hollow opening forms a recessed groove (channel td) with the top surface of the planar layer 23, and the recessed groove (channel td) of the recessed portion extends through the support member 30, so that the material can enter the cathode overlap area NA2 through the recessed groove.

[0072] For another example, in an embodiment, the channel td includes at least one first hollow opening t1 and a plurality of second hollow openings t2. A first hollow opening t1 is connected to at least one second hollow opening t2. The first hollow opening t1 and the second hollow opening t2 both penetrate the planar layer 23 and the pixel definition layer 24. The first hollow opening t1 is located in the buffer area NA1, and the second hollow opening t2 penetrates the support member 30. That is, the bottom surface of the channel td is equal to the above-mentioned reference surface.

[0073] In the orthographic projection pattern of the display panel 100, the extension direction m of the second hollow opening t2 intersects the extension direction of the wire 11.

[0074] In the orthographic projection pattern of the display panel 100, the extension direction m of the second hollow opening t2 intersects the extension direction of the wire 11.

[0075] It can be understood that the less the front end barrier of the second hollow opening t2 is, the more material will pass through the second hollow opening t2. In addition, the deeper the depth of the second hollow opening t2 is, that is, the lower the front end barrier of the first opening k1 is, the more material will enter the first opening k1, thereby improving the stability of the overlap with the wire 11.

[0076] Referring to Figure 1 and Figure 2 In the orthographic projection pattern of the display panel 100, the extension direction m of the second hollow opening t2 intersects the extension direction of the wire 11. In the orthographic projection pattern of the display panel 100, the extension direction m of the second hollow opening t2 intersects the extension direction of the wire 11.

[0077] Optionally, in the orthographic projection pattern of the display panel 100, the extension direction m of the second hollow t2 is perpendicular to the extension direction of the wire 11, so that the distance of the material entering the first opening k1 is the same, and the partial area of the cathode 22 cannot be overlapped with the wire 11.

[0078] Optionally, in the orthographic projection pattern of the display panel 100, the plurality of channels td are arranged along the extension direction of the wire 11, and the channel td is arranged along the extension direction perpendicular to the wire 11.

[0079] Optionally, the first opening k1 has at least one, and in the orthographic projection pattern of the display panel 100, one first opening k1 corresponds to at least one second hollow t2 arranged in the extension direction m.

[0080] Optionally, please refer to Figure 2 In the orthographic projection pattern of the display panel 100, a plurality of first openings k1 are arranged along the extension direction of the wire 11, and one first opening k1 corresponds to one second hollow t2 arranged in the extension direction m.

[0081] Among them, the plurality of first openings k1 are arranged so that the wire 11 is covered with the insulating layer 12, which reduces the risk of wire 11 peeling.

[0082] Optionally, please refer to Figure 5 In an embodiment of the present application, the first opening k1 is one, and in the orthographic projection pattern of the display panel 100, the first opening k1 is arranged along the extension direction of the wire 11, and one first opening k1 corresponds to a plurality of second hollows t2 arranged in the extension direction m. Among them, a long strip-shaped first opening k1 is used to expose the wire 11, which increases the exposed area of the wire 11, so that the cathode 22 can be more overlapped with the wire 11, and the overlapping area is increased.

[0083] Optionally, in an embodiment, it can also be that in the orthographic projection pattern of the display panel 100, a plurality of first openings k1 are arranged along the extension direction of the wire 11, and one first opening k1 corresponds to at least two second hollows t2 arranged in the extension direction m. Such arrangement can consider the overlapping area of the cathode 22 and the wire 11, and also reduce the risk of wire 11 peeling.

[0084] Optionally, in an embodiment, the support member 30 has a plurality of, and in the orthographic projection pattern of the display panel 100, a plurality of support members 30 are arranged along the extension direction of the wire 11. In the extension direction m parallel to the second hollow t2, the support member 30 is located between the adjacent two first openings k1.

[0085] The cathode 22 includes a plurality of overlapping portions 22a located in the cathode overlapping area NA2. One overlapping portion 22a is arranged in one first opening k1 and connected to the trace 11, and the plurality of overlapping portions 22a are arranged in the extension direction of the trace 11.

[0086] The plurality of overlapping portions 22a are arranged in intervals and cover the side wall of the first opening k1, which on the one hand increases the overlapping area of the overlapping portion 22a and the film layer, thereby improving the stability of the attachment; on the other hand, the overlapping portions 22a are arranged in intervals, which improves the stress release performance of the cathode 22 in the cathode overlapping area NA2, facilitating the bending of the display panel 100.

[0087] Optionally, in the orthographic projection pattern of the display panel 100, along the extension direction m of the second hollow t2, the support member 30 overlaps the two side areas of the first opening k1.

[0088] It can be understood that the angle of the material passing through the second hollow t2 has randomness, so appropriately enlarging the width of the first opening k1 can improve the overlapping area of the cathode 22 and the trace 11.

[0089] In an embodiment, in the orthographic projection pattern of the display panel 100, along the extension direction m of the second hollow t2, the support member 30 is located between the boundaries of the adjacent two first openings k1.

[0090] Optionally, in an embodiment, the thickness h of the support member 30 is greater than or equal to 4 microns, such as 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns, 29 microns, 30 microns, 35 microns, 40 microns, 45 microns, or 50 microns, etc.

[0091] It can be understood that the greater the thickness h of the support member 30, the farther the distance between the mask plate and the bottom surface of the channel td, and the greater the range of material diffusion into the cathode overlapping area NA2, and the higher the success rate and stability of the cathode 22 overlapping the trace 11.

[0092] Optionally, in an embodiment, the width z1 of the second hollow t2 is between 10 microns and 500 microns, such as 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 150 microns, 200 microns, 250 microns, 300 microns, 350 microns, 400 microns, 450 microns, or 500 microns.

[0093] It can be understood that the smaller the width z1 of the second hollow opening t2 is, the smaller the area of the cathode 22 overlapping the trace 11 is, and the stronger the strength of the support member 30 supporting the mask plate is; the larger the width z1 of the second hollow opening t2 is, the larger the area of the cathode 22 overlapping the trace 11 is, and the weaker the strength of the support member 30 supporting the mask plate is, and the more easily the opening edge of the mask plate deforms, so the selection of the width z1 of the second hollow opening t2 meets the area of the cathode 22 overlapping the trace 11 and the strength requirement of supporting the mask plate.

[0094] Optionally, in an embodiment, the width z1 of the at least one second hollow opening t2 increases from the middle region to the two end directions, so that more overlapping area of the cathode 22 and the trace 11 is obtained.

[0095] The cathode 22 covers the bottom surface of the second hollow opening t2 and forms a clamping portion with a small middle width and a large two-end width in the area of the second hollow opening t2, that is, the connection area of the overlapping portion 22a and the clamping portion is increased, the risk of the cathode 22 moving is limited, and the risk of the overlapping portion 22a of the cathode 22 peeling off is reduced.

[0096] Optionally, in an embodiment, the width z2 of the support member 30 is greater than or equal to 10 microns, which can be 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 150 microns, 200 microns, 250 microns, 300 microns, 350 microns, or 400 microns, etc.

[0097] Optionally, in an embodiment, the width of the support member 30 is also less than or equal to 400 microns.

[0098] It can be understood that the smaller the width z2 of the support member 30 is, the larger the area of the cathode 22 overlapping the trace 11 is, and the weaker the strength of the support member 30 supporting the mask plate is, and the more easily the opening edge of the mask plate deforms; the larger the width z2 of the support member 30 is, the smaller the area of the cathode 22 overlapping the trace 11 is, and the stronger the strength of the support member 30 supporting the mask plate is, so the selection of the width z2 of the support member 30 meets the area of the cathode 22 overlapping the trace 11 and the strength requirement of supporting the mask plate.

[0099] Optionally, in an embodiment, at least one of the planar layer 23 and the pixel definition layer 24 is arranged in the same layer and made of the same material as at least part of the support member 30. For example, the support member 30 can be formed by using the same mask plate as the planar layer 23 or the pixel definition layer 24. For example, part of the support member 30 is formed by using the same mask plate as the planar layer 23, and another part of the support member 30 is formed by using the same mask plate as the pixel definition layer 24.

[0100] In an embodiment, the support member 30 can also be formed by other film layers different from the planar layer 23 and the pixel definition layer 24 using the same mask plate. Alternatively, a part of the support member 30 is formed by the same mask plate as the planar layer 23 or the pixel definition layer 24, and another part of the support member 30 is formed by the same mask plate as other film layers.

[0101] Optionally, in an embodiment, the support member 30 includes a first part 31, a second part 32 and a third part 33 stacked in sequence on the insulating layer 12. The first part 31 is arranged in the same layer as the planar layer 23 and made of the same material. The second part 32 is arranged in the same layer as the pixel definition layer 24 and made of the same material. The third part 33 is arranged in the same layer as the spacer and made of the same material. Such arrangement can simplify the process.

[0102] It should be understood that the electronic functional layer 21 of the display panel 100 in the embodiments of the present application can be prepared by an evaporation process, and the cathode 22 can be prepared by an evaporation process or a sputtering process. When both are prepared by an evaporation process, the evaporation angle for preparing the cathode 22 is smaller than the evaporation angle for preparing the electronic functional layer 21. When the electronic functional layer 21 can be prepared by an evaporation process and the cathode 22 can be prepared by a sputtering process, the angle problem does not need to be considered, and the electronic functional layer 21 and the cathode 22 can be prepared by a conventional process.

[0103] When the electronic functional layer 21 and the cathode 22 are both prepared by an evaporation process, the evaporation angle for preparing the cathode 22 is θ. In the channel td region, the distance from the first opening k1 to the planar layer 23 and the pixel definition layer 24 located in the display area AA is greater than or equal to the thickness h / tanθ of the support member 30, so as to ensure that the planar layer 23 and the pixel definition layer 24 block the material from passing through the channel td. The embodiments of the present application are described by taking the electronic functional layer 21 prepared by an evaporation process and the cathode 22 prepared by a sputtering process as an example.

[0104] Based on the different principles of film formation by an evaporation process and a sputtering process, the sputtering direction of the material particles is random when the film is formed by a sputtering process, while the material particles are limited by the evaporation angle when the film is formed by an evaporation process. Therefore, when the same mask plate is used for film formation, the film layer diffusion area formed by a sputtering process is greater than the film layer diffusion area formed by an evaporation process, that is, when the same opening pattern mask plate is used, the film layer coverage area of the cathode 22 is greater than the film layer coverage area of the electronic functional layer 21, as shown in FIG. 5. Figure 6

[0105] Since the electronic functional layer 21 and the cathode 22 use the same mask plate, only one film formation chamber can be provided on the production line to prepare the electronic functional layer 21 and the cathode 22, thereby saving one film formation chamber and reducing the preparation cost.

[0106] In another embodiment, refer to FIG. 6 and FIG. 7. Figure 7 Figure 8 ​​Compared with the above embodiment, the channel td has multiple channels, and the channels td are arranged at intervals along the extension direction of the trace 11. The planar layer 23 and the pixel definition layer 24 extend to the buffer area NA1 and are connected to the support member 30. The channel td penetrates the planar layer 23 and the pixel definition layer 24.

[0107] The first part 31 of the support member 30 is integrally formed with the planar layer 23, and the second part 32 is integrally formed with the pixel definition layer 24, so as to improve the stability of the support member 30 attached to the insulating layer 12.

[0108] In an embodiment, as shown in FIG. 1, the planar layer 23 does not extend into the buffer area NA1, and the pixel definition layer 24 extends into the buffer area NA1 and is connected to the support member 30. The second part 32 of the support member 30 is integrally formed with the pixel definition layer 24. Figure 9

[0109] Correspondingly, the application further provides a preparation method of a display panel. The display panel includes a display area and a non-display area located on at least one side of the display area. The non-display area includes a buffer area and a cathode overlap area located on a side of the buffer area away from the display area. The preparation method of the display panel includes the following steps:

[0110] A support member is formed on a thin film transistor structure layer. The thin film transistor structure layer includes a trace and an insulating layer covering the trace. In the cathode overlap area, a first opening is arranged on the insulating layer, and the first opening exposes the trace. The support member is arranged on the insulating layer and located at the junction of the buffer area and the cathode overlap area. At least one channel is formed on the support member, and the channel communicates the buffer area and the cathode overlap area. The first opening is located in the extension direction of the channel.

[0111] A mask plate is arranged on the support member. An opening area of the mask plate corresponds to the display area and the buffer area, and a shielding area of the mask plate corresponds to the cathode overlap area.

[0112] Based on the same mask plate, an electronic functional layer and a cathode are sequentially formed on the thin film transistor structure layer. The boundary of the cathode exceeds the boundary of the electronic functional layer. The electronic functional layer at least covers the display area and the buffer area. The cathode covers the display area and the buffer area and is connected to the trace through the channel at the first opening.

[0113] The preparation method of the display panel of the application embodiment is described below.

[0114] It should be understood that the preparation method of the display panel of the application embodiment is used to prepare the display panel 100 described in any one of the above embodiments. ​

[0115] Referring to Figure 10 In step B1, a support member 30 is formed on the thin film transistor structure layer 10. The thin film transistor structure layer 10 includes a trace 11 and an insulating layer 12 covering the trace 11. In the cathode overlap region NA2, the insulating layer 12 is provided with a first opening k1 exposing the trace 11. The support member 30 is disposed on the insulating layer 12 at the junction of the buffer region NA1 and the cathode overlap region NA2. The support member 30 is provided with at least one passage td connecting the buffer region NA1 and the cathode overlap region NA2, and the first opening k1 is located in the extension direction of the passage td.

[0116] In step B1, a support member 30 is formed on the thin film transistor structure layer 10. The thin film transistor structure layer 10 includes a trace 11 and an insulating layer 12 covering the trace 11. In the cathode overlap region NA2, the insulating layer 12 is provided with a first opening k1 exposing the trace 11. The support member 30 is disposed on the insulating layer 12 at the junction of the buffer region NA1 and the cathode overlap region NA2. The support member 30 is provided with at least one passage td connecting the buffer region NA1 and the cathode overlap region NA2, and the first opening k1 is located in the extension direction of the passage td.

[0117] Optionally, the support member 30 includes a first portion 31, a second portion 32 and a third portion 33 stacked in sequence on the insulating layer 12. The first portion 31 is formed using the same mask as the planarization layer 23. The second portion 32 is formed using the same mask as the pixel definition layer 24. The third portion 33 is formed using the same mask as the spacer. Such an arrangement can simplify the process.

[0118] Then proceed to step B2.

[0119] Referring to Figure 11 In step B2, a mask MA is disposed on the support member 30. The opening region ma1 of the mask MA corresponds to the display region AA and the buffer region NA1, and the shielding region ma2 of the mask MA corresponds to the cathode overlap region NA2.

[0120] In step B2, a mask MA is disposed on the support member 30. The opening region ma1 of the mask MA corresponds to the display region AA and the buffer region NA1, and the shielding region ma2 of the mask MA corresponds to the cathode overlap region NA2.

[0121] Before step B2, a step of sequentially forming a hole functional layer 26 and a light emitting layer 27 on the pixel definition layer 24 is further included.

[0122] Then proceed to step B3.

[0123] Referring to Figure 12 In step B3, based on the same mask MA, an electron functional layer 21 and a cathode 22 are sequentially formed on the thin film transistor structure layer 10. The boundary of the electron functional layer 21 exceeds the boundary of the cathode 22. The electron functional layer 21 covers at least the display region AA and the buffer region NA1, and the cathode 22 covers the display region AA and the buffer region NA1 and connects the first opening k1 and the trace 11 through the passage td.

[0124] In the preparation method of the embodiment of the present application, the electron functional layer 21 can be prepared by using an evaporation process, and the cathode 22 can be prepared by using an evaporation process or a sputtering process. When both of them are prepared by using an evaporation process, the evaporation angle for preparing the cathode 22 is smaller than the evaporation angle for preparing the electron functional layer 21. When the electron functional layer 21 can be prepared by using an evaporation process, and the cathode 22 can be prepared by using a sputtering process, the angle problem does not need to be considered, and the electron functional layer 21 and the cathode 22 can be prepared by using a conventional process.

[0125] When both of the electron functional layer 21 and the cathode 22 are prepared by using an evaporation process, the evaporation angle for preparing the cathode 22 is θ. In the channel td region, the distance from the first opening k1 to the planar layer 23 and the pixel definition layer 24 located in the display area AA is greater than or equal to the thickness h / tanθ of the support member 30, so as to ensure that the planar layer 23 and the pixel definition layer 24 block the material from passing through the channel td. The present application is described by taking the electron functional layer 21 prepared by using an evaporation process and the cathode 22 prepared by using a sputtering process as an example.

[0126] Based on the different principles of film formation by using an evaporation process and a sputtering process, when the film is formed by using a sputtering process, the sputtering direction of the material particles is random, while when the film is formed by using an evaporation process, the material particles are limited by the evaporation angle. Therefore, when the same mask plate MA is used for film formation, the diffusion area of the film layer formed by using a sputtering process is greater than the diffusion area of the film layer formed by using an evaporation process, that is, when the same opening pattern mask plate MA is used, the film layer coverage area of the cathode 22 is greater than the film layer coverage area of the electron functional layer 21.

[0127] Since the same mask plate MA is used for the electron functional layer 21 and the cathode 22, only one film formation chamber can be arranged on the production line to prepare the electron functional layer 21 and the cathode 22, thereby saving one film formation chamber and reducing the preparation cost.

[0128] The display panel of the embodiment of the present application is provided with a channel passing through the support member located at the junction of the buffer area and the cathode overlap area on the light emitting device layer, so that the material of the cathode can pass through the channel into the cathode overlap area and overlap on the wire exposed by the first opening.

[0129] The electron functional layer is prepared by using an evaporation process, the cathode is prepared by using an evaporation process with a smaller evaporation angle or a sputtering process, and the electron functional layer and the cathode are formed under the same mask plate. Due to the arrangement of the channel, the materials of the cathode and the electron functional layer can extend to the cathode overlap area through the channel. Since the cathode is prepared by using an evaporation process with a smaller evaporation angle or a sputtering process, the film formation range of the cathode is greater than the film formation range of the electron functional layer, and then the cathode can overlap the wire to realize the light emission of the light emitting device layer, thereby reducing the preparation cost of the display panel.

[0130] The display panel and the preparation method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application. In conclusion, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A display panel comprising a display area and a non-display area located at least on one side of the display area, characterized in that: The non-display area includes a buffer area and a cathode overlapping area located on a side of the buffer area away from the display area, and the display panel includes: a thin film transistor structure layer, the thin film transistor structure layer including a wiring and an insulating layer covering the wiring, wherein a first opening is provided on the insulating layer in the cathode overlapping region, and the first opening exposes the wiring; a light-emitting device layer, the light-emitting device layer being disposed on the thin-film transistor structure layer, the light-emitting device layer comprising an electronic functional layer and a cathode disposed on a side of the electronic functional layer away from the thin-film transistor structure layer; a supporting member, the supporting member being disposed on the insulating layer and located at a junction of the buffer zone and the cathode overlapping zone; Wherein, in the buffer zone, the light-emitting device layer is provided with at least one channel, the channel extending through the support member to the cathode overlapping region, and the first opening is located in the extending direction of the channel; the cathode material diffuses into the cathode overlapping region through the channel and connects to the trace; In the non-display area of ​​the orthographic projection pattern of the display panel, the boundary of the cathode exceeds the boundary of the electronic functional layer, the electronic functional layer at least covers the display area and the buffer zone, and the cathode covers the display area and the buffer zone and is connected to the wiring at the first opening through the channel.

2. The display panel according to claim 1, wherein: The light emitting device layer includes a planar layer covering the insulating layer and a pixel definition layer covering the planar layer, and the electronic function layer covers the pixel definition layer; Taking the side of the insulating layer close to the flat layer as the reference plane, the bottom height of the channel is lower than the side of the pixel definition layer in the display area away from the thin film transistor structure layer, and the bottom height of the channel is higher than or equal to the reference plane.

3. The display panel according to claim 2, wherein: The channel includes at least one first hollow opening and a plurality of second hollow openings, wherein one first hollow opening is connected to at least one second hollow opening, and both the first hollow opening and the second hollow opening pass through the planar layer and the pixel definition layer, the first hollow opening is located in the buffer zone, and the second hollow opening passes through the support member; In the orthographic projection pattern of the display panel, an extension direction of the second hollow opening intersects with an extension direction of the wiring.

4. The display panel according to claim 3, wherein: There is at least one first opening. In the orthographic projection pattern of the display panel, one first opening is at least correspondingly arranged in the extending direction of one second hollow opening.

5. The display panel according to claim 4, wherein: There is one first opening. In the orthographic projection pattern of the display panel, the first opening is extended along the extension direction of the wiring, and one first opening is correspondingly arranged in the extension direction of the plurality of second hollow openings.

6. The display panel according to claim 4, wherein: In the orthographic projection pattern of the display panel, a plurality of the first openings are arranged at intervals along the extension direction of the wiring, and one first opening is correspondingly arranged in the extension direction of one second hollow opening.

7. The display panel according to claim 6, wherein: There are multiple supporting members. In the orthographic projection pattern of the display panel, the multiple supporting members are arranged at intervals along the extension direction of the wiring. In the extension direction parallel to the second hollow opening, the supporting member is located between two adjacent first openings. The cathode includes a plurality of overlapping portions located in the cathode overlapping region. One of the overlapping portions is disposed in the first opening and connected to the wiring. The plurality of overlapping portions are arranged at intervals along an extension direction of the wiring.

8. The display panel according to claim 7, wherein: In the orthographic projection pattern of the display panel, along the extending direction of the second hollow opening, the supporting member overlaps with two side areas of the first opening.

9. The display panel according to claim 7, wherein: The width of the second hollow opening is between 10 micrometers and 500 micrometers.

10. The display panel according to claim 2, wherein: At least one of the planarization layer and the pixel definition layer is provided on the same layer as at least a portion of the support member and is made of the same material.

11. The display panel according to claim 10, wherein: The supporting member includes a first portion, a second portion, and a third portion sequentially stacked on the insulating layer, the first portion being disposed in the same layer and made of the same material as the planar layer, and the second portion being disposed in the same layer and made of the same material as the pixel definition layer.

12. The display panel according to claim 2, wherein: The width of the support member is greater than or equal to 10 micrometers.

13. The display panel according to any one of claims 1 to 12, wherein: The thickness of the support member is greater than or equal to 4 micrometers.

14. The display panel according to any one of claims 1 to 12, wherein: The electronic functional layer is connected to a portion of the wiring at the first opening through the channel, and the cathode covers the electronic functional layer in the first opening and is connected to an exposed portion of the wiring.

15. The display panel according to any one of claims 2 to 12, wherein: The electronic functional layer includes at least one of an electron transport layer and an electron injection layer, the light-emitting device layer also includes an anode, a light-emitting layer and a hole functional layer, the anode is arranged on the flat layer, the pixel definition layer is provided with a second opening, the second opening exposes the anode, the hole functional layer and the light-emitting layer are sequentially arranged on the anode and located in the second opening, and the electronic functional layer is arranged on the light-emitting layer.

16. A method for manufacturing a display panel, wherein the display panel comprises a display area and a non-display area located at least on one side of the display area, wherein: The non-display area includes a buffer area and a cathode overlapping area located on a side of the buffer area away from the display area. The method for preparing the display panel includes the following steps: A support member is formed on a thin film transistor structure layer, the thin film transistor structure layer including a wiring and an insulating layer covering the wiring, a first opening is provided on the insulating layer in the cathode overlapping region, the first opening exposing the wiring, the support member is provided on the insulating layer and is located at the junction of the buffer region and the cathode overlapping region, at least one channel is provided on the support member, the channel connecting the buffer region and the cathode overlapping region, and the first opening is located in an extension direction of the channel; A mask is provided on the supporting member, wherein an opening area of ​​the mask corresponds to the display area and the buffer area, and a shielding area of ​​the mask corresponds to the cathode overlapping area; Based on the same mask, an electronic functional layer and a cathode are sequentially formed on the thin film transistor structure layer, and the material of the cathode diffuses into the cathode overlapping area through the channel and connects to the wiring; the boundary of the cathode exceeds the boundary of the electronic functional layer, and the electronic functional layer at least covers the display area and the buffer zone, and the cathode covers the display area and the buffer zone and is connected to the wiring at the first opening through the channel.

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