Timing control circuit and method for multiple power supplies

Abstract

The application discloses a timing control circuit and method for multiple power supplies. The circuit comprises a power supply module configured to output a control voltage via a power supply end; and multiple delay power-on circuits, an input end of a first delay power-on circuit in the multiple delay power-on circuits being electrically coupled to the power supply end of the power supply module, an output end of one delay power-on circuit in the multiple delay power-on circuits being electrically coupled to an input end of a subsequent delay power-on circuit, so that the multiple delay power-on circuits are cascaded in turn, and the output ends of the multiple delay power-on circuits are also respectively electrically coupled to input ends of multiple controlled power supplies; the multiple delay power-on circuits are configured to sequentially output multiple power-on voltages to the multiple controlled power supplies via the respective output ends based on the control voltage. The application can ensure stable control of the timing of multiple power supplies, improve the applicability of the circuit, and reduce the design cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, in particular to a timing control circuit and method for multiple power supplies. BACKGROUND

[0002] When a system has multiple power supply sources, the system usually has strict requirements for the power-on and power-off sequence of different power supplies, and if the power-on sequence or power-off sequence is not executed according to the requirements, the powered equipment may be damaged, causing serious consequences. Currently, the following four schemes are usually used to realize timing control.

[0003] The first scheme is to use a dedicated power management chip. This scheme is generally used for special-purpose chips and is not suitable for some general-purpose designs or low-cost designs because of the high cost and the fact that the chip cannot be universal.

[0004] The second scheme is to use a front-stage power supply voltage or a front-stage power supply chip with a Power good pin to control the power-on of a rear-stage power supply. This scheme solves the problem of chip universality, but such power supply chips are also relatively expensive, and this scheme can only solve the power-on timing control problem and cannot control the power-off timing.

[0005] The third scheme is to add different RC delay controls to the control pins of an ordinary power supply chip to control the power-on timing. This scheme has the lowest cost, but it is also the most unstable. When the circuit has a situation of quick start after shutdown, the delay capacitor stores the charge that has not been completely discharged, which causes the delay time to be incorrect and leads to unexpected situations in the power-on timing. This scheme also cannot solve the problem of power-off timing control.

[0006] The fourth scheme is to use a dedicated timing control chip. However, because the power supply requirements of different circuits are not uniform, the timing of the dedicated chip is basically fixed after production, and the use is not flexible. Moreover, because of the high cost, this scheme is not popular on the market.

[0007] In summary, the current schemes for realizing multiple power supply timing control have the problems of unstable control, high design cost, and low applicability. SUMMARY

[0008] The technical problem to be solved by the present application is to provide a timing control circuit and method for multiple power supplies, which can ensure stable control of the timing of multiple power supplies, improve the applicability of the circuit, and reduce the design cost.

[0009] In one aspect of the present application, a timing control circuit for multiple power supplies is provided. The circuit comprises a power supply module configured to output a control voltage via a power supply terminal; and a plurality of delay power-on circuits, an input terminal of a first delay power-on circuit of the plurality of delay power-on circuits is electrically coupled to the power supply terminal of the power supply module, an output terminal of a delay power-on circuit of the plurality of delay power-on circuits is electrically coupled to an input terminal of a subsequent delay power-on circuit, such that the plurality of delay power-on circuits are cascaded in sequence, and output terminals of the plurality of delay power-on circuits are further electrically coupled to input terminals of a plurality of controlled power supplies respectively, the plurality of delay power-on circuits are configured to output a plurality of power-on voltages to the plurality of controlled power supplies via the respective output terminals in sequence based on the control voltage.

[0010] In another aspect of the present application, a timing control method for multiple power supplies is provided. The method is applied to the timing control circuit for multiple power supplies described above, and comprises: receiving a control voltage of a power supply module; traversing N-stage delay power-on circuits in a connection order based on the control voltage, when a nth-stage delay power-on circuit is traversed, charging the nth-stage delay power-on circuit by a voltage at an input terminal of the nth-stage delay power-on circuit to obtain a corresponding delay power-on voltage of the nth-stage delay power-on circuit; and starting a nth controlled power supply by the corresponding delay power-on voltage.

[0011] According to the technical solution of the present application, the first delay power-on circuit is charged by the control voltage output by the power supply module, when the power-on voltage of the first delay power-on circuit reaches the starting voltage of the controlled power supply, the controlled power supply connected to the first delay power-on circuit is started. Similarly, the subsequent delay power-on circuit is charged by the power-on voltage of the first delay power-on circuit, when the power-on voltage of the subsequent delay power-on circuit reaches the starting voltage of the controlled power supply, the controlled power supply connected to the subsequent delay power-on circuit is started. In this way, the subsequent controlled power supplies are started one by one in a cascaded order by the delay charging of each delay power-on circuit. The present application cascades a plurality of delay power-on circuits, and realizes the power-on control of different timing based on the difference in charging time in different stages of delay power-on circuits. In this circuit, the voltage of the subsequent controlled power supply cannot be greater than the voltage of the previous controlled power supply, which ensures the accurate control of the timing of multiple power supplies, and does not need to use a dedicated timing chip for logic control, effectively reducing the design cost, and improving the applicability of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a circuit connection diagram of a timing control circuit for multiple power supplies according to an embodiment of the present application;

[0013] Figure 2A circuit connection diagram of a timing control circuit for multiple power supplies according to an embodiment of the present application;

[0014] Figure 3 An effect diagram of power-on simulation test of a timing control circuit for multiple power supplies according to an embodiment of the present application;

[0015] Figure 4 A circuit connection diagram of another timing control circuit for multiple power supplies according to an embodiment of the present application;

[0016] Figure 5 A circuit connection diagram of another timing control circuit for multiple power supplies according to an embodiment of the present application;

[0017] Figure 6 An effect diagram of power-off simulation test of a timing control circuit for multiple power supplies according to an embodiment of the present application;

[0018] Figure 7 A flow chart of a timing control method for multiple power supplies according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the technical content, the achieved purposes and effects of the present application clear, the following will be described in detail in combination with the embodiments and the accompanying drawings.

[0020] In the prior art, when a system has multiple power supply sources, the system usually has strict requirements on the power-on and power-off sequence of different power sources. If the power-on or power-off sequence is not executed according to the requirements, the powered equipment may be damaged, causing serious consequences. At present, the following four schemes are usually used to realize timing control:

[0021] The first scheme is to use a special power management chip, integrate all power sources on a chip, and design corresponding digital logic to control the timing, so as to solve the timing problem of power-on and power-off. This scheme is generally used in special chips because of high cost and non-universal chip, and is not suitable for some general design or low-cost design scenarios.

[0022] The second solution is to control the power supply of the next stage by the power supply of the previous stage or the pin of the power supply chip of the previous stage. The output voltage of the power supply of the previous stage or the pin of the Power good (P.G or P.OK signal, which is a TTL signal compatible with the logical and of the DC output voltage detection signal and the AC input voltage detection signal) of the power supply chip of the previous stage is outputted to control the enable pin of the power supply of the next stage, so as to realize the step-by-step power-on. Although this solution solves the problem of the versatility of the chip, the price of the power supply chip is also relatively high. In addition, if the voltage of the power supply of the previous stage is directly used to control the power-on, the voltage of the power supply of the previous stage may be too low to meet the voltage requirement of the enable pin of the power supply chip of the next stage (for example, the current CPU supply voltage is generally lower than 1V), and this solution can only solve the problem of the power-on timing control, and the power-off timing cannot be controlled.

[0023] The third solution is to use a common power supply chip, to connect a resistor and a capacitor in series to the control pin of the power supply chip, and to change the parameters of the resistor and the capacitor to adjust the delay time, so as to realize the different start-up (power-on) sequence of the power supplies and meet the system requirement. This solution has the lowest cost, but is also the most unstable. When the circuit exists the situation of shutdown and fast startup (the input power supply is not completely powered off and then powered on again), because the charge stored in the delay capacitor is not completely discharged, the delay time is wrong, which easily leads to the unexpected situation of the power-on timing, and this solution also cannot solve the problem of the power-off timing control.

[0024] The fourth solution is to use a special timing control chip, which only has a digital logic control function, to use multiple pins of the chip to control the enable pins of the power supply chips, so as to realize the power-on and power-off timing control of the multiple power supplies. However, because the power supply requirements of different circuits are not unified, the timing of the special chip is basically fixed after production, and the use is not flexible. In addition, because of the high cost, the special chip is not popular on the market.

[0025] Therefore, the current solutions that can realize the timing control of multiple power supplies have the problems of unstable control, high design cost and low applicability.

[0026] To solve at least the above technical problems, the present disclosure provides a timing control circuit for multiple power supplies. According to the present disclosure, a first delay power-on circuit is charged by a control voltage output by a power supply module, and when the power-on voltage of the first delay power-on circuit reaches the start voltage of a controlled power supply, the controlled power supply connected to the first delay power-on circuit starts. Similarly, a subsequent delay power-on circuit is charged by the power-on voltage of the first delay power-on circuit, and when the power-on voltage of the subsequent delay power-on circuit reaches the start voltage of a controlled power supply, the controlled power supply connected to the subsequent delay power-on circuit starts. In this way, the subsequent controlled power supplies are started in a cascading order by the delay charging of each delay power-on circuit. In this way, the embodiment according to the present disclosure can achieve different timing control of power-on, and under this circuit, the voltage of a subsequent controlled power supply cannot be greater than the voltage of a previous controlled power supply, ensuring accurate control of the timing of the power-on of multiple power supplies, and without the need for a dedicated timing chip for logic control, effectively reducing design costs, while improving the applicability of the circuit.

[0027] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0028] Figure 1 FIG. 1 is a circuit connection diagram showing a timing control circuit 100 for multiple power supplies according to an embodiment of the present disclosure. Referring to FIG. 1, Figure 1 the circuit 100 includes a power supply module 102 and a plurality of delay power-on circuits 104.

[0029] The power supply module 102 is configured to output a control voltage via a power supply terminal Vcc.

[0030] The plurality of delay power-on circuits 104 are configured to output a plurality of power-on voltages to a plurality of controlled power supplies 106 in succession, respectively, via respective output terminals based on the control voltage.

[0031] An input terminal of a first delay power-on circuit 104 of the plurality of delay power-on circuits 104 is electrically coupled to the power supply terminal Vcc of the power supply module 102, an output terminal of a delay power-on circuit 104 of the plurality of delay power-on circuits 104 is electrically coupled to an input terminal of a subsequent delay power-on circuit 104, such that the plurality of delay power-on circuits 104 are cascaded in turn, and the output terminals of the plurality of delay power-on circuits 104 are also electrically coupled to input terminals of the plurality of controlled power supplies 106, respectively.

[0032] In some embodiments, each delay power-on circuit 104 of the plurality of delay power-on circuits 104 is configured to output a voltage with a set delay as a power-on voltage via the output terminal based on the voltage at the input terminal. In this way, the different timing control of power-on is achieved by the cascading order of the delay power-on circuits 104.

[0033] Figure 2 is a circuit schematic diagram illustrating a timing control circuit 100 for multiple power supplies according to an embodiment of the present disclosure. Referring to Figure 2 In some embodiments, each of the multiple delay power-on circuits 104 includes a power-on resistor RU and a power-on capacitor C. The first end of the power-on resistor RU of the first one of the multiple delay power-on circuits 104 is electrically coupled to the power supply end Vcc of the power supply module 102, and the first end of the power-on resistor RU of the other ones of the multiple delay power-on circuits 104 is electrically coupled to the output end of the previous delay power-on circuit 104. The second end of the power-on resistor RU is electrically coupled to the first end of the power-on capacitor C, and the first end of the power-on capacitor C and the second end of the power-on resistor RU are electrically coupled to the input end of the next delay power-on circuit 104. The second end of the power-on capacitor C is grounded. The first end of the power-on capacitor C and the second end of the power-on resistor RU are also electrically coupled to the input end of the corresponding controlled power supply 106. The delay is determined based on the resistance value of the power-on resistor RU and the capacitance value of the power-on capacitor C. In this way, the voltage of the power-on capacitor C in the previous delay power-on circuit 104 is charged by the power-on resistor RU in the next delay power-on circuit 104, realizing the cascading of the multiple delay power-on circuits 104, and ensuring that the charging voltage of the power-on capacitor C in the next delay power-on circuit 104 is not greater than that of the power-on capacitor C in the previous delay power-on circuit 104 during the charging process, thereby realizing accurate sequential power-on control.

[0034] Figure 2 In the above equation, VCC represents the power supply end of the power supply module 102, RUn and Cn represent the power-on resistor and the power-on capacitor in the nth delay power-on circuit 104, respectively, and SEQn represents the controlled power supply 106 connected to the nth delay power-on circuit 104.

[0035] In some embodiments, the controlled power supply 106 is a power supply chip. In this way, the power-on timing control of multiple channels of discrete controlled power supplies 106 can be realized. When the voltage on the power-on capacitor C reaches the VIH (lower limit of high level) voltage of the enable pin of the power supply chip, the power supply chip is started, and the start time of the current power supply chip is the delay control timing of the current delay power-on circuit 104.

[0036] According to the embodiment of the present application, one end of the power-on resistor RU of the rear-stage delay power-on circuit 104 is connected to the power-on resistor C of the front-stage delay power-on circuit 104. The voltage on the power-on resistor C in the front-stage delay power-on circuit 104 charges the power-on resistor C in the present-stage delay power-on circuit 104 through the power-on resistor RU of the present-stage delay power-on circuit 104, and when the voltage on the power-on resistor C of the present-stage delay power-on circuit 104 reaches the starting voltage of the controlled power source 106 connected thereto, the power source control power source of the present-stage delay power-on circuit 104 is started.

[0037] In some embodiments, by adjusting the electrical parameters of the power-on resistor RU and the power-on resistor C in each stage of the delay power-on circuit 104, the control of the power-on timing interval of different stages can be realized.

[0038] According to the embodiment of the present application, the input end of the rear-stage delay power-on circuit 104 is connected to the output end of the front-stage delay power-on circuit 104, realizing the cascade of the delay power-on circuit 104. On this basis, during the charging rising process of the power-on resistor C in each delay power-on circuit 104, the voltage on the power-on resistor C of the rear-stage delay power-on circuit 104 cannot be greater than the voltage on the power-on resistor C of the front-stage delay power-on circuit 104, realizing accurate sequential control. At the same time, the problem of abnormal power-on timing caused by different residual voltages or parameter mismatching and inaccuracy of the power-on resistor C in the general delay power-on circuit 104 is solved. In addition, the present application realizes the power-on timing control based on a simple circuit structure, solves the problems of high design cost and low scene application flexibility caused by the use of special timing control chips or power management chips, and provides a clear, simple, accurate and controllable circuit implementation method for multi-channel discrete power source starting control.

[0039] Figure 3 is a schematic diagram showing the effect of power-on simulation test of a timing control circuit 100 for multiple power sources according to an embodiment of the present application. Referring to Figure 3 , the circuit includes three delay power-on circuits 104 and three controlled power sources 106, and when the control voltage is output from the power supply end VCC of the power supply module 102, three clear power-on voltages SEQ1\SEQ2\SEQ3 in sequence can be obtained on the corresponding power-on resistors C1\C2\C3 in each delay power-on circuit 104. When the controlled power source 106 is a power source chip with an enable pin VIH voltage of 1.5V, the power-on interval between the three power-on resistors C is about 2ms.

[0040] Figure 4 is a circuit connection diagram of a timing control circuit 200 for multiple power sources according to an embodiment of the present application. Referring to Figure 4In some embodiments, the power supply module 102 is configured to output a first voltage for power-on control via the power supply terminal Out when the input power supply voltage is greater than or equal to a threshold voltage, and output a second voltage for power-off control via the power supply terminal Out when the input power supply voltage is less than the threshold voltage. In this way, by comparing the input power supply voltage with the threshold voltage, different voltages are output for power-on and power-off control, ensuring the voltage safety of the power-on timing circuit.

[0041] In some embodiments, the power supply module 102 includes a voltage comparator or a reset detector configured to compare the input power supply voltage with the threshold voltage, so that the first voltage or the second voltage is output via the power supply terminal Out.

[0042] In some embodiments, the circuit 200 further includes a plurality of delay discharge circuits 202.

[0043] The plurality of delay discharge circuits 202 are configured to discharge the respective output terminals based on the voltage at the respective input terminals and the control voltage, so that a plurality of power-off voltages are sequentially output to the plurality of controlled power supplies 106, respectively.

[0044] The input terminals of the plurality of delay discharge circuits 202 are electrically coupled to the output terminals of the plurality of delay power-on circuits 104, respectively, the output terminals of the plurality of delay discharge circuits 202 are electrically coupled to the power supply terminal Out of the power supply module 102, and the input terminals of the plurality of delay discharge circuits 202 are also electrically coupled to the input terminals of the plurality of controlled power supplies 106, respectively. In this way, the discharge timing control function is added on the basis of the delay power-on circuit 104. When the power supply module 102 is powered off or under-voltage, the delay discharge circuit 202 discharges each delay power-on circuit 104 at different speeds, achieving step-by-step power-off of each controlled power supply 106, and solving the problem that the current power-on timing circuit cannot control the power-off timing.

[0045] Figure 5 is a circuit schematic diagram showing a timing control circuit 200 for multiple power supplies according to an embodiment of the present disclosure. Referring to Figure 5In some embodiments, each of the plurality of delay discharge circuits 202 includes a discharge resistor RD and an isolation diode D. A first end of the discharge resistor RD is electrically coupled to an output end of the corresponding delay power-on circuit 104, a second end of the discharge resistor RD is electrically coupled to an anode of the isolation diode D, and a cathode of the isolation diode D is electrically coupled to a power supply end Out of the power supply module 102. In this way, when the power supply module 102 outputs a first voltage, the isolation diode D is cut off, and at this time the first voltage is used to control the delay power-on circuit 104 to generate different power-on sequences respectively to start the controlled power supply 106, thereby completing the power-on sequence control. When the power supply module 102 outputs a second voltage, the isolation diode D is turned on, and at this time each delay power-on circuit 104 will step-by-step discharge through the corresponding discharge resistor RD, isolation diode D and power supply module 102. When the power-on voltage of the delay power-on circuit 104 is lower than the start voltage of the controlled power supply 106, the controlled power supply 106 is then turned off, thereby completing the power-off sequence control, and solving the problem that the current power-on and power-off sequences cannot be adjusted at will according to the needs through the logic control of the power supply chip.

[0046] Figure 5 In the formula, U1 represents the power supply module 102, and RDn and Dn represent the discharge resistor and the isolation diode in the nth delay discharge circuit 202, respectively.

[0047] In some embodiments, each of the plurality of controlled power supplies 106 is configured to power on or power off a downstream circuit based on a received voltage.

[0048] In some embodiments, the Vcc pin of the power supply module 102 is used to input an input power supply voltage, and the Out pin of the power supply module 102 is used as a power supply end to output the first voltage or the second voltage.

[0049] In some embodiments, the first voltage is greater than the second voltage. When powering on, the input power supply voltage of the power supply module 102 is greater than or equal to a threshold voltage, and the power supply module 102 outputs a high level to control the delay power-on circuit 104 to charge. When powering off, the input power supply voltage of the power supply module 102 is less than the threshold voltage, and the power supply module 102 outputs a low level to control the delay discharge circuit 202 to discharge.

[0050] In some embodiments, by adjusting the electrical parameters of the discharge resistor RD in each stage of the delay discharge circuit 202, the power-off sequence interval control of the power-on resistor C of different stages can be realized.

[0051] According to the embodiment of the present application, when the input power supply voltage of the power supply module 102 is greater than or equal to the threshold voltage, the power supply module 102 outputs the first voltage, and since the delay discharge circuit 202 is provided with the isolation diode D, the first voltage output by the power supply module 102 cannot affect the subsequent circuits through the delay discharge circuit 202 where the isolation diode D is located. At this time, the first voltage is only used to control the delay power-on circuit 104 to generate different power-on time sequences to start the controlled power supply 106. When the input power supply voltage of the power supply module 102 is less than the threshold voltage, the power supply module 102 outputs the second voltage, and at this time, the voltage of the power-on resistor C in the delay power-on circuit 104 is higher than the second voltage, the isolation diode D is forward-biased, and then the voltage of the power-on resistor C in each stage of the delay power-on circuit 104 is discharged through the discharge resistor RD, the isolation diode D and the power supply module 102. When the voltage of the power-on resistor C is lower than the VIL (upper limit of low level) voltage of the controlled power supply 106 connected to the current power-on resistor C, the controlled power supply 106 is turned off to output, thereby realizing different power-off time sequences.

[0052] Figure 6 FIG. 13 is a schematic diagram illustrating the effect of a power-off simulation test of a timing control circuit 200 for multiple power supplies according to an embodiment of the present application. Referring to FIG. 13, Figure 6 , the circuit includes three delay power-on circuits 104, three delay discharge circuits 202 and three controlled power supplies 106. When the input power supply voltage input through the Vcc pin of the power supply module 102 is insufficient, three clear voltage signals SEQ1\SEQ2\SEQ3 in sequence can be obtained on the power-on resistors C1\C2\C3 connected to each delay discharge circuit 202. When the controlled power supply 106 is a power supply chip with an enable pin VIH voltage of 1.5V, the power-off interval between the three power-on resistors C is between 0.1 and 0.2ms.

[0053] According to the embodiment of the present application, the delay discharge circuit 202 is correspondingly arranged on the delay power-on circuit 104 to realize power-off time sequence control. By using a voltage comparator or a reset detection chip, whether the input power supply voltage has a power-off or undervoltage problem can be detected in time. At the same time, the delay power-on circuit 104 and the delay discharge circuit 202 are isolated by the isolation diode D, and the power-on resistors C connected to each controlled power supply 106 are discharged at different speeds by the discharge resistor RD in the delay discharge circuit 202, thereby realizing step-by-step power-off of each controlled power supply 106, and solving the problem that most timing control power supplies cannot control the power-off time sequence or cannot arbitrarily set the power-on and power-off time sequences according to application requirements.

[0054] Figure 7 FIG. 14 is a flow chart illustrating a timing control method 300 for multiple power supplies according to an embodiment of the present application. Referring to FIG. 14, Figure 7The method 300 is applied to the above-mentioned timing control circuit for multiple power supplies, and comprises the following steps 302 to 306.

[0055] In step 302, a control voltage of a power supply module is received.

[0056] In some embodiments, the receiving of the control voltage of the power supply module comprises: judging whether an input power supply voltage of the power supply module is greater than or equal to a preset threshold voltage, and if yes, receiving a first voltage for power-on control, so that the N-stage delay power-on circuits are sequentially charged according to the connection order based on the first voltage, to respectively power on each controlled power supply. In this way, the first voltage is delayed by the multiple delay power-on circuits, so as to realize different power-on timing control of different stages of controlled power supplies.

[0057] In step 304, the N-stage delay power-on circuits are sequentially charged based on the control voltage according to the connection order, and when the nth-stage delay power-on circuit is reached, the nth-stage delay power-on circuit is charged by a voltage at an input end of the nth-stage delay power-on circuit, to obtain a corresponding delay power-on voltage of the nth-stage delay power-on circuit. In this way, it is ensured that the charging voltage of the next-stage delay power-on circuit is not greater than that of the previous-stage delay power-on circuit during the charging process of each delay power-on circuit. In this way, even if the charge stored in the delay power-on circuit is not completely discharged, the power-on timing will not appear unexpected due to incorrect delay time, and the accurate control of the power-on timing is ensured.

[0058] In step 306, the nth controlled power supply is started by the corresponding delay power-on voltage.

[0059] In some embodiments, the method 300 can further comprise: obtaining a first power-on time of the (n-1)th controlled power supply and a second power-on time of the nth controlled power supply, and adjusting the resistance value of the power-on resistor and the capacitance value of the power-on capacitor in the nth-stage delay power-on circuit according to the first power-on time and the second power-on time. In this way, the power-on time of the controlled power supply corresponding to the delay power-on circuit can be adjusted by adjusting the resistance value of the power-on resistor and the capacitance value of the power-on capacitor, to realize power-on control of different timing intervals, and solve the problem that the current power-on timing control method cannot arbitrarily set the power-on timing according to the demand.

[0060] In some embodiments, adjusting the resistance value of the power-on resistor and the capacitance value of the power-on capacitor in the n-1th stage delay power-on circuit affects the power-on time of the nth controlled power supply. The power-on time of the nth controlled power supply can be calculated step by step in the connection order by solving the step response. Specifically, the estimated start-up time t1 can be divided into at least 10 time amounts, the n-1th stage voltage of the power-on capacitor in the n-1th stage delay power-on circuit is calculated by the formula t1 = -R1*C*ln((Vcc-Vil) / Vcc), and the nth stage voltage of the power-on capacitor in the nth stage delay power-on circuit is calculated by the n-1th stage voltage. Each time the n-1th stage voltage of the power-on capacitor in the n-1th stage delay power-on circuit is calculated, the power-on time of the nth controlled power supply is increased by t1, until the power-on time of the last controlled power supply is calculated. t1 represents the power-on time of the controlled power supply, R1 represents the resistance value of the power-on resistor, C represents the capacitance value of the power-on capacitor, Vcc represents the voltage value of the power-on capacitor, and Vil represents the upper limit voltage of the low level of the controlled power supply.

[0061] In some embodiments, receiving the control voltage of the power supply module also includes receiving a second voltage for power-down control if the input power supply voltage of the power supply module is less than the threshold voltage. The timing control method also includes sequentially discharging the corresponding delay power-on voltage through an N-stage delay discharge circuit according to the second voltage to power down each controlled power supply, respectively.

[0062] In some embodiments, the resistance value of the discharge resistor in the delay discharge circuit is determined by the difference between the voltage of the power-on capacitor connected to the delay discharge circuit and the VIL voltage of the controlled power supply. However, the voltage of the power-on capacitor is affected by other device parameters, but in actual application, because the power supply module needs to be powered down faster than powered up when it is accidentally powered off, the resistance value of the discharge resistor can be set to 1 / 10 of the resistance value of the power-on resistor, so the influence range of the power-on resistor is reduced to within 10%, and therefore only the discharge time of each controlled power supply can be calculated by the formula t2 = -R2*C*ln((Vcc-Vil) / Vcc) at this time. Wherein, t2 represents the discharge time of the controlled power supply, and R2 represents the resistance value of the discharge resistor.

[0063] In summary, the timing control circuit and method for multiple power supplies provided by the application connects the input end of the later-stage delay power-on circuit to the output end of the former-stage delay power-on circuit, realizes the cascade connection of multiple delay power-on circuits in turn, and supplies power to each controlled power supply through the output end of each delay power-on circuit, and realizes the power-on control of each controlled power supply at different time based on the difference in charging time of different delay power-on circuits. Meanwhile, multiple delay discharge circuits are arranged in the circuit, and under the circuit, the voltage of the later controlled power supply cannot be greater than the voltage of the former controlled power supply during power-on, thereby ensuring the accurate control of the power-on sequence of multiple power supplies, and the discharge resistor can discharge the power-on capacitor at different speeds during power-off, thereby realizing the step-by-step power-off of different controlled power supplies. In the process of realizing the power-on and power-off sequence control, the application does not need to use a special timing chip for logical control, effectively reduces the design cost, and improves the applicability of the circuit.

[0064] The above description is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent transformation or direct or indirect application in the related technical field based on the content of the specification and drawings of the application is also included in the patent protection scope of the application.

Claims

1. A timing control circuit for multiple power supplies, characterized in that, include: The power supply module is configured to output control voltage via the power supply terminal; Multiple delayed power-on circuits are provided, wherein the input terminal of the first delayed power-on circuit is electrically coupled to the power supply terminal of the power supply module, and the output terminal of one delayed power-on circuit is electrically coupled to the input terminal of the next delayed power-on circuit, such that the multiple delayed power-on circuits are cascaded sequentially, and the output terminals of the multiple delayed power-on circuits are also electrically coupled to the input terminals of multiple controlled power supplies; and Multiple delayed discharge circuits are provided, with their input terminals electrically coupled to the output terminals of multiple delayed power-on circuits, their output terminals electrically coupled to the power supply terminal of the power supply module, and their input terminals also electrically coupled to the input terminals of multiple controlled power supplies. The power supply module is configured to output a first voltage for power-on control via the power supply terminal when the input power supply voltage is greater than or equal to a threshold voltage, and to output a second voltage for power-off control via the power supply terminal when the input power supply voltage is less than the threshold voltage. When the power supply module outputs the first voltage, the plurality of delayed power-on circuits are configured to successively output a plurality of power-on voltages to the plurality of controlled power supplies via their respective output terminals based on the control voltage. Each of the plurality of delayed power-on circuits includes a power-on resistor and a power-on capacitor. The first terminal of the power-on resistor in the first delayed power-on circuit is electrically coupled to the power supply terminal of the power supply module. The first terminals of the power-on resistors in the other delayed power-on circuits are electrically coupled to the output terminal of the preceding delayed power-on circuit. The second terminal of the power-on resistor is electrically coupled to the first terminal of the power-on capacitor. The first terminal of the power-on capacitor and the second terminal of the power-on resistor are electrically coupled to the input terminal of the following delayed power-on circuit. The second terminal of the power-on capacitor is grounded. When the power supply module outputs the second voltage, the plurality of delayed discharge circuits are configured to discharge each output terminal based on the voltage at each input terminal and the control voltage, so that a plurality of power-down voltages are successively output to the plurality of controlled power supplies.

2. The timing control circuit for multiple power supplies according to claim 1, characterized in that, Each of the plurality of delayed power-on circuits is configured to output a voltage with a set delay via an output terminal based on the voltage at the input terminal as the power-on voltage.

3. The timing control circuit for multiple power supplies according to claim 2, characterized in that, The first end of the powered capacitor and the second end of the powered resistor are also electrically coupled to the input end of the corresponding controlled power supply. The set delay is determined based on the resistance value of the power-on resistor and the capacitance value of the power-on capacitor.

4. The timing control circuit for multiple power supplies according to claim 1, characterized in that, The power supply module includes a voltage comparator or a reset detector, which is configured to compare the input power supply voltage with the threshold voltage, such that the first voltage or the second voltage is output via the power supply terminal.

5. The timing control circuit for multiple power supplies according to claim 1, characterized in that, Each of the plurality of delayed discharge circuits includes a discharge resistor and an isolation diode; The first end of the discharge resistor is electrically coupled to the output end of the corresponding delayed power-on circuit, the second end of the discharge resistor is electrically coupled to the positive terminal of the isolation diode, and the negative terminal of the isolation diode is electrically coupled to the power supply terminal of the power supply module.

6. The timing control circuit for multiple power supplies according to claim 1, characterized in that, Each of the plurality of controlled power sources is configured to power on or off downstream circuits based on the received voltage.

7. A timing control method for multiple power supplies, characterized in that, The timing control circuit for multiple power supplies according to any one of claims 1 to 6 comprises: Receive the control voltage from the power supply module; Based on the control voltage, the N-stage delayed power-on circuits are traversed in connection order. When the nth-stage delayed power-on circuit is reached, it is charged by the voltage at its input terminal to obtain the corresponding delayed power-on voltage. The nth controlled power supply is started by the corresponding delayed power-on voltage.

8. The timing control method for multiple power supplies according to claim 7, characterized in that, Also includes: Obtain the first power-on time of the (n-1)th controlled power source and the second power-on time of the nth controlled power source; Adjust the resistance value of the power-on resistor and the capacitance value of the power-on capacitor in the nth stage delayed power-on circuit according to the first power-on time and the second power-on time.

9. The timing control method for multiple power supplies according to claim 7, characterized in that, The control voltage of the receiving power supply module includes: Determine whether the input power voltage of the power supply module is greater than or equal to a preset threshold voltage; If so, a first voltage for power-on control is received, such that the N-stage delayed power-on circuits are charged sequentially according to the connection order based on the first voltage, so as to power on each controlled power supply respectively.

10. The timing control method for multiple power supplies according to claim 9, characterized in that, The control voltage for the receiving power supply module also includes: If the input power supply voltage of the power supply module is less than the threshold voltage, then a second voltage for power-down control is received; The timing control method further includes: discharging the corresponding delayed power-on voltage sequentially through an N-stage delayed discharge circuit according to the second voltage, so as to power down each controlled power supply respectively.

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