Display panel, display driving method and display device

Abstract

The application belongs to the display field and particularly relates to a display panel, a display driving method and a display device. The display panel comprises multiple rows of scanning lines, multiple columns of data lines, multiple arrayed pixel units, a gate driving circuit and an opening circuit. The pixel units are arranged at the intersection of the scanning lines and the data lines. The pixel units are connected with the scanning lines of the corresponding row and the data lines of the corresponding column. The gate driving circuit is arranged on at least one side of each row of scanning lines. The opening circuit is connected with at least one scanning line. The opening circuit is used for outputting a switch control line signal to the corresponding scanning line to open the corresponding pixel unit in response to a reset control line signal, so that the reset signal can be written through the data line and reset the corresponding pixel unit. The original picture data is cleared through the reset. Compared with refreshing the next frame picture data on the basis of the original picture, the response speed of the pixel unit is improved, and the visual residual is reduced or eliminated.

Description

Technical Field

[0001] This application belongs to the field of display technology, and specifically relates to a display panel, a display driving method, and a display device. Background Technology

[0002] With the development of display technology, Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become the mainstream display device due to its advantages such as high image quality, power saving, thin body and mature and stable manufacturing process. It is widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers.

[0003] A liquid crystal display includes an array of pixel units. After the gate driving circuit provides a gate driving signal on the corresponding gate line, all TFTs connected to the gate line are switched to the on state, so that each pixel on the gate line receives a display signal from its own connected data line and controls the deflection degree of the liquid crystal in different pixels according to the display signal, thereby realizing the display of a row of pixels.

[0004] When an LCD monitor is displaying an image, the display signal on the data cable is maintained until the next frame recharges the pixel unit. The pixel unit continuously holds the image data, and when the next frame changes, the image data is refreshed based on the previous image. With the increase in LCD monitor refresh rates, if the pixel unit does not promptly clear the original display information, it can easily cause visual persistence, resulting in motion blur and affecting the display effect. Summary of the Invention

[0005] The purpose of this application is to provide a display panel, a display driving method, and a display device to reduce or eliminate visual persistence and improve the display effect of the display panel.

[0006] To achieve the above objectives, this application provides a display panel including multiple rows of scan lines, multiple columns of data lines, and multiple pixel units arranged in an array. The pixel units are disposed at the intersections of the scan lines and the data lines, and each pixel unit is connected to the scan line and the data line of its corresponding column. The display panel further includes:

[0007] A gate driving circuit is disposed on at least one side of each row of the scan lines, and is used to output a gate driving signal to turn on the pixel unit connected to the scan line;

[0008] An enable circuit is provided, which is connected to at least one of the scan lines. The enable circuit is used to respond to a reset control line signal by outputting a switch control line signal to the corresponding scan line to enable the corresponding pixel unit, so that a reset signal can be written through the data line to reset the corresponding pixel unit.

[0009] Optionally, the display panel includes one of the activation circuits, and all the scan lines are connected to the same activation circuit; or

[0010] The display panel includes a plurality of the aforementioned power-on circuits, each power-on circuit being connected to at least one of the aforementioned scan lines, and each power-on circuit being connected to a reset control line in a one-to-one correspondence.

[0011] Optionally, the enable circuit is configured to correspond one-to-one with the scan line. In the row blanking area corresponding to the pixel unit in the nth row, the reset control line controls the enable circuit to output the switch control line signal to the scan line in the n+1th row, where n is an integer greater than or equal to 1.

[0012] Optionally, the power-on circuit is connected to m scan lines, where m is an integer greater than or equal to 1. The power-on circuit includes m first transistors, each of which corresponds to one of the scan lines. The control terminal of each first transistor is connected to the corresponding reset control line, the first terminal of each first transistor is connected to the switch control line, and the second terminal of each first transistor is connected to the scan line of the corresponding row.

[0013] Optionally, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit, which are respectively disposed on both sides of each row of the scan line. The first transistor is disposed between the first gate driving circuit and the pixel unit adjacent to the first gate driving circuit. The enabling circuit further includes m second transistors, which are disposed between the second gate driving circuit and the pixel unit adjacent to the second gate driving circuit. The second transistors are disposed in a one-to-one correspondence with the first transistors. The reset control line, the switch control line, and the scan line connected to the second transistors and the first transistors in the same row are the same.

[0014] This application also provides a display driving method for driving the display panel, the display driving method comprising:

[0015] In the frame blanking area of ​​the previous frame or in part of the row blanking area of ​​the current frame, the reset control line controls at least a portion of the pixel units connected to the scan lines to be turned on.

[0016] The pixel unit connected to the power-on circuit is reset by writing a reset signal through the data line.

[0017] The gate driving circuit outputs the gate driving signal to sequentially activate the reset pixel units connected to the scan lines.

[0018] Optionally, the data line is connected to the source drive circuit, and resetting the pixel unit connected to the enable circuit by writing a reset signal through the data line includes:

[0019] The source drive circuit is controlled to pull the data latch signal high, so that the data line signal of column 2p-1 and the data line signal of column 2p are short-circuited, the polarity of the data line signal of column 2p-1 and the data line signal of column 2p are opposite, and p is an integer greater than or equal to 1.

[0020] Optionally, the display panel includes an enable circuit, and all the scan lines are connected to the same enable circuit. The step of controlling the enable of at least some of the pixel units connected to the scan lines via the reset control line in the frame blanking area of ​​the previous frame or a portion of the row blanking area of ​​the current frame includes:

[0021] In the frame blanking area of ​​the previous frame, all pixel units are turned on by the reset control line.

[0022] Optionally, the display panel includes a plurality of the aforementioned activation circuits, each of the activation circuits being connected to at least one of the scan lines. The step of controlling the activation of at least a portion of the pixel units connected to the scan lines via the reset control line in the frame blanking area of ​​the previous frame or a portion of the row blanking area of ​​the current frame includes:

[0023] The blanking area of ​​a portion of the current frame is activated by the pixel units connected to the activation circuit, which are controlled sequentially by the reset control line.

[0024] This application also provides a display device, including:

[0025] Timing controller;

[0026] The display panel, and the timing controller are connected to the display panel.

[0027] The display panel, display driving method, and display device disclosed in this application have the following beneficial effects:

[0028] In this application, the display panel includes multiple rows of scan lines, multiple columns of data lines, multiple arrayed pixel units, a gate driving circuit, and a power-on circuit. The pixel unit is connected to the scan line of its row and the data line of its column. The gate driving circuit is located on at least one side of each row of scan lines. The power-on circuit is connected to at least one scan line and is used to respond to a reset control line signal by outputting a switch control line signal to the corresponding scan line to power on the corresponding pixel unit. This allows the reset signal to be written through the data lines and reset the corresponding pixel unit. This application clears the original image data through reset. Compared to refreshing the image data of the next frame based on the original image, this improves the response speed of the pixel units, reduces or eliminates visual persistence, improves the display effect of the display panel, and is beneficial for increasing the refresh rate of the display panel.

[0029] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 This is a schematic diagram of the display panel structure in Embodiment 1 of this application.

[0033] Figure 2 This is a schematic diagram of the frame blanking area reset pixel unit in Embodiment 1 of this application.

[0034] Figure 3 This is a schematic diagram of a display panel including multiple power-on circuits in Embodiment 1 of this application.

[0035] Figure 4 This is a schematic diagram of the row blanking area reset pixel unit in Embodiment 1 of this application.

[0036] Figure 5 This is a flowchart illustrating the display driving method in Embodiment 2 of this application.

[0037] Figure 6 This is a schematic diagram of the source drive circuit outputting the reset signal in Embodiment 2 of this application.

[0038] Figure 7 This is a schematic diagram of the display device in Embodiment 3 of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100. Display panel; 101. Horizontal blanking area; 102. Frame blanking area; 103. Display area; 111. Scan line; 112. Data line; 113. Pixel unit; 114. Reset control line; 115. Switch control line;

[0041] 120. Gate drive circuit; 130. Enable circuit; 131. First transistor;

[0042] 200. Timing controller. Detailed Implementation

[0043] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0044] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0045] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0046] Example 1

[0047] See Figure 1 As shown, in this embodiment, the display panel 100 includes multiple rows of scan lines 111, multiple columns of data lines 112, and multiple arrayed pixel units 113. The pixel units 113 are disposed at the intersection of the scan lines 111 and the data lines 112, and the pixel units 113 are connected to the scan lines 111 of the row and the data lines 112 of the column.

[0048] The display panel 100 also includes a gate driving circuit 120 and an enable circuit 130. The gate driving circuit 120 includes a GOA (Gate driver on array) circuit or a gate driving chip. The gate driving circuit 120 is disposed on at least one side of each row of scan lines 111 and is used to output a gate driving signal to enable the pixel units 113 connected to the scan lines 111. When a row of pixel units 113 is enabled, a data line 112 signal is written to the pixel unit 113. The voltage of the data line 112 controls the deflection degree of the liquid crystal within the pixel unit 113, that is, the voltage of the data line 112 controls the brightness of the pixel unit 113, thereby realizing the display of one row of pixels. The gate driving circuit 120 enables the pixel units 113 row by row to realize the display of one frame.

[0049] The power-on circuit 130 is connected to at least one scan line 111. In response to the reset control line 114 (Gate on) signal, the power-on circuit 130 outputs the switch control line 115 signal to the corresponding scan line 111 to power on the corresponding pixel unit 113, allowing the reset signal to be written to and reset the corresponding pixel unit 113 via the data line 112. When the reset signal voltage is equal to or close to the common voltage, the reset signal is written to the pixel unit 113. The liquid crystal in the pixel unit 113 does not deflect or has a very small deflection angle, the brightness of the pixel unit 113 is 0 or close to 0, and the pixel unit 113 displays a black screen. The reset control line 114 can be connected to the timing controller 200 (TCON), which controls the operation of the power-on circuit 130. The switch control line 115 can be connected to the gate drive circuit 120.

[0050] In some technical solutions, when the LCD displays an image, the data line 112 signal is held until the next frame recharges the pixel unit 113. The pixel unit 113 continuously holds the image data, and when the next frame changes, the image data is refreshed based on the original image. As the refresh rate of LCDs increases, if the pixel unit 113 does not clear the original image data in time, it can easily cause visual persistence, resulting in motion blur and affecting the display effect.

[0051] In this embodiment, the display panel 100 includes multiple rows of scan lines 111, multiple columns of data lines 112, multiple arrayed pixel units 113, a gate driving circuit 120, and an enable circuit 130. The pixel unit 113 is connected to the scan line 111 of its row and the data line 112 of its column. The gate driving circuit 120 is disposed on at least one side of each row of scan lines 111. The enable circuit 130 is connected to at least one scan line 111. The enable circuit 130 responds to a reset control line 114 signal by outputting a switch control line 115 signal to the corresponding scan line 111 to enable the corresponding pixel unit 113, allowing the reset signal to be written through the data line 112 and reset the corresponding pixel unit 113. This application clears the original image data through reset. Compared to refreshing the image data of the next frame based on the original image, this improves the response speed of the pixel unit 113, reduces or eliminates visual persistence, improves the display effect of the display panel 100, and is beneficial for increasing the refresh rate of the display panel 100.

[0052] In some embodiments, the display panel 100 includes an activation circuit 130, to which all scan lines 111 are connected. The gate driving circuit 120 activates the pixel units 113 line by line, and the activation circuit 130 can activate all the pixel units 113 connected to the scan lines 111 simultaneously.

[0053] See Figure 2 As shown, when the display panel 100 is displaying, the gate driving circuit 120 turns on the pixel units 113 of the display area 103 line by line, that is, it scans the display area 103 line by line. Before scanning the next line after the last line is finished, preparation time for scanning the next line must be reserved, that is, the line blanking area 101; after the line scanning is finished, that is, the display of one frame is realized. Before scanning the first line of the next frame begins after the last line is finished, preparation time for scanning the next frame must be reserved, that is, the frame blanking area 102.

[0054] In the frame blanking region 102, the enable circuit 130 can simultaneously enable all pixel units 113 connected to all scan lines 111. The reset signal can be written through the data line 112 to reset all pixel units 113, thereby improving the response speed of the pixel units 113.

[0055] In some embodiments, see Figure 3As shown, the display panel 100 includes multiple activation circuits 130, each activation circuit 130 being connected to at least one scan line 111. The number of scan lines 111 connected to each activation circuit 130 is determined by the number of activation circuits 130; at least one activation circuit 130 is provided, and the number of activation circuits 130 can be equal to the number of scan lines 111. Each activation circuit 130 is connected to a reset control line 114 in a one-to-one correspondence, meaning different activation circuits 130 are controlled by different reset control lines 114, allowing the pixel units 113 controlled by the scan lines 111 connected to the activation circuit 130 to be activated sequentially. For example, the display panel 100 may have two or three activation circuits 130, each activation circuit 130 being connected to an equal or approximately equal number of scan lines 111, and the activation circuits 130 dividing the display area 103 into two or three display sub-areas.

[0056] See Figure 4 As shown, before scanning the first display sub-area from top to bottom, the pixel unit 113 of the first display sub-area can be reset in the frame blanking area 102 of the previous frame or the line blanking area 101 corresponding to the last display sub-area. Preferably, before scanning the first display sub-area from top to bottom, the pixel unit 113 of the first display sub-area can be reset in the frame blanking area 102 of the previous frame. When scanning the first display sub-area, the pixel unit 113 of the second display sub-area can be reset in the line blanking area 101 corresponding to the first display sub-area, that is, a certain display sub-area is reset first, and then the reset display sub-area is scanned to improve the response speed of the pixel unit 113. In the line blanking area 101 or the frame blanking area 102, the pixel unit 113 of the display sub-area is not turned on by the gate driving circuit 120 or the turn-on circuit 130, and the pixel unit 113 of the display sub-area is in a maintenance state.

[0057] In some embodiments, the enable circuits 130 and scan lines 111 are configured in a one-to-one correspondence, and the number of enable circuits 130 is equal to the number of scan lines 111. The gate drive circuit 120 includes a gate drive circuit, which is connected to the enable circuit 130. After the gate drive circuit enables the pixel unit 113 in the nth row, in the row blanking region 101 corresponding to the pixel unit 113 in the nth row, the reset control line 114 controls the enable circuit 130 to output the switch control line 115 signal to the scan line 111 in the (n+1)th row, where n is an integer greater than or equal to 1. That is, a certain row of pixel units 113 is reset first, and then the reset row of pixel units 113 is scanned to improve the response speed of the pixel units 113.

[0058] In some embodiments, the power-on circuit 130 is connected to m scan lines 111, where m is an integer greater than or equal to 1. The power-on circuit 130 includes m first transistors 131, each corresponding to one scan line 111. The control terminal of each first transistor 131 is connected to the corresponding reset control line 114, the first terminal of each first transistor 131 is connected to the switch control line 115, and the second terminal of each first transistor 131 is connected to the scan line 111 of the corresponding row. That is, each scan line 111 is connected to one first transistor 131. The first transistors 131 in the power-on circuit 130 turn on or off in response to the reset control line 114 signal, and write the switch control line 115 signal into the pixel unit 113 through the scan line 111.

[0059] The enable circuit 130 includes m first transistors 131. Each first transistor 131 controls the pixel unit 113 connected to a row of scan lines 111. The structure is simple, and the gate drive circuit 120 and the enable circuit 130 do not interfere with each other, which facilitates the design of the timing of the reset control line 114 signal.

[0060] In some embodiments, the gate driving circuit 120 includes a first gate driving circuit and a second gate driving circuit, which are respectively disposed on both sides of each row of scan lines 111. That is, the display panel 100 is driven by a dual-sided gate driving circuit to improve the driving capability of the gate driving circuit. The first transistor 131 of the power-on circuit 130 is disposed between the first gate driving circuit and the pixel unit 113 adjacent to the first gate driving circuit. The power-on circuit 130 may also include m second transistors, which are disposed between the second gate driving circuit and the pixel unit 113 adjacent to the second gate driving circuit. The second transistors are disposed in a one-to-one correspondence with the first transistors 131. The reset control line 114, switch control line 115 and scan line 111 connected to the second transistors and the first transistors 131 in the same row are the same.

[0061] When the display panel 100 is driven by a dual-side gate driving circuit, the transistors controlling each row of pixel units 113 in the turn-on circuit 130 are respectively located on both sides of all pixel units 113 in each row, which can enhance the driving capability of the switch control line 115 signal.

[0062] Example 2

[0063] In this embodiment, the display driving method is used to drive the display panel 100 disclosed in Embodiment 1. See also... Figure 5 As shown, the display driving method includes:

[0064] S100: In the frame blanking area 102 of the previous frame or in part of the line blanking area 101 of the current frame, at least some of the pixel units 113 connected by the scan lines 111 are turned on by the reset control line 114.

[0065] S200: Write a reset signal via data line 112 to reset the pixel unit 113 connected to the enable circuit 130;

[0066] S300: The gate drive circuit 120 outputs a gate drive signal to turn on the reset pixel units 113 connected to the scan line 111 line by line.

[0067] Before scanning a line, the pixel unit 113 connected to it is turned on by the power-on circuit 130, and the pixel unit 113 connected to the power-on circuit 130 is reset by writing a reset signal through the data line 112. After the pixel unit 113 is reset, the line is scanned one by one, which can improve the response speed of the pixel unit 113, reduce or eliminate visual persistence, and improve the display effect of the display panel 100.

[0068] In some embodiments, the data line 112 is connected to the source driving circuit, and the pixel unit 113 connected to the reset enable circuit 130 is reset by writing a reset signal through the data line 112.

[0069] The control source drive circuit pulls the data latch signal (TP) high, shorting the data line 112 output to column 2p-1 and the data line 112 output to column 2p. The polarities of the data line 112 output to column 2p-1 and the data line 112 output to column 2p are opposite, where p is an integer greater than or equal to 1. For example, the data line 112 output to column 2p-1 may be greater than the common voltage, while the data line 112 output to column 2p may be less than the common voltage. Because the polarities of the data line 112 output to column 2p-1 and the data line 112 output to column 2p are opposite, when the source drive circuit internally shorts the data line 112 output to column 2p-1 and the data line 112 output to column 2p, the two signals will neutralize to generate a reset signal. The reset signal voltage is equal to or close to the common voltage. Figure 6 As shown, both data line 112 in column 2p-1 and data line 112 in column 2p output reset signals.

[0070] By using a source drive circuit to generate a reset signal, without the need for external circuitry, the structure of the display panel 100 can be simplified, and the manufacturing cost of the display panel 100 can be reduced.

[0071] It should be noted that the reset signal is generated by pulling the data latch signal high, but it is not limited to this. The reset signal can also be generated by connecting the data line 112 of column 2p-1 and the data line 112 of column 2p through an external circuit, depending on the situation.

[0072] In some embodiments, the display panel 100 includes an enable circuit 130, with all scan lines 111 connected to the same enable circuit 130. Controlling the activation of at least some of the pixel units 113 connected to the scan lines 111 via a reset control line 114 in the frame blanking area 102 of the previous frame or a portion of the line blanking area 101 of the current frame includes:

[0073] In the frame blanking area 102 of the previous frame, all pixel units 113 are turned on by the reset control line 114.

[0074] In the frame blanking region 102, the control enable circuit 130 simultaneously enables all pixel units 113 connected to all scan lines 111, and controls the source drive circuit to generate a reset signal and reset all pixel units 113 through the data line 112, which can improve the response speed of pixel units 113.

[0075] In some embodiments, the display panel 100 includes a plurality of activation circuits 130, each activation circuit 130 being connected to at least one scan line 111. The display panel 100 may have two or three activation circuits 130, each activation circuit 130 being connected to an equal or approximately equal number of scan lines 111. The activation circuits 130 divide the display area 103 into two or three display sub-areas. In the frame blanking area 102 of the previous frame or a portion of the line blanking area 101 of the current frame, controlling the activation of at least a portion of the pixel units 113 connected to the scan lines 111 via the reset control line 114 includes:

[0076] The blanking area 101 of the current frame is partially controlled by the reset control line 114 to turn on the pixel units 113 connected to the turn-on circuit 130.

[0077] Before scanning the first display sub-area from top to bottom, the pixel unit 113 of the first display sub-area can be reset in the frame blanking area 102 of the previous frame or the line blanking area 101 corresponding to the last display sub-area; when scanning the first display sub-area, the pixel unit 113 of the second display sub-area can be reset in the line blanking area 101 corresponding to the first display sub-area, that is, a certain display sub-area is reset first, and then the reset display sub-area is scanned to improve the response speed of the pixel unit 113.

[0078] Example 3

[0079] See Figure 7As shown, the display device includes a display panel 100 and a timing controller 200. The timing controller 200 is connected to the display panel 100 via a gate driving circuit 120 and a source driving circuit. A reset control line 114 can be connected to the timing controller 200. The display panel 100 includes the display panel 100 disclosed in Embodiment 1. The timing controller 200 executes the display driving method disclosed in Embodiment 2 to drive the display panel 100 to display an image.

[0080] The display device includes a display panel 100, which includes multiple rows of scan lines 111, multiple columns of data lines 112, multiple arrayed pixel units 113, a gate driving circuit 120, and an enable circuit 130. The pixel unit 113 is connected to the scan line 111 of its row and the data line 112 of its column. The gate driving circuit 120 is disposed on at least one side of each row of scan lines 111. The enable circuit 130 is connected to at least one scan line 111 and is used to respond to a reset control line 114 signal by outputting a switch control line 115 signal to the corresponding scan line 111 to enable the corresponding pixel unit 113, allowing a reset signal to be written through the data lines 112 and reset the corresponding pixel unit 113. This application clears the original image data through reset. Compared to refreshing the image data of the next frame based on the original image, this improves the response speed of the pixel unit 113, reduces or eliminates visual persistence, improves the display effect of the display panel 100, and is beneficial for increasing the refresh rate of the display panel 100.

[0081] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0082] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0083] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0084] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display panel comprising multiple rows of scan lines, multiple columns of data lines, and multiple pixel units arranged in an array, wherein the pixel units are disposed at the intersections of the scan lines and the data lines, and the pixel units are connected to the scan lines of their corresponding rows and the data lines of their corresponding columns, characterized in that, The display panel also includes: A gate driving circuit is disposed on at least one side of each row of the scan lines, and is used to output a gate driving signal to turn on the pixel unit connected to the scan line; An enable circuit is provided, which is connected to at least one of the scan lines. The enable circuit is used to respond to a reset control line signal and output a switch control line signal to the corresponding scan line to enable the corresponding pixel unit. This allows a reset signal to be written to the pixel unit through the data line. The voltage of the reset signal is equal to the common voltage. The reset signal can reset the pixel unit so that the liquid crystal in the pixel unit is not deflected.

2. The display panel according to claim 1, characterized in that, The display panel includes one of the aforementioned activation circuits, and all the scan lines are connected to the same activation circuit; or The display panel includes a plurality of the aforementioned power-on circuits, each power-on circuit being connected to at least one of the aforementioned scan lines, and each power-on circuit being connected to a reset control line in a one-to-one correspondence.

3. The display panel according to claim 2, characterized in that, The activation circuit is configured in a one-to-one correspondence with the scan lines. In the row blanking area corresponding to the pixel unit in the nth row, the reset control line controls the activation circuit to output the switch control line signal to the scan line in the n+1th row, where n is an integer greater than or equal to 1.

4. The display panel according to any one of claims 1 to 3, characterized in that, The power-on circuit is connected to m scan lines, where m is an integer greater than or equal to 1. The power-on circuit includes m first transistors, each of which corresponds to one scan line. The control terminal of each first transistor is connected to the corresponding reset control line, the first terminal of each first transistor is connected to the switch control line, and the second terminal of each first transistor is connected to the scan line of the corresponding row.

5. The display panel according to claim 4, characterized in that, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit, which are respectively disposed on both sides of each row of the scan line. The first transistor is disposed between the first gate driving circuit and the pixel unit adjacent to the first gate driving circuit. The enable circuit also includes m second transistors, which are disposed between the second gate driving circuit and the pixel unit adjacent to the second gate driving circuit. The second transistors are disposed in a one-to-one correspondence with the first transistors. The reset control line, the switch control line and the scan line connected to the second transistors and the first transistors in the same row are the same.

6. A display driving method, characterized in that, The display driving method is used in the display panel as described in any one of claims 1 to 5, and the display driving method includes: In the frame blanking area of ​​the previous frame or in part of the row blanking area of ​​the current frame, the reset control line controls at least a portion of the pixel units connected to the scan lines to be turned on. The pixel unit connected to the power-on circuit is reset by writing a reset signal through the data line. The gate driving circuit outputs the gate driving signal to sequentially activate the reset pixel units connected to the scan lines.

7. The display driving method according to claim 6, characterized in that, The data line is connected to the source driving circuit, and resetting the pixel unit connected to the enable circuit by writing a reset signal through the data line includes: The source drive circuit is controlled to pull the data latch signal high, so that the data line signal of column 2p-1 and the data line signal of column 2p are short-circuited, the polarity of the data line signal of column 2p-1 and the data line signal of column 2p are opposite, and p is an integer greater than or equal to 1.

8. The display driving method according to claim 6, characterized in that, The display panel includes an activation circuit, and all scan lines are connected to the same activation circuit. The step of controlling the activation of at least some of the pixel units connected to the scan lines via the reset control line in the frame blanking area of ​​the previous frame or a portion of the row blanking area of ​​the current frame includes: In the frame blanking area of ​​the previous frame, all pixel units are turned on by the reset control line.

9. The display driving method according to claim 6, characterized in that, The display panel includes a plurality of the aforementioned activation circuits, each of the activation circuits being connected to at least one of the scan lines. The step of controlling the activation of at least a portion of the pixel units connected to the scan lines via the reset control line in the frame blanking area of ​​the previous frame or a portion of the row blanking area of ​​the current frame includes: The blanking area of ​​a portion of the current frame is activated by the pixel units connected to the activation circuit, which are controlled sequentially by the reset control line.

10. A display device, characterized in that, include: Timing controller; The display panel as described in any one of claims 1 to 5, wherein the timing controller is connected to the display panel.

Images