Semiconductor device and method of forming in-device deep trenches and shallow trenches

Abstract

Semiconductor device and method for forming deep and shallow trenches in the device, the invention relates to the method for forming power semiconductor device, in order to overcome the adverse effects caused by the prior art in the formation of trenches with different depths at the same time, the invention uses the protection of hard mask layer and trench filler to form trenches with different depths in turn, the invention proposes several methods for forming trench network structure in trench devices, which is beneficial to reduce the height transition area between deep trenches and shallow trenches, and can reduce the difficulty of process control, increase the uniformity and consistency of the depth and width of deep trenches and shallow trenches in the trench network structure of the trench power device.

Description

Technical Field

[0001] This invention relates to a method for forming power semiconductor devices, and particularly to a method for forming deep trenches and shallow trenches in a trench network of a power semiconductor device. Background Technology

[0002] To further improve the performance of trench power devices, it is necessary to form a trench network structure consisting of deep trenches 101 and shallow trenches 102 in the trench device, as shown in Chinese patent applications CN2023116607210 and CN2023113557510.

[0003] The method for forming deep and shallow trenches in a trench network is as follows: A hard mask pattern is formed on the semiconductor. By adjusting the etching process and etching simultaneously, shallow trenches are etched at the narrower pattern opening, and deep trenches are etched at the wider pattern opening. Due to simultaneous etching, the depth difference between the deep and shallow trenches cannot be too large, and precise process control is required. Furthermore, since the trench depth is entirely controlled by the hard mask width, process offsets in the hard mask pattern opening width, surface material residue, and slight deviations in the etching angle can easily lead to defects in the trench structure after etching. For example, an over-etched region may appear at the junction of deep trench 101 and shallow trench 102. Figure 1 As shown in Figure A, for example, an under-etched area appears in the shallow trench 102, such as... Figure 1 As shown in B, this type of trench defect can affect subsequent trench filling processes and even cause device failure, thus reducing production yield. In addition, there is a significant transition region between the deep trench 101 and the shallow trench 102, which limits the further reduction of cell size along the shallow trench direction, thereby limiting further improvement in device performance.

[0004] Another method for forming deep and shallow trenches in a trench network is as follows: First, a hard mask is formed on the semiconductor. A first photolithography step is performed to form openings in the first hard mask pattern, and then etching is performed to create the first type of trenches. Next, a second photolithography step is performed to form openings in the second hard mask pattern. Finally, etching is performed, resulting in deep trenches formed from the first type of trenches and shallow trenches formed below the openings in the second hard mask pattern. In other words, different openings are formed sequentially on the hard mask, and then different openings are etched to form trenches of different depths. This method can increase the depth difference between deep and shallow trenches and improve the control requirements of the etching process. However, it still cannot solve the problem of excessively long transition regions between deep and shallow trenches. Furthermore, in the manufacturing process of devices with trench network structures, it is necessary to reduce the difficulty of process control for photolithography and trench etching, and to increase the uniformity and consistency of the depth and width of deep and shallow trenches in the trench network structure of trench power devices. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes a method for forming deep trenches and shallow trenches in semiconductor devices, wherein the method comprises:

[0006] First, a patterned hard mask layer is formed on the upper surface of the semiconductor by photolithography, and etching is performed under the protection of the hard mask layer to form the first trench;

[0007] Next, the first trench is filled with trench filler;

[0008] Next, expose the location of the second trench, form the second trench under the protection of the hard mask layer and the trench filler, and then connect the first trench and the second trench to form a raised transition area at the junction;

[0009] The first and second trenches are trenches of different depths.

[0010] When the first groove is a deep groove and the second groove is a shallow groove, the manufacturing method includes the following steps:

[0011] The first step is to form a patterned hard mask layer on the upper surface of the semiconductor by photolithography, and then to form deep trenches by vertical semiconductor etching.

[0012] The second step involves etching the hard mask layer back onto the semiconductor platform and filling the deep trench with trench filler. The trench filler extends beyond the deep trench and reaches the retracted position of the hard mask layer on the side of the trench.

[0013] The third step is to form a patterned photoresist and expose the hard mask layer at the shallow trench etched area;

[0014] The fourth step is to etch the exposed hard mask layer and then remove the photoresist;

[0015] The fifth step involves etching the semiconductor under the protection of the trench filler and the retained hard mask layer to form shallow trenches and raised transition regions.

[0016] The sixth step is to remove the trench filler to connect the deep and shallow trenches, forming a trench network structure.

[0017] When the first groove is a shallow groove and the second groove is a deep groove, the manufacturing method includes the following steps:

[0018] The first step is to form a patterned hard mask layer on the upper surface of the semiconductor by photolithography, and then to perform semiconductor etching in the vertical direction to form shallow trenches.

[0019] The second step is to form a trench filler in the shallow trench;

[0020] The third step is to form a patterned photoresist and expose the hard mask layer at the deep trench etched area;

[0021] The fourth step is to etch the exposed hard mask layer;

[0022] The fifth step is to remove the photoresist and etch the semiconductor under the protection of the trench filler and the retained hard mask layer to form a deep trench. A protected area is retained between the deep trench and the shallow trench.

[0023] Step 6: Remove the trench filler;

[0024] The seventh step involves etching the semiconductor using an isotropic method to connect the deep trenches and shallow trenches, and forming a raised transition region at the junction of the deep trenches and shallow trenches to form a trench network structure within the semiconductor device.

[0025] Furthermore, in the sixth step, the hard mask is etched back onto the semiconductor platform, during which the residual hard mask layer located between the deep trench and the shallow trench is completely removed.

[0026] When the first groove is a shallow groove and the second groove is a deep groove, the manufacturing method includes the following steps:

[0027] The first step is to form a patterned hard mask layer on the upper surface of the semiconductor by photolithography, and then to perform semiconductor etching in the vertical direction to form shallow trenches.

[0028] The second step is to form a trench filler in the shallow trench;

[0029] The third step is to form a patterned photoresist and expose the hard mask layer at the deep trench etched area;

[0030] The fourth step is to etch the exposed hard mask layer;

[0031] The fifth step is to remove the photoresist and etch the semiconductor under the protection of the trench filler and hard mask layer to form a deep trench. At this time, the deep trench and the shallow trench are not connected, and a protected area is retained between them.

[0032] Step 6: Remove the trench filler;

[0033] The seventh step involves thermal oxidation to form sacrificial oxides within the trenches, where the semiconductor protection zone between the deep and shallow trenches is completely oxidized to form sacrificial oxides.

[0034] Step 8: Remove the sacrificial oxide between the deep trenches and the shallow trenches to connect the deep trenches and the shallow trenches, and form a raised transition region at the junction of the deep trenches and the shallow trenches to form a trench network structure in the device.

[0035] The manufacturing process for forming a shielded gate trench MOSFET device using this method is as follows:

[0036] The first step is to form a hard mask thin oxide layer, a hard mask thin nitride layer, and a hard mask thick oxide layer on the semiconductor layer, respectively. Then, photolithography is performed to form openings in the hard mask pattern. Next, the semiconductor is etched to form deep trenches.

[0037] The second step is to form a trench oxide layer in the trench, and then form a shielding gate electrode in the trench.

[0038] The third step is to form an oxide on the upper surface of the semiconductor and perform chemical mechanical polishing on the oxide, with the polishing stopping on the hard mask thin nitride layer;

[0039] The fourth step is to perform photolithography, under the protection of photoresist, to remove the hard mask thin nitride layer and the hard mask thin oxide layer below it, exposing the shallow trench etching area, wherein the width of the exposed shallow trench etching area is slightly smaller than the width of the shallow trench.

[0040] The fifth step involves etching the semiconductor to form shallow trenches, at which point the deep trenches and shallow trenches are interconnected; a raised transition region is formed in the transition area between the etched deep trenches and shallow trenches.

[0041] Step 6: Etch the oxide on the upper part of the deep trench and expose the trench sidewalls, while the raised transition area is preserved;

[0042] The seventh step is to form a gate oxide layer through thermal oxidation;

[0043] Step 8: Form the gate electrode;

[0044] The ninth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

[0045] Furthermore, in the sixth step, photolithography is first performed, using photoresist to protect some of the oxides on the left and right sides of the shielding gate electrode in the deep trench. The oxides are then dry-etched to expose the upper sidewalls of the deep trench. The remaining oxides on the left and right sides of the shielding gate electrode form a thicker inter-electrode isolation oxide layer.

[0046] The present invention also provides a semiconductor device comprising a trench network consisting of deep trenches and shallow trenches, characterized in that the deep trenches and shallow trenches are formed by the above-described forming method, a raised transition region is provided at the junction of the edge of the shallow trench and the deep trench, the length of the raised transition region is less than one-third of the length of the shallow trench and is between 0.03-1 μm, and the height of the raised transition region is between 0.05-0.5 μm.

[0047] Furthermore, the raised transition area is a smooth arc surface that smoothly transitions from the sidewall to the inside of the shallow groove.

[0048] This invention proposes several methods for forming trench network structures in trench devices, which helps to reduce the height transition area between deep and shallow trenches, reduce the difficulty of manufacturing process control, and increase the uniformity and consistency of the depth and width of deep and shallow trenches in the trench network structure of trench power devices. Attached Figure Description

[0049] Figure 1 A-1B represents a defect that occurs during the formation of an existing trench network structure.

[0050] Figure 2-7 This is a cross-sectional schematic diagram of a key step in forming a trench network structure according to an embodiment of the present invention. Figure 8-13 This is a cross-sectional schematic diagram of a key step in forming a trench network structure according to another embodiment of the present invention.

[0051] Figure 14-21 This is a cross-sectional schematic diagram of the key steps in the manufacturing process of a shielded gate trench MOSFET device according to an embodiment of the present invention.

[0052] Figure 22 This is a cross-sectional schematic diagram of a key step in the manufacturing process of a shielded gate trench MOSFET device according to another embodiment of the present invention. Detailed Implementation

[0053] The positional terms used in this document, such as "up," "down," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," refer to the relative positions shown in the reference illustrations. No fixed orientation is restricted in actual implementation. It should be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines representing the boundaries of doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.

[0054] Example 1

[0055] The method of the first embodiment of the present invention is as follows: Figure 2-7 As shown.

[0056] The first step involves forming a patterned hard mask layer 121 on the upper surface of the semiconductor using photolithography, followed by vertical semiconductor etching to form deep trenches 101. Figure 2 As shown.

[0057] The second step involves forming a trench filler 105 within the deep trench 101. The trench filler 105 fills above the deep trench and extends to the side of the trench to the retraction position 104 of the hard mask layer 121. Figure 3 As shown.

[0058] The third step involves forming a patterned photoresist and exposing the hard mask layer 121 at the shallow trench etched region 202, such as... Figure 4 As shown.

[0059] The fourth step is to etch the exposed hard mask layer 121, and then remove the photoresist, such as... Figure 5 As shown.

[0060] Fifth, under the protection of trench filler 105 and hard mask layer 121, the semiconductor is etched to form shallow trench 102, such as... Figure 6 As shown;

[0061] Step 6: Remove the trench filler 105. The deep trench 101 and shallow trench 102 are connected to form a trench network structure. Since the retraction position 104 is filled with trench filler, the etching in step 5 will form a raised transition region 103. This raised transition region 103 is formed at the junction of two trenches, such as... Figure 7 As shown.

[0062] During the etching of the shallow trench 102 in step five of the above process, the morphology of the deep trench 101 is not affected by the etching of the shallow trench, under the protection of the trench filler 105 and the hard mask layer 121. The morphologies of the deep trench 101 and the shallow trench 102 are controlled by different etching processes, thus allowing for better adjustment of the morphologies of the deep trench 101 and the shallow trench 102, while also achieving better uniformity.

[0063] The hard mask layer 121 may be a nitrided layer, an oxide layer, or a combination of a nitrided layer and an oxide layer.

[0064] The trench filler 105 may be an oxide, nitride, organic compound, or a combination layer of oxide and polysilicon. In one embodiment, the trench filler 105 is an oxide and is formed by a deposition process.

[0065] After the trench filler 105 is formed, it may be etched back through etching or chemical mechanical polishing processes to expose the upper surface of the hard mask layer 121.

[0066] In one embodiment, a chemical mechanical polishing process is used to remove the trench filler 105 on the upper surface of the semiconductor, and a hard mask layer 121 is used as the polishing stop layer.

[0067] Typically, before forming the trench filler 105 in the second step, the hard mask may be retracted onto the semiconductor platform through processes such as etching, which is beneficial for subsequent trench filling processes. This hard mask retraction process can also adjust the morphology at the junction of shallow and deep trenches: such as... Figure 5As shown, in the shallow trench etching region 202, after the hard mask retracted to the upper surface of the semiconductor is removed, the semiconductor platform has trench filler 105 extending from the trench into the semiconductor platform. That is, the trench filler 105 extends into the trench, thereby enabling the trench filler 105 to make the trench depth at the connection between the deep trench 101 and the shallow trench 102 shallower during the fifth step of semiconductor etching. This results in the shallow trench 102 being a concave shape, shallow on both sides and deep in the middle, with a raised transition region 103 formed at the edge. Figure 6 and 7 As shown, in the process of forming a shielded gate device, this morphology helps to reduce the electric field strength between the gate oxide layer and the underlying semiconductor at the trench connection when reverse biased, which can reduce gate leakage current and enhance the reliability of the device.

[0068] Example 2

[0069] In the above embodiments, deep trenches 101 are formed first, followed by shallow trenches 102. In some layout designs with high deep trench density, the high surface stress of the wafer after forming deep trenches may cause wafer warping, resulting in an uneven semiconductor surface, which in turn affects the subsequent shallow trench formation process and even the subsequent trench filling. Therefore, in another embodiment of the present invention, shallow trenches 102 may be formed first, followed by deep trenches 101. A feasible embodiment is as follows:

[0070] The method of the second embodiment of the present invention is as follows: Figure 8-13 As shown.

[0071] The first step involves forming a patterned hard mask layer 121 on the upper surface of the semiconductor using photolithography, followed by vertical semiconductor etching to form shallow trenches 102. Figure 8 As shown.

[0072] The second step is to form a groove filler 105 within the shallow groove 102, such as... Figure 9 As shown.

[0073] The third step is to form a patterned photoresist and expose the hard mask layer 121 at the deep trench etched region 201.

[0074] The fourth step is to etch the exposed hard mask layer 121, as shown below. Figure 10 As shown.

[0075] The fifth step involves removing the photoresist and etching the semiconductor under the protection of the trench filler 105 and the retained hard mask layer 121 to form a deep trench 101. At this point, the deep trench 101 and the shallow trench 102 are not connected, with a protective zone 106 remaining in between. Figure 11 As shown.

[0076] Step 6: Remove the trench filler 105, as shown. Figure 12As shown.

[0077] Step 7: Etch the semiconductor using an isotropic method to connect the deep trench 101 and the shallow trench 102, and form a raised transition region 103 at the junction of the deep trench 101 and the shallow trench 102, thus forming a trench network structure, such as... Figure 13 As shown.

[0078] In step seven, the semiconductor etching method may be wet etching. After semiconductor etching, the trench depth at the connection between the deep trench 101 and the shallow trench 102 is shallower, and a raised transition region 103 is formed in the transition region. This helps to reduce the electric field strength between the gate oxide layer and the underlying semiconductor at the trench connection under reverse bias, thereby reducing gate leakage current and enhancing device reliability. In addition, since the breakdown voltage of the raised transition region 103 is higher than that of the connected shallow trench 102, it can ensure that the path of the avalanche current is far away from the trench transition region during device avalanche breakdown, preventing the thinner gate oxide layer in the transition region from being broken down, thus improving the overall avalanche breakdown resistance of the device.

[0079] The length of the raised transition zone 103 is less than one-third of the length of the shallow trench and is between 0.03-1 μm. The height of the raised transition zone is between 0.05-0.5 μm. It is a smooth arc surface that smoothly transitions from the sidewall position of the shallow trench inward.

[0080] In the above process steps, the morphology of deep trench 101 and shallow trench 102 is controlled by different etching processes, so the morphology of deep trench 101 and shallow trench 102 can be better adjusted, and the depth and width have better uniformity.

[0081] In the above process steps, before forming the trench filler 105 in the second step, the hard mask may be retracted onto the semiconductor platform through processes such as etching. However, in some embodiments, because the etching depth and width of the shallow trench 102 are relatively shallow, the hard mask layer 121 does not extend beyond the semiconductor platform after etching (e.g., Figure 8 As shown in the figure, the hard mask will not affect the subsequent trench filling process, and no additional hard mask retraction process is required.

[0082] The hard mask layer 121 may be a nitride layer, an oxide layer, or a combination of a nitride layer and an oxide layer. The trench filler 105 may be an oxide, a nitride, an organic compound, or a combination layer of oxide and polysilicon. After the trench filler 105 is formed, it may be etched back through etching or chemical mechanical polishing processes to expose the upper surface of the hard mask layer 121.

[0083] In the sixth step of the above process, before or after removing the trench filler 105, the hard mask may be retracted onto the semiconductor platform through etching or other processes. At this time, a small section of the hard mask layer 121 remaining between the deep trench 101 and the shallow trench 102 may be completely removed.

[0084] Example 3

[0085] In a variation of the above embodiments, the semiconductor may not be etched using an isotropic method, but rather a method with better process uniformity. One embodiment is as follows:

[0086] Steps one through six are as described in Example 2 above.

[0087] The seventh step involves thermal oxidation to form a sacrificial oxide within the trenches, wherein the semiconductor protection zone 106 between the deep trench 101 and the shallow trench 102 is completely oxidized to form the sacrificial oxide.

[0088] Step 8: Remove the sacrificial oxide between the deep trench 101 and the shallow trench 102 to make the deep trench 101 and the shallow trench 102 interconnected, and form a raised transition region 103 at the junction of the deep trench 101 and the shallow trench 102 to form a trench network structure in the device.

[0089] This method can make the morphology of the trench transition region more uniform.

[0090] The trench network formation methods described in the above embodiments can be applied to the manufacturing processes of various trench devices, forming new device manufacturing processes based on existing device formation steps.

[0091] Example 4

[0092] The manufacturing process of a shielded gate trench MOSFET device according to an embodiment of the present invention is as follows:

[0093] First, a hard mask thin oxide layer 133, a hard mask thin nitride layer 132, and a hard mask thick oxide layer 131 are formed on the semiconductor layer 100, respectively. Then, photolithography is performed to form openings in the hard mask pattern. Next, the semiconductor is etched to form a deep trench 101, as shown below. Figure 14 As shown.

[0094] Typically, after forming the deep trench 101, the hard mask thin nitride layer 132 is etched to retract it into the semiconductor platform so as not to affect the subsequent trench filling process.

[0095] The second step involves forming a trench oxide layer 222 within the trench, followed by forming a shielding gate electrode 125 within the trench. Figure 15 As shown.

[0096] The method for forming the trench oxide layer 222 may involve first performing thermal oxidation, followed by oxide deposition. In one embodiment, an oxide layer of 1000-5000 Å is first formed by thermal oxidation, followed by a deposition process to form an oxide layer of 1000-6000 Å. In one embodiment, the oxide layer formed by the deposition process contains phosphorus impurities. The shielding gate electrode 125 may be made of polycrystalline silicon and formed by deposition and dry etching processes.

[0097] The third step involves forming an oxide layer on the upper surface of the semiconductor and then performing chemical mechanical polishing on the oxide layer. The polishing stops on the thin nitride layer 132 of the hard mask. Figure 16 As shown.

[0098] The method for forming the oxide may be oxide deposition, followed by a reflow process. In one embodiment, the oxide deposition may be high-density plasma deposition.

[0099] The fourth step is photolithography. Under the protection of photoresist, the hard mask thin nitride layer 132 and the underlying hard mask thin oxide layer 133 are removed, exposing the shallow trench etching region 202. The width d1 of the exposed shallow trench etching region 202 is slightly smaller than the width d2 of the shallow trench 102. Figure 17 As shown.

[0100] The fifth step involves etching the semiconductor to form shallow trenches 102. At this stage, deep trenches 101 and shallow trenches 102 are interconnected, as shown below. Figure 18 As shown.

[0101] The depth of the transition region between the deep trench 101 and the shallow trench 102 after etching is shallower than the depth of the shallow trench 102, and a raised transition region 103 is formed in the transition region.

[0102] In one embodiment, the step of etching the shallow trench 102 is to first perform vertical etching, and then perform isotropic etching.

[0103] Step 6: Etch the oxide on the upper part of the deep trench 101 and expose the trench sidewalls. After the oxide is etched, the raised transition region 103 is retained, such as... Figure 19 As shown.

[0104] The etching method may be dry etching, wet etching, or a combination of dry etching and wet etching.

[0105] In one embodiment, the shallow trench 102 may be filled first, followed by oxide etching, which is beneficial for the uniformity of the etching depth during oxide etching in the deep trench 101. The filler for the shallow trench may be an oxide or an organic compound, and the filler may be completely or partially removed after oxide etching.

[0106] The seventh step involves forming a gate oxide layer through thermal oxidation, such as... Figure 20 As shown.

[0107] Step 8: Form the gate electrode, such as... Figure 21 As shown.

[0108] The gate electrode is typically made of polysilicon, formed by polysilicon deposition and etch-back. The gate electrode may also be made of a metal material such as titanium or tungsten, which helps reduce gate resistance and increase the device's switching depth. The gate electrode may also be formed from a combination of polysilicon and metal layers, such as a metal layer encased in polysilicon, where the polysilicon layer and the gate oxide layer are in contact.

[0109] The ninth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

[0110] In one embodiment, the depth of the final ion implantation body region is deeper than that of the shallow trench.

[0111] In the above device manufacturing process, the depth and width of the deep trench are only affected by one etching process, and have good uniformity.

[0112] In the above device manufacturing process, the inter-electrode isolation oxide layer between the gate electrode and the shielding gate electrode is formed on the polysilicon material of the shielding gate electrode by a thermal oxidation process in step eight. The thickness of the isolation oxide layer formed by this thermal oxidation is limited by the thickness of the gate oxide layer and is usually relatively thin. In some embodiments, other methods may be used to increase the thickness of this inter-electrode isolation oxide layer.

[0113] In a modified embodiment, in the sixth step described above, photolithography is first performed. Photoresist is used to protect the oxide portions at both ends of the shielding gate electrode within the deep trench 101. Dry etching is then performed on the oxides, exposing the upper sidewalls of the deep trench 101. The remaining oxide portions at both ends of the shielding gate electrode form the inter-electrode isolation oxide layer of the device, such as... Figure 22 As shown, this method is beneficial for forming a thicker interpolar isolation oxide layer.

[0114] The above process flow illustrates the key manufacturing steps of the device structure of the present invention. In practice, these steps can be appropriately modified based on existing shielded trench field-effect transistor (SFET) processes. For example, the contact holes are formed using a self-aligned method. Those skilled in the art should understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific detailed manufacturing steps can be obtained based on common manufacturing processes and general knowledge, and can be appropriately added to, subtracted from, and modified.

[0115] Furthermore, those skilled in the art should understand that the structural features and process steps mentioned in the various embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A method for forming deep trenches and shallow trenches in a semiconductor device, characterized in that, The formation method is as follows: First, a patterned hard mask layer is formed on the upper surface of the semiconductor by photolithography, and etching is performed under the protection of the hard mask layer to form the first trench; Next, the first trench is filled with trench filler; Next, expose the location of the second trench, form the second trench under the protection of the hard mask layer and the trench filler, and then connect the first trench and the second trench to form a raised transition area at the junction; The first and second trenches are trenches of different depths. The first trench is a deep trench, and the second trench is a shallow trench. The specific method for forming the trench includes the following steps: The first step is to form a patterned hard mask layer on the upper surface of the semiconductor by photolithography, and then to form deep trenches by vertical semiconductor etching. The second step involves etching the hard mask layer back onto the semiconductor platform and filling the deep trench with trench filler. The trench filler extends beyond the deep trench and reaches the retracted position of the hard mask layer on the side of the trench. The third step is to form a patterned photoresist and expose the hard mask layer at the shallow trench etched area; The fourth step is to etch the exposed hard mask layer and then remove the photoresist; The fifth step involves etching the semiconductor under the protection of the trench filler and the retained hard mask layer to form shallow trenches and raised transition regions. The sixth step is to remove the trench filler to connect the deep and shallow trenches, forming a trench network structure.

2. A method for forming deep trenches and shallow trenches in a semiconductor device, characterized in that, The formation method is as follows: First, a patterned hard mask layer is formed on the upper surface of the semiconductor by photolithography, and etching is performed under the protection of the hard mask layer to form the first trench; Next, the first trench is filled with trench filler; Next, expose the location of the second trench, form the second trench under the protection of the hard mask layer and the trench filler, and then connect the first trench and the second trench to form a raised transition area at the junction; The first and second trenches are trenches of different depths. The first trench is a shallow trench, and the second trench is a deep trench. The specific method for forming the trench includes the following steps: The first step is to form a patterned hard mask layer on the upper surface of the semiconductor by photolithography, and then to perform semiconductor etching in the vertical direction to form shallow trenches. The second step is to form a trench filler in the shallow trench; The third step is to form a patterned photoresist and expose the hard mask layer at the deep trench etched area; The fourth step is to etch the exposed hard mask layer; The fifth step is to remove the photoresist and etch the semiconductor under the protection of the trench filler and the retained hard mask layer to form a deep trench. A protected area is retained between the deep trench and the shallow trench. Step 6: Remove the trench filler; The seventh step involves etching the semiconductor using an isotropic method to connect the deep trenches and shallow trenches, and forming a raised transition region at the junction of the deep trenches and shallow trenches to form a trench network structure within the semiconductor device.

3. The method for forming deep trenches and shallow trenches in a semiconductor device as described in claim 2, characterized in that, In the sixth step, the hard mask is etched back onto the semiconductor platform, during which the residual hard mask layer located between the deep trench and the shallow trench is completely removed.

4. A method for forming deep trenches and shallow trenches in a semiconductor device, characterized in that, The formation method is as follows: First, a patterned hard mask layer is formed on the upper surface of the semiconductor by photolithography, and etching is performed under the protection of the hard mask layer to form the first trench; Next, the first trench is filled with trench filler; Next, expose the location of the second trench, form the second trench under the protection of the hard mask layer and the trench filler, and then connect the first trench and the second trench to form a raised transition area at the junction; The first and second trenches are trenches of different depths. The first trench is a shallow trench, and the second trench is a deep trench. The specific method for forming the trench includes the following steps: The first step involves forming a patterned hard mask layer on the surface of the semiconductor using photolithography, followed by vertical etching to create shallow trenches. The second step is to form a trench filler within the shallow trench; The third step involves forming a patterned photoresist layer and exposing the hard mask layer at the deep trench etched area; The fourth step is to etch the exposed hard mask layer; The fifth step is to remove the photoresist and etch the semiconductor under the protection of the trench filler and hard mask layer to form a deep trench. At this time, the deep trench and the shallow trench are not connected, and a protected area is retained between them. Step 6: Remove the trench filler; The seventh step involves thermal oxidation to form sacrificial oxide within the trenches, where the semiconductor protection zone between the deep and shallow trenches is completely oxidized to form sacrificial oxide. Step 8: Remove the sacrificial oxide between the deep trenches and the shallow trenches to connect the deep trenches and the shallow trenches, and form a raised transition region at the junction of the deep trenches and the shallow trenches to form a trench network structure in the device.

5. A method for forming deep trenches and shallow trenches in a semiconductor device, characterized in that, The formation method is as follows: First, a patterned hard mask layer is formed on the upper surface of the semiconductor by photolithography, and etching is performed under the protection of the hard mask layer to form the first trench; Next, fill the first trench with trench filler; Next, expose the location of the second trench, form the second trench under the protection of the hard mask layer and the trench filler, and then connect the first trench and the second trench to form a raised transition area at the junction; The first trench and the second trench are trenches of different depths, with the first trench being a deep trench and the second trench being a shallow trench. The manufacturing process for forming a shielded gate trench MOSFET device using this method is as follows: The first step is to form a hard mask thin oxide layer, a hard mask thin nitride layer, and a hard mask thick oxide layer on the semiconductor layer, respectively. Then, photolithography is performed to form openings in the hard mask pattern. Next, the semiconductor is etched to form deep trenches. After forming the deep trench, the hard mask thin nitride layer is etched to retract it into the semiconductor platform; The second step is to form a trench oxide layer in the trench, and then form a shielding gate electrode in the trench. The third step is to form an oxide on the upper surface of the semiconductor and perform chemical mechanical polishing on the oxide, with the polishing stopping on the hard mask thin nitride layer; The fourth step is to perform photolithography, under the protection of photoresist, to remove the hard mask thin nitride layer and the hard mask thin oxide layer below it, exposing the shallow trench etching area, wherein the width of the exposed shallow trench etching area is slightly smaller than the width of the shallow trench. The fifth step involves etching the semiconductor to form shallow trenches, at which point the deep trenches and shallow trenches are interconnected; a raised transition region is formed in the transition area between the etched deep trenches and shallow trenches. Step 6: Etch the oxide on the upper part of the deep trench and expose the trench sidewalls, while the raised transition area is preserved; The seventh step is to form a gate oxide layer through thermal oxidation; Step 8: Form the gate electrode; The ninth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

6. The method for forming deep trenches and shallow trenches in a semiconductor device as described in claim 5, characterized in that, In the sixth step, photolithography is first performed. Photoresist is used to protect some of the oxides on the left and right sides of the shielding gate electrode in the deep trench. Dry etching is then performed on the oxides to expose the upper sidewalls of the deep trench. The remaining oxides on the left and right sides of the shielding gate electrode form an inter-electrode isolation oxide layer.

7. A semiconductor device, said semiconductor device comprising a trench network composed of deep trenches and shallow trenches, characterized in that, The deep trench and shallow trench are formed by the forming method described in any one of claims 1-6. A raised transition area is provided at the junction of the edge of the shallow trench and the deep trench. The length of the raised transition area is less than one-third of the length of the shallow trench and is between 0.03-1 μm. The height of the raised transition area is between 0.05-0.5 μm.

8. The semiconductor device as claimed in claim 7, characterized in that, The raised transition area is a smooth arc surface that smoothly transitions from the sidewall to the inside of the shallow groove.

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