A superconducting chip with Josephson junction and preparation method thereof

Abstract

The embodiment of the present invention discloses a superconducting chip with a Josephson junction and a preparation method. The superconducting chip includes a substrate, a lower electrode layer, an oxide layer and an upper electrode layer; the lower electrode layer is located on a side surface of the substrate, and the lower electrode layer includes a first body portion and a first protrusion portion connected in one piece; the oxide layer is located on a side surface of the first protrusion away from the substrate; the upper electrode layer is located on a side surface of the oxide layer away from the substrate, and the upper electrode layer includes a second body portion and a second protrusion portion connected in one piece, and the second protrusion portion and the positive projection of the oxide layer on the substrate at least partially overlap, and the Josephson junction is a structure in which the first protrusion portion, the oxide layer and the second protrusion portion are stacked in sequence. The first protrusion portion and the second protrusion portion are in a trapezoidal shape. Through the trapezoidal structure design, the conventional narrow strip structure is avoided. The superconducting chip limits radiation to the Josephson junction, reduces microwave radiation loss, and reduces the second-level defect concentration and defect sensitivity.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of superconducting chips, and in particular to a superconducting chip with a Josephson junction and a preparation method thereof. Background Art

[0002] As the core basic component of superconducting chips, the structure and preparation process of superconducting Josephson junctions have been widely studied. The quality of superconducting Josephson junctions also greatly affects the performance of superconducting chips. The typical structure of a superconducting Josephson junction includes a lower electrode layer, an upper electrode layer, and an oxide layer between the lower electrode layer and the upper electrode layer. The lower electrode layer and the upper electrode layer are often strip-shaped. The two superconducting strips intersect in a cross structure, and the overlapping area is a Josephson junction.

[0003] On the one hand, the resistance of a Josephson junction is related to its own area, that is, the resistance of a Josephson junction is related to the area of ​​the overlapping region, and the area of ​​a Josephson junction is affected by the line width of the two superconducting strips that overlap in a cross structure. To obtain a high-resistance Josephson junction, the line width of the corresponding two superconducting strips should be smaller under the premise that the thickness of the intermediate oxide layer remains unchanged. However, the smaller the line width of the two superconducting strips, the greater the energy density during operation, and the greater the impact of defects on it, which also requires higher manufacturing process capabilities. At the same time, the shape of the elongated superconducting strips near the Josephson junction is similar to an antenna, which is prone to cause microwave radiation loss, thereby affecting the performance of the Josephson junction.

[0004] On the other hand, the existing preparation methods for Josephson junctions mostly use suspension structure and dual-tilt evaporation. Among them, the suspension structure requires pre-spin coating of a double layer of photoresist, followed by development to form an undercut, and the process is complicated. When preparing the electrode layer by dual-tilt evaporation, the area and resistance uniformity of the Josephson junction within a large wafer size range cannot be guaranteed, which is not conducive to high integration. Summary of the invention

[0005] The embodiment of the present invention provides a superconducting chip with a Josephson junction and a preparation method thereof. By arranging a non-strip-shaped first protrusion and a second protrusion as an electrode layer, microwave radiation is confined to the area of ​​the Josephson junction, thereby effectively reducing microwave radiation loss. At the same time, the increased electrode layer area can reduce the two-level defect concentration and reduce defect sensitivity.

[0006] In a first aspect, an embodiment of the present invention provides a superconducting chip with a Josephson junction, comprising a substrate, a lower electrode layer, an oxide layer and an upper electrode layer;

[0007] In the thickness direction of the base substrate, the lower electrode layer, the oxide layer and the upper electrode layer are all located on the same side of the base substrate;

[0008] The lower electrode layer is located on one side surface of the base substrate, and the lower electrode layer includes a first main body portion and a first protrusion portion that are integrally connected;

[0009] The oxide layer is located on a surface of the first protrusion away from the substrate;

[0010] The upper electrode layer is located on a surface of the oxide layer away from the base substrate, the upper electrode layer includes a second main body portion and a second protruding portion connected in one piece, and the second protruding portion at least partially overlaps with the positive projection of the oxide layer on the base substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence.

[0011] In a second aspect, an embodiment of the present invention further provides a method for preparing a superconducting chip having a Josephson junction, comprising:

[0012] Providing a substrate;

[0013] A lower electrode layer is formed on one side surface of the base substrate; wherein the lower electrode layer includes a first main body portion and a first protrusion portion connected in one piece;

[0014] forming an oxide layer on a surface of the first protrusion away from the substrate;

[0015] An upper electrode layer is formed on a surface of the oxide layer away from the base substrate to prepare the Josephson junction; wherein the upper electrode layer includes a second main body portion and a second protruding portion that are integrally connected, and the second protruding portion at least partially overlaps with the orthographic projection of the oxide layer on the base substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence.

[0016] The embodiment of the present invention provides a superconducting chip with a Josephson junction and a preparation method thereof. The superconducting chip comprises a substrate, a lower electrode layer, an oxide layer and an upper electrode layer; in the thickness direction of the substrate, the lower electrode layer, the oxide layer and the upper electrode layer are all located on the same side of the substrate; the lower electrode layer is located on a side surface of the substrate, and the lower electrode layer comprises a first body portion and a first protruding portion connected in one piece; the oxide layer is located on a side surface of the first protruding portion away from the substrate; the upper electrode layer is located on a side surface of the oxide layer away from the substrate, and the upper electrode layer comprises a second body portion and a second protruding portion connected in one piece, and the orthographic projection of the second protruding portion on the substrate at least partially overlaps with the oxide layer, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence. The superconducting chip is provided with a non-strip-shaped first protrusion and a second protrusion, and the orthographic projection of the oxide layer on the substrate is located within the orthographic projection of the first protrusion on the substrate, and the orthographic projection of the second protrusion and the oxide layer on the substrate at least partially overlap, that is, a Josephson junction is formed at a structure where the first protrusion, the oxide layer and the second protrusion are sequentially stacked, and there is no strip-shaped antenna-like structure near the Josephson junction, so that microwave radiation can be limited to the area of ​​the Josephson junction, and microwave radiation loss is effectively reduced. At the same time, different from the narrow-band structure, the trapezoidal structure with an enlarged area near the junction reduces the energy density during operation, reduces the second-level defect concentration and defect sensitivity, and is conducive to ensuring the stability of the Josephson junction and the superconducting circuit structure in the superconducting chip. In addition, the vertical evaporation method simplifies the preparation process steps of the superconducting chip with the Josephson junction, and can prepare a high-performance, uniform, stable and controllable Josephson junction within a large wafer size range, and is suitable for the regulation and preparation of small-area and large-area Josephson junctions, thereby improving the production efficiency of superconducting chips with Josephson junctions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic flow chart of a method for preparing a superconducting chip with a Josephson junction provided by an embodiment of the present invention;

[0018] Figure 2 yes Figure 1 A structural flow chart of a method for preparing a superconducting chip having a Josephson junction is shown;

[0019] Figure 3 is a schematic diagram of a top view of a superconducting chip with a Josephson junction provided by an embodiment of the present invention;

[0020] Figure 4 yes Figure 3 A schematic diagram of the side view structure of a superconducting chip with a Josephson junction is shown;

[0021] Figure 5is a schematic diagram of a top view of another superconducting chip with a Josephson junction provided by an embodiment of the present invention;

[0022] Figure 6 yes Figure 5 A schematic diagram of the side view structure of a superconducting chip with a Josephson junction is shown;

[0023] Figure 7 It is a schematic flow chart of another method for preparing a superconducting chip with a Josephson junction provided by an embodiment of the present invention;

[0024] Figure 8 yes Figure 7 A structural flow chart of a method for preparing a superconducting chip having a Josephson junction is shown;

[0025] Fig. 9 It is a schematic flow chart of another method for preparing a superconducting chip with a Josephson junction provided by an embodiment of the present invention;

[0026] Fig.10 yes Fig. 9 The structural flow chart of the method for preparing a superconducting chip with a Josephson junction is shown. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0028] Figure 1 is a schematic flow chart of a method for preparing a superconducting chip having a Josephson junction provided by an embodiment of the present invention, Figure 2 yes Figure 1 The structural flow chart of the method for preparing a superconducting chip with a Josephson junction is shown in FIG. Figure 3 is a schematic diagram of a top view of a superconducting chip with a Josephson junction provided by an embodiment of the present invention, Figure 4 yes Figure 3 The side view of the superconducting chip with a Josephson junction is shown in FIG. Figure 1-Figure 4 As shown, the method for preparing the superconducting chip with a Josephson junction comprises:

[0029] S110, providing a substrate.

[0030] Specifically, refer to Figure 2In part a), a substrate substrate 10 is provided. The substrate substrate 10 is a substrate that has been smoothly polished and has a flat surface, which can help the growth of subsequent film layers. In this embodiment, the type of the substrate substrate 10 is not specifically required or specially limited. It can be reasonably selected according to the operation requirements. The substrate substrate 10 can be a silicon substrate (for example, a high-resistance silicon substrate and an intrinsic silicon substrate. The orientation of the silicon substrate can be selected according to the actual coating requirements) or a sapphire substrate (for example, an A-face sapphire substrate, a C-face sapphire substrate, an R-face sapphire substrate, and an M-face sapphire substrate). For example, the substrate substrate 10 can use a C-face sapphire substrate. In addition, in this embodiment, the size of the substrate substrate 10 is not specifically required or specially limited. It can be reasonably selected according to the operation requirements. For example, the thickness of the substrate substrate 10 can be 0.43mm-0.50mm, the shape of the substrate substrate 10 can be circular, and the diameter of the substrate substrate 10 can be 2 inches-8 inches.

[0031] Before the subsequent film layer is grown, the substrate 10 needs to be pretreated to clean the surface of the substrate 10. Exemplarily, the pretreatment process may include chemical cleaning and high-temperature environment annealing, etc., so that the surface of the substrate 10 is clean, smooth and has distinct atomic steps. Exemplarily, the chemical cleaning process includes organic chemical cleaning and inorganic chemical cleaning, wherein the organic chemical cleaning is ultrasonic cleaning using acetone solution and isopropanol solution alternately, and the number of alternating cleanings can be determined according to actual needs, and this embodiment is not limited here. Inorganic chemical cleaning is soaking and cleaning using piranha solution (that is, a mixed solution of concentrated sulfuric acid solution and hydrogen peroxide solution, such as a volume ratio of concentrated sulfuric acid solution and hydrogen peroxide solution of 2:1). Afterwards, the substrate 10 needs to be ultrasonically cleaned with deionized water, and dried with nitrogen for standby use. Exemplarily, the high-temperature environment annealing process includes placing the substrate 10 in an oxygen atmosphere, setting the annealing temperature to 1200°C, and the annealing time to 2h, so as to obtain a substrate 10 surface with distinct atomic steps and smoothness.

[0032] S120, forming a lower electrode layer on one side surface of the base substrate; wherein the lower electrode layer includes a first main body portion and a first protruding portion that are integrally connected.

[0033] Specifically, refer to Figure 2b) part, a lower electrode layer 20 is formed on one side surface of the substrate 10. This embodiment does not make specific requirements and special limitations on the formation method of the lower electrode layer 20. Photolithography and etching processes can be reasonably selected according to operational requirements. For example, the photolithography method can be one or a combination of at least two of ultraviolet exposure, electron beam exposure, and laser exposure methods, and the etching method can be one or a combination of at least two of wet etching and dry etching. Among them, the lower electrode layer 20 includes a first body part 21 and a first protruding part 22 connected as a whole. It should be particularly pointed out that the structure of the first protruding part 22 discussed in this embodiment is different from the narrow band structure of the conventionally prepared Josephson junction. For example, the shape of the structure of the first protruding part 22 is different from the shape of the narrow band structure of the conventionally prepared Josephson junction, and the size of the structure of the first protruding part 22 is larger than the size of the narrow band structure of the conventionally prepared Josephson junction. Thus, compared with the structure in which the first main body 21 and the first protruding part 22 of the lower electrode layer 20 are separately arranged, the first main body 21 and the first protruding part 22 of the lower electrode layer 20 are an integrally connected structure, which can effectively avoid the problem of fracture in the overlapping area between the first main body 21 and the first protruding part 22 caused by the subsequent step-by-step preparation, and also avoid the formation of a parasitic junction at the overlapping area between the subsequent first main body 21 and the first protruding part 22, reducing the influence of the subsequent parasitic junction on the Josephson junction, and ensuring the stability of the internal circuit connection of the superconducting chip. At the same time, the first main body 21 and the first protruding part 22 of the lower electrode layer 20 are an integrally connected structure, which ensures the flatness and uniformity of the film surface of the entire lower electrode layer 20, and avoids the defects and losses of the lower electrode layer 20 caused by the step-by-step preparation process.

[0034] S130, forming an oxide layer on a surface of a side of the first protrusion away from the base substrate.

[0035] Specifically, refer to Figure 2 c) part, an oxide layer 30 is formed on the surface of the first protrusion 22 on the side away from the substrate 10. This embodiment does not make specific requirements and special limitations on the formation method of the oxide layer 30, and a process such as oxidation or deposition can be reasonably selected according to operation requirements. For example, the oxidation method can be one of quasi-in-situ high-temperature thermal oxidation and low-temperature wet oxidation, or a combination of at least two of them, and the deposition method can be one of magnetron sputtering deposition and atomic layer deposition, or a combination of at least two of them.

[0036] It should be noted that the oxide layer 30 described in this embodiment is formed on the side surface of the first protrusion 22 away from the base substrate 10, and the thickness of the oxide layer 30 is not specifically required or limited, and can be set according to actual needs. At the same time, the oxide layer 30 can also be formed on the side surface of the first body part 21 away from the base substrate 10, that is, the oxide layer 30 is formed on the side surface of the entire lower electrode layer 20 away from the base substrate 10. And, the oxide layer 30 can also be formed on the side of the first protrusion 22 and the side of the first body part 21, that is, the oxide layer 30 is formed on the side of the entire lower electrode layer 20. For example, the side can connect the side surface of the lower electrode layer 20 away from the base substrate 10 and the side surface of the lower electrode layer 20 close to the base substrate 10. It is understandable that the present embodiment requires an oxide layer 30 to be formed at least on the surface of the first protrusion 22 away from the base substrate 10, so as to define the subsequent formation position of the Josephson junction. For example, the orthographic projection of the Josephson junction on the base substrate 10 is located in the orthographic projection of the first protrusion 22 on the base substrate 10. For example, Figure 2 In part c), the oxide layer 30 is formed on the entire surface of the lower electrode layer 20 away from the base substrate 10 as an example.

[0037] S140. Form an upper electrode layer on the surface of the oxide layer away from the substrate to prepare a Josephson junction; wherein the upper electrode layer includes a second main body portion and a second protruding portion that are integrally connected, and the second protruding portion at least partially overlaps with the positive projection of the oxide layer on the substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence.

[0038] Specifically, refer to Figure 2 Part d) of Figure 3 and Figure 4, an upper electrode layer 40 is formed on the surface of the side of the oxide layer 30 away from the substrate 10, so as to prepare a Josephson junction 50 in the area where the lower electrode layer 20, the oxide layer 30 and the upper electrode layer 40 are stacked in sequence. In this embodiment, no specific requirements and special limitations are made on the formation method of the upper electrode layer 40, and processes such as photolithography and etching can be reasonably selected according to the operation requirements. For example, the photolithography method can be one of ultraviolet exposure, electron beam exposure, and laser exposure, or a combination of at least two of them, and the etching method can be one of wet etching and dry etching, or a combination of at least two of them. Among them, the upper electrode layer 40 includes a second body part 41 and a second protruding part 42 connected in an integral manner. It should be particularly pointed out that the structure of the second protruding part 42 discussed in this embodiment is different from the narrow band structure of the conventionally prepared Josephson junction 50. For example, the shape of the structure of the second protruding part 42 is different from the shape of the narrow band structure of the conventionally prepared Josephson junction 50, and the size of the structure of the second protruding part 42 is larger than the narrow band structure of the conventionally prepared Josephson junction 50. Thus, compared with the structure in which the second body part 41 and the second protrusion part 42 of the upper electrode layer 40 are separately arranged, the second body part 41 and the second protrusion part 42 of the upper electrode layer 40 are an integrally connected structure, which can effectively avoid the problem of fracture in the overlapping area between the second body part 41 and the second protrusion part 42 caused by the subsequent step-by-step preparation, and also avoid the formation of a parasitic junction at the overlapping area between the subsequent second body part 41 and the second protrusion part 42, reducing the influence of the parasitic junction on the Josephson junction 50, and ensuring the stability of the internal circuit connection of the superconducting chip. At the same time, the second body part 41 and the second protrusion part 42 of the upper electrode layer 40 are an integrally connected structure, which ensures the flatness and uniformity of the film surface of the entire upper electrode layer 40, and avoids the defects and losses of the upper electrode layer 40 caused by the step-by-step preparation process. And, the orthographic projection of the oxide layer 30 on the base substrate 10 is located within the orthographic projection of the first protrusion 22 on the base substrate 10, and the second protrusion 42 overlaps at least partially with the orthographic projection of the oxide layer 30 on the base substrate 10, that is, it can be understood that the second protrusion 42 of the upper electrode layer 40 overlaps on the oxide layer 30, and the second protrusion 42 of the upper electrode layer 40 overlaps on the first protrusion 22 of the lower electrode layer 20. And, the first body portion 21 of the lower electrode layer 20 and the second body portion 41 of the upper electrode layer 40 are located on the opposite sides of the first protrusion 22 of the lower electrode layer 20, and the first body portion 21 of the lower electrode layer 20 and the second body portion 41 of the upper electrode layer 40 are located on the opposite sides of the second protrusion 42 of the upper electrode layer 40. In this way, a Josephson junction 50 can be formed in the overlapping area, and the Josephson junction 50 is a structure in which the first protrusion 22, the oxide layer 30 and the second protrusion 42 are stacked in sequence.Afterwards, during the application of the Josephson junction 50, the current can flow from the first main body 21 of the lower electrode layer 20, the first protrusion 22 of the lower electrode layer 20, the oxide layer 30, the second protrusion 42 of the upper electrode layer 40 to the second main body 41 of the upper electrode layer 40, thus forming a conductive structure.

[0039] Continue to refer Figure 3 and Figure 4 A superconducting chip with a Josephson junction prepared by the method for preparing a superconducting chip with a Josephson junction according to an embodiment of the present invention comprises: a substrate 10, a lower electrode layer 20, an oxide layer 30 and an upper electrode layer 40; in the thickness direction of the substrate 10, the lower electrode layer 20, the oxide layer 30 and the upper electrode layer 40 are all located on the same side of the substrate 10; the lower electrode layer 20 is located on one side surface of the substrate 10, and the lower electrode layer 20 comprises a first body portion 21 and a first protrusion portion 22 connected in one piece; the oxide layer 30 is located on a side surface of the first protrusion portion 22 away from the substrate 10; the upper electrode layer 40 is located on a side surface of the oxide layer 30 away from the substrate 10, and the upper electrode layer 40 comprises a second body portion 41 and a second protrusion portion 42 connected in one piece, and the orthographic projection of the second protrusion portion 42 and the oxide layer 30 on the substrate 10 at least partially overlaps, and the Josephson junction 50 is a structure in which the first protrusion portion 22, the oxide layer 30 and the second protrusion portion 42 are stacked in sequence.

[0040] Specifically, the present embodiment does not make any specific requirements or special restrictions on the materials of the lower electrode layer 20 and the upper electrode layer 40. By way of example, the materials of the lower electrode layer 20 and the upper electrode layer 40 may be metal materials such as superconducting tantalum, superconducting aluminum, and superconducting niobium, or ceramic materials such as titanium nitride and niobium nitride. The materials of the lower electrode layer 20 and the upper electrode layer 40 may be the same or different. The present embodiment does not make any specific requirements or special restrictions on the materials of the oxide layer 30. By way of example, the materials of the oxide layer 30 may be oxides such as tantalum oxide, aluminum oxide, and niobium oxide. The metal atoms in the materials of the oxide layer 30 may be the same or different from the metal atoms in the materials of the lower electrode layer 20 and the upper electrode layer 40, and the oxide layer 30 has insulating properties.

[0041] In a specific embodiment, the material of the lower electrode layer 20 can be tantalum metal, which has a high superconducting transition temperature and superconducting energy gap, and has the characteristics of low quasiparticle density in superconducting quantum bits. The material of the oxide layer 30 can be tantalum pentoxide, which has the characteristics of high compactness, low dielectric loss and high stability. The material of the upper electrode layer 40 can be tantalum metal, which has a high superconducting transition temperature and superconducting energy gap, and has the characteristics of low quasiparticle density in superconducting quantum bits. In this way, in the structure of the Josephson junction 50, the sandwich composition of tantalum / tantalum pentoxide / tantalum has low dielectric loss and high stability, and the oxide layer 30 of tantalum pentoxide can exist stably for a long time on the entire superconducting tantalum metal surface, playing a passivation protection role, and the vertical evaporation preparation scheme together ensures the large-scale preparation of high-performance, uniform, stable and controllable Josephson junctions 50 within a large wafer size range. In addition, it should be noted that, based on the chemical stability of tantalum pentoxide, after the preparation of the Josephson junction 50 is completed, it can also be soaked and cleaned with a strong oxidizing solution, such as piranha solution (that is, a mixed solution of concentrated sulfuric acid solution and hydrogen peroxide solution, for example, a volume ratio of concentrated sulfuric acid solution to hydrogen peroxide solution of 2:1), which can optimize the exposed tantalum metal on the surface of the Josephson junction 50, increase the thickness and density of tantalum pentoxide, play a passivation protection role, and also protect the superconducting tunneling channel in the Josephson junction 50, and at the same time further remove the process residual glue near the Josephson junction 50.

[0042] Optionally, continue to refer to Figure 3 and Figure 4 The second protruding portion 42 includes a first portion 421 and a second portion 422 that are integrally connected, the second portion 422 is located on a side of the first portion 421 away from the second main body portion 41, and at least a portion of the second portion 422 is projected onto the base substrate 10 in the projection of the oxide layer 30 onto the base substrate 10, and the Josephson junction 50 is a structure in which the first protruding portion 22, the oxide layer 30 and the second portion 422 are stacked in sequence.

[0043] Specifically, the lower electrode layer 20 includes a first main body portion 21 and a first protruding portion 22 that are integrally connected. The oxide layer 30 is located on a side surface of the first protruding portion 22 away from the base substrate 10, that is, the orthographic projection of the oxide layer 30 on the base substrate 10 is located within the orthographic projection of the first protruding portion 22 on the base substrate 10. The upper electrode layer 40 includes a second main body portion 41 and a second protruding portion 42 that are integrally connected, the second protruding portion 42 includes a first portion 421 and a second portion 422 that are integrally connected, the second portion 422 is located on a side of the first portion 421 away from the second main body portion 41, and at least part of the orthographic projection of the second portion 422 on the base substrate 10 is located in the orthographic projection of the oxide layer 30 on the base substrate 10, that is, it can be understood that the second portion 422 of the upper electrode layer 40 overlaps the oxide layer 30, and the orthographic projection of at least part of the second portion 422 of the upper electrode layer 40 on the base substrate 10 is located in the orthographic projection of the first protruding portion 22 of the lower electrode layer 20 on the base substrate 10. Continue to refer to Figure 3 and Figure 4 , the orthographic projection of part of the second portion 422 on the base substrate 10 is located in the orthographic projection of the oxide layer 30 on the base substrate 10. In this way, a Josephson junction 50 can be formed in the overlapped area, and the Josephson junction 50 is a structure in which the first protrusion 22, the oxide layer 30 and the second portion 422 are stacked in sequence. Afterwards, during the application of the Josephson junction 50, the current can flow from the first body portion 21 of the lower electrode layer 20, the first protrusion 22 of the lower electrode layer 20, the oxide layer 30, the second portion 422 of the upper electrode layer 40, the first portion 421 of the upper electrode layer 40 to the second body portion 41 of the upper electrode layer 40, so as to form a conductive structure.

[0044] It should be noted that, continue to refer to Figure 3 and Figure 4 , the oxide layer 30 on the surface of the side of the first protrusion 22 of the lower electrode layer 20 away from the base substrate 10 is overlapped with the second protrusion 42 of the upper electrode layer 40 through the second portion 422. There is a transition region 60 between the orthographic projection of the first protrusion 22 of the lower electrode layer 20 on the base substrate 10 and the orthographic projection of the second protrusion 42 of the upper electrode layer 40 on the base substrate 10, that is, there is another part of the second portion 422 between the trapezoidal structure of the first protrusion 22 of the lower electrode layer 20 and the trapezoidal structure of the second protrusion 42 of the upper electrode layer 40, and this part of the second portion 422 can be understood as the transition region 60, and this part of the second portion 422 is not used to prepare the Josephson junction 50.

[0045] Figure 5 is a schematic diagram of a top view of another superconducting chip with a Josephson junction provided by an embodiment of the present invention, Figure 6 yes Figure 5 The side view of the superconducting chip with a Josephson junction is shown in FIG. Figure 5 and Figure 6 As shown, the lower electrode layer 20 includes a first body portion 21 and a first protrusion portion 22 connected in one piece. The oxide layer 30 is located on the surface of the first protrusion portion 22 on the side away from the base substrate 10, that is, the orthographic projection of the oxide layer 30 on the base substrate 10 is located within the orthographic projection of the first protrusion portion 22 on the base substrate 10. The upper electrode layer 40 includes a second body portion 41 and a second protrusion portion 42 connected in one piece, the second protrusion portion 42 includes a first portion 421 and a second portion 422 connected in one piece, the second portion 422 is located on the side of the first portion 421 away from the second body portion 41, and the orthographic projection of the second portion 422 on the base substrate 10 is located in the orthographic projection of the oxide layer 30 on the base substrate 10, that is, it can be understood that the second portion 422 of the upper electrode layer 40 is completely overlapped on the oxide layer 30, and the orthographic projection of the second portion 422 of the upper electrode layer 40 on the base substrate 10 is completely located in the orthographic projection of the first protrusion portion 22 of the lower electrode layer 20 on the base substrate 10. In this way, a Josephson junction 50 can be formed in the overlap region, and the Josephson junction 50 is a structure in which the first protrusion 22, the oxide layer 30 (exemplarily, here refers to the oxide layer 30 formed on the surface of the first protrusion 22 away from the substrate 10) and the second part 422 are stacked in sequence. Afterwards, in the application process of the Josephson junction 50, the current can flow from the first body part 21 of the lower electrode layer 20, the first protrusion 22 of the lower electrode layer 20, the oxide layer 30 (exemplarily, here refers to the oxide layer 30 formed on the surface of the first protrusion 22 away from the substrate 10), the second part 422 of the upper electrode layer 40, the first part 421 of the upper electrode layer 40 to the second body part 41 of the upper electrode layer 40, so as to form a conductive structure. At the same time, a Josephson junction 50 can be formed in the overlap region, and the Josephson junction 50 also includes a structure in which the first protrusion 22, the oxide layer 30 (exemplarily, here refers to the oxide layer 30 formed on the side of the first protrusion 22) and the first part 421 are stacked in sequence. Afterwards, during the application of the Josephson junction 50, the current can also flow from the first main body 21 of the lower electrode layer 20, the first protruding portion 22 of the lower electrode layer 20, the oxide layer 30 (exemplarily, here refers to the oxide layer 30 formed on the side of the first protruding portion 22), the first portion 421 of the upper electrode layer 40 to the second main body 41 of the upper electrode layer 40, thereby forming a conductive structure.

[0046] Optionally, continue to refer to Figure 5 and Figure 6, the orthographic projection of the second portion 422 on the base substrate 10 is located in the orthographic projection of the oxide layer 30 on the base substrate 10. It should be noted that the oxide layer 30 on the surface of the first protrusion 22 of the lower electrode layer 20 away from the base substrate 10 and the second protrusion 42 of the upper electrode layer 40 are overlapped through the second portion 422. There is no transition region 60 between the orthographic projection of the first protrusion 22 of the lower electrode layer 20 on the base substrate 10 and the orthographic projection of the second protrusion 42 of the upper electrode layer 40 on the base substrate 10, that is, there is no other part of the second portion 422 between the trapezoidal structure of the first protrusion 22 of the lower electrode layer 20 and the trapezoidal structure of the second protrusion 42 of the upper electrode layer 40, and the entire second portion 422 is used to prepare the Josephson junction 50. In this way, the area of ​​the overlapping wire near the Josephson junction 50 can be maximized, the energy density during operation can be reduced, and then the defect sensitivity can be reduced. The trapezoidal structure design reduces current crowding, and the microwave radiation loss can be reduced by changing the current characteristics flowing through the lower electrode layer 20 and the upper electrode layer 40. At the same time, compared with narrow strip-shaped wires, the large line width process can ensure a low defect concentration and reduce the process difficulty.

[0047] Optionally, continue to refer to Figure 3-Figure 6 The orthographic projection of the first protrusion 22 on the base substrate 10 is a trapezoidal shape, the orthographic projection of the first portion 421 on the base substrate 10 is a trapezoidal shape, and the orthographic projection of the second portion 422 on the base substrate 10 is a rectangular shape.

[0048] Specifically, different from the existing strip-shaped antenna-like structural design of the lower electrode layer 20 and the upper electrode layer 40, the first protrusion 22 of the lower electrode layer 20 is designed to be trapezoidal, the first part 421 of the upper electrode layer 40 is designed to be trapezoidal, and the overlapping structure of the second part 422 of the upper electrode layer 40 is designed to be rectangular. In this way, the energy density during operation can be effectively reduced, the defect sensitivity can be reduced, and the quasiparticles can be confined. At the same time, compared with the narrow-band design, the trapezoidal design can reduce current crowding, thereby changing the current characteristics flowing through the lower electrode layer 20 and the upper electrode layer 40 to reduce microwave radiation loss.

[0049] Optionally, continue to refer to Figure 3-Figure 6, the trapezoidal shape of the first protruding portion 22 includes a first side, which is a side of the first protruding portion 22 away from the first main body portion 21; the trapezoidal shape of the first portion 421 includes a second side, which is a side of the first portion 421 away from the second main body portion 41; the rectangular shape of the second portion 422 includes a third side, which is a side of the second portion 422 close to the first portion 421; in the orthographic projection on the base substrate 10, the length of the first side, the length of the second side and the length of the third side are the same or different. In this way, on the basis of defining the shapes of the first protruding portion 22, the first portion 421 and the second portion 422, the side length parameters of the first protruding portion 22, the first portion 421 and the second portion 422 can be set arbitrarily, and are not limited here.

[0050] Optionally, continue to refer to Figure 3-Figure 6 In the thickness direction of the base substrate 10, the first body portion 21 and the first protruding portion 22 have the same thickness, the second body portion 41 and the second protruding portion 42 have the same thickness, and the thickness of the second body portion 41 is greater than or equal to the thickness of the first body portion 21. In this way, the subsequent fracture in the overlapping area between the second protruding portion 42 and the first protruding portion 22 caused by the vertical evaporation preparation scheme can be effectively avoided, that is, the subsequent fracture in the overlapping area between the second portion 422 and the first protruding portion 22 can be effectively avoided.

[0051] In addition, optionally, a superconducting circuit structure is also included, and the superconducting circuit structure includes at least a resonant cavity, a read line, and a capacitance and inductance structure of a bit; in the thickness direction of the substrate, the superconducting circuit structure, the lower electrode layer, the oxide layer, and the upper electrode layer are all located on the same side of the substrate, and the superconducting circuit structure is electrically connected to the lower electrode layer and the upper electrode layer, respectively. It should be noted that the superconducting circuit structure discussed in this embodiment does not include the above-mentioned Josephson junction and its corresponding electrode layer structure, and the orthographic projection of the superconducting circuit structure on the substrate does not overlap with the orthographic projection of the Josephson junction and its corresponding electrode layer on the substrate. Exemplarily, the superconducting circuit structure can be used to regulate the Josephson junction prepared above.

[0052] The technical solution in the embodiment of the present invention is that the preparation method first provides a substrate, and then forms a lower electrode layer on one side surface of the substrate; wherein the lower electrode layer includes a first main body portion and a first protrusion portion connected in one piece, and then an oxide layer is formed on the side surface of the first protrusion portion away from the substrate, and finally an upper electrode layer is formed on the side surface of the oxide layer away from the substrate to prepare a Josephson junction; wherein the upper electrode layer includes a second main body portion and a second protrusion portion connected in one piece, and the second protrusion portion and the oxide layer are at least partially overlapped in their orthographic projections on the substrate, and the Josephson junction is a structure in which the first protrusion portion, the oxide layer and the second protrusion portion are stacked in sequence. By using the above method, the superconducting chip is provided with a non-strip-shaped first protrusion and a second protrusion, and the positive projection of the oxide layer on the substrate is located within the positive projection of the first protrusion on the substrate, and the positive projection of the second protrusion and the oxide layer on the substrate at least partially overlap, that is, the structure where the first protrusion, the oxide layer and the second protrusion are sequentially stacked is a Josephson junction, and there is no strip-shaped antenna-like structure near the Josephson junction, which can limit microwave radiation to the area of ​​the Josephson junction, effectively reducing microwave radiation loss, and increasing the conductor area, which can reduce the energy density of the junction when it is working, and then reduce the defect sensitivity and the second-level defect concentration. At the same time, the vertical evaporation preparation scheme simplifies the preparation process steps of the superconducting chip with the Josephson junction, and ensures the preparation of high-performance, uniform, stable and controllable Josephson junctions within a large wafer size range, thereby improving the production efficiency of the superconducting chip with the Josephson junction. In addition, the scheme proposed by the present invention can also be applied to the regulation and preparation of small-area and large-area Josephson junctions.

[0053] Optionally, forming an oxide layer on a surface of the first protrusion away from the substrate includes: oxidizing or depositing the lower electrode layer to form an oxide layer on a surface of the first protrusion away from the substrate.

[0054] Specifically, continue to refer to Figure 2c) part, the lower electrode layer 20 is oxidized or deposited to form an oxide layer 30 on the surface of the side of the first protrusion 22 away from the substrate 10. Exemplarily, the oxidation method may be to oxidize the surface of the side of the lower electrode layer 20 away from the substrate 10, and the deposition method may be to deposit and evaporate a film layer of oxide on the surface of the side of the lower electrode layer 20 away from the substrate 10, so as to form an oxide layer 30 at least on the surface of the side of the first protrusion 22 away from the substrate 10. Of course, the oxide layer 30 may also be formed on the surface of the side of the entire lower electrode layer 20 away from the substrate 10. This embodiment is only an example and is not limited here. In addition, since the lower electrode layer 20 has a certain thickness, the oxide layer 30 may also be formed on the surface of the side of the lower electrode layer 20, especially on the surface of the side corresponding to the first protrusion 22. Depending on the thickness of the lower electrode layer 20, the area of ​​the Josephson junction 50 may include or exclude the side area. This embodiment is only an example and is not limited here.

[0055] Figure 7 is a flow chart of another method for preparing a superconducting chip having a Josephson junction provided by an embodiment of the present invention, Figure 8 yes Figure 7 The structural flow chart of the method for preparing a superconducting chip with a Josephson junction is shown in FIG. 1 , and this embodiment is optimized on the basis of the above embodiment. Optionally, a lower electrode layer is formed on a surface of one side of the substrate, including:

[0056] A first superconducting thin film is formed on one side surface of the substrate by vertical evaporation method;

[0057] A first photolithography mask layer is formed on a surface of the first superconducting film away from the substrate, and the first superconducting film is patterned according to the first photolithography mask layer to form a first main body portion and a first protrusion portion that are integrally connected.

[0058] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 7 and Figure 8 As shown, the method for preparing the superconducting chip with a Josephson junction comprises:

[0059] S210, providing a substrate.

[0060] S220, forming a first superconducting thin film on one side surface of the base substrate by vertical evaporation method.

[0061] Specifically, refer to Figure 8 b), a first superconducting film 61 is formed on one side of the substrate 10 by vertical evaporation method, so as to obtain the lower electrode layer 20 in the subsequent preparation. Therefore, the first superconducting film 61 and the lower electrode layer 20 are Figure 8The drawing filling in is the same. It can be understood that, different from the traditional double-tilt evaporation method, the vertical evaporation method can ensure the uniformity of the deposition thickness of the first superconducting film 61, especially for the substrate 10 with a large wafer size, it can ensure the uniformity and stability of the thickness of the subsequently prepared Josephson junction 50 at various positions, thereby ensuring the performance stability of the device using the superconducting chip with the Josephson junction 50. This embodiment does not make specific requirements and special restrictions on the formation of the first superconducting film 61, and can reasonably select the deposition evaporation method according to the needs. For example, the formation method of the first superconducting film 61 can be one of magnetron sputtering, molecular beam epitaxy, laser pulse deposition or electron beam evaporation, or a combination of at least two of them. This embodiment does not make specific requirements and special restrictions on the material of the first superconducting film 61. For example, the material of the first superconducting film 61 can be a metal material such as superconducting tantalum, superconducting aluminum, superconducting niobium, or a ceramic material such as titanium nitride and niobium nitride.

[0062] S230, forming a first photolithography mask layer on a surface of the first superconducting film away from the substrate, and patterning the first superconducting film according to the first photolithography mask layer to form a first main body portion and a first protrusion portion that are integrally connected.

[0063] Specifically, refer to Figure 8 c) part, a first photolithography mask layer is formed on the surface of the first superconducting film 61 away from the substrate 10, and the first superconducting film 61 is patterned according to the first photolithography mask layer to form an integrally connected first body portion 21 and a first protrusion portion 22. This step is a process of transferring the pattern of the first superconducting film 61 according to the first photolithography mask layer. Exemplarily, a dry or wet etching process can be used to etch the first superconducting film 61 to complete the patterning. Taking dry etching as an example, an inductively coupled plasma etcher is used, and carbon tetrafluoride (CF4) gas is used as the main etching gas. The integrally connected first body portion 21 and the first protrusion portion 22 formed by the pattern transfer are located on the surface of one side of the substrate 10.

[0064] S240, forming an oxide layer on a surface of a side of the first protrusion away from the base substrate.

[0065] S250, forming an upper electrode layer on the surface of the side of the oxide layer away from the substrate to prepare a Josephson junction; wherein the upper electrode layer includes a second main body portion and a second protruding portion that are integrally connected, and the second protruding portion at least partially overlaps with the positive projection of the oxide layer on the substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence.

[0066] Fig. 9 is a schematic flow chart of another method for preparing a superconducting chip with a Josephson junction provided by an embodiment of the present invention, Fig.10 yes Fig. 9 The structural flow chart of the method for preparing a superconducting chip with a Josephson junction is shown in FIG. This embodiment is optimized based on the above embodiment. Optionally, an upper electrode layer is formed on the surface of the oxide layer away from the substrate to prepare a Josephson junction, including:

[0067] A second superconducting thin film is formed on a surface of the oxide layer away from the substrate by vertical evaporation method;

[0068] A second photolithography mask layer is formed on a surface of the second superconducting film away from the substrate, and the second superconducting film is patterned according to the second photolithography mask layer to form an integrally connected second body portion and a second protrusion portion to prepare a Josephson junction.

[0069] For details not yet provided in this embodiment, please refer to the above embodiments. Fig. 9 and Fig.10 As shown, the method for preparing the superconducting chip with a Josephson junction comprises:

[0070] S310, providing a substrate.

[0071] S320, forming a lower electrode layer on one side surface of the base substrate; wherein the lower electrode layer includes a first main body portion and a first protruding portion that are integrally connected.

[0072] S330, forming an oxide layer on a surface of a side of the first protrusion away from the substrate.

[0073] S340, forming a second superconducting thin film on a surface of the oxide layer away from the substrate by vertical evaporation.

[0074] Specifically, refer to Fig.10 d), a second superconducting film 62 is formed on the surface of the oxide layer 30 away from the substrate 10 by vertical evaporation method, so as to obtain the upper electrode layer 40 in the subsequent preparation. Therefore, the second superconducting film 62 and the upper electrode layer 40 are Fig.10The drawing filling in is the same. It can be understood that, different from the traditional double-tilt evaporation method, the vertical evaporation method can ensure the uniformity of the deposition thickness of the second superconducting film 62, especially for the substrate 10 with a large wafer size, and can ensure the uniformity and stability of the thickness of the subsequently prepared Josephson junction 50 at various positions, thereby ensuring the performance stability of the device using the superconducting chip with the Josephson junction 50. It can be understood that due to the use of the vertical evaporation method, the thickness of the second superconducting film 62 formed on the side surface of the oxide layer 30 away from the substrate 10 is the same as the thickness of the second superconducting film 62 formed on the side surface of the substrate 10. This embodiment does not make specific requirements and special limitations on the formation of the second superconducting film 62, and the deposition evaporation method can be reasonably selected according to the needs. For example, the formation method of the second superconducting film 62 can be one of magnetron sputtering, molecular beam epitaxy, laser pulse deposition or electron beam evaporation, or a combination of at least two. The present embodiment does not make any specific requirements or special restrictions on the material of the second superconducting film 62. For example, the material of the second superconducting film 62 may be a metal material such as superconducting tantalum, superconducting aluminum, superconducting niobium, or a ceramic material such as titanium nitride or niobium nitride. In addition, it should be noted that the materials of the first superconducting film 61 and the second superconducting film 62 may be the same or different, and the thicknesses of the first superconducting film 61 and the second superconducting film 62 may be the same or different. The present embodiment is only an example and is not limited here.

[0075] S350, forming a second photolithography mask layer on a surface of the second superconducting film away from the substrate, and patterning the second superconducting film according to the second photolithography mask layer to form a second main body portion and a second protrusion portion connected in one piece, so as to prepare a Josephson junction.

[0076] Specifically, refer to Fig.10 e) of Figure 3 and Figure 4, a second photolithography mask layer is formed on the side surface of the second superconducting film 62 away from the substrate 10, and the second superconducting film 62 is patterned according to the second photolithography mask layer to form an integrally connected second body portion 41 and a second protrusion portion 42, so as to prepare a Josephson junction 50. This step is a process of transferring the pattern of the second superconducting film 62 according to the second photolithography mask layer. Exemplarily, a dry or wet etching process can be used to etch the second superconducting film 62 to complete the patterning. Taking dry etching as an example, an inductively coupled plasma etcher is used, and carbon tetrafluoride (CF4) gas is used as the main etching gas. The integrally connected second body portion 41 and the second protrusion portion 42 formed by the pattern transfer are located on the side surface of the substrate 10. And, the orthographic projection of the first protrusion 22 on the base substrate 10 overlaps at least partially with the orthographic projection of the oxide layer 30 on the base substrate 10, and the orthographic projection of the second protrusion 42 overlaps at least partially with the orthographic projection of the oxide layer 30 on the base substrate 10, that is, it can be understood that the second protrusion 42 of the upper electrode layer 40 overlaps on the oxide layer 30, and the second protrusion 42 of the upper electrode layer 40 overlaps on the first protrusion 22 of the lower electrode layer 20. In this way, a Josephson junction 50 can be formed in the overlapping area, and the Josephson junction 50 is a structure in which the first protrusion 22, the oxide layer 30 and the second protrusion 42 are stacked in sequence. Afterwards, in the application process of the Josephson junction 50, the current can flow from the first body part 21 of the lower electrode layer 20, the first protrusion 22 of the lower electrode layer 20, the oxide layer 30, the second protrusion 42 of the upper electrode layer 40 to the second body part 41 of the upper electrode layer 40, so as to form a conductive structure.

[0077] Optionally, a second photolithography mask layer is formed on a surface of the second superconducting film away from the substrate, and the second superconducting film is patterned according to the second photolithography mask layer to form a second main body and a second protrusion that are integrally connected to prepare a Josephson junction. The method also includes: patterning the second superconducting film according to the second photolithography mask layer to form a superconducting circuit structure; wherein the superconducting circuit structure includes at least a resonant cavity, a read line, and a capacitance and inductance structure of a bit, and the superconducting circuit structure is electrically connected to the lower electrode layer and the upper electrode layer, respectively.

[0078] Specifically, this step is still a process of pattern transfer of the second superconducting film according to the second photolithography mask layer, in which the upper electrode layer and the superconducting circuit structure can be prepared at the same time. Exemplarily, the second superconducting film is patterned according to the second photolithography mask layer, and a second body portion and a second protrusion portion connected in an integral manner are formed in the vicinity of the lower electrode layer to prepare a Josephson junction, and at the same time, a superconducting circuit structure is formed in an area different from the upper electrode layer and the lower electrode layer. Exemplarily, a dry or wet etching process can be used to etch the second superconducting film to complete the patterning. Taking dry etching as an example, an inductively coupled plasma etcher is used, and carbon tetrafluoride (CF4) gas is used as the main etching gas. The superconducting circuit structure is formed by pattern transfer, and the superconducting circuit structure, the lower electrode layer, the oxide layer and the upper electrode layer are all located on the same side of the substrate, and the superconducting circuit structure is electrically connected to the lower electrode layer and the upper electrode layer respectively. It should be noted that the superconducting circuit structure discussed in this embodiment does not include the Josephson junction and its electrode layer structure mentioned above, and the orthographic projection of the superconducting circuit structure on the substrate substrate does not overlap with the orthographic projection of the Josephson junction and its electrode layer structure on the substrate substrate. By way of example, the superconducting circuit structure can be used to regulate the Josephson junction prepared above.

[0079] And, the present embodiment limits the patterning of the second superconducting film to prepare the superconducting circuit structure and the upper electrode layer at the same time. It should be noted that on one side surface of the substrate, the second superconducting film is first formed, and then the second photolithography mask layer is formed. In this way, the substrate does not need to carry the photoresist into the vacuum evaporation chamber. Instead, a whole layer of the second superconducting film is formed on one side surface of the substrate using a vertical evaporation method, and then the vacuum evaporation chamber is taken out for uniform coating to form the second photolithography mask layer, and finally etching is performed. That is, the superconducting circuit structure is prepared lagging (the superconducting circuit structure and the upper electrode layer are prepared at the same time, rather than the superconducting circuit structure and the lower electrode layer are prepared at the same time), which can reduce the adverse effects of residual glue pollution and etching damage on the superconducting circuit structure caused by subsequent processing technology, and also avoid the existence of other parasitic junctions. That is, during the evaporation process of the second superconducting film, there is no need to introduce photoresist into the vacuum chamber, which avoids the photoresist from causing glue contamination to the vacuum evaporation chamber and affecting the vacuum, thereby ensuring the high purity and high quality of the second superconducting film. At the same time, there is no need to consider the growth conditions of the second superconducting film being restricted by the presence of photoresist, and technicians can try better methods and conditions to prepare the second superconducting film.

[0080] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A superconducting chip having a Josephson junction, characterized in that: It includes a substrate, a lower electrode layer, an oxide layer and an upper electrode layer; In the thickness direction of the base substrate, the lower electrode layer, the oxide layer and the upper electrode layer are all located on the same side of the base substrate; The lower electrode layer is located on one side surface of the base substrate, and the lower electrode layer includes a first main body portion and a first protrusion portion that are integrally connected; The oxide layer is located on a surface of the first protrusion away from the substrate; The upper electrode layer is located on a surface of the oxide layer away from the base substrate, the upper electrode layer includes a second body portion and a second protrusion portion connected in one piece, and the second protrusion portion at least partially overlaps with the positive projection of the oxide layer on the base substrate, and the Josephson junction is a structure in which the first protrusion portion, the oxide layer and the second protrusion portion are stacked in sequence; The second protrusion includes a first portion and a second portion connected in an integral manner, the second portion is located on a side of the first portion away from the second main portion, and at least a portion of the orthographic projection of the second portion on the substrate is located in the orthographic projection of the oxide layer on the substrate, and the Josephson junction is a structure in which the first protrusion, the oxide layer and the second portion are stacked in sequence; The orthographic projection of the first protrusion on the base substrate is a trapezoidal shape, and the orthographic projection of the first portion on the base substrate is a trapezoidal shape.

2. The superconducting chip according to claim 1, characterized in that: The orthographic projection of the second portion on the base substrate is a rectangular shape.

3. The superconducting chip according to claim 2, characterized in that: The trapezoidal shape of the first protrusion includes a first side, the first side is a side of the first protrusion away from the first body part; the trapezoidal shape of the first part includes a second side, the second side is a side of the first part away from the second body part; the rectangular shape of the second part includes a third side, the third side is a side of the second part close to the first part; In the orthographic projection on the base substrate, the length of the first side, the length of the second side and the length of the third side are the same as or different from each other.

4. The superconducting chip according to claim 1, characterized in that: In the thickness direction of the base substrate, the first body portion and the first protrusion portion have the same thickness, and the second body portion has a thickness greater than or equal to a thickness of the first body portion.

5. The superconducting chip according to claim 1, characterized in that: Also included is a superconducting circuit structure, which includes at least a resonant cavity, a read line, and a capacitance and inductance structure of a bit; In the thickness direction of the base substrate, the superconducting circuit structure, the lower electrode layer, the oxide layer and the upper electrode layer are all located on the same side of the base substrate, and the superconducting circuit structure is electrically connected to the lower electrode layer and the upper electrode layer respectively.

6. A method for preparing a superconducting chip having a Josephson junction, characterized in that: include: Providing a substrate; A lower electrode layer is formed on one side surface of the base substrate; wherein the lower electrode layer includes a first main body portion and a first protrusion portion connected in one piece; forming an oxide layer on a surface of the first protrusion away from the substrate; An upper electrode layer is formed on a surface of the oxide layer on a side away from the base substrate to prepare the Josephson junction; wherein the upper electrode layer includes a second main body portion and a second protruding portion connected in one piece, and the second protruding portion at least partially overlaps with the orthographic projection of the oxide layer on the base substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second protruding portion are stacked in sequence; the second protruding portion includes a first portion and a second portion connected in one piece, the second portion is located on a side of the first portion away from the second main body portion, and at least a portion of the orthographic projection of the second portion on the base substrate is located in the orthographic projection of the oxide layer on the base substrate, and the Josephson junction is a structure in which the first protruding portion, the oxide layer and the second portion are stacked in sequence; the orthographic projection of the first protruding portion on the base substrate is a trapezoidal shape, and the orthographic projection of the first portion on the base substrate is a trapezoidal shape.

7. The preparation method according to claim 6, characterized in that: A lower electrode layer is formed on one side surface of the base substrate, comprising: Forming a first superconducting thin film on one side surface of the substrate by vertical evaporation method; A first photolithography mask layer is formed on a surface of the first superconducting film at a side away from the base substrate, and the first superconducting film is patterned according to the first photolithography mask layer to form the first main body and the first protrusion that are integrally connected.

8. The preparation method according to claim 6, characterized in that: An upper electrode layer is formed on a surface of the oxide layer away from the substrate to prepare the Josephson junction, comprising: Forming a second superconducting thin film on a surface of the oxide layer away from the substrate by vertical evaporation; A second photolithography mask layer is formed on a surface of the second superconducting film away from the substrate, and the second superconducting film is patterned according to the second photolithography mask layer to form the second main body and the second protrusion that are integrally connected to obtain the Josephson junction.

9. The preparation method according to claim 8, characterized in that: A second photolithography mask layer is formed on a surface of the second superconducting film on a side away from the substrate, and the second superconducting film is patterned according to the second photolithography mask layer to form the second main body portion and the second protrusion portion connected in one piece to prepare the Josephson junction, and further includes: According to the second photolithography mask layer, the second superconducting film is patterned to form a superconducting circuit structure; wherein the superconducting circuit structure at least includes a resonant cavity, a read line, and a capacitance and inductance structure of a bit, and the superconducting circuit structure is electrically connected to the lower electrode layer and the upper electrode layer respectively.

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