Chip and method for preparing the same

Abstract

The present invention relates to the technical field of semiconductor packaging technology, and provides a chip and a preparation method thereof, wherein the chip comprises a substrate, a plurality of insulating layers and a plurality of rewiring layers; the plurality of insulating layers are laid on the substrate, the plurality of insulating layers are stacked in sequence, and each insulating layer is provided with a plurality of grooves, a plurality of limiting cavities and a plurality of micro-copper pillars; the plurality of grooves are arranged on a side of the insulating layer away from the substrate; each limiting cavity is located on a side of the groove close to the substrate and is connected to the groove; the plurality of micro-copper pillars are arranged in a one-to-one correspondence with the plurality of grooves, and each micro-copper pillar is filled in a corresponding groove and a corresponding limiting cavity; the plurality of rewiring layers are arranged in a one-to-one correspondence with the plurality of insulating layers, each rewiring layer is arranged on a side of the insulating layer away from the substrate, and is connected to the plurality of micro-copper pillars on the grooves, the limiting cavity plays a role of further limiting the micro-copper pillars, and reinforces the micro-copper pillars, and the micro-copper pillars are connected to the rewiring layer, thereby improving the connection strength between the rewiring layer and the insulating layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip and a preparation method thereof. Background Art

[0002] Integrated circuit (IC) or microcircuit, microchip, chip is a way to miniaturize circuits (mainly semiconductor devices, but also passive components, etc.) in electronics, and is often manufactured on the surface of semiconductor wafers. Existing chips include a substrate, an insulating layer and a rewiring layer, the insulating layer is arranged on the substrate, and the rewiring layer is arranged on the insulating layer. At present, the rewiring layer and the insulating layer in the chip are prone to delamination or even separation. Summary of the invention

[0003] In view of this, the present invention proposes a chip and a preparation method thereof, which adds the limiting cavity and the micro-copper pillar. The limiting cavity further limits the micro-copper pillar and reinforces the micro-copper pillar. The micro-copper pillar is connected to the rewiring layer, thereby limiting and reinforcing the rewiring layer, improving the connection strength between the rewiring layer and the insulating layer, and avoiding the problem of delamination or even separation between the rewiring layer and the insulating layer in the current chip.

[0004] The technical solution of the present invention is implemented as follows: the present invention provides a chip, including a substrate, a plurality of insulating layers and a plurality of rewiring layers; the plurality of insulating layers are laid on the substrate, the plurality of insulating layers are stacked in sequence, and each insulating layer is provided with a plurality of grooves, a plurality of limiting cavities and a plurality of micro copper pillars; the plurality of grooves are arranged on a side of the insulating layer away from the substrate; the plurality of limiting cavities are arranged in a one-to-one correspondence with the plurality of grooves, each limiting cavity is located on a side of the groove close to the substrate, and is connected to the groove, and the projection of the end of the groove close to the limiting cavity along the thickness direction of the insulating layer is located in the limiting cavity; the plurality of micro copper pillars are arranged in a one-to-one correspondence with the plurality of grooves, each micro copper pillar extends into the limiting cavity through the groove, and the micro copper pillars are filled in the corresponding grooves and the corresponding limiting cavity; the plurality of rewiring layers are arranged in a one-to-one correspondence with the plurality of insulating layers, each rewiring layer is arranged on a side of the insulating layer away from the substrate, and is connected to the plurality of micro copper pillars on the grooves.

[0005] On the basis of the above technical solution, preferably, the multiple grooves and the multiple limiting cavities on each insulating layer are arranged alternately with the multiple grooves and the multiple limiting cavities on an adjacent insulating layer.

[0006] On the basis of the above technical solution, preferably, each groove is funnel-shaped, and an end with a larger diameter of the groove is arranged away from the substrate.

[0007] Based on the above technical solution, preferably, the depth of the limiting cavity along the thickness direction of the insulating layer is 1-1.5 times the thickness of the rewiring layer; and / or the rewiring layer includes a metal wire, the limiting cavity is funnel-shaped, and the diameter of the limiting cavity is 0.5-1 times the width of the metal wire.

[0008] On the basis of the above technical solution, preferably, the limiting cavity is a spherical cavity, and a limiting protrusion is provided on the inner side wall of the cavity away from the groove.

[0009] On the basis of the above technical solution, preferably, the material for preparing the substrate includes a silicon wafer, a glass wafer or a ceramic wafer; and / or the material for preparing the insulating layer includes photosensitive polyimide.

[0010] The present invention also provides a method for preparing a chip, comprising the following steps:

[0011] S1. Laying an insulating layer on the substrate, and forming the plurality of grooves and the plurality of limiting cavities;

[0012] S2, embedding the micro copper pillars into corresponding grooves and limiting cavities;

[0013] S3, laying a rewiring layer on the side of the insulating layer away from the substrate, wherein the rewiring layer is connected to the micro copper pillars on the insulating layer, thus completing the laying of one insulating layer;

[0014] S4. Repeat steps S1-S3 to arrange multiple insulating layers stacked in sequence to obtain a chip.

[0015] On the basis of the above technical solution, preferably, in step S1, the insulating layer laid on the substrate is obtained by dropping photosensitive polyimide on the substrate and applying it evenly.

[0016] On the basis of the above technical solution, preferably, in step S1, the plurality of grooves are prepared on the insulating layer by a photolithography process; and / or, in step S1, the plurality of limiting cavities are etched by an etching process.

[0017] On the basis of the above technical solution, preferably, in step S2, the micro copper pillars are prepared by a magnetron sputtering copper process.

[0018] A chip and a preparation method thereof of the present invention have the following beneficial effects compared with the prior art:

[0019] (1) The present invention adds the limiting cavity and the micro copper pillar. The limiting cavity further limits the micro copper pillar and reinforces the micro copper pillar. The micro copper pillar is connected to the rewiring layer, thereby limiting and reinforcing the rewiring layer, improving the connection strength between the rewiring layer and the insulating layer, and avoiding the problem of easy delamination or even separation between the rewiring layer and the insulating layer in the current chip.

[0020] (2) The limiting protrusion provided in the limiting cavity of the present invention can further play the role of limiting and stabilizing the micro copper pillar.

[0021] (3) The present invention directly prepares the insulating layer by spin coating on the substrate, then opens holes in the insulating layer and prepares the rewiring layer. Compared with the prior art, metal pillars are first implanted into the substrate, and then an insulating layer is coated, and then the substrate is ground and thinned to reveal the metal pillars, and solder balls are implanted to obtain a through-hole structure and then interconnected with the rewiring layer. The preparation steps of the present application are simpler and faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 This is a schematic diagram of the structure of the invented chip;

[0024] Figure 2 for Figure 1 sectional view of

[0025] Figure 3 for Figure 2 A partial enlarged view of

[0026] Figure 4 FIG. 4 is a partial cross-sectional view of a chip in another embodiment.

[0027] Reference numerals: chip 100 , substrate 1 , insulating layer 2 , groove 21 , limiting protrusion 211 , limiting cavity 22 , micro copper pillar 23 , rewiring layer 3 . DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] like Figure 1-4 As shown, the present invention provides a chip 100, comprising a substrate 1, a plurality of insulating layers 2 and a plurality of rewiring layers 3; the plurality of insulating layers 2 are laid on the substrate 1, the plurality of insulating layers 2 are stacked in sequence, and each insulating layer 2 is provided with a plurality of grooves 21, a plurality of limiting cavities 22 and a plurality of micro copper pillars 23; the plurality of grooves 21 are arranged on a side of the insulating layer 2 away from the substrate 1; the plurality of limiting cavities 22 are arranged in a one-to-one correspondence with the plurality of grooves 21, each limiting cavity 22 is located on a side of the groove 21 close to the substrate 1, and is communicated with the groove 21, the grooves 21 are arranged on the substrate 1, and the plurality of limiting cavities 22 are arranged on the substrate 1, and the plurality of micro copper pillars 23 are arranged on the substrate 1; the plurality of micro copper pillars 23 ... The projection of the end of the groove 21 close to the limiting cavity 22 along the thickness direction of the insulating layer 2 is located in the limiting cavity 22; the multiple micro-copper pillars 23 are arranged in a one-to-one correspondence with the multiple grooves 21, and each micro-copper pillar 23 extends into the limiting cavity 22 through the groove 21, and the micro-copper pillars 23 are filled in the corresponding grooves 21 and the corresponding limiting cavity 22; the multiple re-wiring layers 3 are arranged in a one-to-one correspondence with the multiple insulating layers 2, and each re-wiring layer 3 is arranged on the side of the insulating layer 2 away from the substrate 1, and is connected to the multiple micro-copper pillars 23 on the grooves 21.

[0030] In the above technical solution, the materials of the substrate 1 and the insulating layer 2 are not limited. In some embodiments, the material of the substrate 1 includes a silicon wafer, a glass sheet or a ceramic sheet. In other embodiments, the insulating layer 2 includes photosensitive polyimide, which is a permanent material with good mechanical and thermodynamic properties, high reliability, chemical resistance and heat resistance. Of course, the specific material of the rewiring layer 3 is not limited. The specific material of the rewiring layer 3 is selected according to actual needs, for example, it can be made of copper, aluminum and other materials. A groove 21 is provided on each insulating layer 2, and the groove 21 is connected to the limiting cavity 22. The groove 21 and the limiting cavity 22 together form a limiting groove, and the micro copper pillar 23 is located in the limiting groove, wherein the groove 21 is limited as follows: the projection of the end of the groove 21 close to the limiting cavity 22 along the thickness direction of the insulating layer 2 is located in the limiting cavity 22, for the purpose of setting the waist position of the limiting groove to have the smallest diameter, so that the part of the micro copper pillar 23 located in the limiting cavity 22 is difficult to go out, that is, it plays a role in limiting the micro copper pillar 23. Since the limiting cavity 22 limits and stabilizes the micro copper pillar 23, in some embodiments, in order to further stabilize the micro copper pillar 23, the limiting cavity 22 is set to a spherical cavity, and a limiting protrusion 211 is provided on the inner side wall of the cavity away from the groove 21. The present invention does not limit the specific number of the grooves 21 , the limiting cavities 22 and the micro copper pillars 23 , which can be determined according to actual conditions.

[0031] The present invention adds the limiting cavity 22 and the micro copper pillar 23. The limiting cavity 22 further limits the micro copper pillar 23 and reinforces the micro copper pillar 23. The micro copper pillar 23 is connected to the rewiring layer 3, thereby limiting and reinforcing the rewiring layer 3, improving the connection strength between the rewiring layer 3 and the insulating layer 2, and avoiding the problem of easy delamination or even separation between the rewiring layer 3 and the insulating layer 2 in the current chip 100.

[0032] Furthermore, the multiple grooves 21 and the multiple limiting cavities 22 on each insulating layer 2 are staggered with the multiple grooves 21 and the multiple limiting cavities 22 on the adjacent insulating layer 2 to improve packaging reliability and reduce the warping effect caused by the multi-layer redistribution layer 3.

[0033] Specifically, each groove 21 is funnel-shaped, and the end of the groove 21 with a larger diameter is arranged away from the substrate 1. The purpose of setting the groove 21 into a funnel shape is to make the side wall of the groove 21 inclined, so as to facilitate the flow of liquid used to prepare the micro copper column 23.

[0034] Furthermore, the depth of the limiting cavity 22 along the thickness direction of the insulating layer 2 is 1-1.5 times the thickness of the rewiring layer 3, further limiting the micro copper pillar 23 to avoid the interconnection crosstalk problem between the layers of the rewiring layer 3 caused by the depth being too deep; if the depth is too shallow, the expected limiting effect cannot be achieved.

[0035] Furthermore, the rewiring layer 3 includes a metal wire, and the limiting cavity 22 is funnel-shaped. The diameter of the limiting cavity 22 is 0.5-1 times the width of the metal wire, further limiting the micro copper column 23 to avoid stress concentration problems at the interface due to a large diameter, reduce warping of the rewiring layer 3, and reduce the possibility of cracks at the interface. If the diameter is too small, the expected limiting effect cannot be achieved.

[0036] The present invention provides a method for preparing a chip 100, comprising the following steps:

[0037] S1, laying an insulating layer 2 on the substrate 1, and forming the plurality of grooves 21 and the plurality of limiting cavities 22;

[0038] S2, embedding the micro copper pillar 23 into the corresponding groove 21 and the limiting cavity 22;

[0039] S3, laying a rewiring layer 3 on the side of the insulating layer 2 away from the substrate 1, wherein the rewiring layer 3 is connected to the micro copper pillars 23 on the insulating layer 2, thus completing the laying of one insulating layer 2;

[0040] S4. Repeat steps S1 to S3 to arrange multiple insulating layers 2 stacked in sequence to obtain the chip 100.

[0041] The present invention directly prepares the insulating layer 2 by spin coating on the substrate 1, then opens holes in the insulating layer 2, and prepares the rewiring layer 3. Compared with the prior art, metal pillars are first implanted into the substrate 1, and then the insulating layer 2 is coated, and then the substrate 1 is ground and thinned to reveal the metal pillars, and solder balls are implanted to obtain a through-hole structure and then interconnected with the rewiring layer 3. The preparation of the present application is simpler and faster.

[0042] In the above technical solutions, the method for preparing the chip 100 includes all the technical solutions and beneficial effects of the aforementioned chip 100, which will not be described one by one here.

[0043] Specifically, in some embodiments, the insulating layer 2 is applied by dropping photosensitive polyimide on the substrate 1 and applying it evenly. The present invention does not limit the specific method of opening the multiple grooves 21 and the multiple limiting cavities 22. In some embodiments, the multiple grooves 21 are prepared on the insulating layer 2 by a photolithography process, and in other embodiments, the multiple limiting cavities 22 are etched by an etching process. In some embodiments, the multiple grooves 21 and the rewiring layer 3 are patterned and prepared by photolithography, development, and curing processes; the limiting cavity 22 is etched by an etching process; and the copper electroplating process is used to intelligently identify the fixed-point electroplating to complete the preparation of the micro copper pillars 23 and the rewiring layer 3. The chip 100 is placed on a wafer, and the photolithography process includes wafer surface treatment, glue coating, soft baking, alignment, exposure, development, post-baking, and curing. The wafer surface is treated by plasma treatment, and the substrate 1 is cleaned by plasma in a nitrogen or oxygen atmosphere to remove pollutants and increase the interface adhesion of the substrate 1; the glue coating process uses a sprayer to spray PSPI (photosensitive polyimide) solution to ensure that PSPI is evenly coated on the wafer and avoid stress problems caused by uneven film thickness; the soft baking process uses a vacuum tube furnace for baking, and nitrogen is filled in a vacuum for soft baking for a period of time, which helps to release the stress of the film and avoid air pollution of the film; the alignment process uses laser position calibration to avoid pattern misalignment during the photolithography process; the exposure process uses step-and-scan projection exposure to avoid damage to the mask during the exposure process and avoid contact between the mask and PSPI colloid, greatly reducing pollution and reducing defects generated during the preparation process; the development process uses multiple rotation development and deionized water for cleaning to reduce the amount of developer and ensure uniform pattern development; the post-baking process uses a vacuum tube furnace and nitrogen is filled in a vacuum to effectively reduce the standing wave effect and stimulate the film protective group to react chemically with the acid generated by the film PAG; the curing process uses vacuum curing to enhance the film interface adhesion and further reduce the standing wave effect. The optimized etching process adopts dry etching to prepare the micro copper pillars 23, avoiding the chemical safety problems and chemical pollution caused by wet etching, and effectively utilizing the anisotropy and micro groove effect of dry etching. The preparation method combining photolithography and etching processes can effectively overcome the problems of pattern dislocation, distortion and pollution in the process, and enhance the interface adhesion.

[0044] In some embodiments, the redistribution layer 3 is prepared by an electroplating copper process, and the electroplating process includes three steps: electroplating pre-treatment, electroplating, and electroplating post-treatment. The preparation process is required to use ultrasonic cleaning technology in the pre-treatment step to effectively remove impurities on the wafer surface and increase the surface adhesion between the electroplated layer and the thin film layer; the electroplating step uses an alkaline copper plating method to facilitate electroplating a smooth and delicate copper surface; the post-treatment step dehydrates and passivates the coating to improve the corrosion resistance and bonding of the coating.

[0045] In addition, in order to avoid a sealing effect in the groove 21 during the electroplating of the micro-copper pillar 23, a micro-copper pillar that is convenient for electroplating and filling copper particles can be supplemented on the basis of the micro-copper pillar 23, and the manufacturing process is the same.

[0046] Furthermore, in step S2, the micro copper pillars 23 are prepared by using a magnetron sputtering copper process to make the installation more secure.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip, characterized in that: It comprises a substrate (1), a plurality of insulating layers (2) and a plurality of rewiring layers (3); A plurality of insulating layers (2) are laid on the substrate (1), the plurality of insulating layers (2) are stacked in sequence, and each insulating layer (2) is provided with a plurality of grooves (21), a plurality of limiting cavities (22) and a plurality of micro copper pillars (23); A plurality of grooves (21) are arranged on a side of the insulating layer (2) away from the substrate (1); A plurality of limiting cavities (22) are arranged in one-to-one correspondence with the plurality of grooves (21); each limiting cavity (22) is located on a side of the groove (21) close to the substrate (1) and is in communication with the groove (21); a projection of an end of the groove (21) close to the limiting cavity (22) along a thickness direction of the insulating layer (2) is located within the limiting cavity (22); A plurality of micro-copper pillars (23) are arranged in one-to-one correspondence with the plurality of grooves (21), each micro-copper pillar (23) extends into the limiting cavity (22) through the groove (21), and the micro-copper pillars (23) are filled in the corresponding groove (21) and the corresponding limiting cavity (22); A plurality of rewiring layers (3) are arranged in one-to-one correspondence with the plurality of insulating layers (2), each rewiring layer (3) being arranged on a side of the insulating layer (2) away from the substrate (1) and connected to the plurality of micro copper pillars (23) on the groove (21); The depth of the limiting cavity (22) along the thickness direction of the insulating layer (2) is 1 to 1.5 times the thickness of the rewiring layer (3); and / or, The rewiring layer (3) comprises a metal wire, the limiting cavity (22) is funnel-shaped, and the diameter of the limiting cavity (22) is 0.5 to 1 times the width of the metal wire.

2. The chip according to claim 1, characterized in that: The plurality of grooves (21) and the plurality of limiting cavities (22) on each insulating layer (2) are arranged alternately with the plurality of grooves (21) and the plurality of limiting cavities (22) on an adjacent insulating layer (2).

3. The chip according to claim 1, characterized in that: Each groove (21) is funnel-shaped, and an end with a larger diameter of the groove (21) is arranged away from the substrate (1).

4. The chip according to claim 1, characterized in that: The limiting cavity (22) is a spherical cavity, and a limiting protrusion (211) is provided on the inner side wall of the cavity away from the groove (21).

5. The chip according to claim 1, characterized in that: The material for preparing the substrate (1) includes a silicon wafer, a glass wafer or a ceramic wafer; and / or, The material used to prepare the insulating layer (2) includes photosensitive polyimide.

6. The method for preparing a chip according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, laying an insulating layer (2) on the substrate (1), and providing the plurality of grooves (21) and the plurality of limiting cavities (22); S2, embedding the micro copper pillar (23) into the corresponding groove (21) and the limiting cavity (22); S3, laying a rewiring layer (3) on the side of the insulating layer (2) away from the substrate (1), wherein the rewiring layer (3) is connected to the micro copper pillars (23) on the insulating layer (2), thereby completing the laying of one insulating layer (2); S4, repeating steps S1-S3 to arrange multiple insulating layers (2) stacked in sequence, thereby obtaining a chip (100).

7. The preparation method according to claim 6, characterized in that: In step S1, photosensitive polyimide is dripped onto the substrate (1) and spread evenly to obtain an insulating layer (2) laid on the substrate (1).

8. The preparation method according to claim 6, characterized in that: In step S1, the plurality of grooves (21) are prepared on the insulating layer (2) by a photolithography process; and / or, In step S1, a plurality of limiting cavities (22) are etched using an etching process.

9. The preparation method according to claim 6, characterized in that: In step S2, the micro copper pillars (23) are prepared by using a magnetron sputtering copper process.

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