Ferroelectric device and method of manufacturing the same

Abstract

The present disclosure provides a ferroelectric device and a preparation method thereof, which can be applied to the technical field of semiconductors. The ferroelectric device comprises a substrate layer; a bottom gate electrode located in the substrate layer; a ferroelectric layer located in the ferroelectric device, a lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer surrounding the ferroelectric layer; a channel layer in contact with an upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, all of which are in contact with an upper surface of the channel layer; a second device isolation layer between the source electrode, the drain electrode and the top gate electrode; and a stop layer between the first device isolation layer and the second device isolation layer, and surrounding the source electrode, the drain electrode and the top gate electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a ferroelectric device and a preparation method thereof. BACKGROUND

[0002] Due to the problems of memory wall and power wall, the classical Von Neumann architecture is difficult to meet the demand of big data and artificial intelligence for computing power. Based on this, as one of the improvement schemes, in-memory computing has been widely studied. The basic idea of in-memory computing is to combine operation and storage into one, reducing the frequency of processor accessing memory.

[0003] Due to its significant advantages in low power consumption, compatibility and reliability, ferroelectric transistor (FeFET) has gradually become one of the main implementation schemes of in-memory computing, and its core is the MOS structure of metal-ferroelectric-insulator-semiconductor (MFIS) stack. However, this structure is facing many problems. First, as the device size is miniaturized, the ferroelectric gate dielectric also needs to be thinned, which will lead to a decrease in the number of effective ferroelectric flip domains, and in turn narrow the storage window, which is not conducive to multi-bit storage; second, whether the device is prepared using the front gate process or the back gate process, the ferroelectric crystallization annealing and the source-drain activation annealing will interfere with each other and affect the device performance; third, the change of the ferroelectric polarization state requires a large bias voltage, while the logic operation requires a small bias voltage, and the contradiction between the two exacerbates the damage to the gate oxide interface layer, affecting the device reliability. SUMMARY

[0004] In view of the above problems, the present disclosure provides a ferroelectric device and a preparation method thereof.

[0005] According to one aspect of the present disclosure, a ferroelectric device is provided, comprising: a substrate layer; a bottom gate electrode located in the substrate layer; a ferroelectric layer located inside the ferroelectric device, a lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer surrounding the ferroelectric layer; a channel layer in contact with an upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, all of which are in contact with an upper surface of the channel layer; a second device isolation layer between the source electrode, the drain electrode and the top gate electrode; and a stop layer between the first device isolation layer and the second device isolation layer, and surrounding the source electrode, the drain electrode and the top gate electrode.

[0006] According to an embodiment of the present disclosure, the ferroelectric layer comprises a first ferroelectric layer and a second ferroelectric layer, and the first device isolation layer surrounds the first ferroelectric layer and the second ferroelectric layer, respectively.

[0007] According to an embodiment of the present disclosure, the channel layer includes a first channel layer and a second channel layer, the source electrode includes a first source electrode and a second source electrode, the drain electrode includes a first drain electrode and a second drain electrode, the top gate electrode includes a first top gate electrode and a second top gate electrode, the bottom gate electrode includes a first bottom gate electrode and a second bottom gate electrode, the electrode material of the first top gate electrode is different from that of the second top gate electrode, and the electrode material of the first bottom gate electrode is different from that of the second bottom gate electrode; wherein the lower surface of the first ferroelectric layer is in contact with the first bottom gate electrode, the upper surface of the first ferroelectric layer is in contact with the first channel layer, the upper surface of the first channel layer is in contact with the first source electrode, the first drain electrode and the first top gate electrode, and the first top gate electrode is located between the first source electrode and the first drain electrode; the lower surface of the second ferroelectric layer is in contact with the second bottom gate electrode, the upper surface of the second ferroelectric layer is in contact with the second channel layer, the upper surface of the second channel layer is in contact with the second source electrode, the second drain electrode and the second top gate electrode, and the second top gate electrode is located between the second source electrode and the second drain electrode.

[0008] According to an embodiment of the present disclosure, the material of the first ferroelectric layer and the material of the second ferroelectric layer are the same, and the material of the first ferroelectric layer and the material of the second ferroelectric layer both include hafnium dioxide doped with a target element, the target element including at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum and strontium; the electrode material of the first top gate electrode includes hafnium dioxide, titanium nitride and tungsten; the electrode material of the second top gate electrode includes hafnium dioxide, titanium aluminum and tungsten; the electrode material of the first bottom gate electrode includes silicon nitride, tungsten and titanium nitride; the electrode material of the second bottom gate electrode includes silicon nitride, tungsten and titanium aluminum; and the material of the source electrode and the material of the drain electrode both include tungsten and titanium nitride.

[0009] According to another aspect of the present disclosure, a preparation method of a ferroelectric device is provided, including: etching an upper surface of a substrate layer according to a predetermined pattern to obtain a patterned substrate layer, wherein the patterned substrate layer includes etched regions corresponding to the predetermined pattern; depositing a gate material in the etched regions to obtain a substrate layer including a bottom gate layer; depositing a ferroelectric material on the bottom gate layer to form a ferroelectric layer in contact with the bottom gate layer; depositing an isolation layer material on the substrate layer to form a first device isolation layer surrounding the ferroelectric layer; preparing a channel layer, a stop layer, a top gate electrode, a source electrode and a drain electrode, and a second device isolation layer for isolating the top gate electrode, the source electrode and the drain electrode on the ferroelectric layer; thinning the substrate layer to expose the bottom gate layer to a lower surface of the substrate layer; and forming a bottom gate electrode based on the material of the bottom gate layer exposed to the lower surface of the substrate layer to obtain the ferroelectric device.

[0010] According to an embodiment of the present disclosure, the method for preparing a first device isolation layer surrounding a ferroelectric layer on a substrate layer comprises: bonding a surface of the ferroelectric layer and a surface of a silicon material implanted with hydrogen ions, and pre-bonding the ferroelectric layer and the silicon material to fix the silicon material on the surface of the ferroelectric layer; thinning the silicon material fixed on the surface of the ferroelectric layer to obtain a silicon layer on the surface of the ferroelectric layer; etching the silicon layer and the ferroelectric layer according to a pattern corresponding to a position of a bottom gate layer to obtain a patterned ferroelectric layer and a patterned silicon layer; and depositing silicon dioxide surrounding the patterned ferroelectric layer and the patterned silicon layer on the substrate layer to obtain the first device isolation layer.

[0011] According to an embodiment of the present disclosure, the method for preparing a channel layer, a stop layer, a top gate electrode, a source electrode and a drain electrode, and a second device isolation layer for isolating the top gate electrode, the source electrode and the drain electrode on the ferroelectric layer comprises: sequentially depositing silicon dioxide, polysilicon, silicon dioxide, silicon nitride and silicon dioxide on a surface of a silicon layer to obtain an alternating deposition layer; etching the alternating deposition layer according to a pattern corresponding to a position of the silicon layer to obtain a patterned structure on the silicon layer; growing a side wall surrounding the patterned structure using silicon nitride; depositing a silicon germanium layer surrounding the side wall on the surface of the silicon layer; performing ion implantation on the silicon germanium layer to form a source layer and a drain layer on the surface of the silicon layer; annealing the source layer and the drain layer to obtain an annealed source layer and an annealed drain layer; depositing silicon nitride on the annealed source layer, the annealed drain layer and the first device isolation layer to form the stop layer; thinning the patterned structure according to a thickness of the stop layer to obtain a thinned patterned structure, wherein the thinned patterned structure comprises a silicon dioxide structure and a polysilicon structure; performing wet etching on silicon dioxide and polysilicon located inside the silicon dioxide structure according to a pattern corresponding to a position of the polysilicon located inside the silicon dioxide structure until the channel layer is exposed; depositing a gate material on a surface of the channel layer located inside the silicon dioxide structure to obtain the top gate electrode; depositing silicon dioxide on the top gate electrode and the stop layer, and etching the silicon dioxide and the stop layer according to a pattern corresponding to positions of the source layer and the drain layer until the source layer and the drain layer are exposed to form the second device isolation layer; and sequentially depositing titanium nitride, tungsten and titanium nitride on the source layer and the drain layer to obtain the source electrode and the drain electrode.

[0012] According to an embodiment of the present disclosure, the method for depositing a gate material on a surface of a channel layer located inside a silicon dioxide structure to obtain a top gate electrode comprises: using ozone to oxidize the surface of the channel layer located inside the silicon dioxide structure to form a silicon oxide layer; and depositing the gate material on a surface of the silicon oxide layer to obtain the top gate electrode.

[0013] According to an embodiment of the present disclosure, the method for depositing a ferroelectric material on a bottom gate layer to form a ferroelectric layer in contact with the bottom gate layer comprises: sequentially depositing the ferroelectric material and titanium nitride on the bottom gate layer to obtain a substrate layer covering the ferroelectric material and titanium nitride; performing ferroelectric annealing on the substrate layer covering the ferroelectric material and titanium nitride to obtain an annealed substrate layer, wherein the annealing temperature of the ferroelectric annealing corresponds to the material type of the ferroelectric material; and removing the titanium nitride on the surface of the annealed substrate layer to obtain the ferroelectric layer.

[0014] According to an embodiment of the present disclosure, the etching region comprises a first etching region and a second etching region; and the method for obtaining a substrate layer comprising a bottom gate layer by depositing a gate material in the etching region comprises: sequentially depositing silicon nitride, tungsten and titanium nitride in the first etching region to form a first bottom gate layer, and sequentially depositing silicon nitride, tungsten and titanium aluminum in the second etching region to form a second bottom gate layer, to obtain the substrate layer comprising the bottom gate layer.

[0015] According to an embodiment of the present disclosure, the present disclosure directly ferroelectricizes a BOX (Buried Oxide) layer to obtain a ferroelectric layer by combining the process of an SOI wafer, and realizes device separation by using a method of pre-embedding a bottom gate layer. Thus, the top layer device can be used as a logic operation unit, and the bottom layer device can be used as a data storage unit, so that the top layer device and the bottom layer device share a channel and source-drain. The top layer device can comprise a top gate electrode and other devices above the channel layer, and the bottom layer device can comprise a bottom gate electrode and other devices below the channel layer.

[0016] Based on this, by separating the gate into a top gate electrode and a bottom gate electrode, different ranges of bias voltage can be applied to the top gate electrode and the bottom gate electrode respectively, reducing the damage to the gate oxide of the top gate electrode caused by repeatedly applying a large bias voltage. Moreover, the ferroelectric layer no longer follows the size shrinkage of the top layer logic device, ensuring the operation speed of the logic and the reliability of the ferroelectric storage. At the same time, before the device is prepared, the ferroelectric layer has been completely crystallized, the metal layer that most affects the ferroelectric phase is removed, and a higher temperature is required for the transition to a non-ferroelectric phase. Thus, the thermal budget of ferroelectric crystallization and source-drain activation can be achieved without interfering with each other, expanding the selection of ferroelectric materials and source-drain processes.

[0017] Based on this, the ferroelectric SOI pre-embedded gate substrate preparation technology and the ferroelectric SOI double-gate CMOS device structure of the present disclosure have the advantages of low power consumption, high operation speed, high reliability, and being conducive to heterogeneous integration and stacked packaging. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1A schematic diagram of a ferroelectric device is illustratively shown in accordance with an embodiment of the present disclosure.

[0020] Figure 2 A flowchart of a method of fabricating a ferroelectric device is illustratively shown in accordance with an embodiment of the present disclosure.

[0021] Figure 3 A schematic diagram of etching a hard mask is illustratively shown in accordance with an embodiment of the present disclosure.

[0022] Figure 4 A schematic diagram of etching a substrate layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0023] Figure 5 A schematic diagram of depositing a gate material in an etched region is illustratively shown in accordance with an embodiment of the present disclosure.

[0024] Figure 6 A schematic diagram of depositing a titanium nitride layer on a surface of a ferroelectric layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0025] Figure 7 A schematic diagram of a ferroelectric layer after removing a titanium nitride layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0026] Figure 8 A schematic diagram of a silicon material after depositing a silicon dioxide layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0027] Figure 9 A schematic diagram of implanting a hydrogen element into a silicon material is illustratively shown in accordance with an embodiment of the present disclosure.

[0028] Figure 10 A schematic diagram of a silicon material after implanting a hydrogen element is illustratively shown in accordance with an embodiment of the present disclosure.

[0029] Figure 11 A schematic diagram of cleaving a silicon material is illustratively shown in accordance with an embodiment of the present disclosure.

[0030] Figure 12 A schematic diagram of depositing a first device isolation layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0031] Figure 13 A schematic diagram of growing an alternating deposition layer is illustratively shown in accordance with an embodiment of the present disclosure.

[0032] Figure 14 A schematic diagram of etching a patterned structure is illustratively shown in accordance with an embodiment of the present disclosure.

[0033] Figure 15 A schematic diagram of growing a germanosilicon is illustratively shown in accordance with an embodiment of the present disclosure.

[0034] Figure 16 A schematic diagram illustrating preparation of a source layer and a drain layer according to embodiments of the present disclosure is shown schematically.

[0035] Figure 17 A schematic diagram illustrating thinning of a patterned structure according to embodiments of the present disclosure is shown schematically.

[0036] Figure 18 A schematic diagram illustrating deposition of a second device isolation layer according to embodiments of the present disclosure is shown schematically.

[0037] Figure 19 A schematic diagram illustrating preparation of a source terminal electrode and a drain terminal electrode according to embodiments of the present disclosure is shown schematically.

[0038] Figure 20 A schematic diagram illustrating preparation of a bottom gate electrode according to embodiments of the present disclosure is shown schematically. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, the drawings are designed for a description only, and are not intended to limit the scope of the present disclosure. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and

[0040] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present disclosure. The terms "include" and "have" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0041] All terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present description, and should not be interpreted in an idealized or excessively formal manner.

[0042] In the case of using expressions similar to "at least one of A, B, and C, etc.", it is generally construed that the meaning is interpreted as including one or plural of the relevant items, unless otherwise specifically defined (e.g., "a system having at least one of A, B, and C" should be construed to include one system having A alone, one system having B alone, one system having C alone, one system having 2 of A and B, one system having 2 of A and C, one system having 2 of B and C, and / or one system having all of A, B, and C, etc.).

[0043] This disclosure proposes a ferroelectric SOI (Silicon On Insulator) dual-gate CMOS (Complementary Metal Oxide Semiconductor) device structure. By using a FE BOX layer instead of a SiO2 BOX layer, the above-mentioned problems can be effectively alleviated.

[0044] Figure 1 A schematic diagram of a ferroelectric device according to an embodiment of the present disclosure is shown.

[0045] like Figure 1 As shown, the ferroelectric device in this embodiment includes: a substrate layer 1, a channel layer 2, a first device isolation layer 3, a stop layer 4, a second device isolation layer 5, a bottom gate electrode Gb, a ferroelectric layer FE BOX, a source electrode S, a drain electrode D, and a top gate electrode Gt. For example, in the accompanying drawings of embodiments of this disclosure, different colors may be used to indicate the materials corresponding to different structures.

[0046] For example, the bottom gate electrode Gb is located within substrate layer 1. The material of substrate layer 1 can be silicon, etc. Figure 1 The structure formed of silicon can be shown in blue. For example, the bottom gate electrode Gb includes a first bottom gate electrode and a second bottom gate electrode. The electrode materials of the first bottom gate electrode and the second bottom gate electrode are different. For example, the electrode material of the first bottom gate electrode includes silicon nitride, tungsten, and titanium nitride, etc. The electrode material of the second bottom gate electrode includes silicon nitride, tungsten, and titanium aluminide, etc. Figure 1 In the diagram, structures formed of silicon nitride may be shown in red, structures formed of tungsten may be shown in black, structures formed of titanium nitride may be shown in yellow, and structures formed of titanium aluminide may be shown in gray.

[0047] The ferroelectric layer FE BOX is located inside the ferroelectric device. The lower surface of the ferroelectric layer FE BOX is in contact with the bottom gate electrode Gb. For example, the ferroelectric layer FE BOX includes a first ferroelectric layer and a second ferroelectric layer. For example, the lower surface of the first ferroelectric layer is in contact with the first bottom gate electrode. The lower surface of the second ferroelectric layer is in contact with the second bottom gate electrode.

[0048] For example, the materials of the first and second ferroelectric layers are the same, and both materials include hafnium dioxide doped with a target element, which includes at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium. It should be noted that the appropriate doping ratio of the target element and the ferroelectric crystallization temperature can be selected according to requirements, and this disclosure does not limit this. Figure 1 In the diagram, the structure formed by doping hafnium dioxide with the target element can be shown in purple.

[0049] The first device isolation layer 3 surrounds the ferroelectric layer FE BOX. The material of the first device isolation layer 3 can be silicon dioxide or the like. In Figure 1 The structure formed of silicon dioxide in the middle can be shown in green. For example, the first device isolation layer 3 surrounds the first ferroelectric layer and the second ferroelectric layer, respectively.

[0050] The channel layer 2 contacts the upper surface of the ferroelectric layer FE BOX. The material of the channel layer 2 can be silicon or germanium or the like. For example, the channel layer 2 includes a first channel layer and a second channel layer. The upper surface of the first ferroelectric layer contacts the first channel layer. The upper surface of the second ferroelectric layer contacts the second channel layer.

[0051] The source electrode S, the drain electrode D and the top gate electrode Gt all contact the upper surface of the channel layer 2. For example, the source electrode S includes a first source electrode and a second source electrode, and the drain electrode D includes a first drain electrode and a second drain electrode. For example, the material of the source electrode S and the material of the drain electrode D both include tungsten and titanium nitride or the like.

[0052] The top gate electrode Gt includes a first top gate electrode and a second top gate electrode. The electrode material of the first top gate electrode is different from that of the second top gate electrode. For example, the electrode material of the first top gate electrode includes hafnium dioxide, titanium nitride and tungsten or the like. The electrode material of the second top gate electrode includes hafnium dioxide, titanium aluminum and tungsten or the like.

[0053] For example, the upper surface of the first channel layer contacts the first source electrode, the first drain electrode and the first top gate electrode, and the first top gate electrode is located between the first source electrode and the first drain electrode.

[0054] The upper surface of the second channel layer contacts the second source electrode, the second drain electrode and the second top gate electrode, and the second top gate electrode is located between the second source electrode and the second drain electrode.

[0055] The second device isolation layer 5 is located between the source electrode, the drain electrode and the top gate electrode. For example, the material of the second device isolation layer 5 includes silicon dioxide and the like. For example, the second device isolation layer 5 can be located between the first source electrode, the second source electrode, the first drain electrode, the second drain electrode, the first top gate electrode and the second top gate electrode. For example, the second device isolation layer 5 can be used to electrically isolate the device layer of the ferroelectric device from the metal wiring located on the surface of the ferroelectric device. For example, the method for preparing the first device isolation layer 3 can include but is not limited to STI (Shallow Trench Isolation) technology, LOCOS (Local Oxidation of Silicon) technology and the like. The method for preparing the second device isolation layer 5 can include PVD (Physical Vapor Deposition) technology and the like.

[0056] The stop layer 4 is located between the first device isolation layer 3 and the second device isolation layer 5, and surrounds the source electrode, the drain electrode and the top gate electrode. For example, the material of the stop layer 4 can be silicon nitride and the like.

[0057] Based on this, the above-mentioned first source electrode, the first drain electrode, the first top gate electrode, the first ferroelectric layer and the first bottom gate electrode can constitute a first transistor. The above-mentioned second source electrode, the second drain electrode, the second top gate electrode, the second ferroelectric layer and the second bottom gate electrode can constitute a second transistor. For example, one of the first transistor and the second transistor can be an N-type transistor, and the other can be a P-type transistor. For example, the first device isolation layer 3 can be used to electrically isolate the first transistor and the second transistor.

[0058] According to the embodiments of the present disclosure, the present disclosure directly ferroelectricizes the BOX layer by combining the process of the SOI wafer to obtain the ferroelectric layer FE BOX, and uses the method of pre-embedding the bottom gate layer to realize device separation. In this way, the top layer device can be used as a logic operation unit, and the bottom layer device can be used as a data storage unit, so that the top layer device and the bottom layer device share the channel and the source and drain. Among them, the top layer device can include a top gate electrode Gt and the like located above the channel layer 2, and the bottom layer device can include a bottom gate electrode Gb and the like located below the channel layer 2.

[0059] Based on this, by separating the gate into the top gate electrode Gt and the bottom gate electrode Gb, different ranges of bias voltages can be applied to the top gate electrode Gt and the bottom gate electrode Gb respectively, reducing the damage to the gate oxide of the top gate electrode Gt caused by repeatedly applying a large bias voltage. Moreover, the ferroelectric layer FE BOX no longer follows the size shrinkage of the top layer logic device, ensuring the operation speed of the logic and the reliability of the ferroelectric storage. At the same time, before the device is prepared, the ferroelectric layer FE BOX has been completely crystallized, the metal layer that most affects the ferroelectric phase is removed, and a higher temperature is required to convert into a non-ferroelectric phase. Thus, the thermal budget of ferroelectric crystallization and source-drain activation can be expanded without interfering with each other, expanding the selection of ferroelectric materials and source-drain processes.

[0060] Based on this, the ferroelectric SOI pre-buried gate substrate preparation technology and the ferroelectric SOI double-gate CMOS device structure of the present application have the advantages of low power consumption, high operation speed, high reliability, and being conducive to heterogeneous integration, stacked packaging, etc.

[0061] In order to better understand the content of the present disclosure, the content of the present disclosure is further described in combination with the preparation method of the ferroelectric device of the embodiments of the present disclosure. It should be noted that the labels in the Figures 2-20 of the embodiments of the present disclosure are the same as the above Figure 1 , which will not be repeated here.

[0062] Figure 2 The preparation method of the ferroelectric device according to the embodiments of the present disclosure is schematically shown.

[0063] As shown in Figure 2 , the preparation method of the ferroelectric device of this embodiment includes operations S210-S270.

[0064] In operation S210, the upper surface of the substrate layer 1 is etched according to a predetermined pattern to obtain a patterned substrate layer 1, wherein the patterned substrate layer 1 includes an etching region corresponding to the predetermined pattern.

[0065] According to the embodiments of the present disclosure, as Figure 3 and Figure 4As shown, a hard mask can be formed on the upper surface of the substrate layer 1. Deep hole etching is performed on the substrate layer 1 covered by the hard mask according to a predetermined pattern to obtain a patterned substrate layer 1. In this way, by means of the hard mask, etching to other areas can be avoided when deep hole etching is performed. For example, a silicon dioxide layer and a silicon nitride layer can be sequentially deposited on the upper surface of the substrate layer 1, and photolithography is performed on the silicon dioxide layer and the silicon nitride layer according to a predetermined pattern to obtain a silicon dioxide layer corresponding to the predetermined pattern and a silicon nitride layer corresponding to the predetermined pattern. Both the silicon dioxide layer corresponding to the predetermined pattern and the silicon nitride layer corresponding to the predetermined pattern include etching areas corresponding to the predetermined pattern. Based on this, deep hole etching can be performed on the etching areas to obtain a patterned substrate layer 1. It should be noted that, in the embodiment, the hard mask is formed on the upper surface of the substrate layer 1. Alternatively, the hard mask can be formed on the lower surface of the substrate layer 1. Figure 4 In the embodiment, the first etching area and the second etching area are indicated by black arrows to show the positions of the first etching area and the second etching area on the substrate layer 1.

[0066] In operation S220, a gate material is deposited in the etching area to obtain a substrate layer 1 including a bottom gate layer 6.

[0067] According to an embodiment of the present disclosure, the gate material can include silicon nitride, tungsten, and titanium nitride. In this way, by depositing the gate material, the bottom gate layer 6 located in the substrate layer 1 can be obtained.

[0068] In operation S230, a ferroelectric material is deposited on the bottom gate layer 6 to form a ferroelectric layer FE BOX in contact with the bottom gate layer 6.

[0069] In operation S240, an isolation layer material is deposited on the substrate layer 1 to form a first device isolation layer 3 surrounding the ferroelectric layer FE BOX.

[0070] In operation S250, a channel layer 2, a stop layer 4, a top gate electrode Gt, a source electrode S, a drain electrode D, and a second device isolation layer 5 for isolating the top gate electrode Gt, the source electrode S, and the drain electrode D are prepared on the ferroelectric layer FE BOX.

[0071] In operation S260, the bottom gate layer 6 is exposed to the lower surface of the substrate layer 1 by thinning the substrate layer 1.

[0072] In operation S270, a bottom gate electrode Gb is formed based on the bottom gate layer material exposed to the lower surface of the substrate layer 1 to obtain a ferroelectric device.

[0073] According to an embodiment of the present disclosure, titanium nitride can be deposited on the surface exposed by the bottom gate layer 6 to obtain the bottom gate electrode Gb.

[0074] According to the embodiments of the present disclosure, the BOX layer is directly ferroelectricized to obtain a ferroelectric layer FE BOX in combination with the process of the SOI wafer, and the device separation is realized by using the method of pre-embedding the bottom gate layer 6. Thus, the top layer device can be used as a logic operation unit, and the bottom layer device can be used as a data storage unit, so that the top layer device and the bottom layer device share the channel and the source and drain. The top layer device can include a top gate electrode Gt and the like located above the channel layer 2, and the bottom layer device can include a bottom gate electrode Gb and the like located below the channel layer 2.

[0075] Based on this, by separating the gate into the top gate electrode Gt and the bottom gate electrode Gb, different ranges of bias voltages can be applied to the top gate electrode Gt and the bottom gate electrode Gb respectively, reducing the damage of repeatedly applying a large bias voltage to the gate oxide of the top gate electrode Gt. Moreover, the ferroelectric layer FE BOX no longer follows the size shrinkage of the top layer logic device, ensuring the operation speed of the logic and the reliability of the ferroelectric storage. At the same time, before the device is prepared, the ferroelectric layer FE BOX has been completely crystallized, the metal layer which greatly affects the ferroelectric phase is removed, and a higher temperature is required for the transition to a non-ferroelectric phase. Thus, the thermal budget of ferroelectric crystallization and source and drain activation can be realized without interfering with each other, expanding the selection of ferroelectric materials and source and drain processes.

[0076] Based on this, the ferroelectric SOI pre-embedded gate substrate preparation technology and the ferroelectric SOI double-gate CMOS device structure of the present application have the advantages of low power consumption, high operation speed, high reliability, and being conducive to heterogeneous integration, stacked packaging and the like.

[0077] According to the embodiments of the present disclosure, the etching region includes a first etching region and a second etching region. In the etching region, the substrate layer 1 including the bottom gate layer 6 is obtained by depositing a gate material, including: in the first etching region, sequentially depositing silicon nitride, tungsten and titanium nitride to form a first bottom gate layer, and in the second etching region, sequentially depositing silicon nitride, tungsten and titanium nitride to form a second bottom gate layer, to obtain the substrate layer 1 including the bottom gate layer 6.

[0078] According to the embodiments of the present disclosure, as Figure 5As shown, silicon nitride, tungsten and titanium nitride can be sequentially deposited on the substrate layer 1 including the first etching area and the second etching area. Then, the photoresist is used as a mask to protect the area on the upper surface of the substrate layer 1 except the second etching area, and the titanium nitride in the second etching area is etched away by wet etching. Then, the photoresist on the upper surface of the substrate layer 1 is removed, and titanium aluminide is deposited on the upper surface of the substrate layer 1 so as to deposit the titanium aluminide in the second etching area. Then, the CMP (Chemical-Mechanical Planarization) technology is used to polish the upper surface of the substrate layer 1 to remove the silicon nitride, tungsten, titanium nitride and titanium aluminide on the upper surface of the substrate layer 1, and to keep the materials in the etching area. In this way, the preparation of the first bottom gate layer and the second bottom gate layer can be completed.

[0079] According to an embodiment of the present disclosure, as shown in Figure 6 and Figure 7 As shown, the ferroelectric material is deposited on the bottom gate layer 6 to form the ferroelectric layer FE BOX in contact with the bottom gate layer 6, including: sequentially depositing the ferroelectric material and titanium nitride on the bottom gate layer 6 to obtain the substrate layer 1 covering the ferroelectric material and the titanium nitride. The substrate layer 1 covering the ferroelectric material and the titanium nitride is subjected to ferroelectric annealing to obtain the annealed substrate layer 1, wherein the annealing temperature of the ferroelectric annealing corresponds to the material type of the ferroelectric material. The titanium nitride on the surface of the annealed substrate layer 1 is removed to obtain the ferroelectric layer FE BOX.

[0080] According to an embodiment of the present disclosure, by depositing titanium nitride first and then annealing the ferroelectric layer FE BOX to activate the ferroelectric layer FE BOX, the ferroelectric phase can be maintained during the annealing process, thereby ensuring that the performance of the ferroelectric layer FE BOX meets the requirements.

[0081] According to an embodiment of the present disclosure, the type of ferroelectric material is different, and the annealing temperature of the ferroelectric annealing is different. Based on this, the annealing temperature corresponding to the ferroelectric material can be selected for annealing according to different types of ferroelectric materials.

[0082] According to an embodiment of the present disclosure, on the substrate layer 1, the first device isolation layer 3 surrounding the ferroelectric layer FE BOX is formed by depositing an isolation layer material, including: bonding the surface of the ferroelectric layer FE BOX and the surface of the silicon material 7 implanted with hydrogen ions, and pre-bonding the ferroelectric layer FE BOX and the silicon material 7, so that the silicon material 7 is fixed on the surface of the ferroelectric layer FE BOX. The silicon material 7 fixed on the surface of the ferroelectric layer FE BOX is thinned to obtain a silicon layer 72 located on the surface of the ferroelectric layer FE BOX. The silicon layer 72 and the ferroelectric layer FE BOX are etched according to a pattern corresponding to the position of the bottom gate layer 6 to obtain a patterned ferroelectric layer FE BOX and a patterned silicon layer 72. Silicon dioxide is deposited on the substrate layer 1 to surround the patterned ferroelectric layer FE BOX and the patterned silicon layer 72 to obtain the first device isolation layer 3.

[0083] According to an embodiment of the present disclosure, as shown in Figures 8-10 , the silicon dioxide layer can be thermally grown on the upper surface of the silicon material 7, and then the silicon dioxide layer is implanted with hydrogen ions, so that the damage caused by the hydrogen ion implantation to the silicon material 7 is alleviated by the silicon dioxide layer. After the hydrogen ion implantation is completed, the silicon dioxide layer can be removed to obtain the silicon material 7 implanted with hydrogen ions.

[0084] Based on this, as shown in Figure 11 , the upper surface of the ferroelectric layer FE BOX and the upper surface of the silicon material 7 can be bonded, and the bonded ferroelectric layer FE BOX and silicon material 7 are high-temperature annealed to pre-bond, so that the silicon material 7 is fixed on the surface of the ferroelectric layer FE BOX.

[0085] During high-temperature annealing, hydrogen microbubbles are formed in the silicon material 7, so that the internal structure of the silicon material 7 becomes loose. Therefore, the silicon material 7 can be thinned by splitting the silicon material 7 to obtain a silicon structure 71 and a silicon layer 72 located on the surface of the ferroelectric layer FE BOX. In some embodiments, the silicon layer 72 located on the surface of the ferroelectric layer FE BOX can be further polished to make the thickness of the silicon layer 72 meet the requirements.

[0086] According to an embodiment of the present disclosure, the silicon layer 72 and the ferroelectric layer FE BOX can be etched according to a pattern corresponding to the position of the bottom gate layer 6 to obtain a patterned ferroelectric layer FE BOX and a patterned silicon layer 72. For example, the patterned ferroelectric layer FE BOX can include a first ferroelectric layer and a second ferroelectric layer. The patterned silicon layer 72 can include a first silicon layer and a second silicon layer. The upper surface of the first ferroelectric layer can be covered with the first silicon layer. The upper surface of the second ferroelectric layer can be covered with the second silicon layer.

[0087] As shown in Figure 12As shown, silicon dioxide surrounding the first ferroelectric layer, the second ferroelectric layer, the first silicon layer and the second silicon layer can be deposited on the substrate layer 1 to obtain a first device isolation layer 3. In this way, isolation between the first ferroelectric layer and the second ferroelectric layer can be achieved, and isolation between the first silicon layer and the second silicon layer can be achieved, and the first ferroelectric layer can be made to be in contact with only the first bottom gate layer so as to be electrically connected between the first ferroelectric layer and the first bottom gate layer, and the second ferroelectric layer can be made to be in contact with only the second bottom gate layer so as to be electrically connected between the second ferroelectric layer and the second bottom gate layer.

[0088] According to embodiments of the present disclosure, as shown in FIG. 1, a first ferroelectric layer 1, a second ferroelectric layer 2, a first silicon layer 71 and a second silicon layer 72 can be sequentially deposited on a substrate layer 1. The first ferroelectric layer 1 and the second ferroelectric layer 2 can be formed of the same material, and the first silicon layer 71 and the second silicon layer 72 can be formed of the same material. The first ferroelectric layer 1 and the second ferroelectric layer 2 can be formed of a material having a ferroelectric property, such as hafnium oxide, hafnium zirconium oxide, lead zirconium titanate, barium titanate, bismuth ferrite, bismuth titanate, or the like. The first silicon layer 71 and the second silicon layer 72 can be formed of a material such as silicon, germanium, or the like. The substrate layer 1 can be formed of a material such as silicon, germanium, or the like. Figures 13-20 As shown in FIG. 1, a channel layer 2, a stop layer 4, a top gate electrode Gt, a source electrode S and a drain electrode D, and a second device isolation layer 5 for isolating the top gate electrode Gt, the source electrode S and the drain electrode D are prepared on the ferroelectric layer FE BOX, including: sequentially depositing silicon dioxide, polysilicon, silicon dioxide, silicon nitride and silicon dioxide on a surface of the silicon layer 72 to obtain an alternating deposition layer. The alternating deposition layer is etched according to a pattern corresponding to the position of the silicon layer 72 to obtain a patterned structure on the silicon layer 72. A sidewall surrounding the patterned structure is grown using silicon nitride. A silicon germanium layer surrounding the sidewall is deposited on the surface of the silicon layer 72. For example, in the drawings of embodiments of the present disclosure, the structure formed of silicon germanium can be shown in a light blue color lighter than the above-mentioned blue color corresponding to silicon. The silicon germanium layer is ion implanted to form a source layer 91 and a drain layer 92 on the surface of the silicon layer 72. The source layer 91 and the drain layer 92 are annealed to obtain an annealed source layer 91 and an annealed drain layer 92. Silicon nitride is deposited on the annealed source layer 91, the annealed drain layer 92 and the first device isolation layer 3 to form the stop layer 4. The patterned structure is thinned according to the thickness of the stop layer 4 to obtain a thinned patterned structure, wherein the thinned patterned structure includes a silicon dioxide structure and a polysilicon structure. For example, in the drawings of embodiments of the present disclosure, the structure formed of polysilicon can be shown in brown. The silicon dioxide and the polysilicon inside the silicon dioxide structure are wet etched according to a pattern corresponding to the position of the polysilicon inside the silicon dioxide structure until the channel layer 2 is exposed. The gate material is deposited on the surface of the channel layer 2 inside the silicon dioxide structure to obtain the top gate electrode Gt. Silicon dioxide is deposited on the top gate electrode Gt and the stop layer 4, and the silicon dioxide and the stop layer 4 are etched according to a pattern corresponding to the position of the source layer 91 and the drain layer 92 until the source layer 91 and the drain layer 92 are exposed to form the second device isolation layer 5. Titanium nitride, tungsten and titanium nitride are sequentially deposited on the source layer 91 and the drain layer 92 to obtain the source electrode S and the drain electrode D.

[0089] According to an embodiment of the present disclosure, the alternating deposition layers are etched in a pattern corresponding to the positions of the silicon layers 72 to obtain a patterned structure on the silicon layers 72. For example, the patterned structure can include a first patterned structure and a second patterned structure, the first patterned structure being in contact with only the first silicon layer, and the second patterned structure being in contact with only the second silicon layer. The first patterned structure and the second patterned structure are not in contact with each other.

[0090] Silicon nitride can be used to grow a sidewall around the patterned structure. After the sidewall is grown, the sidewall can be etched so that the area of the patterned structure surrounded by the sidewall is smaller than the area of the silicon layer 72. For example, silicon nitride can be used to grow a sidewall around the first patterned structure and a sidewall around the second patterned structure. The sidewalls can be etched so that the area of the first patterned structure surrounded by the sidewall is smaller than the area of the first silicon layer, and the area of the second patterned structure surrounded by the sidewall is smaller than the area of the second silicon layer.

[0091] Silicon germanium layers can be deposited on the upper surfaces of the first silicon layer and the second silicon layer, respectively, around the sidewalls.

[0092] An LDD (Lightly Doped Drain) implantation is performed on the silicon germanium layers, and then silicon nitride is used to grow sidewalls around the sidewalls, and S / D (Source / Drain) ion implantation is performed to form source layers 91 and drain layers 92 on the upper surfaces of the first silicon layer and the second silicon layer, respectively. The ion doping degree of the source layers 91 and the drain layers 92 on the upper surface of the first silicon layer can be different from the ion doping degree of the source layers 91 and the drain layers 92 on the upper surface of the second silicon layer.

[0093] Annealing can be performed on the source layers 91 and the drain layers 92 to activate impurities and repair damage in the source layers 91 and the drain layers 92, to obtain annealed source layers 91 and annealed drain layers 92.

[0094] Based on this, the annealed source layers 91 and the annealed drain layers 92 can be subjected to a Silicide process to adjust the contact barrier of the source layers 91 and the drain layers 92 and reduce the source-drain contact resistance. For example, the Silicide process can include depositing nickel platinum (NiPt) and annealing the deposited source layers 91 and drain layers 92 to form SiNi (silicon nickel compound) and the like.

[0095] According to an embodiment of the present disclosure, silicon nitride is deposited on the annealed source layer 91, the annealed drain layer 92 and the first device isolation layer 3 to form a stop layer 4. A silicon dioxide layer can be further deposited on the stop layer 4, and then the patterned structure and the silicon dioxide layer are thinned according to the thickness of the stop layer 4 to obtain a thinned patterned structure surrounded by the stop layer 4. The thinned patterned structure includes a silicon dioxide structure and a polysilicon structure. It can be understood that in actual wafer processes, the formed structure can have uneven parts, and thus by depositing a silicon dioxide layer and then removing the entire silicon dioxide layer and part of the stop layer 4, the stress can be weakened.

[0096] The silicon dioxide and the polysilicon located inside the first silicon dioxide structure can be wet-etched with high selectivity according to a pattern corresponding to the position of the polysilicon located inside the first silicon dioxide structure to remove the silicon dioxide and the polysilicon located inside the first silicon dioxide structure until the channel layer 2 is exposed. In addition, the silicon dioxide and the polysilicon located inside the second silicon dioxide structure can be wet-etched according to a pattern corresponding to the position of the polysilicon located inside the second silicon dioxide structure to remove the silicon dioxide and the polysilicon located inside the second silicon dioxide structure until the channel layer 2 is exposed.

[0097] According to an embodiment of the present disclosure, a gate material is deposited on the surface of the channel layer 2 located inside the silicon dioxide structure to obtain a top gate electrode Gt, including: using ozone to oxidize the surface of the channel layer 2 located inside the silicon dioxide structure to form a silicon oxide layer. The silicon oxide layer is a gate oxide layer. The gate material is deposited on the surface of the silicon oxide layer to obtain the top gate electrode Gt.

[0098] For example, hafnium dioxide, titanium nitride and tungsten can be sequentially deposited on the stop layer 4 to sequentially deposit hafnium dioxide, titanium nitride and tungsten inside the first silicon dioxide structure. After the deposition is completed, the hafnium dioxide, titanium nitride and tungsten located on the surface of the stop layer 4 can be patterned and etched to obtain a first top gate electrode. In addition, hafnium dioxide, titanium aluminum and tungsten can be sequentially deposited on the stop layer 4 to sequentially deposit hafnium dioxide, titanium aluminum and tungsten inside the second silicon dioxide structure. After the deposition is completed, the hafnium dioxide, titanium aluminum and tungsten located on the surface of the stop layer 4 can be patterned and etched to obtain a second top gate electrode.

[0099] On the top gate electrode Gt and the stop layer 4, silicon dioxide is deposited, and the silicon dioxide and the stop layer 4 are etched according to a pattern corresponding to the positions of the source electrode layer 91 and the drain electrode layer 92 until the source electrode layer 91 and the drain electrode layer 92 are exposed, to form a second device isolation layer 5. Based on this, titanium nitride and tungsten can be sequentially deposited on the second device isolation layer 5, so that the source electrode layer 91 and the drain electrode layer 92 sequentially deposit titanium nitride and tungsten. After the deposition is completed, the titanium nitride and tungsten located on the surface of the second device isolation layer 5 can be removed using the CMP technology. Based on this, a titanium nitride layer can be re-deposited on the upper surface of the second device isolation layer 5, and the titanium nitride layer is patterned and etched according to a pattern corresponding to the positions of the source electrode layer 91 and the drain electrode layer 92, to obtain a patterned titanium nitride. In this way, the preparation of the source electrode S and the drain electrode D is completed.

[0100] After the preparation of the source electrode S and the drain electrode D is completed, the substrate layer 1 can be thinned to expose the bottom gate layer 6 to the lower surface of the substrate layer 1. Then, a titanium nitride layer is deposited on the surface exposed by the bottom gate layer 6. The titanium nitride layer can be patterned and etched according to a pattern corresponding to the bottom gate layer 6, to obtain a patterned titanium nitride layer. In this way, the preparation of the bottom gate electrode Gb is completed. Based on this, the preparation of the ferroelectric device of the present disclosure is realized.

[0101] It should be noted that the device preparation process includes Gate First (front gate) and Gate Last (back gate) technologies, and the embodiments of the present disclosure mainly elaborate on the back gate process, but in practice, the process used can be adjusted according to actual needs, which is not limited by the present disclosure.

[0102] The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the text are known to those skilled in the art, and are not described in detail. In addition, the definitions of the elements and methods described above are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and can be simply changed or replaced by those skilled in the art.

[0103] Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in understanding the present disclosure, conventional structures or configurations will be omitted.

[0104] And the shape and size of each component in the figure do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure. In addition, in the claims, any reference symbol located between parentheses should not be construed as a limitation on the claims.

[0105] Unless otherwise indicated herein, the numerical parameters in this description and the accompanying claims are approximations. Although the numerical parameters are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values in some instances can have been obtained with a degree of error not exceeding 0.1 %.

[0106] The use of the terms "first", "second", "third", etc. to describe a component having a particular numerical designation does not imply any order of these components with respect to one another but is used merely as a label to distinguish one component from another. Consequently, "first", "second", "third", etc. can be understood as a non- limiting label of a certain component, and does not necessarily mean that this component has a certain order with respect to another component or a certain order in a manufacturing process.

[0107] The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the present disclosure is not intended to be limited to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein, and any references below to specific languages are provided for disclosure of enablement of the best mode of the disclosure.

[0108] The present disclosure can be implemented with the help of hardware comprising several different elements and with the help of a suitably programmed computer. The various component embodiments of the present disclosure can be implemented in hardware, or as software modules running in one or more processors, or combinations thereof. Those skilled in the art will appreciate that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functionality of some or all of the components in the related devices according to the embodiments of the present disclosure. The present disclosure can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for performing part or all of the methods described herein. Such a program implementing the present disclosure can be stored on a computer readable medium or can be in the form of one or more signals.

[0109] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all combinations of all features disclosed in this specification (including accompanying claims, abstract and drawings) and all processes or units of any methods or apparatuses so disclosed can be adopted in any combination. Unless explicitly stated otherwise, each feature disclosed in this specification (including accompanying claims, abstract and drawings) can be replaced by alternative features providing the same, equivalent, or similar functionality. And in unitary claim recitations of a plurality of apparatuses, several of the apparatuses can be embodied by one and the same hardware item with non-coinciding functions.

[0110] Similarly, it is to be understood that the embodiments of the present disclosure described above and illustrated in the drawings are by way of example only, and are not intended to limit the various aspects of the disclosure in their full scope. In order to facilitate an understanding of one or more aspects of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, a figure, or described in a description of one or more embodiments. However, the disclosure should not be construed as reflecting a necessity to

[0111] The specific embodiments described above are further intended to address the purposes, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above description is merely specific embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A ferroelectric device, comprising: Substrate layer; The bottom gate electrode is located within the substrate layer; A ferroelectric layer is located inside the ferroelectric device, and the lower surface of the ferroelectric layer is in contact with the bottom gate electrode. A first device isolation layer surrounds the ferroelectric layer; The channel layer is in contact with the upper surface of the ferroelectric layer; The source electrode, drain electrode, and top gate electrode are all in contact with the upper surface of the channel layer, including: the source layer of the source electrode is formed on the upper surface of the ferroelectric layer and is in contact with one sidewall and the upper surface of the channel layer; the drain layer of the drain electrode is formed on the upper surface of the ferroelectric layer and is in contact with the other sidewall and the upper surface of the channel layer; the top gate electrode is formed on the upper surface of the channel layer; wherein, when a bias voltage is applied to the top gate electrode, the top gate electrode, the source electrode, the drain electrode, and the channel layer together serve as a logic operation unit; when a bias voltage is applied to the bottom gate electrode, the bottom gate electrode, the source electrode, the drain electrode, and the channel layer together serve as a data storage unit; A second device isolation layer is located between the source electrode, the drain electrode, and the top gate electrode; A stop layer is located between the first device isolation layer and the second device isolation layer, and surrounds the source electrode, the drain electrode and the top gate electrode.

2. The device according to claim 1, wherein, The ferroelectric layer includes a first ferroelectric layer and a second ferroelectric layer, and the first device isolation layer surrounds the first ferroelectric layer and the second ferroelectric layer respectively.

3. The device according to claim 2, wherein, The channel layer includes a first channel layer and a second channel layer; the source electrode includes a first source electrode and a second source electrode; the drain electrode includes a first drain electrode and a second drain electrode; the top gate electrode includes a first top gate electrode and a second top gate electrode; the bottom gate electrode includes a first bottom gate electrode and a second bottom gate electrode; the electrode materials of the first top gate electrode and the second top gate electrode are different; the electrode materials of the first bottom gate electrode and the second bottom gate electrode are different. Wherein, the lower surface of the first ferroelectric layer is in contact with the first bottom gate electrode, the upper surface of the first ferroelectric layer is in contact with the first channel layer, the upper surface of the first channel layer is in contact with the first source electrode, the first drain electrode and the first top gate electrode, and the first top gate electrode is located between the first source electrode and the first drain electrode. The lower surface of the second ferroelectric layer is in contact with the second bottom gate electrode, the upper surface of the second ferroelectric layer is in contact with the second channel layer, the upper surface of the second channel layer is in contact with the second source electrode, the second drain electrode and the second top gate electrode, and the second top gate electrode is located between the second source electrode and the second drain electrode.

4. The device according to claim 3, wherein, The first ferroelectric layer is made of the same material as the second ferroelectric layer. Both the first and second ferroelectric layers contain hafnium dioxide doped with a target element, which includes at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium. The electrode materials of the first top gate electrode include hafnium dioxide, titanium nitride, and tungsten; The electrode materials of the second top gate electrode include hafnium dioxide, titanium aluminide, and tungsten; The electrode materials of the first bottom gate electrode include silicon nitride, tungsten, and titanium nitride; The electrode materials of the second bottom gate electrode include silicon nitride, tungsten, and titanium aluminide; The materials of both the source electrode and the drain electrode include tungsten and titanium nitride.

5. A method for fabricating a ferroelectric device, comprising: According to a predetermined pattern, the upper surface of the substrate is etched to obtain a patterned substrate, wherein the patterned substrate includes an etched area corresponding to the predetermined pattern; Within the etched area, a substrate layer including a bottom gate layer is obtained by depositing gate material; Ferroelectric material is deposited on the bottom gate layer to form a ferroelectric layer in contact with the bottom gate layer; An isolation layer material is deposited on the substrate to form a first device isolation layer surrounding the ferroelectric layer; A channel layer, a stop layer, a top gate electrode, a source electrode, and a drain electrode are fabricated on the ferroelectric layer, along with a second device isolation layer for isolating the top gate electrode, the source electrode, and the drain electrode. The source electrode has a source layer formed on the upper surface of the ferroelectric layer and contacts one sidewall and the upper surface of the channel layer. The drain electrode has a drain layer formed on the upper surface of the ferroelectric layer and contacts the other sidewall and the upper surface of the channel layer. The top gate electrode is formed on the upper surface of the channel layer. By thinning the substrate layer, the bottom gate layer is exposed on the lower surface of the substrate layer; A bottom gate electrode is formed based on the bottom gate layer material exposed on the lower surface of the substrate layer to obtain the ferroelectric device; Specifically, when a bias voltage is applied to the top gate electrode, the top gate electrode, the source electrode, the drain electrode, and the channel layer are used together as a logic operation unit; when a bias voltage is applied to the bottom gate electrode, the bottom gate electrode, the source electrode, the drain electrode, and the channel layer are used together as a data storage unit.

6. The method according to claim 5, wherein, The deposition of an isolation layer material on the substrate to form a first device isolation layer surrounding the ferroelectric layer includes: The surface of the ferroelectric layer and the surface of the silicon material implanted with hydrogen ions are bonded together, and the ferroelectric layer and the silicon material are pre-bonded to fix the silicon material on the surface of the ferroelectric layer. The silicon material fixed on the surface of the ferroelectric layer is thinned to obtain a silicon layer located on the surface of the ferroelectric layer. The silicon layer and the ferroelectric layer are etched according to the pattern corresponding to the position of the bottom gate layer to obtain the patterned ferroelectric layer and the patterned silicon layer. Silicon dioxide is deposited on the substrate layer surrounding the patterned ferroelectric layer and the patterned silicon layer to obtain a first device isolation layer.

7. The method according to claim 6, wherein, The fabrication of a channel layer, a stop layer, a top gate electrode, a source electrode, and a drain electrode on the ferroelectric layer, as well as a second device isolation layer for isolating the top gate electrode, the source electrode, and the drain electrode, includes: Silicon dioxide, polycrystalline silicon, silicon dioxide, silicon nitride, and silicon dioxide are sequentially deposited on the surface of the silicon layer to obtain alternating deposition layers; The alternating deposition layers are etched according to a pattern corresponding to the position of the silicon layer to obtain a patterned structure on the silicon layer. The sidewalls surrounding the patterned structure are grown using silicon nitride. On the surface of the silicon layer, a silicon germanium layer is deposited around the sidewalls; Ion implantation is performed on the silicon germanium layer to form a source layer and a drain layer located on the surface of the silicon layer; The source layer and the drain layer are annealed to obtain an annealed source layer and an annealed drain layer. Silicon nitride is deposited on the annealed source layer, the annealed drain layer and the first device isolation layer to form the stop layer; According to the thickness of the stop layer, the patterned structure is thinned to obtain a thinned patterned structure, wherein the thinned patterned structure includes a silicon dioxide structure and a polycrystalline silicon structure; Wet etching is performed on the silicon dioxide and polysilicon located inside the silicon dioxide structure according to a pattern corresponding to the position of the polysilicon located inside the silicon dioxide structure, until the channel layer is exposed; The gate material is deposited on the surface of the channel layer located inside the silicon dioxide structure to obtain the top gate electrode; On the top gate electrode and the stop layer, silicon dioxide is deposited, and the silicon dioxide and the stop layer are etched according to a pattern corresponding to the positions of the source layer and the drain layer until the source layer and the drain layer are exposed to form the second device isolation layer; Titanium nitride, tungsten, and titanium nitride are sequentially deposited on the source layer and the drain layer to obtain the source electrode and the drain electrode.

8. The method according to claim 7, wherein, The method of depositing the gate material on the surface of the channel layer located inside the silicon dioxide structure to obtain the top gate electrode includes: The surface of the channel layer located inside the silicon dioxide structure is oxidized using ozone to form a silicon oxide layer; The gate material is deposited on the surface of the silicon oxide layer to obtain the top gate electrode.

9. The method according to claim 5, wherein, The deposition of ferroelectric material on the bottom gate layer to form a ferroelectric layer in contact with the bottom gate layer includes: The ferroelectric material and titanium nitride are sequentially deposited on the bottom gate layer to obtain a substrate layer covering the ferroelectric material and the titanium nitride; The substrate layer covering the ferroelectric material and the titanium nitride is subjected to ferroelectric annealing to obtain an annealed substrate layer, wherein the annealing temperature of the ferroelectric annealing corresponds to the material type of the ferroelectric material; The titanium nitride on the surface of the annealed substrate is removed to obtain the ferroelectric layer.

10. The method according to claim 5, wherein, The etched area includes a first etched area and a second etched area; The process of depositing a gate material within the etched area to obtain a substrate layer including a bottom gate layer includes: In the first etched region, silicon nitride, tungsten, and titanium nitride are deposited sequentially to form a first bottom gate layer, and in the second etched region, silicon nitride, tungsten, and titanium aluminide are deposited sequentially to form a second bottom gate layer, thereby obtaining a substrate layer including the bottom gate layer.

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