A dynamic random access memory with adjustable storage time and a manufacturing method thereof

Abstract

The application belongs to the technical field of chip structure design, and more particularly to a dynamic random access memory with adjustable storage time and a preparation method thereof. The dynamic random access memory has a heterogeneous integrated sensing and computing integrated structure, wherein the drain of the first field effect transistor is connected with the bottom gate electrode of the second floating gate transistor. During operation, the bottom gate injection charge of the second floating gate transistor is adjusted by applying a pulse voltage signal to the first field effect transistor, the gate voltage of the bottom gate of the second floating gate transistor is instantaneously regulated, the potential barrier of the floating gate and the tunneling layer is changed, the number of stored charges in the floating gate storage layer is changed to realize the modulation of the threshold voltage of the second floating gate transistor, and flexible storage function is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip structure design, and more particularly to a dynamic random access memory with dynamically adjustable storage time and a preparation method thereof. BACKGROUND

[0002] With the continuous development of the artificial intelligence (AI) big data information era, the explosion of data poses a huge challenge to the transmission, storage and processing capacity of information, and there is an urgent need for more efficient processors to access data at high speed.

[0003] However, the traditional dynamic random access memory (DRAM) relies on charge refresh to maintain data, resulting in high static power consumption and making it difficult to meet the needs of low-power scenarios such as the Internet of Things and edge computing. As the process node approaches the physical limit (such as below 1x nm), the leakage current and capacitive coupling problems of traditional silicon-based DRAM are exacerbated. The current 2T DRAM memory device structure with separate read and write transistors also faces the challenge of difficult storage time period control, making it difficult to meet the current dynamic and complex task requirements.

[0004] The charge retention time of the traditional floating gate memory is determined by the fixed material stack (such as SiO2 / Si3N4 dielectric layer), which is difficult to dynamically adjust. Some external high-voltage pulse erasing is lacking in real-time adjustability. SUMMARY

[0005] In view of the defects of the prior art, the purpose of the present application is to provide a low-power dynamic random access memory with dynamically adjustable storage time period and low read voltage, and a preparation method thereof, aiming to solve the technical problem of difficult storage time period control of the existing technology.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides a dynamic random access memory with dynamically adjustable storage time, comprising:

[0007] a first field effect transistor, the first field effect transistor comprising a first bottom gate electrode, a first dielectric barrier layer, a first channel layer, a first source electrode and a first drain electrode which are sequentially stacked on a substrate; and

[0008] a second floating gate transistor, the second floating gate transistor comprising a second bottom gate electrode, a second dielectric barrier layer, a floating gate storage layer, a tunneling layer, a second channel layer, a second source electrode and a second drain electrode;

[0009] The first drain electrode of the first field effect transistor is connected with the second bottom gate electrode of the second floating gate transistor through a metal connecting layer; in use, the pulse current signal is applied to the first field effect transistor to adjust the injected charge of the second bottom gate electrode of the second floating gate transistor, the gate voltage of the bottom gate of the second floating gate transistor is instantaneously regulated, the potential barrier of the floating gate and the tunneling layer and the number of stored charges in the floating gate storage layer are changed, the modulation of the threshold voltage of the second floating gate transistor is realized, and thus the flexible storage function is realized.

[0010] According to another aspect of the present application, a horizontal connection preparation method of the dynamic random memory is provided, comprising the following steps:

[0011] The first bottom gate electrode of the first field effect transistor and the second bottom gate electrode of the second floating gate transistor are defined and prepared on the surface of the substrate;

[0012] The dielectric barrier material is deposited on the surface of the first bottom gate electrode and the second bottom gate electrode; the channel region of the first field effect transistor is defined on the surface of the dielectric barrier material, and the preparation of the first channel layer of the first field effect transistor is completed;

[0013] The first through hole region is defined, the end surface of the second bottom gate electrode of the second floating gate transistor is exposed through the bottom of the first through hole, but the end surface of the first bottom gate electrode of the first field effect transistor is not exposed; the first dielectric barrier layer and the second dielectric barrier layer can be separated through the first through hole;

[0014] The floating gate storage layer of the second floating gate transistor is prepared on the surface of the second dielectric barrier layer; the tunneling layer is prepared on the floating gate storage layer of the second floating gate transistor; and the preparation of the second channel layer is completed on the tunneling layer;

[0015] The first source electrode and the first drain electrode of the first field effect transistor are prepared on the first channel layer, and the second source electrode and the second drain electrode of the second floating gate transistor are prepared on the second channel layer; the metal connecting layer material is injected into the first through hole, and the metal connecting layer connects the first drain electrode and the second bottom gate electrode.

[0016] According to another aspect of the present application, a vertical connection preparation method of the dynamic random memory is provided, comprising the following steps:

[0017] The preparation of the first bottom gate electrode is completed on the surface of the substrate; then the materials of the first dielectric barrier layer and the first channel layer are sequentially deposited on the surface of the first bottom gate electrode, and the preparation of the first source electrode and the first drain electrode is completed on the surface of the first channel layer, that is, the preparation of the first field effect transistor is completed;

[0018] Depositing an isolation layer above the first source electrode and the first drain electrode of the first field effect transistor, and then preparing a second bottom gate electrode on the isolation layer;

[0019] Defining a second via hole between the second bottom gate electrode and the first drain electrode, and injecting a metal connecting layer material into the second via hole, so that the second bottom gate electrode and the first drain electrode are connected by the metal connecting layer;

[0020] Preparation of a second dielectric barrier layer, a floating gate storage layer, a tunneling layer and a second channel layer on the surface of the second bottom gate electrode in sequence, and finally preparation of a second source electrode and a second drain electrode on the second channel layer.

[0021] Overall, compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects:

[0022] (1) The dynamic random access memory mentioned in the present application has a heterogeneous integrated sensing and computing integrated structure, wherein the drain of the first field effect transistor is connected to the bottom gate electrode of the second floating gate transistor. When in use, the gate voltage of the floating gate transistor is adjusted by applying a pulse current signal to the field effect transistor to inject charges into the bottom gate of the floating gate transistor, so as to instantaneously control the gate voltage of the bottom gate of the floating gate transistor, change the potential barrier of the floating gate and the tunneling layer, change the number of stored charges in the floating gate layer to realize the modulation of the threshold voltage of the second floating gate transistor, and further realize flexible storage function.

[0023] (2) In the preferred embodiment of the present application, IGZO FET is used as a gating tube, and IGZO amorphous oxide is used as the channel material of the transistor. The off-state current is extremely low, and static power consumption can be realized.

[0024] (3) The preferred embodiment of the present application uses two-dimensional material as the channel material of the floating gate device. The atomic level thin layer of two-dimensional material and the appropriate energy band structure are more conducive to electron tunneling. The atomic level flat interface of two-dimensional material as the tunneling layer material can significantly improve the charge retention characteristics, and the tunneling layer can eliminate the bulk dielectric isolation layer required by traditional floating gate devices.

[0025] (4) The application adopts a specific combination mode of a first field effect transistor (1T) and a second floating gate transistor (1FGT), and the synergistic control of 1FGT+1T can dynamically modulate the barrier height or tunneling probability of the floating gate (FG) (such as through energy band engineering or polarization effect of the channel material) by controlling the gate bias of the transistor (T), so as to realize real-time programmable storage time and high-speed access to data. Moreover, the floating gate device (Floating Gate) has good storage characteristics and long charge preservation time, and the storage time of the floating gate device can be dynamically adjusted by adjusting the gate bias of the transistor. The 1FGT+1T structure is constructed, and then the new channel material is combined, so that the challenge of difficult storage time period control can be effectively alleviated. Moreover, the DRAM device of the new hetero-integrated architecture proposed in the application can support 3D stacking and simplify the manufacturing process, can break through the limit of planar micro-fraction, and the unit area can be compressed to 4F 2 Promote the improvement of device integration performance.

[0026] (5) The metal oxide is perfectly qualified for the role of switch due to its ultra-low off-state current characteristics, can reliably control the connection and isolation of the floating gate bottom gate, and can minimize the energy loss and data interference in the non-operation state. The two-dimensional material utilizes its excellent gate control ability, high mobility and low leakage characteristics as the core (floating gate transistor channel) of the storage unit, can sensitively respond to the floating gate charge change, realize efficient data writing, erasing and reliable reading, and has low power consumption and high performance potential. The metal oxide and the two-dimensional material are respectively used as the channel layer materials of the first field effect transistor and the second floating gate transistor, the combination fully gives play to the respective physical characteristic advantages of the two materials, and cooperates with the specific memory construction mode of 1FGT+1T of the application, so as to provide a promising solution for constructing a high-performance and low-power-consumption memory. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a preparation method schematic diagram of step S01 of embodiment 1 of the application;

[0028] Figure 2 is a preparation method schematic diagram of step S02 of embodiment 1 of the application;

[0029] Figure 3 is a preparation method schematic diagram of step S03 of embodiment 1 of the application;

[0030] Figure 4 is a preparation method schematic diagram of step S04 of embodiment 1 of the application;

[0031] Figure 5 is a preparation method schematic diagram of step S05 of embodiment 1 of the application;

[0032] Figure 6This is a schematic diagram of the preparation method in step S06 of Embodiment 1 of this application;

[0033] Figure 7 This is a schematic diagram of the preparation method in step S07 of Embodiment 1 of this application;

[0034] Figure 8 This is a schematic diagram of the preparation method in step S01 of Embodiment 2 of this application;

[0035] Figure 9 This is a schematic diagram of the preparation method of step S02 in Embodiment 2 of this application;

[0036] Figure 10 This is a schematic diagram of the preparation method of step S03 in Embodiment 2 of this application;

[0037] Figure 11 This is a schematic diagram of the preparation method of step S04 in Embodiment 2 of this application;

[0038] Figure 12 This is a schematic diagram of the preparation method of step S05 in Embodiment 2 of this application;

[0039] Figure 13 This is a schematic diagram of the preparation method of step S06 in Embodiment 2 of this application;

[0040] Figure 14 This is a schematic diagram of the preparation method in step S07 of Embodiment 2 of this application;

[0041] Figure 15 This is a schematic diagram of the preparation method of step S08 in Embodiment 2 of this application;

[0042] Figure 16 This is a schematic diagram of the preparation method of step S09 in Embodiment 2 of this application;

[0043] Figure 17 These are photographs of the actual memory device prepared in Example 1;

[0044] Figure 18 It is the response signal of the second floating gate transistor collected when a pulse current signal is applied to the first field-effect transistor of the memory prepared in Example 1;

[0045] Figure 19 It is the response signal of the second floating gate transistor collected when a pulse current signal is applied to the first field-effect transistor of the memory prepared in Example 3.

[0046] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0047] 101-Substrate; 102-First bottom gate electrode; 103-First dielectric barrier layer; 104-First channel layer; 105-First source electrode; 106-First drain electrode; 107-First via; 108-Metal interconnect layer;

[0048] 201 - Isolation layer; 202 - Second bottom gate electrode; 203 - Second dielectric barrier layer; 204 - Second channel layer; 205 - Second source electrode; 206 - Second drain electrode; 207 - Floating gate storage layer; 208 - Tunneling layer; 209 - Second via. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] This invention provides a low-power dynamic random access memory with dynamically adjustable storage time, comprising:

[0051] A first field-effect transistor, comprising a first bottom gate electrode 102, a first dielectric barrier layer 103, a first channel layer 104, a first source electrode 105, and a first drain electrode 106 sequentially stacked on a substrate 101; and

[0052] The second floating gate transistor includes a second bottom gate electrode 202, a second dielectric barrier layer 203, a floating gate storage layer 207, a tunneling layer 208, a second channel layer 204, a second source electrode 205, and a second drain electrode 206.

[0053] In this configuration, the first drain electrode 106 of the first field-effect transistor and the second bottom gate electrode 202 of the second floating gate transistor are connected through a metal interconnect layer 108. During use, a pulsed current signal is applied to the first field-effect transistor to adjust the injected charge at the second bottom gate electrode of the second floating gate transistor, instantaneously controlling the gate voltage of the second floating gate transistor. This changes the potential barrier between the floating gate and the tunneling layer, as well as the amount of charge stored in the floating gate storage layer, thereby modulating the threshold voltage of the second floating gate transistor and achieving flexible storage functionality. Specifically, a pulsed voltage signal can be input to the first source of the first field-effect transistor as needed, and a constant voltage signal can be input to the first bottom gate electrode to ensure the first field-effect transistor is turned on; alternatively, a pulsed voltage signal can be input to the first bottom gate electrode of the first field-effect transistor, and a constant voltage signal can be input to the first source to ensure the first field-effect transistor is turned on. By applying a pulsed current signal to the first field-effect transistor and utilizing the connection between the first drain and the second bottom gate electrode, the second floating gate transistor can be instantaneously controlled, achieving flexible storage.

[0054] Unless otherwise specified, the materials used for the bottom gate electrode, dielectric barrier layer, channel layer, floating gate storage layer, tunneling layer, source electrode, and drain electrode in the memory structure of this invention may be the types of materials commonly used in current technology.

[0055] In some embodiments, the first bottom gate electrode 102 and the second bottom gate electrode 202 are each independently made of one of W, Cr / Au, Ni / Au, Ag, Pt, Ni, Ti, and Al, or an alloy thereof; the fabrication processes of the first bottom gate electrode and the second bottom gate electrode include, but are not limited to, electron beam evaporation and magnetron sputtering, and the thickness of the first bottom gate electrode and the second bottom gate electrode is 10 nm-50 nm; the metal interconnect layer 108 is made of one of W, Cr / Au, Ni / Au, Ag, Pt, Ni, Ti, and Al, or an alloy thereof. Here, "Cr / Au" and "Ni / Au" indicate a metal thin film stacked structure, with Cr or Ni as the adhesive layer and Au as the conductive layer.

[0056] In some embodiments, the first dielectric barrier layer 103 and the second dielectric barrier layer 203 are each independently made of one of Al2O3, HfO2, SiO2 or a composite material thereof; their preparation processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PECVD), magnetron sputtering, chemical vapor deposition (CVD) or molecular beam epitaxy, etc., and their thickness is 30 nm-50 nm.

[0057] In some embodiments, the first channel layer 104 and the second channel layer 204 are each independently made of indium gallium zinc oxide (IGZO). x Ga y Zn z O), Indium gallium silicon oxide (IGSO, In x Ga y Si z O), Indium tin zinc oxide (ITZO, In x Sn y Zn z O), indium zinc oxide (IZO, In) x Zn y O), zinc oxide (ZnO, Zn) x O), zinc tin oxide (ZTO, Zn) x Sn y O), zinc nitrides (ZnON, Zn) x O y N), Zirconium zinc tin oxide (ZZTO, Zr) x Zn y Sn zO), tin oxide (SnO, Sn) x O), hafnium indium zinc oxide (HIZO, Hf) x In y Zn z O), gallium zinc tin oxide (GZTO, Ga x Zn y Sn z O), aluminum zinc tin oxide (AZTO, Al) x Zn y Sn z O), ytterbium gallium zinc oxide (YGZO, Yb x Ga y Zn z O), Indium gallium oxide (IGO, In x Ga y The preparation process includes one of O), MoS2, WS2 or a composite material thereof, and the thickness ranges from 4 nm to 15 nm.

[0058] In some embodiments, the floating gate storage layer 207 is made of a metallic or non-metallic material. The metallic material is selected from W, Pt, or gold nanoparticles, and the non-metallic material is selected from graphene or Si3N4. Its fabrication process includes, but is not limited to, atomic vapor deposition, magnetron sputtering, chemical vapor deposition, and electron beam evaporation, with a thickness of 5 nm-10 nm.

[0059] In some embodiments, the tunneling layer 208 is made of h-BN, Al2O3, or HfO2. Its fabrication process includes, but is not limited to, atomic vapor deposition, magnetron sputtering, and mechanical transfer, with a thickness of 5 nm to 15 nm.

[0060] In some embodiments, the first source electrode 105, the second source electrode 205, the first drain electrode 106 and the second drain electrode 206 are made of Cr / Au or Ti / Au materials; their preparation processes include, but are not limited to, magnetron sputtering, electron beam evaporation, etc., with a thickness of 30 nm-150 nm.

[0061] The present invention also provides a method for preparing the horizontal interconnect of the dynamic random access memory, comprising the following steps:

[0062] The first bottom gate electrode 102 of the first field-effect transistor and the second bottom gate electrode 202 of the second floating gate transistor are defined and fabricated on the surface of the substrate 101.

[0063] A dielectric barrier layer material is deposited on the surface of the first bottom gate electrode 102 and the second bottom gate electrode 202; a channel region of the first field-effect transistor is defined on the surface of the dielectric barrier layer material, and the fabrication of the first channel layer 104 of the first field-effect transistor is completed.

[0064] A first via 107 region is defined, the bottom of the first via 107 exposes the end face of the second bottom gate electrode 202 of the second floating gate transistor, but does not expose the end face of the first bottom gate electrode 102 of the first field-effect transistor; the first via 107 can be used to separate the first dielectric barrier layer 103 and the second dielectric barrier layer 203.

[0065] A floating gate storage layer 207 of a second floating gate transistor is fabricated on the surface of the second dielectric barrier layer 203; a tunneling layer 208 is fabricated on the floating gate storage layer 207 of the second floating gate transistor; and a second channel layer 204 is fabricated on the tunneling layer 208.

[0066] A first source electrode 105 and a first drain electrode 106 of a first field-effect transistor are fabricated on the first channel layer 104, and a second source electrode 205 and a second drain electrode 206 of a second floating gate transistor are fabricated on the second channel layer 204; a metal interconnect layer 108 material is injected into the first via 107, and the metal interconnect layer 108 connects the first drain electrode 106 and the second bottom gate electrode 202.

[0067] The present invention also provides another method for fabricating the vertical interconnect of the dynamic random access memory, comprising the following steps:

[0068] The first bottom gate electrode 102 is fabricated on the surface of the substrate 101; then the materials of the first dielectric barrier layer 103 and the first channel layer 104 are sequentially deposited on the surface of the first bottom gate electrode 102; then the first source electrode 105 and the first drain electrode 106 are fabricated on the surface of the first channel layer 104, thus completing the fabrication of the first field-effect transistor.

[0069] An isolation layer 201 is deposited above the first source electrode 105 and the first drain electrode 106 of the first field-effect transistor, and then a second bottom gate electrode 202 is fabricated on the isolation layer.

[0070] A second via 209 is defined between the second bottom gate electrode 202 and the first drain electrode 106, and a metal interconnect layer 108 material is injected into the second via 209, the metal interconnect layer 108 enabling the second bottom gate electrode 202 and the first drain electrode 106 to be interconnected via the via.

[0071] The second dielectric barrier layer 203, the floating gate storage layer 207, the tunneling layer 208, and the second channel layer 204 are sequentially fabricated on the surface of the second bottom gate electrode 202. Finally, the second source electrode 205 and the second drain electrode 206 are fabricated on the second channel layer 204.

[0072] In some embodiments, the material of the isolation layer 201 is Al2O3, HfO2 or SiO2; the thickness is 100-150 nm, and its preparation process includes, but is not limited to, magnetron sputtering, chemical vapor deposition (CVD).

[0073] The interconnect structure formed by the dynamic random access memory provided by this invention includes, but is not limited to, planar device interconnects and 3D vertical stacked interconnects. The first field-effect transistor acts as a gate transistor to control the charge storage capability of the second floating-gate transistor.

[0074] The embodiments of the present invention are implemented under the premise of the technical solution of the present invention, and detailed implementation methods and processes are given. However, the protection scope of the present invention is not limited to the following embodiments. The process parameters in the following embodiments that do not specify specific conditions are generally in accordance with conventional conditions.

[0075] The endpoints and any values ​​of the ranges disclosed in this invention are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this invention.

[0076] The process parameters in the following examples, unless otherwise specified, are generally performed under conventional conditions.

[0077] The embodiments of this application are described below with reference to the accompanying drawings.

[0078] Example 1

[0079] Fabrication of horizontally connected structural devices.

[0080] S01. Substrate Cleaning. In this embodiment, a high-resistivity silicon substrate 101 with a surface of 300 nm SiO2 is selected. Impurities on the substrate 101 are cleaned using the standard RCA process, and then dried with high-purity nitrogen. A 5 nm / 15 nm Cr / Au (i.e., 5 nm Cr + 15 nm Au) layer is prepared as the metal bottom gate electrode layer using a process of spin coating, baking, photolithography, development, and electron beam evaporation. The first bottom gate electrode 102 of the first field-effect transistor and the second bottom gate electrode 202 of the second floating gate transistor are defined and fabricated on the surface of the substrate 101 using a lift-off technique. Figure 1 As shown.

[0081] S02. Using atomic layer deposition (ALD) technology, deposit the first dielectric barrier layer 103 of the first field-effect transistor and the second dielectric barrier layer 203 of the second floating gate transistor onto the surfaces of the first bottom gate electrode 102 and the second bottom gate electrode 202. The material is HfO2, with a growth temperature of 250℃ and a thickness of 30 nm. Figure 2 As shown.

[0082] S03. Using a spin coating, baking, photolithography, and development process, the channel region of the first field-effect transistor is defined on the surface of the first dielectric barrier layer 103. MoS2 deposition of the first channel layer 104 of the first field-effect transistor is completed using a magnetron sputtering process, with a thickness of 4 nm. Figure 3 As shown.

[0083] S04. Using the processes of spin coating, baking, photolithography, development, and etching, the region of the first via 107 is defined. The bottom of the first via 107 exposes the end face of the second bottom gate electrode 202 of the second floating gate transistor, but does not expose the end face of the first bottom gate electrode 102 of the first field-effect transistor; the first via 107 enables the separation of the first dielectric barrier layer 103 and the second dielectric barrier layer 203, such as... Figure 4 As shown.

[0084] S05. Using a process of spin coating, baking, photolithography, development, and electron beam evaporation, a 5 nm thick Pt layer is prepared on the surface of the second dielectric barrier layer 203 to serve as the floating gate storage layer 207 for the second floating gate transistor. The floating gate storage layer 207 is defined using a lift-off technique. Figure 5 As shown.

[0085] S06. Using a mechanical transfer step, a 10 nm thick h-BN layer is transferred onto the floating gate storage layer 207 of the second floating gate transistor as a tunneling layer 208. Figure 6 As shown.

[0086] S07. MoS2 (7nm) is transferred to the tunneling layer 208 of the second floating gate transistor using a mechanical transfer method to serve as the second channel layer 204. Using spin coating, baking, photolithography, development, and electron beam evaporation processes, a 5 / 50 nm Cr / Au layer is prepared on the first channel layer 104 as the first source electrode 105 and the first drain electrode 106 of the first field-effect transistor. A 5 / 50 nm Cr / Au layer is prepared on the second channel layer 204 as the second source electrode 205 and the second drain electrode 206 of the second floating gate transistor. Simultaneously, a 5 / 50 nm Cr / Au layer is prepared within the first via 107 as a metal interconnect layer 108. The definitions of the first source electrode 105, the first drain electrode 106, the second source electrode 205, and the second drain electrode 206 are completed using a lift-off technique. Figure 7 As shown.

[0087] Example 2

[0088] Fabrication of 3D stacked structure devices.

[0089] S01. The fabrication process of this 3D stacked structure device first involves RCA cleaning and nitrogen drying of a high-resistivity silicon substrate 101 with 300 nm SiO2. Then, a 5 / 15 nm Cr / Au bottom electrode metal layer for the first field-effect transistor, i.e., the first bottom gate electrode 102, is fabricated using photolithography, electron beam evaporation, and lift-off techniques. Figure 8 As shown.

[0090] S02. A 30 nm HfO2 first dielectric barrier layer 103 is deposited on the first bottom gate electrode 102 using the ALD process; then, the channel region is defined and MoS2 material is deposited as the first channel layer 104 with a thickness of 4 nm using the magnetron sputtering process. Following this, a 5 / 25 nm Cr / Au first source electrode 105 and a first drain electrode 106 are fabricated on the first channel layer 104 using spin coating, baking, photolithography, development, and electron beam evaporation processes, thus completing the fabrication of the first field-effect transistor. Figure 9 As shown.

[0091] S03. To construct a 3D stacked structure, a 150 nm Al2O3 layer 201 is deposited as an isolation layer 201 above the first field-effect transistor using ALD deposition. In this embodiment, the Al2O3 growth temperature is 250°C. Figure 10 As shown.

[0092] S04. A 5 / 15 nm Cr / Au layer is fabricated on the surface of the isolation layer using photolithography, electron beam evaporation, and lift-off techniques to serve as the second bottom gate electrode 202 of the second floating gate transistor. Figure 11 As shown.

[0093] S05. Define a second via 209 between the second bottom gate electrode 202 and the first drain electrode 106 by photolithography and etching, such as Figure 12 As shown.

[0094] S06. 5 / 200 nm Cr / Au is injected into the second via 209 as a metal interconnect layer 108 material. This metal interconnect layer 108 enables the via interconnection between the second bottom gate electrode 202 and the first drain electrode 106. Figure 13 As shown.

[0095] S07. A 30 nm HfO2 layer is deposited on the surface of the second bottom gate electrode 202 as a second dielectric barrier layer 203 using an ALD process. In this embodiment, the HfO2 growth temperature is 250°C. Figure 14 As shown.

[0096] S08. A 5 nm Pt metal floating gate storage layer 207 as the second floating gate transistor is fabricated using electron beam evaporation, and a 10 nm h-BN is transferred as a tunneling layer 208 using mechanical transfer. Figure 15 As shown.

[0097] S09. An 8 nm thick MoS2 layer 204 is applied as the second channel layer using a mechanical transfer method. Then, a 5 / 25 nm Cr / Au second source electrode 205 and a second drain electrode 206 are fabricated using a process involving homogenization, baking, photolithography, development, and electron beam evaporation. Figure 16 As shown.

[0098] Example 3

[0099] The other conditions are the same as in Example 1, except that the material used for the first channel layer 104 of the first field-effect transistor is IGZO.

[0100] The device prepared in Example 1 (see physical image) Figure 17 As shown, a pulsed current test was performed: A pulsed voltage was applied to the bottom gate electrode of the first field-effect transistor (FET), starting from 1V and gradually increasing by an intermediate difference of 0.5V (1V, 1.5V, 2V, 2.5V, and 3V respectively), with a pulse duration of 500 ms. A constant voltage of 500 mV was applied to the source of the first FET to ensure its conduction. This generated a pulsed current signal at the drain of the first FET. A readout voltage of 60 mV was applied to the source of the second floating gate transistor, and the drain current of the second floating gate transistor was collected. The test results are shown below. Figure 18As shown in the figure, different pulse voltages are represented by different colors in the test results. The test results show that, because the first drain and the second bottom gate electrode are connected, the drain current collected by the second floating gate transistor varies in magnitude and duration under different pulse voltages and currents of the first field-effect transistor. This indicates that by controlling the pulse voltage of the first field-effect transistor, the bottom gate injection charge of the floating gate transistor can be adjusted, the gate voltage of the bottom gate transistor can be instantaneously controlled, the potential barrier between the floating gate and the tunneling layer can be changed, and the amount of charge stored in the floating gate layer can be changed to modulate the threshold voltage of the second floating gate transistor, thereby achieving flexible storage functionality.

[0101] Figure 19 Following the same testing method described above, a pulsed current signal was applied to the first field-effect transistor in the memory device prepared in Example 3, and the current response signal was collected at the drain of the second floating gate transistor. It can be clearly seen that compared to Example 1, where both the first and second channel layers are made of MoS2, in Example 3, where the first channel layer uses IGZO and the second channel layer uses MoS2, under the same conditions, the signal response speed of the second floating gate transistor is faster, and the device is more stable. See details... Figure 19 .

[0102] contrast Figure 18 and Figure 19 It is evident that as the pulse voltage increases, the drain current holding time of the controlled floating gate transistor in the device combining IGZO and MOS2 in Example 3 becomes more stable, and its drain current value is much smaller than that under the same pulse voltage. Figure 18 The drain current indicates that the power consumption of the device prepared by combining IGZO and MOS2 in Example 3 is significantly lower than that of the device prepared by using MOS2 as the channel material in Example 1, and the regulation performance is better. The possible reason is that the material of IGZO itself has the characteristic of low leakage current, which can significantly reduce the switching power consumption of the switching transistor, and MOS2 has high carrier mobility, which improves the electron tunneling speed.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dynamic random access memory with dynamically adjustable storage time, characterized in that, include: A first field-effect transistor, comprising a first bottom gate electrode (102), a first dielectric barrier layer (103), a first channel layer (104), a first source electrode (105), and a first drain electrode (106) sequentially stacked on a substrate (101); and The second floating gate transistor includes a second bottom gate electrode (202), a second dielectric barrier layer (203), a floating gate storage layer (207), a tunneling layer (208), a second channel layer (204), a second source electrode (205), and a second drain electrode (206). The first drain electrode (106) of the first field-effect transistor and the second bottom gate electrode (202) of the second floating gate transistor are connected through a metal interconnect layer (108). In use, by applying a pulse current signal to the first field-effect transistor to adjust the injected charge of the second bottom gate electrode of the second floating gate transistor, the gate voltage of the bottom gate of the second floating gate transistor is instantaneously controlled, the potential barrier between the floating gate and the tunneling layer and the amount of charge stored in the floating gate storage layer are changed, thereby realizing the modulation of the threshold voltage of the second floating gate transistor and thus realizing a flexible storage function.

2. The dynamic random access memory as described in claim 1, characterized in that, The first bottom gate electrode (102) and the second bottom gate electrode (202) are each made of one of W, Cr / Au, Ni / Au, Ag, Pt, Ni, Ti, Al, or an alloy thereof; the first bottom gate electrode and the second bottom gate electrode are fabricated by electron beam evaporation or magnetron sputtering, and the thickness of the first bottom gate electrode and the second bottom gate electrode is 10 nm-50 nm. The metal bonding layer (108) is made of one of W, Cr / Au, Ni / Au, Ag, Pt, Ni, Ti, Al, or an alloy thereof.

3. The dynamic random access memory as described in claim 1, characterized in that, The first dielectric barrier layer (103) and the second dielectric barrier layer (203) are each made of one of Al2O3, HfO2, SiO2 or a composite material thereof; their preparation process is atomic layer deposition, physical vapor deposition, magnetron sputtering, chemical vapor deposition or molecular beam epitaxy, and their thickness is 30 nm-50 nm.

4. The dynamic random access memory as described in claim 1, characterized in that, The materials used for the first channel layer (104) and the second channel layer (204) are each independently one of indium gallium zinc oxide, indium gallium silicon oxide, indium tin zinc oxide, indium zinc oxide, zinc oxide, zinc tin oxide, zinc nitride oxide, zirconium zinc tin oxide, tin oxide, hafnium indium zinc oxide, gallium zinc tin oxide, aluminum zinc tin oxide, ytterbium gallium zinc oxide, indium gallium oxide, MoS2, WS2 or composite materials thereof, and their preparation process is magnetron sputtering, mechanical transfer or chemical vapor deposition, with a thickness of 4 nm-15 nm.

5. The dynamic random access memory as described in claim 1, characterized in that, The floating gate storage layer (207) is made of a metallic material or a non-metallic material. The metallic material is selected from W, Pt or gold nanoparticles, and the non-metallic material is selected from graphene or Si3N4. Its preparation process is atomic vapor deposition, magnetron sputtering or chemical vapor deposition, and the thickness is 5nm-10nm.

6. The dynamic random access memory as described in claim 1, characterized in that, The tunneling layer (208) is made of h-BN, Al2O3 or HfO2; its preparation process is atomic vapor deposition or magnetron sputtering, and its thickness is 5 nm-15 nm.

7. The dynamic random access memory as described in claim 1, characterized in that, The first source electrode (105), the second source electrode (205), the first drain electrode (106), and the second drain electrode (206) are made of Cr / Au or Ti / Au materials; their preparation process is magnetron sputtering or electron beam evaporation, and the thickness is 30 nm-150 nm.

8. A method for fabricating horizontal interconnects of a dynamic random access memory as described in any one of claims 1 to 7, characterized in that, Includes the following steps: The first bottom gate electrode (102) of the first field-effect transistor and the second bottom gate electrode (202) of the second floating gate transistor are defined and fabricated on the surface of the substrate (101); A dielectric barrier layer material is deposited on the surface of the first bottom gate electrode (102) and the second bottom gate electrode (202); a channel region of the first field-effect transistor is defined on the surface of the dielectric barrier layer material, and the fabrication of the first channel layer (104) of the first field-effect transistor is completed. A first via (107) region is defined, the bottom of the first via (107) exposes the end face of the second bottom gate electrode (202) of the second floating gate transistor, but does not expose the end face of the first bottom gate electrode (102) of the first field-effect transistor; the first via (107) can be used to separate the first dielectric barrier layer (103) and the second dielectric barrier layer (203); A floating gate storage layer (207) of a second floating gate transistor is prepared on the surface of the second dielectric barrier layer (203); a tunneling layer (208) is prepared on the floating gate storage layer (207) of the second floating gate transistor; and a second channel layer (204) is prepared on the tunneling layer (208). A first source electrode (105) and a first drain electrode (106) of a first field-effect transistor are fabricated on the first channel layer (104), and a second source electrode (205) and a second drain electrode (206) of a second floating gate transistor are fabricated on the second channel layer (204); a metal interconnect layer (108) material is injected into the first via (107), and the metal interconnect layer (108) connects the first drain electrode (106) and the second bottom gate electrode (202).

9. A method for fabricating a vertical interconnect of a dynamic random access memory as described in any one of claims 1 to 7, characterized in that, Includes the following steps: The first bottom gate electrode (102) is fabricated on the surface of the substrate (101); then the materials of the first dielectric barrier layer (103) and the first channel layer (104) are sequentially deposited on the surface of the first bottom gate electrode (102); then the first source electrode (105) and the first drain electrode (106) are fabricated on the surface of the first channel layer (104), thus completing the fabrication of the first field-effect transistor. An isolation layer (201) is deposited above the first source electrode (105) and the first drain electrode (106) of the first field-effect transistor, and then a second bottom gate electrode (202) is fabricated on the isolation layer. A second via (209) is defined between the second bottom gate electrode (202) and the first drain electrode (106), and a metal interconnect layer (108) material is injected into the second via (209), the metal interconnect layer (108) enabling the second bottom gate electrode (202) and the first drain electrode (106) to complete via interconnection; The second dielectric barrier layer (203), floating gate storage layer (207), tunneling layer (208) and second channel layer (204) are sequentially fabricated on the surface of the second bottom gate electrode (202). Finally, the second source electrode (205) and the second drain electrode (206) are fabricated on the second channel layer (204).

10. The preparation method according to claim 9, characterized in that, The material of the isolation layer (201) is Al2O3, HfO2 or SiO2; the thickness is 100 nm-150 nm, and its preparation process is magnetron sputtering or chemical vapor deposition.

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