A digital gain control method and a SerDes system

Abstract

The present invention provides a digital gain control method and a SerDes system. The method includes: performing PAM modulation and pre - equalization processing on an encoded data stream, converting the processed data signal into an analog signal by using a digital - to - analog converter, performing low - pass filtering on the analog signal, and then sending it to a line; receiving the analog signal from the line, successively performing attenuation, equalization, and amplification processing, and quantizing the analog signal into a digital signal by an analog - to - digital converter based on a clock control signal; adaptively adjusting the gain of the quantized digital signal with a predefined decision target level as the target, and performing equalization processing to obtain a decision input signal, and providing the decision input signal to a decision - making device to achieve symbol decision. The technical solution of the present invention realizes more precise gain control.

Description

Technical Field

[0001] The present invention belongs to the field of digital gain control, and particularly relates to a digital gain control method and a SerDes system. Background Art

[0002] SerDes is a collective term for a serializer and a deserializer. SerDes is used to perform serial-to-parallel and parallel-to-serial conversions in a high-speed serial link to ensure data interconnection for data to flow freely between servers in a data center. At the sending end, multiple low-speed parallel signals are converted into high-speed serial signals, which pass through a transmission medium (optical cable or copper wire) and finally, at the receiving end, the high-speed serial signals are reconverted into low-speed parallel signals. This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of required transmission channels and device pins, increases the signal transmission speed, and thus reduces the communication cost.

[0003] The schematic diagram of the SerDes interface is as Figure 1 shown, giving an example of the data rate at different positions. Figure 1 In the figure, 8-bit parallel data with a clock rate of 125 MHz (8 ns per clock cycle, a total of 8-bit data) is serialized and converted into 1-bit serial data at 1 Gbps (1 ns per unit interval (UI), containing 1-bit data). After passing through the transmitter and the channel, it reaches the receiver. After being processed by the receiver, it is still 1 Gbps, and after deserialization, it is restored to 8-bit parallel data with a clock rate of 125 MHz. Through serialization, the number of I / Os can be reduced from 8 to 2 (signal transmission mostly uses differential form), which can effectively relieve the tension of chip I / O numbers and at the same time reduce the complexity of PCB traces. Smaller packages and fewer PCB traces, cables, and connectors, etc., will overall reduce the system cost.

[0004] The growing bandwidth demand is driving the development of 400 Gbps, 800 Gbps, and 1.6 Tbps SerDes. Currently, the main demand in the data center is for 400 Gbps bandwidth; for SerDes, there is currently no definition that can support a single cable or optical fiber. Therefore, 400 Gbps connections can be implemented as 40×10 Gbps, 16×25 Gbps, 8×50 Gbps, and 4×100 Gbps, and the best choice depends on per-bit, power consumption, and physical space requirements. Most 400 Gbps ports are implemented as 8×50 Gbps or 4×100 Gbps. At such high line rates, maintaining signal integrity even for a relatively short period of time is a very big challenge.

[0005] Traditional serdes PHY adopts the non-return-to-zero (NRZ) modulation method, where each symbol period carries information about a single bit, i.e., "1" or "0", and there are only two transmission levels, as Figure 2 shown. The serdes transmitter does not require a DAC, and the receiver does not require an ADC. The 0 or 1 bit can be directly determined through an analog sampling decision device. As the required line rate of a single channel increases, for example, the protocol with a single-channel transmission rate of 100 Gbps defined in the current Ethernet standard 802.3ck, additional information overhead needs to be added to transmit such a high data rate on a single channel. This overhead totals 6.25%. The actual data rate is 100 Gbps. Therefore, the Ethernet rate of each channel is 106.25 Gbps. With such a high single-channel rate, if the NRZ method is adopted, the symbol rate is 106.25 GBaud, and the channel bandwidth requires 53.125 GHz. With such a high channel bandwidth, the attenuation of the channel is very large, and the signal integrity problem is very serious. As Figure 3 shown is the channel S-parameter of a typical backplane scenario, and its transmission loss reaches more than 100 dB at a frequency of 53 GHz. Summary of the Invention

[0006] The object of the present invention is to provide a digital gain control method and a serdes system, aiming to achieve more precise gain control.

[0007] According to the first aspect of the present invention, a digital gain control method is provided, including:

[0008] Perform PAM modulation and pre-equalization processing on the encoded data stream, convert the processed data signal into an analog signal using a digital-to-analog converter, perform low-pass filtering on the analog signal, and then send it to the line;

[0009] Receive the analog signal from the line, perform attenuation, equalization, and amplification processing in sequence, and quantize the analog signal into a digital signal based on a clock control signal through an analog-to-digital converter;

[0010] Taking a predefined decision target level as the target, adaptively adjust the gain of the quantized digital signal, and perform equalization processing to obtain a decision input signal, and provide the decision input signal to a decision device to achieve symbol decision.

[0011] Preferably, the performing PAM modulation and pre-equalization processing on the encoded data stream further includes:

[0012] Perform PAM4 modulation on the encoded data stream based on non-Gray mapping and Gray mapping;

[0013] Coefficients c(-1), c(0), c(+1), c(+2) and c(+3) are set to perform pre - equalization on the modulated PAM4 symbols, where the following is satisfied:

[0014] abs(c(-1)) + abs(c(0)) + abs(c(+1)) + abs(c(+2)) + abs(c(+3)) ≤ 1.

[0015] Preferably, the analog - to - digital converter quantizes the analog signal into a digital signal based on a clock control signal, and further includes:

[0016] Locating the transmit - receive clock deviation based on the clock control signal, recovering a clock suitable for sampling by the analog - to - digital converter from the received data, and then adjusting the sampling phase through a phase interpolator.

[0017] Preferably, the adaptive adjustment of the gain of the quantized digital signal further includes:

[0018] Constructing a digital gain controller using a digital filter or a digital amplifier, and adjusting the gain of the digital signal by adjusting the coefficients of the digital filter or the gain value of the digital amplifier.

[0019] Preferably, the digital signal values of the predefined decision target levels are +3, +1, -1, -3, or -1, -1 / 3, +1 / 3, +1, or 0, 1, 2, 3, or k times the above values, where k is a natural number.

[0020] According to a second aspect of the present invention, a serdes system with digital gain control is provided, including:

[0021] A transmitting module for performing PAM modulation and pre - equalization processing on an encoded data stream, converting the processed data signal into an analog signal using a digital - to - analog converter, performing low - pass filtering on the analog signal, and then transmitting it onto the line;

[0022] A receiving module for receiving the analog signal from the line, performing attenuation, equalization, and amplification processing in sequence, and quantizing the analog signal into a digital signal based on a clock control signal through an analog - to - digital converter;

[0023] A decision module for adaptively adjusting the gain of the quantized digital signal with a predefined decision target level as the target, performing equalization processing, obtaining a decision input signal, and providing the decision input signal to a decision maker to implement symbol decision.

[0024] Compared with the related art, the technical solution of the present invention has the following advantages:

[0025] For SerDes applications in different scenarios, it can be achieved only by adding a digital filter with one tap, without the need for adaptive update of the decision target level value, reducing the digital logic in RTL implementation, as well as the resources and power consumption of ASIC. Digital gain enables more precise gain control conveniently. Since a fixed decision level is implemented, on the one hand, the dependence of the system convergence performance on the convergence of the decision level is reduced, and on the other hand, performance statistics (such as SNR) can be carried out conveniently and accurately.

[0026] Other features and advantages of the present invention will be described in the subsequent specification, and will be partially obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained through the structures and processes pointed out in the specification, claims, and drawings. Brief Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are certain embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 is a schematic diagram of a SerDes interface according to related technologies.

[0029] Figure 2 is a schematic diagram of two-level NRZ according to related technologies.

[0030] Figure 3 is a schematic diagram of the channel S parameters in a typical backplane scenario according to related technologies.

[0031] Figure 4 is a schematic diagram of the PAM4 debugging method according to related technologies.

[0032] Figure 5 is a PMA system of an ADC-based serdes PHY according to related technologies.

[0033] Figure 6 corresponds to Figure 5 the transmitted PAM4 sampling eye diagram.

[0034] Figure 7 and Figure 8 corresponds to Figure 5 the channel insertion loss diagram of the Channel part.

[0035] Figure 9 corresponds to Figure 5 the signal after passing through the receiving-end channel.

[0036] Figure 10 is the signal after analog equalization at the receiving end corresponding to Figure 5 .

[0037] Figure 11 is the received signal eye diagram after analog equalization at the receiving end corresponding to Figure 5 .

[0038] Figure 12 is the schematic diagram of multiple gears of CTLE according to the related art.

[0039] Figure 13 are respectively the decision eye diagrams after analog gain adjustment corresponding to Figure 5 .

[0040] Figure 14 and 15 are respectively the signal decision eye diagrams according to different channel insertion losses of the related art.

[0041] Figure 16 is the schematic diagram of the FFE, DFE and Slicer structures according to the related art.

[0042] Figure 17 is the schematic diagram of the need for convergence according to the decision target level value of the related art.

[0043] Figure 18 is the flowchart of the digital gain control method according to the present invention.

[0044] Figure 19 is the block diagram of the serdes system with digital gain control according to the present invention.

[0045] Figure 20 is the schematic diagram of the implementation structure of the pre - equalization module at the transmitting end according to the present invention.

[0046] Figure 21 is the schematic diagram of the digital gain controller structure according to the present invention.

[0047] Figures 22 - 25 is the final decision level value under different links according to the present invention. Specific embodiments

[0048] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0049] A new modulation format (PAM4, 4-level pulse amplitude modulation) is defined in the recent 802.3ck, with a symbol rate of 53.125 GBaud and a data rate of 106.25 Gbps for a single channel. To achieve the same rate, the channel bandwidth only needs to be half of that of NRZ (26.5625 GHz). The PAM4 coding scheme is as Figure 4 shown, using four voltage levels, where each level represents two digital bits. In this way, the number of bits transmitted per second is doubled compared to NRZ modulation. As Figure 4 shown, the highest voltage level represents the value "10" instead of "11". This coding form is called Gray coding, and Gray code ensures that an error between two adjacent voltage levels only results in a 1-bit error in the output symbol. The interconnection lines in the data center are very long, which can cause strong attenuation of high-frequency signals. In addition, for the interconnection lines at the data center level, the transmission line effect must be considered, and signal reflection must be considered at very high data rates. Both of these will cause signal integrity problems, and the perfect waveform at the transmitting end can hardly be distinguished at the receiving end. To solve this problem, channel equalization technology (equalization) must be used to restore the data to its original state.

[0050] For a PAM4 system with such a large insertion loss, it is difficult to meet the system performance only by analog equalization processing. It is necessary to convert the analog signal to a digital signal through an ADC and perform digital equalization processing in the digital domain. Therefore, the present invention is mainly described based on an ADC_based serdes system.

[0051] The serdes interface IP can be used for the interconnection between PHY / switch / MAC or optical modules, and there are mainly three application scenarios:

[0052] BP: Backplane, used for connecting multiple PCBs to the same backplane;

[0053] CM: Chip to module, connected to the optical module for remote transmission;

[0054] CC: Chip to chip, used for connecting chips on the same PCB;

[0055] In different application scenarios, the communication distance varies, the attenuation experienced by the signal is different, and the dynamic range of the signal when input to the ADC is relatively large. To adapt to the optimal range of the ADC, different intensity input signals need to be amplified by different analog gains through AAGC (Analog Automatic Gain Control) using a VGA (Variable Gain Amplifier), so that the amplitude of the signal input to the ADC meets a certain working range. On the other hand, through channels with different attenuations, the inter-symbol interference between signals is different. The greater the attenuation difference between high and low frequencies in a channel with a long communication distance, the more serious the signal broadening and the greater the inter-symbol interference (ISI). Equalization technology is required to eliminate the difference between high and low frequencies and thus eliminate inter-symbol interference.

[0056] Figure 5 It is a typical PMA (Physical Medium Attachment) system of an ADC-based serdes PHY. The transmitting part of the serdes PHY is responsible for generating NRZ or PAM4 symbols. Pre-equalization is performed at the transmitting end, and then it is converted into an analog signal through a digital-to-analog converter DAC, and is sent to the line after passing through an LD, analog low-pass filtering, etc.; the receiving part receives the differential signal from the line, passes through a terminal resistor Term and an electromagnetic coil Tcoil, and after being processed by AC coupling, CTLE, and VGA, it is finally transmitted to the ADC for sampling. The sampled digital signal is transmitted to the digital part of the PMA_RX receiving module for equalization and other processing, and finally the bit stream is demodulated and transmitted to the PCS layer for further decoding.

[0057] After the PAM4 signal at the transmitting end passes through the transmit pre-equalization TxFFE and is transmitted through the channel after being converted by the DAC and processed at the receiving end, the eye diagram of each point is as follows. The PAM4 sampling eye diagram at the transmitting end is as Figure 6 shown. The channel insertion loss differences in different scenarios are relatively large. There is a channel scenario with an attenuation of 15 dB at the 28 GHz frequency point (such as Figure 7 ), and there is a channel scenario with an attenuation of 30 dB at the 28 GHz frequency point (such as Figure 8 ). The signal eye diagram after passing through the receiving end channel channel is as Figure 9 . It can be seen that after passing through the channel, the eye diagram has become blurred and the three eyes cannot be recognized.

[0058] The signal eye diagram after passing through the analog equalization at the receiving end, the schematic diagram of the analog equalization is as Figure 10 . The purpose of equalization is to flatten the high and low frequencies and eliminate the attenuation difference between high and low frequencies. For example, the received signal eye diagram of a signal with a 10 dB channel insertion loss after being equalized by an analog CTLE is as Figure 11, if it is a 30dB signal, the received signal eye diagram will be more blurred, indicating that the eye diagram performance is far from meeting the requirements. It is necessary to further convert it to the digital domain through ADC and perform digital equalization FFE / DFE in the digital domain to obtain a better-performing eye diagram.

[0059] In related solutions, the analog circuit analog equalization is generally designed to cover different gears for small, medium, and large insertion loss links. For example, Figure 12 as shown, multiple gears of CTLE are designed. After an adaptive adjustment process, CTLE selects a suitable gear. For example, for the channel insertion loss of 30dB@28GHz link in this example, CTLE selects Figure 12 the curve with the maximum Boost in. After CTLE equalization, the signal amplitude is very small, which is not suitable for the ADC to work in the best working range. It is necessary to go through the AAGC adaptive adjustment algorithm to obtain a suitable VGA gain, so that the input signal of the ADC reaches a target level. After converting to the digital domain, further equalization of FFE / DFE is performed to eliminate inter-symbol interference and obtain a relatively clean decision eye diagram. Please refer to Figure 13 .

[0060] Compared with the transmitter eye diagram, the level value of the above eye diagram has changed. The ultimate goal of the present invention is to make a decision on the equalized signal to obtain the symbol sent by the transmitter. In related solutions, due to the different adjustment targets of CTLE and VGA, the target decision level of the decision maker Slicer obtained after equalization compensation for the high and low frequency attenuation difference is different in different scenarios, and the target decision level of Slicer also needs to be adaptively adjusted. The disadvantage of this method is that the performance of the system depends heavily on the convergence of the target decision level value of the decision maker, which is likely to cause instability in the system convergence.

[0061] As Figure 14 and 15 shown, when the channel insertion loss is 15dB, the decision eye diagram level of the signal is as Figure 14 , when the channel insertion loss is 30dB, the decision eye diagram level of the signal is as Figure 15 . The target level value of the above eye diagram needs to be obtained through adaptive training of the least mean square algorithm LMS. Among them, the implementation of FFE / DFE / Slicer generally adopts the implementation structure of FFE / DFE / Slicer as Figure 16 shown. The digital implementation method of the decision maker is generally:

[0062] See Figure 17, taking PAM4 as an example, first obtain four decision target level values slicer_level0, slicer_level1, slicer_level2, slicer_level3 through adaptive adjustment, as well as three decision threshold values top_thr = (slicer_level2 + slicer_level3) / 2, mid_thr = (slicer_level1 + slicer_level2) / 2, bot_thr = (slicer_level0 + slicer_level1) / 2, and then obtain the decision symbol according to the following decision method:

[0063] if dfe_out > top_thr

[0064] sli_out = slicer_level3

[0065] elseif dfe_out <= top_thr && dfe_out > mid_thr

[0066] sli_out = slicer_leve12

[0067] elseif dfe_out <= mid_thr && dfe_out > bot_thr

[0068] sli_out = slicer_level1

[0069] elseif dfe_out <= bot_thr

[0070] sli_out = slicer_leve10

[0071] end

[0072] In the related technology implementation solution, it is necessary to perform LMS adaptive adjustment training on the signal target level value after equalization. This method will additionally increase the LMS Engine circuit, increase the hardware resources and power consumption. In addition, the more unknown parameters that need to be trained in the system, the more complex the system will be, bringing certain stability problems.

[0073] Based on the above analysis, the present invention proposes a digital gain control method and a SerDes system. By using fixed decision levels of a slicer, for example, equally spaced signals in the digital domain such as +3, +1, -1, -3 (or 0, 1, 2, 3, or +1, +1 / 3, -1 / 3, -1), or k times these values (k is a natural number, i.e., k = 1, 2, 3,...), as long as it does not exceed the maximum numerical range supported by the decision levels in the system. To achieve a fixed decision level, a digital gain control module needs to be added to adaptively adjust the digital gain value to reach the target value of the fixed decision level.

[0074] Referring to Figure 18 the flowchart of, the digital gain control method provided by the present invention includes:

[0075] Step 101: Perform PAM modulation and pre - equalization processing on the encoded data stream, convert the processed data signal into an analog signal using a digital - to - analog converter, perform low - pass filtering on the analog signal, and then send it to the line.

[0076] As Figure 19 shown, the digital part module at the sending end includes a PAM4 generation module (PAM4 Gen module) and a pre - equalization TxFFE module. The modulated digital signal is sent to the digital - to - analog conversion module DAC, converted into an analog signal, and then sent to the line through signal driving by a line driver LD and analog low - pass filtering.

[0077] Specifically, the PAM4 Gen module is used to perform PAM modulation on the data stream encoded by the physical coding sublayer PCS layer. In this embodiment, PAM4 is taken as an example. PAM4 maps 2 bits into one PAM4 symbol, which can be based on non - Gray mapping and Gray mapping (Gray Mapper), as shown in Table 1.

[0078] Table 1

[0079] 2-bit data PAM4 non-Gray mapping PAM4 Gray mapping 00 -3 -3 01 -1 -1 10 +1 +3 11 +3 +1

[0080] To cope with greater channel attenuation and higher rates, the pre - equalization Tx FFE module at the sending end is used to pre - equalize the transmitted symbols to compensate for the loss of the high - frequency part of the link. The implementation structure is as Figure 20 shown. The pre - equalization ability is obtained by setting different coefficients c(-1), c(0), c(+1), c(+2), and c(+3) for multiple delay units or registers, and it needs to satisfy:

[0081] abs(c(-1)) + abs(c(0)) + abs(c(+1)) + abs(c(+2)) + abs(c(+3)) ≤ 1.

[0082] The signal after pre - equalization is converted into an analog signal by a digital - to - analog converter (DAC), and is sent to the transmission link through a line driver (LD), an analog low - pass filter (LPF).

[0083] Step 102: Receive the analog signal from the line, perform attenuation, equalization, and amplification processing in sequence, and quantize the analog signal into a digital signal by an analog - to - digital converter based on a clock control signal.

[0084] After passing through transmission links of different lengths, the attenuation amounts of different frequency components by the transmission link are inconsistent. The transmission link as a whole has a low - pass characteristic. Therefore, there is an attenuation difference between high - frequency signals and low - frequency signals, which will cause serious inter - symbol interference in the received signal. Therefore, different equalization means need to be adopted at the receiving end to reduce the influence of the low - pass frequency characteristic of the channel.

[0085] The differential signal from the transmission link, after passing through a termination resistor, an electromagnetic coil, and ac coupling, will pass through an attenuation circuit (ATT), a continuous - time linear equalizer (CTLE) circuit, and a variable - gain amplifier (VGA) for processing, and the input signal is adjusted to the optimal amplitude range suitable for the operation of the ADC. The ADC samples the analog signal based on the clock control signal of the clock and data recovery (CDR) module, and quantizes and converts it into a digital signal.

[0086] The CDR module is used to locate the clock deviation between transmission and reception, recover the clock suitable for ADC sampling from the received data, then adjust the sampling phase through a phase interpolator to eliminate data jitter, track the frequency offset, maximize the system timing margin, and thus achieve the bit - error rate index.

[0087] Step 103: With a predefined decision target level as the goal, adaptively adjust the gain of the quantized digital signal, and perform equalization processing to obtain a decision input signal, and provide the decision input signal to a decision device to achieve symbol decision.

[0088] The digital signal after ADC sampling is further subjected to precise gain control by a digital automatic gain controller (DAGC, Digital Automatic Gain Control). The digital gain controller is implemented using a digital filter or a digital amplifier. By adjusting the coefficients of the digital filter or the gain value of the amplifier, the gain of the digital signal can be changed. The digital gain controller has the characteristic of discrete adjustability and can achieve precise gain changes. In this embodiment, the DAGC is implemented using a one-tap digital filter, and the coefficients of the digital filter are adaptively adjusted through an adaptive algorithm. The target of the adaptive adjustment is the target level value determined by the present invention. For example, the decision target level value can be +3, +1, -1, -3, or k times these values (k = 1, 2, 3,...). The specific implementation scheme is as Figure 21 shown.

[0089] In a preferred embodiment, the update formula for the DAGC filter coefficient dagc_c is as follows:

[0090] dagc_c(n + 1) = dagc_c(n) + μ * sym * err

[0091] where n is the sampling point index value, μ is the LMS update step size, sym is the decision target level value, and err is the difference between the decision target level value and the signal before decision.

[0092] The signal after digital gain control is further processed by a digital equalization module (feed-forward equalization FFE / decision feedback equalization DFE) to obtain a decision input signal. The level of this decision input signal is close to the target signal level set during DAGC training. Therefore, the decision target signal level of the decision maker is the same in different transmission link scenarios. Figures 22 - 25 It is a block diagram for implementing the final decision level values of different links.

[0093] The signal after digital equalization passes through a decision maker to obtain decision symbols, and further the bit stream corresponding to the decision output symbols can be determined and transmitted to the PCS layer for further decoding.

[0094] It can be seen that the digital gain control method proposed by the present invention has the following advantages compared with the related technologies:

[0095] For serdes applications in different scenarios, it can be achieved only by adding digital filtering for one tap, without the need for adaptive updating of the decision target level value, reducing the digital logic implemented in RTL and reducing the resources and power consumption of the ASIC. The digital gain can be conveniently used for more precise gain control. Since a fixed decision level is implemented, on the one hand, the dependence of the system convergence performance on the convergence of the decision level is reduced, and on the other hand, performance statistics (such as SNR) can be conveniently and accurately performed. For example:

[0096]

[0097] N is the number of samples for err(n) statistics. N represents the total number of samples within the statistical window, n represents the index value of each sample, and n = 0, 1, 2,..., N - 1.

[0098] Correspondingly, in a second aspect, the present invention provides a serdes system with digital gain control, including:

[0099] A transmitting module, configured to perform PAM modulation and pre - equalization processing on the encoded data stream, convert the processed data signal into an analog signal by using a digital - to - analog converter, perform low - pass filtering on the analog signal, and then transmit it onto the line;

[0100] A receiving module, configured to receive the analog signal from the line, perform attenuation, equalization, and amplification processing in sequence, and quantize the analog signal into a digital signal by using an analog - to - digital converter based on a clock control signal;

[0101] A decision module, configured to adaptively adjust the gain of the quantized digital signal with a predefined decision target level as the target, perform equalization processing, obtain a decision input signal, and provide the decision input signal to a decision maker to implement symbol decision.

[0102] The above serdes system can be implemented by the digital gain control method provided in the embodiment of the first aspect. The specific implementation manner can refer to the description in the embodiment of the first aspect and will not be elaborated here.

[0103] It can be understood that the circuit structures, names, and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the usage requirements, and should not limit the concept of the present invention to the specific details of the above examples.

[0104] Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital gain control method, characterized in that: include: Perform PAM modulation and pre-equalization on the coded data stream, convert the processed data signal into an analog signal using a digital-to-analog converter, perform low-pass filtering on the analog signal, and then send it to the line; receiving the analog signal from the line, performing attenuation, equalization and amplification processing in sequence, and quantizing the analog signal into a digital signal through an analog-to-digital converter based on a clock control signal; Taking a predefined decision target level as a target, adaptively adjusting the gain of the quantized digital signal, and performing equalization processing to obtain a decision input signal, and providing the decision input signal to a decision device to implement symbol decision; The adaptively adjusting the gain of the quantized digital signal further comprises: A digital gain controller is constructed by using a digital filter or a digital amplifier, and the digital signal gain is adjusted by adjusting the coefficient of the digital filter or the gain value of the digital amplifier; The adjusting the coefficient of the digital filter further includes updating the filter coefficient dagc_c by the following formula: dagc_c(n+1)=dagc_c(n)+μ*sym*err Where n is the sampling point index value, μ is the LMS update step size, sym is the decision target level value, and err is the difference between the decision target level value and the signal before the decision; The step of providing the decision input signal to a decision device to implement symbol decision further comprises: The signal after digital gain control is input into the digital equalization module for processing to obtain a decision input signal, the level of which is the same in different transmission link scenarios; the decision input signal is processed by the decider to obtain a decision symbol, the bit stream corresponding to the decision output symbol is transmitted to the PCS layer for further decoding.

2. The digital gain control method according to claim 1, characterized in that: The performing PAM modulation and pre-equalization processing on the coded data stream further comprises: PAM4 modulation is performed on the coded data stream based on non-Gray mapping and Gray mapping; Set coefficients c(-1), c(0), c(+1), c(+2), and c(+3) to pre-equalize the modulated PAM4 symbols, where: abs(c(-1))+abs(c(0))+abs(c(+1))+abs(c(+2))+abs(c(+3))≤1.

3. The digital gain control method according to claim 1, characterized in that: The step of quantizing the analog signal into a digital signal based on a clock control signal by an analog-to-digital converter further comprises: The transmission and reception clock deviations are located based on the clock control signal, a clock suitable for sampling by the analog-to-digital converter is recovered from the received data, and then the sampling phase is adjusted by a phase interpolator.

4. The digital gain control method according to claim 1, characterized in that: The digital signal value of the predefined decision target level is +3, +1, -1, -3, or -1, -1 / 3, +1 / 3, +1, or 0, 1, 2, 3, or k times of the above values, where k is a natural number.

5. A serdes system with digital gain control, characterized in that: include: The sending module is used to perform PAM modulation and pre-equalization processing on the coded data stream, convert the processed data signal into an analog signal using a digital-to-analog converter, perform low-pass filtering on the analog signal, and then send it to the line; A receiving module, used for receiving the analog signal from the line, performing attenuation, equalization and amplification processing in sequence, and quantizing the analog signal into a digital signal through an analog-to-digital converter based on a clock control signal; A decision module is used to adaptively adjust the gain of the quantized digital signal with a predefined decision target level as the target, and perform equalization processing to obtain a decision input signal, and provide the decision input signal to a decision device to realize symbol decision; The decision module further comprises: A digital gain controller, wherein the digital gain controller is constructed by using a digital filter or a digital amplifier, and the digital signal gain is adjusted by adjusting the coefficient of the digital filter or the gain value of the digital amplifier; The adjusting the coefficient of the digital filter further includes updating the filter coefficient dagc_c by the following formula: dagc_c(n+1)=dagc_c(n)+μ*sym*err Where n is the sampling point index value, μ is the LMS update step size, sym is the decision target level value, and err is the difference between the decision target level value and the signal before the decision; The step of providing the decision input signal to a decision device to implement symbol decision further comprises: The signal after digital gain control is input into the digital equalization module for processing to obtain a decision input signal, the level of which is the same in different transmission link scenarios; the decision input signal is processed by the decider to obtain a decision symbol, the bit stream corresponding to the decision output symbol is transmitted to the PCS layer for further decoding.

6. The serdes system with digital gain control according to claim 5, characterized in that The sending module further comprises: A PAM4 generation module for performing PAM4 modulation on a coded data stream based on non-Gray mapping and Gray mapping; The transmit pre-equalization module is used to set coefficients c(-1), c(0), c(+1), c(+2) and c(+3) to pre-equalize the modulated PAM4 symbols, where: abs(c(-1))+abs(c(0))+abs(c(+1))+abs(c(+2))+abs(c(+3))≤1.

7. The serdes system with digital gain control according to claim 5, characterized in that The receiving module further comprises: The clock data recovery module is used to locate the transmission and reception clock deviations, recover the clock suitable for sampling by the analog-to-digital converter from the received data, and then adjust the sampling phase through the phase interpolator.

8. The serdes system with digital gain control according to claim 5, characterized in that The digital signal value of the predefined decision target level is +3, +1, -1, -3, or -1, -1 / 3, +1 / 3, +1, or 0, 1, 2, 3, or k times of the above values, where k is a natural number.

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