A method for enhancing error correction, data reading and writing method, and solid state hard disk

Abstract

The present invention belongs to the technical field of solid-state hard disks, and provides an enhanced error correction method, a data reading and writing method, and a solid-state hard disk, wherein the enhanced error correction method comprises: S1. Reading a Raid stripe to perform the first RaidEcc error correction; S2. When the error of the Raid stripe exceeds the error correction capability of the RaidEcc, dividing the stripe unit to be corrected in the Raid stripe to obtain a number of data units; S3. Randomly selecting a data unit to perform the second RaidEcc error correction to obtain an operation result; S4. Splicing the operation result with the data unit to obtain spliced ​​data, and performing LDPC decoding processing on the spliced ​​data; S5. If the decoding is successful, performing descrambling processing on the data successfully decoded by LDPC; if the decoding fails, returning to step S3. The present invention further divides the Raid stripe processed by the RaidEcc error correction to obtain smaller data units, and performs the RaidEcc error correction operation on the data unit to increase the error correction capability of the RaidEcc.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to an enhanced error correction method, a data reading and writing method, and a solid state hard disk. Background Art

[0002] Flash blocks store data by storing charges in floating gate structures or charge trapping structures, and by the amount of stored charges. However, the stored charges will gradually be lost over time, causing bit flips in the data stored in the flash blocks. If the bit flips exceed the error correction capability of the controller, Uncorrectable ECC (Error Correcting Code) will occur, which will affect the data retention (DR) capability of the flash blocks. The strength of the ECC capability directly affects the service life and reliability of the SSD.

[0003] The current RaidEcc algorithms are mainly Raid5 and Raid6. The number of erroneous data that Raid5 can effectively protect is one error in one Raid stripe; the number of erroneous data that Raid6 can effectively protect is two errors in one Raid stripe. The reliability of SSD can be improved through LDPC and RaidEcc protection, but when the number of errors in a Raid stripe exceeds the number of errors in the RaidEcc error correction algorithm, further data recovery will still be impossible. Summary of the invention

[0004] In view of the defects in the prior art, the present invention provides an enhanced error correction method, a data reading and writing method and a solid-state hard disk to solve the problem that the current RaidEcc algorithm has a limit on the number of erroneous data to be protected and recovery cannot be performed if the limit is exceeded.

[0005] In a first aspect, the present invention provides an enhanced error correction method, comprising:

[0006] S1. Read the Raid stripe to perform the first RaidEcc error correction;

[0007] S2. When the error of the Raid strip does not exceed the error correction capability of RaidEcc, the data of other stripe units in the Raid stripe are read to restore the error data of the stripe unit to be corrected, and the error correction data is descrambled;

[0008] When the error of the Raid strip exceeds the error correction capability of RaidEcc, the strip unit to be corrected in the Raid strip is split to obtain a number of data units;

[0009] S3 randomly selects the data unit for a second RaidEcc error correction to obtain the calculation result;

[0010] S4. Splicing the operation result with the data unit to obtain spliced ​​data, and performing LDPC decoding on the spliced ​​data;

[0011] S5. If the decoding is successful, the LDPC decoded data is descrambled; if the decoding fails, return to step S3.

[0012] It can be seen from the above technical scheme that the enhanced error correction method provided by the present invention utilizes the common LDPC and RaidEcc protection method adopted by SSD. On the basis of RaidEcc error correction, the Raid strip processed by RaidEcc error correction is further divided to obtain smaller data units, and RaidEcc error correction operations are performed on the data units to increase the error correction capability of RaidEcc.

[0013] Optionally, the to-be-corrected stripe unit is determined during the first RaidEcc error correction.

[0014] Optionally, the number of the data units selected in step S3 is one or more.

[0015] Optionally, the splicing data is spliced ​​according to a preset rule, and the preset rule includes:

[0016] The operation result obtained in the current cycle is concatenated with the data unit;

[0017] or concatenating the operation results obtained in all loop rounds with the data units that have not been selected;

[0018] Or the operation result obtained in the current cycle round is concatenated with the operation result or the data unit obtained in the previous cycle round.

[0019] Optionally, if decoding fails in step S5, the process returns to step S3 and the data unit reselected is a data unit that has not been selected.

[0020] Optionally, after the decoding fails in step S5 and before returning to step S3, the process further includes:

[0021] The stripe unit to be corrected in the Raid stripe is re-divided to obtain smaller data units; the data unit re-selected in step S3 is made for the smaller data unit.

[0022] Optionally, in step S5, if the decoding fails and the cycle round reaches a preset cutoff round, an SSD exception is output.

[0023] In a second aspect, the present invention provides a data reading and writing method, comprising:

[0024] In response to a data read command, data is read from NAND for LDPC decoding;

[0025] If LDPC decoding fails, enhanced error correction is performed using any enhanced error correction method described in any one of claims 1-7.

[0026] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium having computer program instructions stored thereon, which implement the steps of any of the above methods when executed by a processor.

[0027] In a fourth aspect, an embodiment of the present invention provides a solid-state drive, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any of the above methods when executing the computer program.

[0028] By adopting the above technical solution, the present application has the following beneficial effects:

[0029] An enhanced error correction method provided by the present invention utilizes the common LDPC and RaidEcc protection method of SSD. On the basis of RaidEcc error correction, the stripe unit of the Raid strip processed by RaidEcc error correction is further divided to obtain smaller data units, and RaidEcc error correction operation is performed on the data units to increase the error correction capability of RaidEcc; then, splicing is performed based on the operation results of the data units, and then LDPC decoding is performed, which adds protection measures when erroneous data exceeds the error correction capability and improves data stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0031] Figure 1 A schematic diagram showing the flow of data written and stored in an SSD provided by an embodiment of the present invention is shown;

[0032] Figure 2 A flowchart of an enhanced error correction method provided by an embodiment of the present invention is shown;

[0033] Figure 3 A schematic diagram showing a process of reading and writing SSD data provided by an embodiment of the present invention is shown;

[0034] Figure 4 A schematic diagram of steps S3-S5 provided in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0036] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the invention belongs.

[0037] like Figure 1 As shown, when data is stored in the SSD, when the amount of data aggregated reaches the amount of data that can be operated on the storage medium (nand flash) in one operation, data scrambling and LDPC encoding are performed, and the data is written to the storage medium; at the same time, RaidEcc operation is performed on the written data, and when the data reaches the Raid stripe, the RaidEcc data is written to the storage medium.

[0038] When reading data, read data from the storage medium, perform LDPC decoding, and descramble the data if the decoding is successful to obtain the required data. If LDPC decoding fails, perform basic error correction according to the characteristics of the storage medium. If successful, descramble the data to obtain the data. If basic error correction fails, perform RaidEcc error correction.

[0039] The current RaidEcc algorithms are mainly Raid5 and Raid6. The number of erroneous data that Raid5 can effectively protect is one error in one Raid stripe; the number of erroneous data that Raid6 can effectively protect is two errors in one Raid stripe. However, when the number of erroneous data exceeds the error correction capability of RaidEcc,

[0040] like Figure 2 As shown, in one embodiment, a method for enhancing error correction is provided, comprising:

[0041] S1. Read the Raid stripe to perform the first RaidEcc error correction. Figure 3 The application scenario of the enhanced error correction method provided in this embodiment is in the data reading process, that is, reading data from Nand after LDPC decoding fails. Step S1 is to perform RaidEcc error correction after LDPC decoding fails.

[0042] S2. When the error of the Raid stripe does not exceed the error correction capability of RaidEcc, read the data of other stripe units in the Raid stripe to recover the error data of the stripe unit to be corrected, and de-scramble the data after the error correction; when the error of the Raid stripe exceeds the error correction capability of RaidEcc, divide the stripe unit to be corrected in the Raid stripe into several data units.

[0043] In this step, different measures are taken according to whether the error data can be properly corrected by RaidEcc. When the error of the Raid strip does not exceed the error correction capability of RaidEcc, LDPC can be decoded successfully, and the successfully decoded data is sent to perform descrambling processing, and then the data is obtained by the host. When the error of the Raid strip exceeds the error correction capability of RaidEcc, step S1 performs RaidEcc error correction processing and still fails, and the following steps are performed at this time.

[0044] S3. Randomly select a data unit to perform a second RaidEcc error correction to obtain a calculation result.

[0045] See also Figure 4 The stripe unit to be corrected has been determined during the first RaidEcc error correction. In the case where the erroneous data in the stripe unit to be corrected exceeds the RaidEcc error correction capability, this step divides the stripe unit to be corrected into multiple data units, and then performs a second RaidEcc error correction on the data units to obtain the calculation result.

[0046] In this step, the number of data units selected for the second RaidEcc error correction is one or more.

[0047] Specifically, the data of a stripe unit is stored in DDR, and the selected data unit is taken out from DDR for RaidEcc error correction operation, and the operation result is put back to the original position after the operation. In an optional implementation, the size of the occupied DDR is the size of three stripe units, one for retaining the original data, one for splicing the operation result, and one for saving the spliced ​​data after the operation.

[0048] S4. Concatenate the operation result with the data unit to obtain concatenated data, and perform LDPC decoding on the concatenated data.

[0049] In this step, the splicing data is spliced ​​according to the preset rules, and the preset rules include:

[0050] The calculation result obtained in the current cycle is concatenated with the data unit;

[0051] Or the calculation results obtained in all loop rounds are concatenated with the unselected data units;

[0052] Or the operation result obtained in the current cycle round is concatenated with the operation result obtained in the previous cycle round or the data unit.

[0053] See also Figure 4 When the number of cycles is one, if the data units selected in step S3 are one or more, the operation results obtained by the operation of the data units and the data of the unselected data units are directly spliced ​​to obtain spliced ​​data, and the spliced ​​data is sent to LDPC decoding. If the LDPC decoding is successful, it is sent to descrambling processing.

[0054] When there are multiple cycles, the calculation results of the previous rounds can be selectively retained. For example, all / part of the calculation results of the previous rounds can be retained, and the calculation results of the current round and the remaining data units without retaining the calculation results are spliced. The preset rules are selected according to the actual situation.

[0055] S5. If the decoding is successful, the LDPC decoded data is descrambled; if the decoding fails, return to step S3.

[0056] The correctness of the data after the RaidEcc error correction operation cannot be known, and the purpose of the enhanced error correction method provided in this embodiment is to enable the LDPC decoding step to be successfully decoded. In order to avoid redundant processes, if the decoding fails in step S5, the data unit re-selected in step S3 is a data unit that has not been selected.

[0057] After the decoding fails in step S5 and before returning to step S3, the method further includes:

[0058] The stripe unit to be corrected in the Raid stripe is re-divided to obtain smaller data units; the data unit re-selected in step S3 is made for the smaller data unit.

[0059] If the Raid stripe is divided into smaller data units, the error correction capability of the RaidEcc operation will also be improved.

[0060] In actual application, if the decoding fails in step S5 and the loop round reaches the preset cutoff round, the SSD is abnormally output. If the preset cutoff round is reached and no data that can be successfully decoded by LDPC is obtained, the loop needs to be stopped.

[0061] In one embodiment, a data reading and writing method is also provided, comprising:

[0062] In response to a data read command, data is read from NAND for LDPC decoding;

[0063] If LDPC decoding fails, enhanced error correction is performed using the enhanced error correction method provided in the above embodiment.

[0064] Specifically, the data is based on Figure 3 Perform write and read processes.

[0065] Data write: Aggregate the data. When the aggregated data satisfies a nand flash write operation, enter the data encoding process, scramble the data, LDPC encode the data, write the LDPC encoded data to nand flash, and perform RaidEcc calculation while the data is written to nand flash. When a RaidEcc strip calculation is completed, write the RaidEcc data to nand flash.

[0066] Data reading: When a read command is received, data is read from the nand flash, and LDPC decoding is performed on the read data; if LDPC decoding is successful, data descrambling is performed to obtain the required data. If LDPC decoding fails, preliminary data error correction processing is performed, Retry, Soft decoding, if all fail, enter the RaidEcc error correction process. RaidEcc error correction is based on the number of errors in a written Raid stripe. If the number of errors is less than or equal to the RaidEcc error correction capability, the erroneous data is restored by reading other correct data in the Raid stripe. If the erroneous data is greater than the RaidEcc error correction capability, the enhanced error correction method provided in the above embodiment is used to perform enhanced error correction.

[0067] An embodiment of the present invention provides a computer-readable storage medium for storing computer program instructions used by the above-mentioned electronic device, which includes a program for executing the above-mentioned enhanced error correction method.

[0068] An embodiment of the present invention provides a solid state drive, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned enhanced error correction method when executing the computer program.

[0069] The above embodiments are only used to introduce the technical solutions of the present application in detail, but the description of the above embodiments is only used to help understand the methods of the embodiments of the present invention and should not be understood as limiting the embodiments of the present invention. Any changes or substitutions that can be easily thought of by technicians in this technical field should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for enhancing error correction, characterized in that: include: S1. Read the Raid stripe to perform the first RaidEcc error correction; S2. When the error of the Raid strip does not exceed the error correction capability of RaidEcc, the data of other stripe units in the Raid stripe are read to restore the error data of the stripe unit to be corrected, and the error correction data is descrambled; When the error of the Raid strip exceeds the error correction capability of RaidEcc, the strip unit to be corrected in the Raid strip is split to obtain a number of data units; S3 randomly selects the data unit for a second RaidEcc error correction to obtain the calculation result; S4. Splicing the operation result with the data unit to obtain spliced ​​data, and performing LDPC decoding on the spliced ​​data; The number of the data units selected in step S3 is one or more; The splicing data is spliced ​​according to a preset rule, and the preset rule includes: The operation result obtained in the current cycle is concatenated with the data unit; or concatenating the operation results obtained in all loop rounds with the data units that have not been selected; or the operation result obtained in the current cycle round is concatenated with the operation result or the data unit obtained in the previous cycle round; S5. If the decoding is successful, the data successfully decoded by LDPC is descrambled; if the decoding fails, return to step S3; if the decoding fails in step S5, return to step S3 to reselect the data unit that has not been selected; after the decoding fails in step S5 and before returning to step S3, it also includes: re-dividing the stripe unit to be corrected in the Raid stripe to obtain smaller data units; the data unit reselected by returning to step S3 is made for smaller data units.

2. The method according to claim 1, characterized in that The to-be-corrected stripe unit is determined during the first RaidEcc error correction.

3. The method according to claim 1, characterized in that In step S5, if the decoding fails and the cycle round reaches the preset end round, an SSD exception is output.

4. A data reading and writing method, characterized in that: include: In response to a data read command, data is read from NAND for LDPC decoding; If LDPC decoding fails, enhanced error correction is performed using any enhanced error correction method described in any one of claims 1 to 3.

5. A storage medium having a computer program stored thereon, characterized in that: The computer program is used to execute the steps of the method according to any one of claims 1 to 4.

6. A solid state drive comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

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