System and method for secure transmission of fc data at high speed ports

Abstract

The application provides a system and method for safe transmission of FC data through high-speed port, which comprises: a high-speed port for receiving data and generating a high-speed port recovery clock, and transmitting the received data to a data transceiver module in the high-speed port recovery clock domain; and the data transceiver module for converting the data into output data in the local logic clock domain; wherein the data transceiver module comprises a data storage area, a write control module and a read control module; the data storage area is composed of two clock domains: the write direction adopts the high-speed port recovery clock, and the input data is the high-speed port received data; and the read direction adopts the local logic clock, and is used for controlling the output of the data storage area to a subsequent logic module. The data storage area is configured with an overflow area, an underflow area and an equalization area, and the input and output enables of the fifo are accurately controlled through the data amount cached in the fifo and the current input and output fifo data stream content, so as to ensure the correct transmission of effective data and the normal work of the fifo.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FC network communication technology, in particular to a system and method for safe transceiving of FC data through high-speed port, which can be applied to FC daughter card or FC switch. BACKGROUND

[0002] FC (Fibre Channel, for short, FC) network is a network communication standard proposed by American National Standards Institute (ANSI) in 1988, aiming to solve the problem of internal high-speed data communication of airborne data bus in the application background of aviation and aerospace. FC network is a standard-based network structure, which has the dual advantages of channel and network, so that the current mainstream channel standards and network protocols can be run on the same physical interface. The huge data throughput makes it possible to realize the massive data transmission between different systems, and the same device can be used to establish any topology to meet different connection characteristics, such as point-to-point communication network, arbitration ring communication network, switching network, etc., to realize high-speed communication between node devices, etc.

[0003] In the FC communication topology structure, the node device is usually configured with one or more fiber channel ports (FC ports) to access the FC network. In the FC switch or FC daughter card, high-speed port is often used for data transceiving. In order to ensure the normal transceiving of data, the clock domain design usually adopted is:

[0004] Receiving direction: the recovered clock of high-speed port is used for data receiving;

[0005] Sending direction: the logic clock is used for data sending.

[0006] The recovered clock comes from the frequency collection of received data, that is, it is related to the sending clock frequency of the data sending end; the sending clock comes from the reference clock of the device. Because the sources of the recovered clock and the reference clock of the board are different, the problem of cross-clock domain needs to be considered in the high-speed port of the device.

[0007] In the traditional system design, the cross clock domain is usually implemented in two ways: in the destination clock domain, and using fifo for cross clock. But we found in the actual board test verification process, the receiving direction of the recovery clock and the sending direction of the logical clock frequency exist a small difference, when using the traditional cross clock domain scheme, when the device is in long time persistence transceiver work, the data loss or data increase will occur. The reason is that in the traditional operation of the clock, when the device is running for a long time, with the accumulation of time, the slight difference of clock frequency will cause the destination clock domain clock to collect the source clock domain clock data in a certain clock, resulting in error; when using the traditional fifo for cross clock domain, when the device is running for a long time, with the accumulation of time, the slight difference of clock frequency will cause the fifo to appear empty state or full state, resulting in abnormal fifo readout data. When the data anomaly occurs in the valid data interval, it will cause the error transmission of valid data. SUMMARY

[0008] In view of the defects and deficiencies of the prior art, according to the first aspect of the purpose of the application, a high-speed port safe transceiving FC data system is provided, comprising:

[0009] The high-speed port safe transceiving FC data system comprises:

[0010] The high-speed port is configured to receive data and generate a high-speed port recovery clock, and transmit the received data to the data transceiver module in the high-speed port recovery clock domain;

[0011] The data transceiver module is configured to receive the data transmitted by the high-speed port, convert the data into output data in the local logic clock domain, and transmit the output data to the subsequent logic module;

[0012] The data transceiver module comprises a data storage area, a write control module and a readout control module:

[0013] The data storage area is composed of two clock domains: the write direction uses the high-speed port recovery clock to control the high-speed port to receive data and write the data into the data storage area, and the input data is the high-speed port received data; the readout direction uses the local logic clock to control the output of the data storage area to the subsequent logic module for use by the subsequent logic module;

[0014] The data storage area is configured with an overflow water line and an underflow water line, and the entire data storage area is divided into three parts according to the overflow water line and the underflow water line value, the part above the overflow water line is the overflow area, the part below the underflow water line is the underflow area, and the area between the overflow water line and the underflow water line is the balanced area.

[0015] According to the second aspect of the present application, a high-speed port safe transceiving FC data method is provided, comprising the following steps:

[0016] Step one, the high-speed port receives data sent by the opposite end based on the FC network, generates a high-speed port recovery clock, and sends the received data to the write control module based on the high-speed port recovery clock;

[0017] Step two, the data storage area data volume is in the underflow area, the write module write enable signal is pulled high, the high-speed port received data is continuously written into the data storage area, the readout control module is closed, and the readout control module outputs an IDLE signal to the subsequent logic processing module;

[0018] Step three, the data storage area gradually increases the data volume stored with the increase of the write-in, when the data storage area reaches the equilibrium area, the write module write enable signal is high, the high-speed port received data is continuously written into the data storage area, the readout control module is pulled high, and the readout control module outputs the data of the data storage area to the subsequent logic processing module;

[0019] Step four, with the increase of the working time, if the data volume of the data storage area decreases to the underflow line, the readout control module detects the readout data of the data storage area, when the readout data is in the valid data interval, the readout enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out; when the readout data of the data storage area is IDLE, the readout enable signal of the data storage area is pulled low, and an IDLE signal is output to the subsequent logic module, until the data volume of the data storage area returns to the equilibrium area, and the readout enable signal is pulled high again;

[0020] If the data volume of the data storage area increases to the overflow line, the write control module detects the high-speed port output data, when the high-speed port received data is in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; when the high-speed port received data is IDLE, the write enable signal of the data storage area is pulled low, until the data volume of the data storage area returns to the equilibrium area, and the write enable signal is pulled high again;

[0021] Step four is repeatedly performed until the data transmission is completed.

[0022] According to the third aspect of the present application, a high-speed port safe transceiving FC data method is provided, comprising the following steps:

[0023] Step one, the high-speed port receives data sent by the opposite end based on the FC network, generates a high-speed port recovery clock, and sends the received data to the write control module based on the high-speed port recovery clock;

[0024] Step two, at this time, the data amount in the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port continuously receives data and writes the data into the data storage area; the read enable of the read control module is closed, and the read module outputs an IDLE signal to the subsequent logic processing module;

[0025] Step three, the data amount in the data storage area gradually increases to the equilibrium area, the write enable signal of the write control module is high, the high-speed port continuously receives data and writes the data into the data storage area; the read enable of the read control module is pulled high, and the read control module outputs the data in the data storage area to the subsequent logic processing module;

[0026] Step four, when the clock frequency of the high-speed port is less than the logic clock frequency of the board, that is, the writing speed of data is lower than the reading speed of data, with the increase of working time, the data amount in the data storage area gradually decreases to the underflow line, and the read control module detects the read data in the data storage area:

[0027] When the read data is in the valid data interval, the read enable signal of the data storage area is kept high, that is, the valid data value in the data storage area is continuously read out;

[0028] When the read data in the data storage area is IDLE, the read enable signal of the data storage area is pulled low, and an IDLE signal is output to the subsequent logic module, until the data amount in the data storage area returns to the equilibrium area, and then the read enable signal is pulled high again;

[0029] Step four is repeatedly performed until the data transmission is completed.

[0030] According to a fourth aspect of the object of the application, a high-speed port safe transceiving FC data method is provided, comprising the following steps:

[0031] Step one, the high-speed port receives data sent by the opposite end, generates a high-speed port recovery clock, and transmits the data to the write control module based on the high-speed port recovery clock;

[0032] Step two, at this time, the data amount in the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port continuously receives data and writes the data into the data storage area; the read enable of the read control module is closed, and the read module outputs an IDLE signal to the subsequent logic processing module;

[0033] Step three, the data amount in the data storage area gradually increases to the equilibrium area, the write enable signal of the write control module is high, the high-speed port continuously receives data and writes the data into the data storage area; the read enable of the read control module is pulled high, and the read control module outputs the data in the data storage area to the subsequent logic processing module;

[0034] Step four, when the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, that is, the writing data speed is higher than the reading data speed, with the increase of working time, the data amount of the data storage area gradually increases to the overflow line, the high-speed port output data is detected by the writing control module:

[0035] When the high-speed port receives data in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written to the data storage area;

[0036] When the high-speed port receives data as IDLE, the write enable signal of the data storage area is pulled low until the data amount of the data storage area returns to the balance area, and then the write enable signal is pulled high;

[0037] Step four is repeatedly until the data transmission is completed.

[0038] According to the fifth aspect of the object of the application, a high-speed port safe transceiving FC data method is provided, comprising the following steps:

[0039] Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and sends the data to the writing control module based on the high-speed port recovery clock;

[0040] Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the writing control module is pulled high, the high-speed port receives data is continuously written to the data storage area; the readout control module is closed, and the readout control module outputs the IDLE signal to the subsequent logic processing module;

[0041] Step three, the data amount stored in the data storage area gradually increases to the balance area, the write enable signal of the writing control module is pulled high, the high-speed port receives data is continuously written to the data storage area; the readout control module is pulled high, and the readout module outputs the data of the data storage area to the subsequent logic processing module;

[0042] Step four, since the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, that is, the writing data speed is equal to the reading data speed, the data amount of the data storage area will remain in the balance area, and the read and write enable signals of the data storage area are pulled high at the same time until the data transmission is completed.

[0043] In combination with the above embodiments of the present application, the system and method for safe FC data transmission and reception of high-speed port according to the present application optimizes the traditional fifo design, designs the overflow pipeline and underflow pipeline, configures the overflow area, underflow area and balance area, and precisely controls the input and output enable of fifo through the data amount buffered in fifo and the data stream content of current input and output fifo, to ensure the correct transmission of effective data and the normal work of fifo. Through the board verification, when there is a difference between the recovery clock and the logic clock of the board, long time data transmission and reception can be ensured to ensure the effective and safe transmission of effective data.

[0044] It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter. Additionally, all combinations of claimed subject matter are contemplated as part of the inventive subject matter.

[0045] For a more complete understanding of the present teachings and their features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings in which: BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical, or nearly identical, component that is illustrated in various figures is represented with a like numeral. For purposes of clarity, not every component is called out in every drawing. Embodiments of various aspects of the present teachings are now described in detail with reference to the drawings.

[0047] Figure 1 is a schematic diagram of an FC data stream structure according to an embodiment of the present application.

[0048] Figure 2 is a schematic diagram of a system for safe FC data transmission and reception of high-speed port according to an embodiment of the present application.

[0049] Figure 3 is a schematic diagram of a data storage area in a system for safe FC data transmission and reception of high-speed port according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] For a more complete understanding of the present teachings and their features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings in which:

[0051] Aspects of the present application are described in the disclosure with reference to the accompanying drawings, in which a number of illustrative embodiments are shown. The described embodiments of the disclosure are not meant to include all aspects of the present application. It should be understood that various concepts and embodiments introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the disclosed concepts and embodiments are not limited to any one implementation. Additionally, some aspects of the present disclosure can be used independently of other aspects of the present disclosure, for any suitable purpose.

[0052] System for safe FC data transceiving of high-speed port

[0053] Combination Figure 1 , 2 , 3, the system for safe FC data transceiving of high-speed port according to the embodiment of the present application comprises a high-speed port, a data transceiving module and a subsequent logic module.

[0054] The high-speed port is configured to receive data and generate a high-speed port recovery clock, and deliver the received data to the data transceiving module in the high-speed port recovery clock domain.

[0055] The data transceiving module is configured to receive the data delivered by the high-speed port, convert the data into output data in the local logic clock domain, and deliver the output data to the subsequent logic module.

[0056] Combination Figure 3 As shown in the figure, the data transceiving module comprises a data storage area, a write control module and a read control module.

[0057] The data storage area is composed of two clock domains: the write direction adopts the high-speed port recovery clock, which is used to control the high-speed port to receive data and write the data into the data storage area, and the input data is the high-speed port received data; the read direction adopts the local logic clock, which is used to control the output of the data storage area to the subsequent logic module for use by the subsequent logic module.

[0058] The data storage area is configured with an upper overflow pipeline and a lower overflow pipeline, and the entire data storage area is divided into three parts according to the values of the upper overflow pipeline and the lower overflow pipeline, the part exceeding the upper overflow pipeline is the upper overflow area, the part below the lower overflow pipeline is the lower overflow area, and the area between the upper overflow pipeline and the lower overflow pipeline is the balanced area.

[0059] As an optional embodiment, the upper overflow area, the lower overflow area and the balanced area are all configured to store at least one frame of FC data. The upper overflow pipeline is set to the total storage amount of the data storage area minus 2148B, and the lower overflow pipeline is set to 2148B, thereby dividing the upper overflow area and the lower overflow area. Further, the storage amount between the upper overflow pipeline and the lower overflow pipeline is the uniform area.

[0060] Combination Figure 1The FC data flow structure in transmission is shown. According to the FC protocol, the FC data flow in transmission contains valid data and invalid data.

[0061] The valid data is all data except the IDLE primitive, including data frames, clock primitives, RRDY, OLS, NOS, LR, LRR, etc.

[0062] The invalid data is the IDLE primitive.

[0063] It is stipulated in the FC protocol that the valid data frame length ranges from 36 to 2148B, and there is at least a 6-primitive signal containing IDLE between data frames.

[0064] Data read and write control

[0065] Combination Figure 2 , 3 As shown, the data transceiver module contains a data storage area, a write control module and a read control module.

[0066] The data storage area is composed of two clock domains, the write direction adopts a high-speed port recovery clock, and the input data is high-speed port received data. The read direction adopts a board logic clock, and the output data is transmitted to a subsequent logic module for use.

[0067] According to the upper overflow pipeline and the lower overflow pipeline value, the entire data storage area is divided into three parts, the part exceeding the upper overflow pipeline is the upper overflow area, the part below the lower overflow pipeline is the lower overflow area, and the area between the upper and lower overflow pipelines is the balanced area.

[0068] In the embodiment of the present application, considering that the valid data frame of the FC frame is at most 2148B, the upper overflow area, the lower overflow area and the balanced area all need to be able to store at least one frame of data, so the effective storage capacity of the data storage area is set to be greater than or equal to 6444B (i.e. 2148B*3).

[0069] Upper overflow pipeline configuration:

[0070] Since the valid data frame of the FC frame is at most 2148B, when the data storage area capacity is at the upper overflow pipeline, if the input data is exactly at the beginning of the valid data at this time, in order to ensure the continuity of the valid data, the write control module will continuously pull up the write enable signal. In this extreme case, the design of the upper overflow pipeline needs to ensure that the upper overflow area can store at least one frame of data, so in the embodiment of the present application, the upper overflow pipeline is designed as the total storage amount of the data storage area minus 2148B.

[0071] Upper overflow pipeline configuration:

[0072] Since the maximum effective data frame of an FC frame is 2148B, when the data storage area capacity is at the overflow line, if the data to be read from the data storage area happens to be at the beginning of the effective data, in order to ensure the continuity of the effective data, the read control module will continuously pull the read enable signal high. In this extreme case, the overflow line design must ensure that the overflow area can store at least one data frame. Therefore, in the embodiment of the present invention, the overflow line is designed to be 2148B.

[0073] Write control

[0074] Combination Figure 2 , 3 In the example shown, the write control module is configured to control the writing of high-speed port received data to the data storage area in the high-speed port recovery clock domain, wherein:

[0075] When the amount of data in the data storage area is in the balanced area or the underflow area, keep the write enable signal of the data storage area high, that is, continuously write data to the data storage area;

[0076] When the data volume in the data storage area is in the overflow area, invalid data input from the high-speed port will be removed and not written to the data storage area until the data volume in the data storage area is restored to the balanced area, at which point the data writing enable of the data storage area will be restored.

[0077] As an example, the specific operation for writing control is as follows:

[0078] When the amount of data in the data storage area is in the balanced area or the underflow area, the write enable signal of the data storage area is kept high, that is, data is continuously written to the data storage area. This written data includes valid data and invalid data received by the high-speed port.

[0079] When the amount of data in the data storage area is higher than the overflow line, that is, when the amount of data is in the overflow area of ​​the data storage area, the write enable signal of the data storage area is kept high when the data received at the high-speed port is in the valid data range, that is, valid data values ​​are written to the data storage area; when the data received at the high-speed port is in the invalid data range, that is, when the data received at the high-speed port is the IDLE value, the write enable signal of the data storage area is pulled low, that is, invalid data IDLE values ​​are not stored in the data storage area, until the amount of data in the data storage area is restored to the balanced range.

[0080] Readout control

[0081] Combination Figure 3 The readout control module is configured to control the output of data from the data storage area to subsequent logic modules within the logic clock domain of this board, wherein:

[0082] When the data amount of the data storage area is in the balanced zone or the overflow zone, the read enable signal of the data storage area is kept high, i.e. the data stored in the data storage area is continuously output to the subsequent logic module;

[0083] When the data amount of the data storage area is in the underflow zone, when the read data of the data storage area is in the non-valid data area, the read enable signal is pulled low, i.e. the data of the data storage area is not read out, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balanced zone, and then the data read enable of the data storage area is restored.

[0084] As an example, the specific operation is as follows:

[0085] When the data amount of the data storage area is in the balanced zone or the overflow zone, the read enable signal of the data storage area is kept high, i.e. the data of the data storage area is continuously read out, and the read-out data contains valid data and non-valid data.

[0086] When the data amount of the data storage area is lower than the underflow pipeline, i.e. the data amount is in the underflow zone of the data storage area, when the read data of the data storage area is in the valid data interval, the read enable signal of the data storage area is kept high, i.e. the valid data value of the data storage area is continuously read out; when the read data of the data storage area is in the non-valid data interval, i.e. the read data of the data storage area is the IDLE value, the read enable signal of the data storage area is pulled low, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balanced zone.

[0087] Method for safe transceiving FC data through high-speed port

[0088] In combination with Figure 2 , 3 As shown in the figures, the system and method for safe transceiving FC data through high-speed port based on the foregoing embodiments include the following steps:

[0089] Step one, the high-speed port receives data sent by the opposite end based on the FC network, generates a high-speed port recovery clock, and based on the high-speed port recovery clock, the received data is transmitted to the write control module;

[0090] Step two, when the data amount of the data storage area is in the underflow zone, the write enable signal of the write module is pulled high, and the high-speed port receives data continuously written into the data storage area; the read control module closes the read enable, and the read control module outputs the IDLE signal to the subsequent logic processing module;

[0091] Step three, the data storage area gradually increases the amount of data stored as the increase of write, when the data storage area reaches the equilibrium zone, the write enable signal of the write module is high, the high-speed port receives data continuously writes the data storage area; the readout control module pulls up the readout enable, and the readout control module outputs the data of the data storage area to the subsequent logic processing module;

[0092] Step four, with the increase of working time, if the amount of data in the data storage area decreases to the lower overflow line, the readout control module detects the readout data of the data storage area, when the readout data is in the valid data interval, the readout enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out; when the readout data of the data storage area is IDLE, the readout enable signal of the data storage area is pulled down, and an IDLE signal is output to the subsequent logic module, until the amount of data in the data storage area recovers to the equilibrium zone, and then the readout enable signal is pulled up again;

[0093] If the amount of data in the data storage area increases to the upper overflow line, the write control module detects the high-speed port output data, when the high-speed port receives data is in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written to the data storage area; when the high-speed port receives data is IDLE, the write enable signal of the data storage area is pulled down, until the amount of data in the data storage area recovers to the equilibrium zone, and then the write enable signal is pulled up again;

[0094] Step four is repeated until the data transmission is completed.

[0095] Therefore, according to the high-speed port data safe transceiving method of the above scheme, it can be applied to four cases that the high-speed port recovery clock frequency is less than the logic clock frequency of the board, the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, and the high-speed port recovery clock frequency is unstable. Through the accurate control of the input and output enable of the fifo by the amount of data buffered in the fifo and the current input and output fifo data stream content, the correct transmission of valid data and the normal work of the fifo are ensured, and the effective and safe transceiving of data is realized.

[0096] When the high-speed port recovery clock frequency is less than the logic clock frequency of the board, the working mode of the foregoing system is as follows:

[0097] Step one, the high-speed port receives the data sent by the opposite side, generates a high-speed port recovery clock, and based on the high-speed port recovery clock, the data is transmitted to the write control module;

[0098] Step two, at this time the data storage area data volume is in the underflow area, the write control module write enable signal is pulled high, the high-speed port receives data continuously writes into the data storage area; the readout control module closes the readout enable, the readout module outputs the IDLE signal to the subsequent logic processing module;

[0099] Step three, the data storage area data volume gradually increases to the equilibrium area, the write control module write enable signal is high, the high-speed port receives data continuously writes into the data storage area; the readout control module pulls up the readout enable, the readout control module outputs the data storage area data to the subsequent logic processing module;

[0100] Step four, when the high-speed port recovery clock frequency is less than the logic clock frequency of the board, that is, the write data speed is lower than the readout data speed, with the increase of working time, the data volume of the data storage area gradually decreases to the underflow line, the readout control module detects the readout data of the data storage area:

[0101] When the readout data is in the valid data interval, the readout enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out;

[0102] When the readout data of the data storage area is IDLE, the readout enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module, until the data volume of the data storage area recovers to the equilibrium area, and the readout enable signal is pulled up again;

[0103] Step four is repeatedly until the data transmission is completed.

[0104] When the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, the working mode of the foregoing system is as follows:

[0105] Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and based on the high-speed port recovery clock, the data is transmitted to the write control module;

[0106] Step two, at this time the data storage area data volume is in the underflow area, the write control module write enable signal is pulled high, the high-speed port receives data continuously writes into the data storage area; the readout control module closes the readout enable, the readout control module outputs the IDLE signal to the subsequent logic processing module;

[0107] Step three, the data storage area data volume gradually increases to the equilibrium area, the write control module write enable signal is high, the high-speed port receives data continuously writes into the data storage area; the readout control module pulls up the readout enable, the readout control module outputs the data storage area data to the subsequent logic processing module;

[0108] Step four, when the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, that is, the write data speed is higher than the read data speed, as the working time increases, the data storage area data gradually increases to the overflow line, and the write control module detects the high-speed port output data:

[0109] When the high-speed port receives data in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written to the data storage area;

[0110] When the high-speed port receives data as IDLE, the write enable signal of the data storage area is pulled low until the data amount of the data storage area returns to the balance area, and then the write enable signal is pulled high;

[0111] Step four is repeatedly performed until the data transmission is completed.

[0112] When the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, the working mode of the foregoing system is as follows:

[0113] Step one, the high-speed port receives data sent by the opposite end, generates a high-speed port recovery clock, and sends data to the write control module based on the high-speed port recovery clock;

[0114] Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port receives data and continuously writes the data into the data storage area; the read enable signal of the read control module is closed, and the read control module outputs an IDLE signal to the subsequent logic processing module;

[0115] Step three, the data amount stored in the data storage area gradually increases to the balance area, the write enable signal of the write control module is pulled high, the high-speed port receives data and continuously writes the data into the data storage area; the read enable signal of the read control module is pulled high, and the read module outputs the data of the data storage area to the subsequent logic processing module;

[0116] Step four, since the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, that is, the write data speed is equal to the read data speed, the data amount of the data storage area will remain in the balance area, and the read and write enable signals of the data storage area are pulled high at the same time until the data transmission is completed.

[0117] When the high-speed port recovery clock frequency is unstable, the working mode of the foregoing system is as follows:

[0118] Step one, the high-speed port receives data sent by the opposite end, generates a high-speed port recovery clock, and sends data to the write control module based on the high-speed port recovery clock;

[0119] Step two, the data storage area data volume is in the underflow area, the write-in module write-in enable signal is pulled high, the high-speed port receives data is continuously written into the data storage area; the read-out control module closes the read-out enable, the read-out control module outputs the IDLE signal to the subsequent logic processing module;

[0120] Step three, the data storage area gradually increases the data volume stored with the increase of the write-in, when the data storage area stores the data reaching the equilibrium area, the write-in module write-in enable signal is high, the high-speed port receives data continuously writes into the data storage area; the read-out control module pulls up the read-out enable, the read-out control module outputs the data of the data storage area to the subsequent logic processing module;

[0121] Step four, with the increase of the working time, if the data volume of the data storage area reduces to the underflow line, the read-out control module detects the read-out data of the data storage area, when the read-out data is the valid data interval, the read-out enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out; when the read-out data of the data storage area is IDLE, the read-out enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module, until the data volume of the data storage area recovers to the equilibrium area, the read-out enable signal is pulled up again;

[0122] If the data volume of the data storage area increases to the overflow line, the write-in control module detects the high-speed port output data, when the high-speed port receives data is the valid data interval, the write-in enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; when the high-speed port receives data is IDLE, the write-in enable signal of the data storage area is pulled down, until the data volume of the data storage area recovers to the equilibrium area, the write-in enable signal is pulled up again;

[0123] Step four is repeatedly until the data transmission is completed.

[0124] Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Those skilled in the art without departing from the spirit and scope of the present application can make various modifications and decorations. Therefore, the protection scope of the present application is defined by the claims.

Claims

1. A system for secure transmission of FC data at high speed, characterized in that, The system comprises: a high-speed port configured to receive data and generate a high-speed port recovery clock, and transmit the received data to a data transceiver module in the high-speed port recovery clock domain; a data transceiver module configured to receive the data transmitted by the high-speed port, convert the data into output data in the local logic clock domain, and transmit the output data to a subsequent logic module; wherein the data transceiver module comprises a data storage area, a write control module, and a read control module: the data storage area is composed of two clock domains: a write direction using the high-speed port recovery clock to control the high-speed port to receive data and write the data into the data storage area, and the input data being the high-speed port received data; and a read direction using the local logic clock to control the data storage area to output data to the subsequent logic module for use by the subsequent logic module; the data storage area is configured with an upper overflow line and a lower overflow line, and the entire data storage area is divided into three parts according to the values of the upper overflow line and the lower overflow line, the part above the upper overflow line being an overflow area, the part below the lower overflow line being an underflow area, and the area between the upper overflow line and the lower overflow line being an equilibrium area; wherein the system for safely transmitting and receiving FC data through the high-speed port is applicable to FC data transmission and reception in four cases: the high-speed port recovery clock frequency being less than the local logic clock frequency, the high-speed port recovery clock frequency being greater than the local logic clock frequency, the high-speed port recovery clock frequency being equal to the local logic clock frequency, and the high-speed port recovery clock frequency being unstable, precise control of the input and output enables of the fifo is achieved by the amount of data buffered in the fifo and the current input and output data flow contents of the fifo, correct transmission of valid data and normal operation of the fifo are ensured, effective and safe transmission and reception of data are achieved, and the system specifically comprises: (1) when the high-speed port recovery clock frequency is less than the local logic clock frequency, the system works as follows: Step one: the high-speed port receives data sent by the opposite end, generates a high-speed port recovery clock, and transmits the data to the write control module based on the high-speed port recovery clock; Step two: at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port received data is continuously written into the data storage area, and the read control module closes the read enable, and the read module outputs an IDLE signal to the subsequent logic processing module; Step three: the data amount of the data storage area gradually increases to the equilibrium area, the write enable signal of the write control module is high, the high-speed port received data is continuously written into the data storage area, and the read control module pulls up the read enable, and the read control module outputs the data of the data storage area to the subsequent logic processing module; Step four: when the high-speed port recovery clock frequency is less than the local logic clock frequency, that is, the write data speed is lower than the read data speed, the data amount of the data storage area gradually decreases to the lower overflow line with the increase of the working time, and the read control module detects the read data of the data storage area: when the read data is in the valid data interval, the read enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out. When the read data of the data storage area is IDLE, the read enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balance area, and then the read enable signal is pulled up again; Step four is repeatedly performed until the data transmission is completed; (2) When the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, the system works as follows: Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and transmits the data to the write control module based on the high-speed port recovery clock; Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled up, and the high-speed port continuously writes the received data into the data storage area; the read enable signal of the read control module is closed, and the IDLE signal of the read control module is output to the subsequent logic processing module; Step three, the data amount of the data storage area gradually increases to the balance area, the write enable signal of the write control module is high, and the high-speed port continuously writes the received data into the data storage area; the read enable signal of the read control module is pulled up, and the data of the data storage area is output to the subsequent logic processing module by the read control module; Step four, when the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, that is, the write data speed is higher than the read data speed, as the working time increases, the data amount of the data storage area gradually increases to the overflow line, and the write control module detects the high-speed port output data: When the high-speed port receives the data in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; When the high-speed port receives the IDLE data, the write enable signal of the data storage area is pulled down until the data amount of the data storage area returns to the balance area, and then the write enable signal is pulled up again; Step four is repeatedly performed until the data transmission is completed; (3) When the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, the system works as follows: Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and transmits the data to the write control module based on the high-speed port recovery clock; Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled up, and the high-speed port continuously writes the received data into the data storage area; the read enable signal of the read control module is closed, and the IDLE signal of the read control module is output to the subsequent logic processing module; Step three, the data amount of the data storage area gradually increases to the balance area, the write enable signal of the write control module is high, and the high-speed port continuously writes the received data into the data storage area; the read enable signal of the read control module is pulled up, and the data of the data storage area is output to the subsequent logic processing module by the read control module; Step four, since the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, that is, the write data speed is equal to the read data speed, the data amount of the data storage area will remain in the balance area, and the read and write enable signals of the data storage area are pulled up at the same time until the data transmission is completed; (4) When the high-speed port recovery clock frequency is unstable, the system works as follows: Step one, high-speed port based on FC network receives data sent by the opposite end, generates high-speed port recovery clock, and based on high-speed port recovery clock, the received data is transported to the write control module; Step two, the data storage area data volume is in the underflow area, the write module write enable signal is pulled high, the high-speed port receives data is continuously written into the data storage area; the readout control module closes the readout enable, and the readout control module outputs the IDLE signal to the subsequent logic processing module; Step three, the data storage area gradually increases the data volume stored with the increase of the write-in, when the data storage area stores the data reaches the equilibrium area, the write module write enable signal is high, the high-speed port receives data continuously writes into the data storage area; the readout control module pulls up the readout enable, and the readout control module outputs the data of the data storage area to the subsequent logic processing module; Step four, with the increase of the working time, if the data volume of the data storage area decreases to the underflow line, the readout control module detects the readout data of the data storage area, when the readout data is the valid data interval, the readout enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out; when the readout data of the data storage area is IDLE, the readout enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module, until the data volume of the data storage area recovers to the equilibrium area, and then the readout enable signal is pulled up again; If the data volume of the data storage area increases to the overflow line, the write control module detects the high-speed port output data, when the high-speed port receives data is the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; when the high-speed port receives data is IDLE, the write enable signal of the data storage area is pulled down, until the data volume of the data storage area recovers to the equilibrium area, and then the write enable signal is pulled up again; Step four is repeatedly performed until the data transmission is completed.

2. The system for secure FC data transmission and reception at high speed according to claim 1, wherein, The overflow area, the underflow area and the equilibrium area are configured to store at least one frame of FC data.

3. The system for secure FC data transmission and reception at high speed according to claim 1, wherein, The overflow line is set to the total storage amount of the data storage area minus 2148B.

4. The system for secure FC data transmission and reception at high speed according to claim 1, wherein, The underflow line is set to 2148B.

5. The system for secure FC data transmission of high-speed ports according to claim 1, wherein, The write control module is arranged to control the high-speed port receiving data to write into the data storage area in the high-speed port recovery clock domain, wherein: When the data volume of the data storage area is in the equilibrium area or the underflow area, the write enable signal of the data storage area is kept high, that is, the data is continuously written into the data storage area; When the data volume of the data storage area is in the overflow area, the non-valid data input by the high-speed port is rejected, and is not written into the data storage area, until the data volume of the data storage area recovers to the equilibrium area, and then the data write enable of the data storage area is restored.

6. The system for secure FC data transmission of high-speed ports according to claim 1, wherein, The readout control module is arranged to control the data in the data storage area to be output to the subsequent logic module in the board logic clock domain, wherein: When the data volume of the data storage area is in the equilibrium area or the overflow area, the readout enable signal of the data storage area is kept high, that is, the data stored in the data storage area is continuously output to the subsequent logic module; When the data volume of the data storage area is in the equilibrium area or the overflow area, the readout enable signal of the data storage area is kept high, that is, the data stored in the data storage area is continuously output to the subsequent logic module; When the data amount of the data storage area is in the underflow region, when the read data of the data storage area is in the invalid data region, the read enable is pulled down, that is, the data read of the data storage area is disabled, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balance region, and then the data read enable of the data storage area is recovered.

7. The method for securely transmitting and receiving FC data at a high-speed port according to any one of claims 1-6, characterized in that, The method comprises: Step one, the high-speed port receives data sent by the opposite end based on the FC network, generates a high-speed port recovery clock, and sends the received data to the write control module based on the high-speed port recovery clock; Step two, when the data amount of the data storage area is in the underflow region, the write enable signal of the write module is pulled up, and the received data is continuously written into the data storage area; the read control module closes the read enable, and the read control module outputs the IDLE signal to the subsequent logic processing module; Step three, as the data amount stored in the data storage area increases with the increase of the write-in, when the data amount stored in the data storage area reaches the balance region, the write enable signal of the write module is high, and the received data is continuously written into the data storage area; the read control module pulls up the read enable, and the read control module outputs the data of the data storage area to the subsequent logic processing module; Step four, as the working time increases, if the data amount of the data storage area decreases to the underflow line, the read data of the data storage area is detected by the read control module, when the read data is in the valid data interval, the read enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read; when the read data of the data storage area is IDLE, the read enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balance region, and then the read enable signal is pulled up again; If the data amount of the data storage area increases to the overflow line, the write control module detects the data output by the high-speed port, when the received data is in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; when the received data is IDLE, the write enable signal of the data storage area is pulled down until the data amount of the data storage area returns to the balance region, and then the write enable signal is pulled up again; Step four is repeatedly performed until the data transmission is completed.

8. A method of transmitting and receiving FC data through a high-speed port of a system for transmitting and receiving FC data through a high-speed port according to any one of claims 1 to 6, characterized by, The method comprises: Step one, the high-speed port receives data sent by the opposite end, generates a high-speed port recovery clock, and sends the data to the write control module based on the high-speed port recovery clock; Step two, at this time, the data amount of the data storage area is in the underflow region, the write enable signal of the write control module is pulled up, the received data is continuously written into the data storage area, the read control module closes the read enable, and the read module outputs the IDLE signal to the subsequent logic processing module; Step three, the data amount of the data storage area gradually increases to the balance region, the write enable signal of the write control module is high, the received data is continuously written into the data storage area, the read control module pulls up the read enable, and the read control module outputs the data of the data storage area to the subsequent logic processing module; Step four, as the working time increases, if the data amount of the data storage area decreases to the underflow line, the read data of the data storage area is detected by the read control module, when the read data is in the valid data interval, the read enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read; when the read data of the data storage area is IDLE, the read enable signal of the data storage area is pulled down, and the IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balance region, and then the read enable signal is pulled up again; If the data amount of the data storage area increases to the overflow line, the write control module detects the data output by the high-speed port, when the received data is in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; when the received data is IDLE, the write enable signal of the data storage area is pulled down until the data amount of the data storage area returns to the balance region, and then the write enable signal is pulled up again; Step four is repeatedly performed until the data transmission is completed. Step four, when the high-speed port recovery clock frequency is less than the logic clock frequency of the board, that is, the write data speed is lower than the read data speed, with the increase of working time, the data amount of the data storage area gradually decreases to the underflow line, and the read control module detects the read data of the data storage area: When the read data is in the valid data interval, the read enable signal of the data storage area is kept high, that is, the valid data value of the data storage area is continuously read out; When the read data of the data storage area is IDLE, the read enable signal of the data storage area is pulled low, and an IDLE signal is output to the subsequent logic module until the data amount of the data storage area returns to the balance area, and then the read enable signal is pulled high again; Step four is repeatedly executed until the data transmission is completed.

9. A method of transmitting and receiving FC data through a high-speed port of a system for transmitting and receiving FC data through a high-speed port according to any one of claims 1 to 6, characterized by, The method comprises: Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and sends the data to the write control module based on the high-speed port recovery clock; Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port continuously writes the received data into the data storage area, the read enable of the read control module is closed, and the read control module outputs an IDLE signal to the subsequent logic processing module; Step three, the data amount stored in the data storage area gradually increases to the balance area, the write enable signal of the write control module is high, the high-speed port continuously writes the received data into the data storage area, the read enable of the read control module is pulled high, and the read control module outputs the data of the data storage area to the subsequent logic processing module; Step four, when the high-speed port recovery clock frequency is greater than the logic clock frequency of the board, that is, the write data speed is higher than the read data speed, with the increase of working time, the data amount of the data storage area gradually increases to the overflow line, and the write control module detects the high-speed port output data: When the high-speed port receives the data in the valid data interval, the write enable signal of the data storage area is kept high, that is, the valid data value is written into the data storage area; When the high-speed port receives the data as IDLE, the write enable signal of the data storage area is pulled low until the data amount of the data storage area returns to the balance area, and then the write enable signal is pulled high again; Step four is repeatedly executed until the data transmission is completed.

10. A method of transmitting and receiving FC data through a high-speed port of a system for transmitting and receiving FC data through a high-speed port according to any one of claims 1 to 6, characterized by, The method comprises: Step one, the high-speed port receives the data sent by the opposite end, generates a high-speed port recovery clock, and sends the data to the write control module based on the high-speed port recovery clock; Step two, at this time, the data amount of the data storage area is in the underflow area, the write enable signal of the write control module is pulled high, the high-speed port continuously writes the received data into the data storage area, the read enable of the read control module is closed, and the read control module outputs an IDLE signal to the subsequent logic processing module; Step three, the data amount stored in the data storage area gradually increases to the balance area, the write enable signal of the write control module is high, the high-speed port continuously writes the received data into the data storage area, the read enable of the read control module is pulled high, and the read control module outputs the data of the data storage area to the subsequent logic processing module; Step four, because the high-speed port recovery clock frequency is equal to the logic clock frequency of the board, that is, the write data speed is equal to the read data speed, the data storage area data volume will remain in the balance area, and the data storage area read and write enable is pulled up at the same time until the data transmission is completed.

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