Automatic routing method, system and storage medium for very large scale integrated circuits

Abstract

The application discloses an automatic routing method and system of a very large scale integrated circuit and a storage medium, and comprises the following steps: establishing a corresponding routing frame for each wire net; constructing a frame connection graph; splitting the frame connection graph into two or more subgraphs according to the edge weight and minimum of each subgraph; calculating the number of paths in conflict and the conflict coefficient between each wire net in the same subgraph, and constructing a track conflict graph of the same subgraph according to the number of paths and the conflict coefficient; and solving the maximum independent set of the track conflict graph to obtain the routing track of each wire net. The application can not only meet the DRC constraints such as routing line width and spacing when routing, but also can convert the routing layering problem into a multiple partitioning problem of subgraphs to process, thereby improving the rationality and efficiency of automatic routing.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to an automatic routing method, system and storage medium for a very large scale integrated circuit. BACKGROUND

[0002] A very large scale integrated circuit (VLSI) is an integrated circuit that combines a large number of transistors into a single chip, and its integration level is higher than that of a large scale integrated circuit. The number of integrated transistors varies in different standards. In some standards, an integrated circuit with more than 100,000 elements or more than 10,000 gate circuits on a single chip is called a very large scale integrated circuit. In the design of a very large scale integrated circuit, the purpose of routing is to realize the physical connection between various modules in the circuit within the specified routing area, which is one of the most critical steps in the physical design of a VLSI.

[0003] In VLSI design, each metal layer of the circuit has regularly arranged routing tracks, and actual routing should be performed within these tracks and meet certain DRC constraints such as line width and spacing. Due to the large number of elements involved in VLSI design and the complex constraints, existing automatic routing is difficult to meet the requirements of VLSI routing. SUMMARY

[0004] In view of the above problems, the present application provides an automatic routing method for a very large scale integrated circuit to solve the technical problem of difficult routing of a very large scale integrated circuit.

[0005] To achieve the above purpose, an automatic routing method for a very large scale integrated circuit is provided, comprising the following steps:

[0006] A corresponding routing frame is established for each wire mesh;

[0007] A frame connection graph is constructed;

[0008] The frame connection graph is split into two or more subgraphs under the condition of the edge weight and minimum of each subgraph, and each subgraph is a wire mesh placed on the same layer;

[0009] The number of paths and the conflict coefficient of each wire mesh in the same subgraph are calculated, and a track conflict graph of the same subgraph is constructed according to the number of paths and the conflict coefficient;

[0010] The maximum independent set of the track conflict graph is solved to obtain the routing track of each wire mesh.

[0011] Further, the establishing a corresponding routing frame for each wire net comprises: judging whether the wire net is greater than a preset value, if yes, splitting the routing frame of the wire net into two or more routing frames.

[0012] Further, the constructing a frame connection graph comprises:

[0013] judging whether there is an overlap between the routing frames, if yes, in constructing the frame connection graph, setting the routing frames with the overlap as adjacent points, adding a bidirectional arc between the points, and setting the weight of the points as a maximum value of a ratio of the overlap part to the area of each routing frame.

[0014] Further, the super large scale integrated circuit comprises a plurality of layers, each layer being provided with a routing channel; and the solving the maximum independent set of the track conflict graph comprises selecting, in each wire net, a routing track in the routing channel, and the routing direction of the routing track on adjacent layers being perpendicular to each other.

[0015] Further, the routing channel satisfies a constraint condition, the constraint condition comprising: a design rule, a routing plan, a line width and a parallel wire spacing.

[0016] Further, the method further comprises the steps of:

[0017] For the wire net which is not successfully routed, attempting to route layer by layer.

[0018] Further, the calculating the number of paths and the conflict coefficient of mutual conflict between the wire nets in the same subgraph further comprises:

[0019] In each routing frame in each subgraph, taking all possible connection modes as a point set, a track graph is constructed;

[0020] all the tracks in the same wire net are connected to each other, and the tracks intersecting in different routing frames are connected.

[0021] To solve the above technical problems, the application further provides another technical scheme:

[0022] An automatic routing system of a super large scale integrated circuit, comprising:

[0023] a frame module, configured to establish a corresponding routing frame for each wire net, and construct a frame connection graph;

[0024] a layering module, configured to split the frame connection graph into two or more subgraphs according to the edge weight and the minimum of each subgraph, each subgraph being a wire net placed on the same layer;

[0025] a solving module, configured to calculate the number of paths in conflict with each other between each of the line nets in the same subgraph and a conflict coefficient, and construct a track conflict graph of the same subgraph according to the number of paths and the conflict coefficient; and

[0026] solving a maximum independent set of the track conflict graph to obtain a routing track of each of the line nets.

[0027] Further, the frame module is further configured to: judge whether the line net is greater than a preset value, and if yes, split the routing frame of the line net into two or more routing frames.

[0028] To solve the above technical problems, the present application further provides another technical scheme:

[0029] A computer readable storage medium has a computer program stored therein, and the computer program is run by a processor to execute the automatic routing method of the very large scale integrated circuit according to any one of the technical schemes.

[0030] Different from the prior art, the above technical scheme first establishes a routing frame of a line net and a frame connection graph when automatically routing the very large scale integrated circuit, then splits the frame connection graph into a plurality of subgraphs to obtain the minimum edge weight between the subgraphs, and finally calculates a maximum independent set of routing track conflicts. In the technical scheme, the layering when automatically routing the line net is converted into a multiple partitioning problem of a graph, and when routing, not only the DRC constraints such as routing line width and spacing can be met, but also the routing layering problem can be converted into a multiple partitioning problem of a subgraph to be processed, thereby improving the rationality and efficiency of automatic routing.

[0031] The above invention content related description is only a summary of the technical scheme of the present application. In order for those skilled in the art to more clearly understand the technical scheme of the present application, and then can be implemented according to the content described in the specification and the drawings, and in order for the above and other purposes, features and advantages of the present application to be more easily understood, the following describes the specific embodiments of the present application and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] The drawings only serve to show the principles, implementation modes, applications, characteristics and effects of the specific embodiments and other related contents of the present application, and cannot be considered as limiting the present application.

[0033] In the drawings of the specification:

[0034] Figure 1 The flowchart of the automatic routing method of the very large scale integrated circuit described in the specific embodiments;

[0035] Figure 2 The schematic diagram of establishing a routing frame in the specific embodiments;

[0036] Figure 3 schematic diagram of the frame connection graph described in the detailed description;

[0037] Figure 4 schematic diagram of the wire mesh layering result described in the detailed description;

[0038] Figure 5 schematic diagram of the trajectory graph of the wire mesh described in the detailed description;

[0039] Figure 6 schematic diagram of the automatic routing method of the very large scale integrated circuit described in the detailed description;

[0040] Figure 7 schematic diagram of the automatic routing system of the very large scale integrated circuit described in the detailed description;

[0041] Figure 8 schematic diagram of the computer readable storage medium described in the detailed description;

[0042] The reference signs involved in the above-mentioned drawings are explained as follows:

[0043] 700, automatic routing system of a very large scale integrated circuit; 701, frame module; 702, layering module; 703, solving module;

[0044] 800, computer readable storage medium; DETAILED DESCRIPTION

[0045] In order to make the possible application scenarios, technical principles, specific schemes that can be implemented, purposes and effects that can be achieved of the present application clear, the following will be described in detail in combination with the specific embodiments listed and with the drawings. The embodiments described in the present document are only used to more clearly illustrate the technical schemes of the present application, and therefore only serve as examples, but cannot limit the protection scope of the present application.

[0046] In the present document, the term "embodiment" means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present application. The term "embodiment" appearing at various positions in the specification does not necessarily refer to the same embodiment, and does not particularly limit the independence or association between other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form a corresponding implementable technical scheme.

[0047] Unless otherwise defined, the meanings of the technical terms used in the present document are the same as those commonly understood by the person skilled in the art to which the present application belongs; the use of related terms in the present document is only for the purpose of describing specific embodiments, and is not intended to limit the present application.

[0048] In the description of the present application, the phrase "and / or" is a description of a logical relationship between objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases: A exists, B exists, and A and B exist at the same time. In addition, the character " / " herein generally represents that the associated objects before and after are a "or" logical relationship.

[0049] In the present application, phrases such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, primary and secondary, or order relationship between the entities or operations.

[0050] In the present application, without more limitation, the "includes", "contains", "has" or other similar open expressions used in the sentence are intended to cover non-exclusive inclusion, and these expressions do not exclude the presence of other elements in the process, method or product including the described elements, so that the process, method or product including a series of elements can not only include those limited elements, but also include other elements not explicitly listed, or also include elements inherent to such process, method or product.

[0051] As the same understanding as in the "Guidelines for Examination", in the present application, the expressions "greater than", "less than", "exceed" and the like are understood as not including the number; the expressions "above", "below", "within" and the like are understood as including the number. In addition, in the description of the embodiments of the present application, the meaning of "multiple" is more than two (including two), and similar expressions related to "multiple" are also understood in this way, for example, "multiple groups", "multiple times" and the like, unless otherwise explicitly limited.

[0052] In the description of the embodiments of the present application, the spatial-related expressions used, such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "perpendicular", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or the drawings, and are only for the convenience of describing the specific embodiments of the present application or for the reader to understand, and do not indicate or imply that the indicated device or component must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0053] Unless otherwise defined, or the context dictates otherwise, the terms "mount", "connected", "connection", "fixed", "set", and the like used in the description of the embodiments of the application are to be construed in a broad sense. For example, "connection" can be fixed connection, or detachable connection, or integrated setting; it can be mechanical connection, or electrical connection, or communication connection; it can be direct connection, or indirect connection through intermediate medium; it can be the internal communication of two elements, or the interaction relationship between two elements. For those skilled in the art to which the present application belongs, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0054] Referring to Figure 1 , the embodiment provides an automatic routing method of a very large scale integrated circuit. The automatic routing method of the very large scale integrated circuit is applied to a very large scale integrated circuit in which more than 100,000 elements are integrated on a single chip, and is used for automatic layering and routing of each net in the very large scale integrated circuit. The very large scale integrated circuit includes a plurality of layers, and each layer is provided with a routing channel; when routing, the automatic routing method of the very large scale integrated circuit arranges the net in the net channel, and the routing satisfies the set DRC constraints such as line width and spacing. In the embodiment, the net layering problem can be converted into a subgraph multiple partitioning problem of a frame connection graph, so that the net layering is more reasonable and efficient.

[0055] As Figure 1 shown, the automatic routing method of the very large scale integrated circuit of the embodiment includes the following steps:

[0056] S101, establishing a corresponding routing frame for each net;

[0057] S102, constructing a frame connection graph;

[0058] S103, splitting the frame connection graph into two or more subgraphs under the condition of minimum edge weight of each subgraph, and each subgraph is a net placed on the same layer;

[0059] S104, calculating the number of paths in conflict with each other between the nets in the same subgraph and the conflict coefficient, and constructing a track conflict graph of the same subgraph according to the number of paths and the conflict coefficient;

[0060] S105, solving the maximum independent set of the track conflict graph to obtain the routing track of each net.

[0061] As Figure 2 shown, it is a schematic diagram of the routing frame established in step S101, wherein each small rectangular frame in the large rectangular frame is a routing frame. In the embodiment, an abstract model for automatic routing of the net is established, as Figure 2As shown, each layer has regularly arranged routing tracks. The preferred direction for layer M1 is horizontal, and the preferred direction for layer M2 is vertical (where layers M1 and M2 are metal layers). The routing path is selected between the routing tracks. The design of the routing tracks depends on the design rules and routing plan to meet constraints such as wire width and parallel-run spacing.

[0062] In some embodiments, when establishing a corresponding wiring border for each net, the method further includes: determining whether the net is larger than a preset value; if so, splitting the wiring border of the net into two or more wiring borders.

[0063] like Figure 3 The diagram shown is a schematic representation of the border connection diagram in step S102. Constructing the border connection diagram includes:

[0064] If the wiring borders overlap, then when constructing the border connection graph, the overlapping wiring borders are set as adjacent points, a bidirectional arc is added between the points, and the weight of each point is set to the maximum value of the ratio of the overlapping portion to the area of ​​each wiring. In this embodiment, each wiring border (i.e., a small rectangular area) is treated as a point. If two wiring borders (rectangular areas) overlap, their corresponding points are adjacent, and their weight is set to the maximum value of the ratio of the overlapping portion to their respective areas.

[0065] like Figure 3 As shown, R1,...,R5 correspond to the routing borders of the five nets. A net border connection diagram is constructed. If Ri and Rj intersect, a bidirectional arc is added between Ri and Rj, with the following weights: and |R j |

[0066] In step S103, the bounding graph is split into several subgraphs such that the sum of edge weights between subgraphs is minimized, thus transforming the problem into a subgraph multipartition problem (i.e., the maximum multicut problem), to solve the mesh layering problem. In the maximum multicut problem, the bounding graph is divided into k parts such that the sum of the weights of all edges within each part is minimized. This yields the layering result for each mesh. Figure 4 As shown, if the weight of the arc inside each Li is as small as possible, then each L obtained in the end is a net placed on the same layer.

[0067] In step S104, for each layer Li in the VLSI, given arbitrary nets N1 and N2, considering the conflict relationships between net trajectories, the number of conflicting paths and their conflict coefficients are calculated to construct a trajectory conflict map. In one embodiment, the calculation of the number of conflicting paths and conflict coefficients between nets in the same sub-graph is further included before:

[0068] Within each of the wiring borders in each of the subgraphs, a trajectory graph is constructed using all possible connection methods as the point set; all trajectories within the same net are connected to each other, and intersecting trajectories within different wiring borders are also connected.

[0069] like Figure 5 The diagram shown is a schematic of the trajectory graph of the net. For each layer Li, the wiring border Ri of the net is constructed by considering all possible connection methods within that border, treating each connection method as a point set. All trajectories within the same net are connected to each other. Trajectories within two different borders are connected by an edge if they intersect.

[0070] In step S105, the maximum independent set of the trajectory conflict graph is solved to determine the trajectory of each net.

[0071] In some embodiments, for the nets that have not been successfully routed, they can be added back to the routing list and the routing can be attempted layer by layer.

[0072] In this embodiment, during routing, the nets are arranged within the net channels, and the routing satisfies the set DRC constraints such as line width and spacing. Furthermore, the net layering problem can be transformed into a subgraph multi-partitioning problem of the border connection graph, thereby making the net layering more reasonable and efficient.

[0073] In one embodiment, in solving the maximum independent set of the trajectory conflict graph to obtain the wiring trajectory of each net, the wiring trajectories are all selected within the wiring channel, and the wiring directions of the wiring trajectories on adjacent layers are perpendicular to each other.

[0074] In some embodiments, the wiring channel satisfies constraints, including: design rules, wiring planning, line width, and spacing between horizontal running lines.

[0075] like Figure 6 The following describes the specific steps of an automatic routing method for very large-scale integrated circuits in one embodiment:

[0076] Obtain the cell layout, routing paths, and all nets that need to be routed for the VLSI;

[0077] Calculate the cross weights of the wire mesh, and construct the wiring boundary diagram and the boundary connection diagram;

[0078] Solve the maximum multipartition problem to perform layering during net routing;

[0079] Establish the routing path for each net across all routing borders;

[0080] Create a trajectory conflict map for each layer;

[0081] Find the maximum independent set in the trajectory conflict graph;

[0082] Determine if there are any unrouted net borders. If so, select one unrouted net border and attempt to route it on other layers. If the attempt fails, skip it. If there are no unrouted net borders, end the process.

[0083] like Figure 7 As shown, in one embodiment, an automatic routing system 700 for very large-scale integrated circuits is provided. The automatic routing system 700 for very large-scale integrated circuits includes: a border module 701, a layering module 702, and a solving module 703.

[0084] The border module 701 is used to create a corresponding wiring border for each net and to construct the border connection diagram;

[0085] The layering module 702 is used to split the border connection graph into two or more subgraphs based on the condition that the sum of the edge weights of each subgraph is minimized, and each subgraph is a wire mesh placed on the same layer.

[0086] The solver module 703 is used to calculate the number of conflicting paths and the conflict coefficient between the nets in the same subgraph, construct a trajectory conflict graph of the same subgraph based on the number of paths and the conflict coefficient, and solve the maximum independent set of the trajectory conflict graph to obtain the wiring trajectory of each net.

[0087] The automatic routing system 700 for very large-scale integrated circuits (VLSI) in this embodiment can be applied to VLSIs that integrate more than 100,000 components on a single chip. It is used for automatically layering and routing the nets within the VLSI. The VLSI comprises multiple layers, and each layer has routing channels.

[0088] In this embodiment, an abstract model for automatic net routing is established, such as... Figure 2As shown, each layer has regularly arranged routing tracks. The preferred direction for layer M1 is horizontal, and the preferred direction for layer M2 is vertical (where layers M1 and M2 are metal layers). The routing path is selected between the routing tracks. The design of the routing tracks depends on the design rules and routing plan to meet constraints such as wire width and parallel-runspacing.

[0089] In this embodiment, each wiring border (i.e., a small rectangular area) is treated as a point. If two wiring borders (rectangular areas) overlap, their corresponding points are adjacent, and their weight is set to the maximum value of the ratio of the overlapping part to their respective areas.

[0090] like Figure 3 As shown, R1,...,R5 correspond to the routing borders of the five nets. A net border connection diagram is constructed. If Ri and Rj intersect, a bidirectional arc is added between Ri and Rj, with the following weights: and

[0091] This automatic routing method for VLSI (Very Large Scale Integration) arranges nets within net channels during routing, ensuring that the routing meets set DRC constraints such as linewidth and spacing. Furthermore, in this embodiment, the net layering problem can be transformed into a subgraph multi-partitioning problem of the boundary connection graph, thereby making net layering more reasonable and efficient.

[0092] In one embodiment, the border module 701 is further configured to: determine whether the wire mesh is larger than a preset value; if so, split the wire mesh's wiring border into two or more wiring borders.

[0093] like Figure 8 As shown, in one embodiment, a computer-readable storage medium 800 is provided, which stores a computer program. When the computer program is run by a processor, it executes the automatic routing method for very large-scale integrated circuits described in any of the above embodiments.

[0094] In this embodiment, the computer program in the computer-readable storage medium 800, when executed by a processor, can perform automatic routing of very large-scale integrated circuits. During routing, the nets are arranged within net channels, and the routing satisfies set DRC constraints such as linewidth and spacing. Furthermore, in this embodiment, the net layering problem can be transformed into a subgraph multi-partitioning problem of the boundary connection graph, thereby making net layering more reasonable and efficient.

[0095] Finally, it should be noted that the above embodiments have been described in the specification and drawings of the application, but this does not limit the patent protection scope of the application. Any equivalent structure or equivalent process replacement or modification based on the essential concept of the application, using the content described in the specification and drawings of the application, and directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, etc., are all included in the patent protection scope of the application.

Claims

1. An automatic routing method for very large-scale integrated circuits, characterized in that, Includes the following steps: Create a corresponding wiring border for each net; Construct a border connection graph; The border connection graph is split into two or more subgraphs based on the condition that the sum of the edge weights of each subgraph is minimized. Each subgraph is a wire mesh placed on the same layer. Within each wiring border of each subgraph, a trajectory graph is constructed using all possible connection methods as the point set; all trajectories within the same net are connected to each other, and intersecting trajectories within different wiring borders are also connected. Calculating the number of conflicting paths and the conflict coefficient between each net in the same subgraph, and constructing a trajectory conflict graph of the same subgraph based on the number of paths and the conflict coefficient, includes: for each layer in a very large-scale integrated circuit, for any given net, calculating the number of conflicting paths and the conflict coefficient between them, and constructing a trajectory conflict graph. Solve for the maximum independent set of the trajectory conflict graph to obtain the wiring trajectory of each of the nets.

2. The automatic routing method for very large-scale integrated circuits according to claim 1, characterized in that, The step of establishing a corresponding wiring border for each net includes: determining whether the net is larger than a preset value; if so, splitting the wiring border of the net into two or more wiring borders.

3. The automatic routing method for very large-scale integrated circuits according to claim 1, characterized in that, The construction of the border connection diagram includes: Determine whether there is overlap between the wiring borders. If there is, when constructing the border connection diagram, set the overlapping wiring borders as adjacent points, add a bidirectional arc between the points, and set the weight of the points as the maximum value of the ratio of the overlapping part to the area of ​​each wiring.

4. The automatic routing method for very large-scale integrated circuits according to any one of claims 1 to 3, characterized in that, The very large-scale integrated circuit includes multiple layers, and each layer is provided with a wiring channel; in solving the maximum independent set of the trajectory conflict graph to obtain the wiring trajectory of each net, the wiring trajectories are all selected within the wiring channel, and the wiring directions of the wiring trajectories on adjacent layers are perpendicular to each other.

5. The automatic routing method for very large-scale integrated circuits according to claim 4, characterized in that, The cabling channel satisfies the following constraints, which include: design rules, cabling planning, line width, and spacing between horizontal running lines.

6. The automatic routing method for very large-scale integrated circuits according to claim 1, characterized in that, It also includes the following steps: For the network that failed to be routed, attempt to route it layer by layer.

7. An automatic routing system for very large-scale integrated circuits, characterized in that, include: The border module is used to create a corresponding wiring border for each net and to construct the border connection diagram. The layering module is used to split the border connection graph into two or more subgraphs based on the condition that the sum of the edge weights of each subgraph is minimized, and each subgraph is a wire mesh placed on the same layer. The solution module is used to construct a trajectory map within each wiring border of each subgraph, using all possible connection methods as the point set; connect all trajectories within the same net to each other, and connect intersecting trajectories within different wiring borders; calculate the number of conflicting paths and conflict coefficients between nets in the same subgraph, and construct a trajectory conflict map of the same subgraph based on the number of paths and conflict coefficients, including: for each layer in a VLSI, for any given net, calculate the number of conflicting paths and their conflict coefficients, and construct a trajectory conflict map; as well as Solve for the maximum independent set of the trajectory conflict graph to obtain the wiring trajectory of each of the nets.

8. The automatic routing system for very large-scale integrated circuits according to claim 7, characterized in that, The border module is also used to: determine whether the wire mesh is larger than a preset value; if so, split the wire mesh's wiring border into two or more wiring borders.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is run by the processor, it executes the automatic routing method for very large-scale integrated circuits as described in any one of claims 1 to 6.

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