Programmable non-volatile memory and operating method

Abstract

The embodiment of the present disclosure provides a programmable non-volatile memory and an operating method. The memory comprises: a plurality of protection transistors, a first end of each protection transistor being connected to a bit line, and a second end and a gate of each protection transistor being connected to a power supply node; and a voltage conversion circuit connected to a first node and a second node, the first node being used for providing a first voltage, the second node being used for providing a second voltage, and the voltage conversion circuit being configured to receive an input signal, work in response to the input signal during a programming operation to turn on a transmission path between the power supply node and the first node, work in response to the input signal during a reading operation, and turn on a transmission path between the power supply node and the second node, wherein a level value of the input signal during the programming operation and the reading operation is different, and the second voltage and the first voltage satisfy: 0 < V2 < V1. The embodiment of the present disclosure is beneficial to improving reading accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a programmable non-volatile memory and its operation method. Background Technology

[0002] Anti-fuse memory is a common type of programmable non-volatile memory. Anti-fuse memory consists of multiple rows and columns of anti-fuse cells. When a high voltage is applied to the gate oxide layer of an anti-fuse cell, the gate oxide layer is broken down, reducing the impedance of the path. By detecting the impedance state of the path after breakdown, the information stored in the anti-fuse cell can be read.

[0003] Current antifuse memories still suffer from low read accuracy. Summary of the Invention

[0004] This disclosure provides a programmable non-volatile memory and an operation method applied to the programmable non-volatile memory, which at least helps to improve the accuracy of read operations.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a programmable non-volatile memory, characterized in that it includes: antifuse units arranged in multiple rows and columns, each column of the antifuse units being connected to a data line via a corresponding column switch, and each column of the antifuse units being connected to a bit line via a corresponding row switch, and all the row switches connected to the antifuse units in the same row being connected to a word line; a plurality of protection transistors, each protection transistor having a first terminal connected to a bit line, and a second terminal and a gate of each protection transistor being connected to a power supply node; and a voltage conversion circuit connecting the first node and the second node. A first node is configured to provide a first voltage, and a second node is configured to provide a second voltage. The nodes are configured to receive an input signal, operate in response to the input signal during a programming operation to establish a transmission path between the power supply node and the first node, and operate in response to the input signal during a reading operation to establish a transmission path between the power supply node and the second node. The input signal has different voltage levels during the programming operation and the reading operation. The second voltage and the first voltage satisfy: 0 < V2 < V1, where V2 is the second voltage and V1 is the first voltage.

[0006] In some embodiments, the voltage conversion circuit includes: a receiving module configured to receive the input signal and provide a feedback signal corresponding to the input signal; and a gating module connected to the power supply node, the first node, and the second node, configured to, in response to the feedback signal, enable a transmission path between the power supply node and the first node, or enable a transmission path between the power supply node and the second node.

[0007] In some embodiments, the receiving module has a third node and a fourth node, and the receiving module is further configured to: receive a reference signal, compare the difference between the level values ​​of the input signal and the reference signal, and provide the feedback signal to the third node and a differential feedback signal to the fourth node as a comparison result, wherein the feedback signal and the differential feedback signal are differential signals to each other; wherein, if the level value of the input signal is greater than the level value of the reference signal, then the level value of the feedback signal is less than the level value of the differential feedback signal; if the level value of the input signal is less than the level value of the reference signal, then the level value of the feedback signal is greater than the level value of the differential feedback signal.

[0008] In some embodiments, the reference signal and the input signal are inverse signals.

[0009] In some embodiments, the receiving module includes: an input unit connected to the third node and the fourth node, configured to receive the input signal and the reference signal, compare the difference between the level value of the input signal and the level value of the reference signal, and provide the feedback signal to the third node and the differential feedback signal to the fourth node; and a latch unit connected to the third node and the fourth node, configured to amplify the level difference between the feedback signal and the differential feedback signal.

[0010] In some embodiments, the input unit includes: a first NMOS transistor, whose gate receives the input signal, whose source is grounded, and whose drain is connected to the third node; and a second NMOS transistor, whose gate receives the reference signal, whose source is grounded, and whose drain is connected to the fourth node; the latch unit includes: a first PMOS transistor, whose gate is connected to the third node, whose source is connected to the first node, and whose drain is connected to the fourth node; and a second PMOS transistor, whose gate is connected to the fourth node, whose source is connected to the first node, and whose drain is connected to the third node.

[0011] In some embodiments, the receiving module further includes: a first switching unit connected between the third node and the input unit, and connected between the fourth node and the input unit, configured to receive a first enable signal, and to be turned on during the period when the first enable signal is valid, and to be turned off during the period when the first enable signal is invalid.

[0012] In some embodiments, the first switching unit includes: a first switching transistor, whose gate receives the first enable signal, whose drain is connected to the third node, and whose source is connected to the input unit; and a second switching transistor, whose gate receives the first enable signal, whose drain is connected to the fourth node, and whose source is connected to the input unit.

[0013] In some embodiments, the gating module includes: a first gating unit connected to the power supply node and the first node, configured to, during a programming operation, respond to the feedback signal and the differential feedback signal to enable a transmission path between the power supply node and the first node; and a second gating unit connected to the power supply node and the second node, configured to, during a read operation, respond to the feedback signal and the differential feedback signal to enable a transmission path between the power supply node and the second node.

[0014] In some embodiments, the first gating unit includes: a third PMOS transistor, with its gate connected to the third node, its source connected to the first node, and its drain connected to the power supply node; and a fourth PMOS transistor, with its gate connected to the fourth node, its source connected to the first node, and its drain connected to the fifth node; the second gating unit includes: a third NMOS transistor, with its gate connected to the fifth node, its drain connected to the drain of the third PMOS transistor, and its source connected to the second node; and a fourth NMOS transistor, with its gate connected to the power supply node, its drain connected to the drain of the fourth PMOS transistor, and its source connected to the second node.

[0015] In some embodiments, the voltage conversion circuit is further configured to receive a second enable signal and, during the period when the second enable signal is valid, provide a third voltage to the power supply node, the third voltage being less than the second voltage; wherein, at the same time, one of the first enable signal and the second enable signal is valid.

[0016] In some embodiments, the second enable signal and the first enable signal are inverse signals of each other.

[0017] In some embodiments, the voltage conversion circuit includes: a reset module connected between the operating power supply and the third node and the fourth node, configured to be turned on in response to a valid second enable signal, so that both the third node and the fourth node are connected to the operating power supply; and a power supply module connected between the sixth node and the power supply node, configured to be turned on in response to a valid second enable signal, so that the power supply node is connected to the sixth node, the sixth node being used to receive the third voltage.

[0018] In some embodiments, the reset module includes: a fifth NMOS transistor, whose gate receives the second enable signal and is connected between the third node and the operating power supply; and a sixth NMOS transistor, whose gate receives the second enable signal and is connected between the fourth node and the operating power supply.

[0019] In some embodiments, the power supply module includes a seventh NMOS transistor, whose gate receives the second enable signal and is connected between the power supply node and the sixth node.

[0020] In some embodiments, the sixth node is connected to ground; the power supply module further includes: at least one eighth NMOS transistor connected in series between the ground and the seventh NMOS transistor, the eighth NMOS transistor being in a conducting state; and / or, at least one ninth NMOS transistor connected in series between the power supply node and the seventh NMOS transistor, the ninth NMOS transistor being in a conducting state.

[0021] In some embodiments, the system further includes a pre-charging circuit connected to the data line for pre-charging the data line during a read operation.

[0022] According to some embodiments of this disclosure, another aspect of this disclosure provides an operation method applicable to the above-mentioned programmable non-volatile memory, including: during the programming operation of the programmable non-volatile memory, the voltage conversion circuit operates in response to the input signal to provide a first voltage to the power supply node; during the read operation of the programmable non-volatile memory, the voltage conversion circuit operates in response to the input signal to provide a second voltage to the power supply node.

[0023] In some embodiments, when the programmable nonvolatile memory is neither in a programming operation nor in a reading operation, the voltage conversion circuit also responds to a second enable signal to provide a third voltage to the power supply node, the third voltage being less than the second voltage.

[0024] The technical solutions provided in this disclosure have at least the following advantages:

[0025] The voltage conversion circuit can provide different voltages to the gate and second terminal of the protection transistor at different times. Specifically, during programming operations, the voltage conversion circuit can provide a relatively large first voltage to the gate and second terminal of the protection transistor, so that the protection transistor conducts and pulls up the voltage of the non-target bit line, thereby reducing the voltage difference across the antifuse unit connected to the non-target bit line and thus protecting the antifuse unit connected to the non-target bit line. During reading operations, the voltage conversion circuit can provide a second voltage greater than zero and less than the first voltage to the gate and second terminal of the protection transistor, so that the protection transistor can provide a sinking current to the target bit line. This sinking current can compensate for the leakage current in the transmission path between the data line and the target bit line, thereby preventing the charge of the data line from being discharged too quickly. This ensures that the voltage of the data line will not decrease to an undesirable voltage value due to leakage current during reading operations, thus ensuring that the stored data can be read accurately. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram illustrating the voltage level changes of the data line during the reading of stored data "1";

[0028] Figure 2 A schematic diagram of a programmable non-volatile memory provided in an embodiment of this disclosure;

[0029] Figure 3 This is a schematic diagram of the structure of a programmable non-volatile memory during programming operations;

[0030] Figure 4 This is a schematic diagram of the structure of a programmable non-volatile memory during a read operation;

[0031] Figure 5 This is a schematic diagram illustrating the voltage level changes of the data lines during the reading of stored data "1" from a programmable non-volatile memory.

[0032] Figure 6 This is a schematic diagram of another structure for a programmable non-volatile memory;

[0033] Figure 7 This is a functional block diagram of a voltage conversion circuit;

[0034] Figure 8 This is another functional block diagram of a voltage conversion circuit;

[0035] Figure 9 A schematic diagram of a voltage conversion circuit;

[0036] Figure 10 This is another functional block diagram of a voltage conversion circuit;

[0037] Figure 11 This is a schematic diagram of another circuit structure for a voltage conversion circuit;

[0038] Figure 12 This is another functional block diagram of a voltage conversion circuit;

[0039] Figure 13 This is a schematic diagram of another circuit structure for a voltage conversion circuit. Detailed Implementation

[0040] Specifically, the programmable non-volatile memory includes antifuse cells arranged in multiple rows and columns, multiple bit lines, and a protection transistor connected to each bit line. Each bit line is connected to a column of antifuse cells, and each bit line is connected to a data line via a column switch. The data line is connected to a readout circuit, which compares a reference voltage with the voltage of the data line and outputs the stored data.

[0041] During the fusing phase (or programming operation), the bit line connected to the antifuse cell being programmed is defined as the target bit line, and the remaining bit lines are non-target bit lines. The protection transistor is turned on to pull up the voltage of the non-target bit lines, reducing the voltage difference between the gate and source of the unprogrammed antifuse cell, thus protecting the unprogrammed antifuse cell and extending its lifespan. Additionally, during the fusing phase, if the gate dielectric layer of the antifuse cell is broken down, the equivalent impedance of this antifuse cell is very small; that is, the antifuse cell is melted and therefore has a low-resistance state, which can be characterized as storing data "0". Conversely, if the gate dielectric layer of the antifuse cell is not broken down during the fusing phase, the equivalent impedance of this antifuse cell is very large; that is, the antifuse cell is not melted and therefore has a high-resistance state, which can be characterized as storing data "1".

[0042] During the read phase, the data line is pre-charged to a preset voltage; the column switch connected to the target bit line is turned on, connecting the data line to the target bit line and then to the antifuse unit. If the antifuse unit is in a high-resistance state (i.e., storing data "1"), the charge discharge rate of the antifuse unit to the data line is very slow, resulting in a data line voltage greater than the reference voltage, thus causing the read circuit to read the signal of the data line as "1". If the antifuse unit is in a low-resistance state (i.e., storing data "0"), the charge discharge rate of the antifuse unit to the data line is very fast, resulting in a data line voltage less than the reference voltage, thus causing the read circuit to read the signal of the data line as "0".

[0043] However, the accuracy of reading the stored data "1" needs to be further improved. Figure 1 For a diagram illustrating the voltage level changes of the data line during the reading of stored data "1", refer to... Figure 1 During the read phase, the charge on the data line was discharged faster than expected, causing the voltage on the data line to drop below the reference voltage before the read phase was completed. This resulted in stored data that should have been read as "1" being read as "0", affecting the accuracy of data reading and causing an unfused antifuse to be incorrectly identified as a blown antifuse. Analysis revealed that, on the one hand, although the column switch connected to the non-target bit line was not conducting during the read phase, the non-target bit line still constituted a charge discharge path for the data line; on the other hand, during the read phase, the transmission path between the data line and the target bit line was conducting, and the target bit line connected multiple transistors, including protection transistors, row switch transistors, and antifuse units, etc. Although these transistors were in an off state, they still constituted a charge discharge path for the data line. Any of the above-mentioned charge discharge paths will cause unnecessary leakage in the data line, resulting in a drop in the voltage of the data line during the reading phase. This not only affects the sensitivity and speed of the read circuit in reading the stored data, but also causes read errors if the voltage of the data line drops below the reference voltage.

[0044] This disclosure provides a programmable non-volatile memory, which helps improve the accuracy of reading stored data. The programmable non-volatile memory provided in this disclosure will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0045] Figure 2 This is a schematic diagram of a programmable non-volatile memory provided in an embodiment of the present disclosure.

[0046] refer to Figure 2The programmable non-volatile memory includes antifuse units 10 arranged in multiple rows and columns. Each antifuse unit 10 is connected to the data line Faconn via a corresponding column switch transistor 11, and each column of antifuse units 10 is connected to a bit line BL.

[0047] Bit line BL is connected to antifuse units 10 arranged in the extension direction of bit line BL. Antifuse units 10 can be connected to bit line BL via row switching transistors 12, and each column of antifuse units 10 is connected to a bit line BL via a corresponding row switching transistor 12. Specifically, the row switching transistors 12 include 1Add01…1Add0x, 1Add11…1Add1x, 1Add21…1Add2x, and 1Add31…1Add3x.

[0048] It should be noted that, taking the row switch transistor 12 represented by "1Add01" as an example, "01" indicates that it is connected to the antifuse unit "FsBln01", that is, the row switch transistor 1Add01 serves as the row switch transistor of the antifuse unit FsBln01; taking the row switch transistor represented by "1Add2x" as an example, "2x" indicates that it is connected to the antifuse unit "FsBln2x", that is, the row switch transistor 1Add2x serves as the row switch transistor of the antifuse unit FsBln2x; in addition, in the description of some embodiments, if there is no numerical suffix after the designation of 1Add, it indicates that it does not specifically refer to a certain row switch transistor.

[0049] The horizontal switching transistor 12 can be an NMOS transistor or a PMOS transistor. Figure 2 The example uses NMOS transistor 12 as an example.

[0050] In some embodiments, the programmable non-volatile memory may further include word lines WL and row switch transistors 12 arranged in the extending direction of the word lines WL, for turning on the selected row switch transistor 12 according to a row strobe signal. All row switch transistors 12 connected to the antifuse unit 10 of the same row are connected to a word line WL. It should be noted that the row strobe signal is also a word line strobe signal, used to select a target word line WL from among many word lines WL and turn on the row switch transistor 12 connected to the target word line WL.

[0051] Specifically, the gate of the row switch transistor 12 is connected to the word line WL, one end of the source or drain is connected to the antifuse unit 10, and the other end is connected to the bit line BL.

[0052] Programmable non-volatile memory can be antifly memory. Multiple rows and columns of antifly cells 10 constitute a memory array. For example... Figure 2As shown, different antifuse units 10 are identified by FsBln01…FsBln0x, FsBln11…FsBln1x, FsBln21…FsBln2x, and FsBln31…FsBln3x. The antifuse unit 10 is characterized by whether the gate dielectric layer is broken down, indicating the stored 1 bit of data. Specifically, FsBln01…FsBln0x represents antifuse units 10 in the same row, more specifically, antifuse units 10 in row 0. FsBln11…FsBln1x represents antifuse units 10 in the same row, more specifically, antifuse units 10 in row 1. FsBln31…FsBln3x represents antifuse units 10 in the same row, more specifically, antifuse units 10 in row 3.

[0053] In this configuration, multiple antifuse units 10 located in the same row are connected to the same transmission line (not shown). A voltage is applied to the gate of the antifuse unit 10 via this transmission line to control the programming state of the antifuse unit 10 during the programming phase.

[0054] In some embodiments, adjacent row switch transistors 12 can be connected to the bit line BL via the same conductive line in the extension direction of the bit line BL. Connecting adjacent row switch transistors 12 to the bit line BL via the same conductive line allows adjacent row switch transistors 10 to share a source or drain during design, thereby reducing the layout area or integrating more antifuse units 10 in the same area.

[0055] The column switch transistor 11 is used to connect the bit line BL to the data line Faconn. The gate of the column switch transistor 11 is used to receive the column strobe signal. One end of its source or drain is connected to the bit line BL, and the other end is connected to the data line Faconn. The column strobe signal is used to select and turn on the selected column switch transistor 11. It should be noted that the column strobe signal is also the bit line strobe signal, which is used to select a target bit line BL from among many bit lines BL and turn on the column switch transistor 11 connected to the target bit line BL.

[0056] Specifically, the column switch transistors 11 include: 2Add0, 2Add1, ..., 2Addx. Taking the column switch transistor 11 represented by "2Add1" as an example, "1" indicates that it is connected to the first bit line, and the first bit line is connected to the anti-fuse unit "FsBlnz1" through the row switch transistor "1Addz1", where z is any integer from 0 to x; taking the column switch transistor represented by "2Addx" as an example, "x" indicates that it is connected to the xth bit line, and the xth bit line is connected to the anti-fuse unit "FsBlnzx" through the row switch transistor "1Addzx", where z is any integer from 0 to x; in addition, in some embodiments, if there is no numerical suffix after the designation of 2Add, it indicates that it does not specifically refer to a certain column switch transistor.

[0057] The switch 11 can be an NMOS or a PMOS transistor. Figure 2 The example uses NMOS transistor 11 as an example.

[0058] The programmable non-volatile memory also includes a plurality of protection transistors 13, each protection transistor 13 having its first terminal connected to a bit line BL, and its second terminal and gate connected to a power supply node nd. In other words, the number of protection transistors 13 corresponds one-to-one with the number of bit lines BL.

[0059] The protection transistor 13 can also be called a discharge transistor. The protection transistor 13 can be an NMOS transistor or a PMOS transistor. Figure 2 The protection transistor 13 is used as an example of an NMOS transistor.

[0060] The programmable non-volatile memory also includes a voltage conversion circuit 100 connected to a first node n1 and a second node n2. The first node n1 provides a first voltage, and the second node n2 provides a second voltage. The circuit is configured to receive an input signal IN, operate in response to the input signal IN during a programming operation to establish a transmission path between a power supply node nd and the first node n1, and operate in response to the input signal IN during a read operation to establish a transmission path between the power supply node nd and the second node n2. The input signal IN has different voltage levels during the programming and read operations, and the second voltage and the first voltage satisfy: 0 < V2 < V1, where V2 is the second voltage and V1 is the first voltage.

[0061] Figure 3 This is a schematic diagram of the structure of a programmable non-volatile memory during programming operations. Figure 4 This is a schematic diagram of the structure of a programmable non-volatile memory during a read operation. Figure 5 This diagram illustrates the voltage level change of the data line Faconn during the reading of stored data "1" in a programmable non-volatile memory. The protection transistor 13 plays different roles during the programming and reading phases. The following will combine... Figures 3 to 5 The function of the protection transistor 13 will be explained as follows:

[0062] refer to Figure 3During the programming phase, taking the programming of antifuse unit FsBln01 as an example, the voltage of the word line WL connected to the gate of the row switch transistor 1Add01 connected to antifuse unit FsBln01 can be 3V. Therefore, the gate voltage of all row switch transistors 12 connected to this word line WL is 3V. The gate voltage of the column switch transistor 2Add0 corresponding to the bit line BL connected to antifuse unit FsBln01 is 1.2V, making this column switch transistor 2Add0 turn on, while the other column switches 11 remain off. Furthermore, the gate voltage of antifuse units FsBln01 to FsBln0x in the same row can be 5.5V. Taking 5.5V as the high voltage required for programming as an example, the gate dielectric layer of the antifuse unit FsBln01 being programmed is broken down, so the antifuse unit FsBln01 is in a low-resistance state, and the corresponding stored data is "0". It is understandable that if the gate voltage of antifuse cells FsBln01 to FsBln0x in the same row is low, the gate dielectric layer of the programmed antifuse cell FsBln01 is not broken down, so the antifuse cell FsBln01 is in a high-resistance state, and the corresponding stored data is "1".

[0063] The bit line BL connected to the antifuse unit FsBln01 is defined as the target bit line, and the remaining bit lines BL are non-target bit lines. During the programming phase, the voltage conversion circuit 100 conducts the transmission path between the power supply node nd and the first node n1, so that the power supply node nd has a relatively large first voltage. The gate and source of the protection transistor 13 both have the first voltage, so that the protection transistor 13 constitutes an equivalent diode. Thus, the voltage of the non-target bit line is the first voltage minus the threshold voltage of the protection transistor 13, so that the non-target bit line has a higher voltage. For example, if the first voltage is 3V and the threshold voltage of the protection transistor 13 is 0.63V, then the voltage of the non-target bit line is 2.37V. In this way, the voltage difference between the gate and source of the antifuse unit 10 connected to the non-target bit line will be reduced, thereby protecting the antifuse unit 10 connected to the non-target bit line and preventing a large voltage difference between the gate and source of these antifuse units 10 from affecting their service life. Or, in other words, it protects the other antifuse units in the same row as the antifuse unit 10 being programmed.

[0064] Reference Figure 4 and Figure 5During the read phase, taking the stored data as "1" as an example, the antifuse unit 10 constitutes the charge discharge path for the data line Faconn. Since the corresponding antifuse unit 10 is in a high-resistance state, the charge discharge speed of the data line Faconn is slow, and the data line Faconn has a pre-charge voltage before the read phase. Meanwhile, the voltage conversion circuit 100 conducts the transmission path between the power supply node nd and the second node n2, resulting in a relatively small second voltage at the power supply node nd, which is greater than 0. This causes the protection transistor 13 to conduct to a certain extent, injecting compensation current into the bit line BL. This compensates for the leakage current along the entire path after the data line Faconn and the bit line BL are connected, reducing the charge discharge speed of the data line Faconn and ensuring that the data line Faconn has a real-time voltage greater than the reference voltage during the read phase, so as to accurately read the stored data "1".

[0065] In addition, this compensation current can also compensate for the charge discharge loss caused by the non-target bit line to the data line Faconn.

[0066] like Figure 5 As shown, lines 1 and 2 illustrate two different voltage levels of the data line Faconn during the reading phase. Line 1 shows the voltage level change of the data line Faconn when both the second terminal and gate of the protection transistor 13 are connected to 0V. Line 2 shows the voltage level change of the data line Faconn when both the second terminal and gate of the protection transistor 13 are connected to a second voltage. Figure 5 As can be seen, during the reading phase, the voltage of the power supply node nd is the second voltage, and the charge discharge speed of the data line Faconn is slower, so as to ensure that the voltage of the data line Faconn is greater than the reference voltage during the reading phase.

[0067] It should be noted that the voltage values ​​mentioned above are merely examples, and the embodiments disclosed herein do not limit the gate voltage of the antifuse unit, the gate voltage of the row switch, and the gate voltage of the column switch during the programming and reading stages.

[0068] Alternatively, if the protection transistor 13 can be an NMOS transistor, then the second terminal of the protection transistor 13 is the drain, and the first terminal of the protection transistor 13 is the source.

[0069] Understandably, if the stored data to be read is 0, it indicates that the corresponding antifuse unit 10 is blown, i.e., the antifuse unit 10 is in a low-resistance state. During the reading phase, the blown antifuse unit forms a charge discharge path for the data line Faconn, which reduces the voltage of the data line Faconn to less than the reference voltage Vref, so that the read circuit reads the stored data as "0". In this process, the gate and the second terminal of the protection transistor 13 both receive the second voltage V2, so that the protection transistor 13 will still provide a small sink current to the target bit line. However, since the data line Faconn discharges charge very quickly through the blown antifuse unit, the sink current provided by the protection transistor 13 will not affect the result that the voltage of the data line Faconn is less than the reference voltage Vref, and the stored data "0" can still be read correctly by the read circuit.

[0070] Figure 6 This is a schematic diagram of another structure for a programmable non-volatile memory. In some embodiments, reference is made to... Figure 6 The programmable non-volatile memory may further include a block switch transistor 3Add connected to the data line Faconn. Specifically, one end of the block switch transistor 3Add is connected to the data line, the other end is grounded, and its gate receives a control signal. During programming operations, the block switch transistor 3Add is turned on in response to the control signal. During read operations, the block switch transistor 3Add is turned off in response to the control signal.

[0071] The block switch 3Add can be an NMOS or a PMOS transistor. Figure 6 The example uses the block switch 3Add as an NMOS transistor.

[0072] In some embodiments, reference Figure 6 The programmable non-volatile memory may also include a precharge circuit 14, which is connected to the data line Faconn and is used to precharge the data line Faconn before a read operation so that the voltage of the data line Faconn is pulled high.

[0073] The pre-charge circuit 14 can be a PMOS transistor. The gate of the PMOS transistor receives the pre-charge control signal PRE, the source is connected to the working power supply VDD, and the drain is connected to the data line Faconn.

[0074] The programmable non-volatile memory may also include a readout circuit 101, one input of which is connected to the data line Faconn, and the other input receives a reference voltage V. ref The OUT terminal outputs the stored data.

[0075] The readout circuit 101 can be a comparator. If the data line Faconn voltage is greater than the reference voltage V... refThe output terminal OUT will output the stored data "1". If the voltage on the data line Faconn is less than the reference voltage V, the output terminal OUT will output the stored data "1". ref If the output terminal OUT outputs the stored data "0", then the output terminal OUT will output the stored data.

[0076] Figure 7 This is a functional block diagram of a voltage conversion circuit. (Reference) Figure 7 The voltage conversion circuit 100 may include a receiving module 201 and a gating module 202. The receiving module 201 is configured to receive an input signal IN and provide a feedback signal VR1 corresponding to the input signal IN; the gating module 202 is connected to the power supply node nd, the first node n1, and the second node n2, and is configured to, in response to the feedback signal VR1, open the transmission path between the power supply node nd and the first node n1, or open the transmission path between the power supply node nd and the second node n2.

[0077] During the programming operation, the input signal IN has a first voltage level, causing the gating module 202 to activate the transmission path between the power supply node nd and the first node n1 in response to the corresponding feedback signal VR1, thereby causing the power supply node nd to have a first voltage V1. During the reading operation, the input signal IN has a second voltage level, causing the gating module 202 to activate the transmission path between the power supply node nd and the second node n2 in response to the corresponding feedback signal VR1, thereby causing the power supply node nd to have a second voltage V2.

[0078] It is understood that in some embodiments, the gating module 202 may also directly respond to the input signal IN to enable the transmission path between the power supply node nd and the first node n1, or enable the transmission path between the power supply node nd and the second node n2.

[0079] Figure 8 Here is another functional block diagram of the voltage conversion circuit, see reference. Figure 8 The receiving module 201 may have a third node n3 and a fourth node n4. The receiving module 201 is also configured to: receive a reference signal VR0, compare the difference between the input signal IN and the level value of the reference signal VR0, and provide a feedback signal VR1 to the third node n3 and a differential feedback signal VR2 to the fourth node n4 as the comparison result. The feedback signal VR1 and the differential feedback signal VR2 are differential signals to each other.

[0080] If the level of the input signal IN is greater than the level of the reference signal VR0, then the level of the feedback signal VR1 is less than the level of the differential feedback signal VR2; if the level of the input signal IN is less than the level of the reference signal VR0, then the level of the feedback signal VR1 is greater than the level of the differential feedback signal VR2.

[0081] In some embodiments, the reference signal VR0 can be a fixed level value. In some embodiments, the reference signal VR0 and the input signal IN can also be inverted signals.

[0082] Continue to refer to Figure 8 The receiving module 201 may include: an input unit 21, connected to the third node n3 and the fourth node n4, configured to receive an input signal IN and a reference signal VR0, compare the difference between the level value of the input signal IN and the level value of the reference signal VR0, and provide a feedback signal VR1 to the third node n3 and a differential feedback signal VR2 to the fourth node n4; and a latch unit 22, connected to the third node n3 and the fourth node n4, configured to amplify the level difference between the feedback signal VR1 and the differential feedback signal VR2.

[0083] Figure 9 This is a schematic diagram of a voltage conversion circuit. (Reference) Figure 9 The input unit 21 may include: a first NMOS transistor MN1, whose gate receives the input signal IN, whose source is grounded, and whose drain is connected to the third node n3; and a second NMOS transistor MN2, whose gate receives the reference signal VR0, whose source is grounded, and whose drain is connected to the fourth node n4.

[0084] The latch unit 22 may include: a first PMOS transistor MP1, with its gate connected to the third node n3, its source connected to the first node n1, and its drain connected to the fourth node n4; and a second PMOS transistor MP2, with its gate connected to the fourth node n4, its source connected to the first node n1, and its drain connected to the third node n3.

[0085] refer to Figure 9 During programming, the input signal IN is high, and the corresponding reference signal VR0 is low. The first NMOS transistor MN1 is turned on, and the second NMOS transistor MN2 is turned off, making the voltage of the third node n3 less than the voltage of the fourth node n4. Since the gate of the first PMOS transistor MP1 is connected to the third node n3 and the gate of the second PMOS transistor MP2 is connected to the fourth node n4, the first PMOS transistor MP1 turns on before the second PMOS transistor MP2, and the conduction degree of the first PMOS transistor MP1 is greater than that of the second PMOS transistor MP2. Consequently, the current between the first node n1 and the fourth node n4 is greater than the current between the first node n1 and the third node n3, and the voltage of the fourth node n4 gradually increases while the voltage of the third node n3 gradually decreases.

[0086] Continue to refer to Figure 9During the read operation, the input signal IN is a low-level signal and the reference signal VR0 is a high-level signal. The first NMOS transistor MN1 is off, and the second NMOS transistor MN2 is on, making the voltage of the third node n3 greater than the voltage of the fourth node n4. Since the gate of the first PMOS transistor MP1 is connected to the third node n3 and the gate of the second PMOS transistor MP2 is connected to the fourth node n4, the first PMOS transistor MP1 turns on later than the second PMOS transistor MP2, and the conduction degree of the first PMOS transistor MP1 is less than that of the second PMOS transistor MP2. Consequently, the current between the first node n1 and the fourth node n4 is less than the current between the first node n1 and the third node n3, and the voltage of the fourth node n4 gradually decreases while the voltage of the third node n3 gradually increases.

[0087] Continue to refer to Figure 9 The gating module 202 may include: a first gating unit 31, connected to the power supply node nd and the first node n1, configured to respond to the feedback signal VR1 and the differential feedback signal VR2 during programming operations to enable the transmission path between the power supply node nd and the first node n1; and a second gating unit 32, connected to the power supply node nd and the second node n2, configured to respond to the feedback signal VR1 and the differential feedback signal VR2 during reading operations to enable the transmission path between the power supply node nd and the second node n2.

[0088] Specifically, during the programming operation, the first gating unit 31 is turned on to connect the power supply node nd to the first node n1; during the reading operation, the second gating unit 32 is turned on to connect the power supply node nd to the second node n2.

[0089] In some examples, if the voltage value of the feedback signal VR1 is less than the voltage value of the differential feedback signal VR2, indicating the corresponding programming operation stage, then the first gating unit 31 is turned on; if the voltage value of the feedback signal VR1 is greater than the voltage value of the differential feedback signal VR2, indicating the corresponding reading operation stage, then the second gating unit 32 is turned on.

[0090] Understandably, in other examples, depending on the specific connection relationship between the receiving module 201 and the gating module 202, it can also be designed as follows: if the voltage value of the feedback signal VR1 is greater than the voltage value of the differential feedback signal VR2, indicating the corresponding programming operation stage, then the first gating unit 31 is turned on; if the voltage value of the feedback signal VR1 is less than the voltage value of the differential feedback signal VR2, indicating the corresponding reading operation stage, then the second gating unit 32 is turned on.

[0091] refer to Figure 9The first gating unit 31 may include: a third PMOS transistor MP3, with its gate connected to the third node n3, its source connected to the first node n1, and its drain connected to the power supply node nd; and a fourth PMOS transistor MP4, with its gate connected to the fourth node n4, its source connected to the first node n1, and its drain connected to the fifth node n5; the second gating unit 32 includes: a third NMOS transistor MN3, with its gate connected to the fifth node n5, its drain connected to the drain of the third PMOS transistor MP3, and its source connected to the second node n2; and a fourth NMOS transistor MN4, with its gate connected to the power supply node nd, its drain connected to the drain of the fourth PMOS transistor MP4, and its source connected to the second node n2.

[0092] The first node n1 is used to receive the first voltage V1, and the second node n2 is used to receive the second voltage V2.

[0093] refer to Figure 9 When the voltage value of feedback signal VR1 is less than the voltage value of differential feedback signal VR2, it indicates that the operation is in progress and the second gating unit 32 is turned on. If the voltage value of feedback signal VR1 is greater than the voltage value of differential feedback signal VR2, it indicates that the operation is in progress and the first gating unit 31 is turned on.

[0094] During programming, the conduction level of the fourth PMOS transistor MP4 is less than that of the third PMOS transistor MP3, and the voltage at power supply node nd is greater than the voltage at the fifth node n5. The gate of the fourth NMOS transistor MN4 is connected to power supply node nd, and the gate of the third NMOS transistor MN3 is connected to the fifth node n5. The conduction level of the fourth NMOS transistor MN4 will be greater than that of the third NMOS transistor MN3. Thus, the voltage difference between power supply node nd and the fifth node n5 will be further amplified, with the voltage at power supply node nd increasing while the voltage at the fifth node n5 decreases, ultimately resulting in power supply node nd having a first voltage V1.

[0095] During the read operation, the conduction level of the fourth PMOS transistor MP4 is greater than that of the third PMOS transistor MP3, and the voltage at the power supply node nd is less than the voltage at the fifth node n5. The gate of the fourth NMOS transistor MN4 is connected to the power supply node nd, and the gate of the third NMOS transistor MN3 is connected to the fifth node n5. The conduction level of the fourth NMOS transistor MN4 will be less than that of the third NMOS transistor MN3. Thus, the voltage difference between the power supply node nd and the fifth node n5 will be further amplified, with the voltage at the power supply node nd decreasing while the voltage at the fifth node n5 increases, ultimately resulting in the power supply node nd having a second voltage V2.

[0096] It is understandable that during the conduction of the third PMOS transistor MP3, the equivalent resistance of the third PMOS transistor MP3 is very small or even negligible; during the conduction of the third NMOS transistor MN3, the equivalent resistance of the third NMOS transistor MN3 is very small or even negligible.

[0097] Figure 10 This is another functional block diagram of a voltage conversion circuit. (Reference) Figure 10 The receiving module 201 may further include: a first switching unit 23 connected between the third node n3 and the input unit 21, and a fourth node n4 connected between the input unit 21. The first switching unit 23 is configured to receive a first enable signal EN, and to be turned on during the period when the first enable signal EN is valid, and to be turned off during the period when the first enable signal EN is invalid.

[0098] Since the programmable non-volatile memory also has other stages besides the programming stage and the reading stage, such as the idle stage, there is no need to supply power to the power supply node nd in other stages. By adding an additional first switching unit 23, the input unit 21 and the latch unit 22 can be disconnected in other stages, so that the voltage of the third node n3 and the fourth node n4 will not change with the voltage of the input signal IN. That is, the input unit 21 and the latch unit 22 do not work to save power consumption.

[0099] It is understood that the first enable signal EN is valid during both programming and reading operations; and invalid during all other phases, except during programming and reading operations.

[0100] Figure 11 This is a schematic diagram of another circuit structure for a voltage conversion circuit. (Reference) Figure 11 The first switching unit 23 may include: a first switching transistor 231, whose gate receives a first enable signal EN, whose drain is connected to a third node n3, and whose source is connected to the input unit 21; and a second switching transistor 232, whose gate receives a first enable signal EN, whose drain is connected to a fourth node n4, and whose source is connected to the input unit 21.

[0101] Specifically, the first enable signal EN is valid when it is "1" and invalid when it is "0". It can be understood that a first enable signal EN of "1" means that the first enable signal EN is at a high level and the first switch 231 is turned on, while a first enable signal EN of "0" means that the first enable signal EN is at a low level and the first switch 231 is turned off.

[0102] The voltage conversion circuit 100 can also be configured to receive a second enable signal DIS and, during the period when the second enable signal DIS is valid, provide a third voltage to the power supply node nd, the third voltage being less than the second voltage V2; wherein, at the same time, one of the first enable signal EN and the second enable signal DIS is valid.

[0103] In stages other than the reading and programming stages, the voltage conversion circuit 100 can also provide a third voltage smaller than the second voltage V2 to the gate and second terminal of the protection transistor 13 to ensure that the protection transistor is in the cutoff region, that is, the protection transistor is in the off state, thereby reducing power consumption.

[0104] In some examples, the second enable signal DIS and the first enable signal EN can be inverted signals. In other words, when the first enable signal EN is "1", the corresponding second enable signal is "0", and when the first enable signal EN is "0", the corresponding second enable signal DIS is "1".

[0105] Figure 12 This is another functional block diagram of a voltage conversion circuit. (Reference) Figure 12 The voltage conversion circuit 100 may include: a reset module 203, connected between the operating power supply VDD and the third node n3 and the fourth node n4, configured to be turned on in response to a valid second enable signal DIS, so that the third node n3 and the fourth node n4 are both connected to the operating power supply VDD; and a power supply module 204, connected between the sixth node n6 and the power supply node nd, configured to be turned on in response to a valid second enable signal DIS, so that the power supply node nd is connected to the sixth node n6, and the sixth node n6 is used to receive the third voltage.

[0106] In stages other than read and program operations, the reset module 203 is turned on so that the third node n3 and the fourth node n4 are both at high voltage, thereby controlling the third PMOS transistor MP3 and the fourth PMOS transistor MP4 to be turned off, and the first PMOS transistor MP1 and the second PMOS transistor MP2 to be turned off. The power supply module 204 is then turned on so that the power supply node nd is connected to the sixth node n6, thereby giving the sixth node n6 the third voltage.

[0107] Figure 13 This is a schematic diagram of another circuit structure for a voltage conversion circuit. (Reference) Figure 13 The reset module 203 may include: a fifth NMOS transistor, whose gate receives the second enable signal DIS and is connected between the third node n3 and the operating power supply VDD; and a sixth NMOS transistor, whose gate receives the second enable signal DIS and is connected between the fourth node n4 and the operating power supply VDD.

[0108] Understandably, in order to reduce the current flowing from the operating power supply VDD to the third node n3 and the fourth node n4 when the reset module 203 is turned on, the reset module 203 may further include: at least one voltage divider resistor connected in series between the operating power supply VDD and the third node n3; and at least one voltage divider resistor connected in series between the operating power supply VDD and the third node n3. The voltage divider resistor may be composed of an NMOS transistor in the on state.

[0109] In addition, the operating power supply connected to the reset module 203 can be the same as the first voltage provided by the first node n1.

[0110] Continue to refer to Figure 13 The power supply module 204 may include: a seventh NMOS transistor MN7, whose gate receives a second enable signal DIS, and is connected between power supply node nd and sixth node n6 (see reference). Figure 12 Between ), where the sixth node n6 can be connected to ground, meaning the third voltage can be 0.

[0111] Continue to refer to Figure 13 The power supply module 204 may further include: at least one eighth NMOS transistor MN8 connected in series between the ground terminal and the seventh NMOS transistor MN7, wherein the eighth NMOS transistor MN8 is in the on state; and / or, at least one ninth NMOS transistor MN9 connected in series between the power supply node nd and the seventh NMOS transistor MN7, wherein the ninth NMOS transistor MN9 is in the on state.

[0112] It is understandable that the power supply module 204 may include only one of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9, or it may include both the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9.

[0113] The power supply module 204 may further include a seventh NMOS transistor MN7 connected between the fifth node n5 and the ground, a ninth NMOS transistor MN7 connected in series between the fifth node n5 and the seventh NMOS transistor MN7, and / or an eighth NMOS transistor MN8 connected in series between the seventh NMOS transistor MN7 and the ground.

[0114] In the programmable non-volatile memory technical solution provided in the above embodiments, the voltage conversion circuit 100 can provide different voltages to the gate and the second terminal of the protection transistor 13 at different times. Specifically, during programming operations, the voltage conversion circuit 100 can provide a relatively large first voltage to the gate and second terminal of the protection transistor 13, so that the protection transistor 13 is turned on and pulls up the voltage of the non-target bit line, thereby reducing the voltage difference across the antifuse unit 10 connected to the non-target bit line, and thus protecting the antifuse unit 10 connected to the non-target bit line. During reading operations, the voltage conversion circuit 100 can provide a second voltage greater than zero and less than the first voltage to the gate and second terminal of the protection transistor 13, so that the protection transistor 13 can provide a sinking current to the target bit line. This sinking current can compensate for the leakage current on the transmission path between the data line Faconn and the target bit line, thereby preventing the charge of the data line Faconn from being discharged too quickly. This ensures that during the read operation of reading the stored data "1", the voltage of the data line Faconn will not be affected by the leakage current and decrease to an undesirable voltage value, so as to ensure that the stored data "1" can be read accurately.

[0115] Accordingly, this disclosure also provides an operation method for the programmable non-volatile memory provided in the above embodiments. The operation method will be described below. It is understood that the above detailed description of the programmable non-volatile memory is also applicable to the embodiments of the operation method. Similarly, the following description of the operation method is also applicable to the above embodiments of the programmable non-volatile memory.

[0116] The operation method includes: during the programming operation of the programmable non-volatile memory, the voltage conversion circuit operates in response to the input signal to provide a first voltage to the power supply node; during the reading operation of the programmable non-volatile memory, the voltage conversion circuit operates in response to the input signal to provide a second voltage to the power supply node, the second voltage being less than the first voltage.

[0117] During programming, the gate and second terminal of the protection transistor are both connected to a first voltage to turn on the protection transistor. The voltage at the first terminal of the protection transistor is the first voltage minus the threshold voltage of the protection transistor. In other words, the voltage of the bit lines connected to the protection transistor is the first voltage minus the threshold voltage of the protection transistor. The bit lines connected to the protection transistor include both target bit lines and non-target bit lines. Because the first voltage is relatively large, the non-target bit lines have a relatively large voltage, which helps to reduce the voltage difference across the unprogrammed antifuse cells connected to the non-target bit lines. This protects the unprogrammed antifuse cells and improves the lifespan of the programmable non-volatile memory.

[0118] During the read operation, a second voltage is connected to both the gate and the second terminal of the protection transistor to turn it on and provide a sinking current from the second terminal to the first terminal to the target bit line. This counteracts leakage current from other transistors connected to the target bit line, preventing the data line from being discharged too quickly and improving the accuracy of the read results. Furthermore, this sinking current also counteracts leakage current along paths other than the target bit line.

[0119] In some examples, the first voltage can satisfy the following condition: during programming operations, the gate and second terminal of the protection transistor receive the first voltage, causing the protection transistor to operate in the saturation region, V. GS Greater than V TH V DS Greater than V GS -V TH For example, during programming, the magnitude of the first voltage is the same as the voltage received by the word line when it is turned on. Where V GS To protect the voltage between the gate and source of the transistor, V TH To protect the threshold voltage of the transistor, V DS To protect the voltage between the drain and source of the transistor.

[0120] The second voltage should satisfy the following conditions: during the read operation, the gate and second terminal of the protection transistor receive the second voltage, and the sink current flowing out from the first terminal is sufficient to compensate for the leakage current, so as to avoid the problem of read error when reading stored data "1" due to leakage current. Furthermore, this sink current should not be too large. If the sink current is too large, it may cause the discharge to be too slow when reading stored data "0", which may cause the read stored data "0" error.

[0121] Additionally, it is understandable that the magnitude of the second voltage can be set according to the actual situation. For example, a leakage current test can be performed first to obtain the actual leakage current caused by other transistors connected to the target bit line to the target bit line. Then, the sink current provided by the protection transistor can be the same as or close to the actual leakage current. The magnitude of the second voltage can be calculated based on the channel width-to-length ratio, threshold voltage, and actual leakage current of the protection transistor.

[0122] When the programmable non-volatile memory is not in a programming operation or a reading operation, the voltage conversion circuit also responds to a second enable signal to provide a third voltage to the power supply node, the third voltage being less than the second voltage.

[0123] In some embodiments, the third voltage satisfies the condition that the gate and second terminal of the protection transistor receive the second voltage, causing the protection transistor to operate in the cutoff region. This helps to reduce the power consumption of the programmable non-volatile memory.

[0124] In some cases, the third voltage can be 0.

[0125] It should be noted that the terms "high level" and "low level" in the above embodiments are relative concepts (i.e., the voltage value of a high level is higher than the voltage value of its corresponding low level), and there is no limitation on the specific voltage value of the high level or the specific voltage value of the low level. Furthermore, it is not limited that the high voltage applied to different signal lines in this specific embodiment is equal; for example, the high level on the bit line and the high level on the word line can be different voltages. It is also not limited that the high level of a specific signal line is equal at different stages; for example, the high level applied to the bit line during a write operation and during a read operation can be different voltage values.

[0126] Those skilled in the art should understand that the values ​​of the corresponding high and low levels can be set according to process nodes, speed requirements, reliability requirements, etc. Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the protection scope of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A programmable non-volatile memory, characterized in that, include: The antifuse units are arranged in multiple rows and columns. Each column of the antifuse units is connected to the data line via a corresponding column switch, and each column of the antifuse units is connected to a bit line via a corresponding row switch. All the row switches connected to the antifuse units in the same row are connected to a line. Multiple protection transistors, each of which has a first terminal connected to a bit line, and a second terminal and a gate of each of which are connected to a power supply node. A voltage conversion circuit, connecting a first node and a second node, wherein the first node provides a first voltage and the second node provides a second voltage, is configured to receive an input signal, operate in response to the input signal during a programming operation to establish a transmission path between the power supply node and the first node, and operate in response to the input signal during a reading operation to establish a transmission path between the power supply node and the second node, wherein the input signal has different voltage levels during the programming operation and the reading operation, and the second voltage and the first voltage satisfy: 0 < V2 < V1, where V2 is the second voltage and V1 is the first voltage; The voltage conversion circuit includes: The receiving module is configured to receive the input signal and provide a feedback signal corresponding to the input signal; The gating module, connecting the power supply node, the first node, and the second node, is configured to, in response to the feedback signal, either enable the transmission path between the power supply node and the first node, or enable the transmission path between the power supply node and the second node.

2. The programmable non-volatile memory as described in claim 1, characterized in that, The receiving module has a third node and a fourth node, and the receiving module is further configured to: The system receives a reference signal, compares the level difference between the input signal and the reference signal, and provides the feedback signal to the third node and a differential feedback signal to the fourth node as the comparison result. The feedback signal and the differential feedback signal are differential signals to each other. Wherein, if the level value of the input signal is greater than the level value of the reference signal, then the level value of the feedback signal is less than the level value of the differential feedback signal; if the level value of the input signal is less than the level value of the reference signal, then the level value of the feedback signal is greater than the level value of the differential feedback signal.

3. The programmable non-volatile memory as described in claim 2, characterized in that, The reference signal and the input signal are inverse signals.

4. The programmable non-volatile memory as described in claim 2, characterized in that, The receiving module includes: An input unit, connected to the third node and the fourth node, is configured to receive the input signal and the reference signal, compare the difference between the level value of the input signal and the level value of the reference signal, and provide the feedback signal to the third node and the differential feedback signal to the fourth node. The latch unit, connected to the third node and the fourth node, is configured to amplify the level difference between the feedback signal and the differential feedback signal.

5. The programmable non-volatile memory as described in claim 4, characterized in that, The input unit includes: The first NMOS transistor has its gate receiving the input signal, its source grounded, and its drain connected to the third node. The second NMOS transistor has its gate receiving the reference signal, its source grounded, and its drain connected to the fourth node. The latch unit includes: The first PMOS transistor has its gate connected to the third node, its source connected to the first node, and its drain connected to the fourth node. The second PMOS transistor has its gate connected to the fourth node, its source connected to the first node, and its drain connected to the third node.

6. The programmable non-volatile memory as described in claim 4, characterized in that, The receiving module further includes: A first switching unit, connected between the third node and the input unit, and connected between the fourth node and the input unit, is configured to receive a first enable signal and be turned on during the period when the first enable signal is valid, and turned off during the period when the first enable signal is invalid.

7. The programmable non-volatile memory as described in claim 6, characterized in that, The first switching unit includes: The first switching transistor has a gate that receives the first enable signal, a drain that is connected to the third node, and a source that is connected to the input unit. The second switch has its gate receiving the first enable signal, its drain connected to the fourth node, and its source connected to the input unit.

8. The programmable non-volatile memory as described in claim 2, characterized in that, The gating module includes: A first gating unit, connecting the power supply node and the first node, is configured to respond to the feedback signal and the differential feedback signal during programming operations to enable a transmission path between the power supply node and the first node. The second gating unit, connected to the power supply node and the second node, is configured to respond to the feedback signal and the differential feedback signal during a read operation to enable a transmission path between the power supply node and the second node.

9. The programmable non-volatile memory as described in claim 8, characterized in that, The first gating unit includes: The third PMOS transistor has its gate connected to the third node, its source connected to the first node, and its drain connected to the power supply node. The fourth PMOS transistor has its gate connected to the fourth node, its source connected to the first node, and its drain connected to the fifth node. The second gating unit includes: The third NMOS transistor has its gate connected to the fifth node, its drain connected to the drain of the third PMOS transistor, and its source connected to the second node. The fourth NMOS transistor has its gate connected to the power supply node, its drain connected to the drain of the fourth PMOS transistor, and its source connected to the second node.

10. The programmable non-volatile memory as described in claim 6, characterized in that, The voltage conversion circuit is further configured to receive a second enable signal and, during the period when the second enable signal is valid, provide a third voltage to the power supply node, the third voltage being less than the second voltage; At any given time, one of the first enable signal and the second enable signal is active.

11. The programmable non-volatile memory as claimed in claim 10, characterized in that, The second enable signal is the inverse of the first enable signal.

12. The programmable non-volatile memory as claimed in claim 10, characterized in that, The voltage conversion circuit includes: A reset module, connected between the operating power supply and the third node and the fourth node, is configured to be turned on in response to a valid second enable signal, so that both the third node and the fourth node are connected to the operating power supply; A power supply module, connected between the sixth node and the power supply node, is configured to be turned on in response to a valid second enable signal, so that the power supply node is connected to the sixth node, the sixth node being used to receive the third voltage.

13. The programmable non-volatile memory as described in claim 12, characterized in that, The reset module includes: The fifth NMOS transistor, whose gate receives the second enable signal, is connected between the third node and the operating power supply; The sixth NMOS transistor, whose gate receives the second enable signal, is connected between the fourth node and the operating power supply.

14. The programmable non-volatile memory as claimed in claim 12, characterized in that, The power supply module includes: The seventh NMOS transistor, whose gate receives the second enable signal, is connected between the power supply node and the sixth node.

15. The programmable non-volatile memory as described in claim 14, characterized in that, The sixth node is connected to the ground terminal; the power supply module also includes: At least one eighth NMOS transistor is connected in series between the ground terminal and the seventh NMOS transistor, and the eighth NMOS transistor is in the on state; And / or, At least one ninth NMOS transistor is connected in series between the power supply node and the seventh NMOS transistor, and the ninth NMOS transistor is in the on state.

16. The programmable non-volatile memory as claimed in claim 1, characterized in that, Also includes: A pre-charging circuit, connected to the data line, is used to pre-charge the data line during a read operation.

17. An operation method applied to a programmable non-volatile memory as described in any one of claims 1-16, characterized in that, include: During the programming operation of the programmable non-volatile memory, the voltage conversion circuit operates in response to the input signal to provide the first voltage to the power supply node; During a read operation of the programmable nonvolatile memory, the voltage conversion circuit operates in response to the input signal to provide the second voltage to the power supply node.

18. The operating method as described in claim 17, characterized in that, Also includes: When the programmable non-volatile memory is not in a programming operation and is not in a reading operation, the voltage conversion circuit also responds to a second enable signal to provide a third voltage to the power supply node, the third voltage being less than the second voltage.

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