Data transmission method, device, electronic device and storage medium

Abstract

The present application discloses a data transmission method, device, electronic device and storage medium, and relates to the technical field of data processing. The method comprises: determining whether the length of a data packet to be transmitted is less than a preset length; if not, transmitting data to the data packet by DMA; if so, further determining whether there are multiple continuous small data packets: if not, transmitting data to the data packet by DMA; if so, merging the multiple continuous small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets, and then transmitting data to the merged one or more large data packets by DMA. The present application avoids the frequent use of DMA for small data packet transmission, and improves the stability and efficiency of DMA transmission. The present application also discloses a data transmission device, an electronic device and a computer-readable storage medium, which have the above beneficial effects.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data transmission method, device, electronic device and computer-readable storage medium. Background Art

[0002] PCIE (Peripheral Component Interconnect Express) is a commonly used high-speed transmission protocol, usually used for data transmission between the host and various external devices, such as PCIE interface memory, network card, GPU (graphics processing unit), FPGA (Field Programmable Gate Array) and other devices. In the process of PCIE communicating with external devices, DMA (Direct Memory Access) technology is generally used to move data. During the data movement process, the CPU (central processing unit) gives the bus control authority to the DMA controller, and the DMA controller reports an interrupt to the CPU after moving the data. This process can relieve the pressure on the CPU and improve transmission efficiency.

[0003] In the related art, the DMA implementation methods generally used are mainly divided into block DMA and chained DMA. When performing a DMA read or write, multiple linked lists can be configured, so that when the data transmission of a linked list is completed, it will jump to the starting address of the next linked list and continue to transmit data until the next address of the linked list is 0. If the DMA enables the completion interrupt, the completion interrupt will be entered when the DMA send or receive is completed. However, whether it is block DMA or chained DMA, when transmitting small data packets, the bandwidth utilization rate will be severely reduced, resulting in a huge waste of performance. At the same time, frequent use of DMA to move small packet data may also cause the CPU to receive a large number of interrupts, which is extremely likely to cause the host to hang and reduce the stability of data transmission. In other technologies, for small data packets, non-DMA methods are used for processing, which wastes DMA equipment and is still not ideal. Summary of the invention

[0004] The purpose of this application is to provide a data transmission method, device, electronic device and storage medium to improve the utilization of PCIE bandwidth and improve the reliability of host operation.

[0005] In order to solve the above technical problems, the present application provides a data transmission method, comprising:

[0006] Determining whether the length of the data packet to be transmitted is less than a preset first length;

[0007] If not, data transmission of the data packet is performed through DMA;

[0008] If yes, then further determine whether there are multiple consecutive small data packets:

[0009] If not, data transmission of the data packet is performed through DMA;

[0010] If so, the multiple consecutive small data packets are merged into one or more large data packets and the descriptors of the corresponding data packets are modified, and the merged one or more large data packets are transmitted through DMA.

[0011] Furthermore, the data transmission method is suitable for chained DMA transmission.

[0012] Furthermore, the data transmission method is suitable for block DMA transmission.

[0013] Furthermore, the step of merging the multiple consecutive small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets, and transmitting the merged one or more large data packets through DMA also includes: after merging a large data packet, transmitting the merged data packet through DMA, and then merging the next large data packet.

[0014] Furthermore, the step of merging the multiple consecutive small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets also includes: deleting the DMA descriptors of the multiple consecutive small data packets in the DMA linked list, and inserting the DMA descriptors of the merged one or more large data packets.

[0015] Furthermore, the step of merging the multiple consecutive small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets also includes: sequentially merging the multiple consecutive small data packets into a large data packet until the large data packet exceeds a preset second length, and then starting to merge the remaining small data packets into the next large data packet until the multiple consecutive small data packets are all merged.

[0016] Furthermore, the step of merging the multiple continuous small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets also includes: migrating the multiple continuous small data packets to a physically continuous memory area in sequence, and synchronously deleting the DMA descriptors of the migrated small data packets in the DMA linked list.

[0017] This solution first determines whether the length of the data packet to be transmitted is less than a preset length. If it is less than the preset length, it means that the data packet is a small data packet. It further determines whether there are multiple consecutive small data packets. If there are multiple consecutive small data packets, the data descriptor is modified to merge the multiple small data packets into one or more large data packets of appropriate sizes. The large data packets are transmitted using DMA. When it is greater than the preset length, the data packet is directly transmitted using DMA. Since the data descriptor actually belongs to a linked list data structure, it has the advantage of efficient insertion and deletion operations. By modifying the pointers and sizes of several consecutive small data packets, the continuous small data are merged into a large data packet. Then, DMA is still used for data transmission, avoiding the problems existing in the frequent DMA transmission of small data packets, improving the efficiency of data transmission, and at the same time reducing the problems existing in multiple large DMA requests, improving the stability of transmission.

[0018] The present application also provides another data transmission device, electronic device and computer-readable storage medium, which have the above beneficial effects and are not elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate some embodiments of the present application or technical solutions in the prior art, the drawings required for use in the embodiments or descriptions of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0020] Figure 1 DMA descriptors and DMA linked lists provided for some embodiments of the present application;

[0021] Figure 2 A flowchart of a data transmission method provided in some embodiments of the present application;

[0022] Figure 3 A packet conversion flow chart of a data transmission method provided in some embodiments of the present application;

[0023] Figure 4 A schematic diagram of the structure of a packet conversion module of a data transmission method provided by some embodiments of the present application;

[0024] Figure 5 A schematic diagram of the structure of a data transmission device provided in some embodiments of the present application;

[0025] Figure 6 A schematic diagram of the structure of an electronic device provided in some embodiments of the present application;

[0026] Figure 7 A schematic diagram of the structure of a computer storage device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0027] The core of this application is to provide a data transmission method, another data transmission method, two PCIE data transmission devices, an electronic device and a computer-readable storage medium to improve the utilization of PCIE bandwidth and improve the reliability of host operation.

[0028] In order to make the purpose, technical solutions and advantages of some embodiments of the present application clearer, the technical solutions in some embodiments of the present application will be clearly and completely described below in conjunction with the drawings in some embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] In the related art, the DMA implementation methods generally used are mainly divided into block DMA and chain DMA. Block DMA can transmit multiple data packets at a time, reducing interrupt processing. However, when the CPU processes data, it needs to parse the data packet from the entire block of data and copy it to the corresponding cache, which increases the work of the CPU. Chain DMA can record the transmission addresses of different data packets in a linked list. DMA transmits by reading the linked list information, and reports the interrupt only after all the linked list items are processed. If the data packets are continuous, the more linked list items there are, the higher the DMA efficiency. If the data packets are not continuous, too many items will increase the waiting time for the linked list to complete, reducing the CPU's processing efficiency of data. If there are fewer linked list items, the number of interrupts will increase, and interrupt processing will occupy a large amount of CPU resources. However, whether it is block DMA or chain DMA, when transmitting small packets, the bandwidth utilization rate will be seriously reduced, resulting in a huge waste of performance. At the same time, frequent use of DMA to move small packet data may also cause the CPU to receive a large number of interrupts, which is extremely easy to cause the host to hang and reduce the stability of data transmission.

[0030] Figure 1 DMA descriptors and DMA linked lists provided for some embodiments of the present application; see Figure 1, DMA descriptor (Direct Memory Access Descriptor) and DMA chain list (Direct Memory Access Chain List) are two key concepts used in DMA (Direct Memory Access) operations. They are usually used when large amounts of data are transferred between hardware devices and system memory. A DMA descriptor is a data structure that contains all the information required for DMA transfers. This information may include source address, destination address, transfer length, transfer type, pointer to completion interrupt handler, etc. The role of the descriptor is to tell the DMA controller how to transfer data. During DMA transfers, descriptors are used by the DMA controller to guide and control data transfers. A DMA chain list is a chain data structure consisting of a series of DMA descriptors. Each descriptor points to the next descriptor to form a chain list. The DMA chain list is used to manage complex DMA transfers. It can support multiple simultaneous transfers or multiple data blocks involved in a transfer. Through the chain list, continuous data transfer can be achieved without CPU intervention. During DMA transfers, the DMA controller uses the DMA chain list to obtain the next DMA descriptor to be processed. When a DMA transfer is completed, the DMA controller jumps to the next descriptor according to the pointer in the chain list and continues to perform the next transfer task. Therefore, DMA descriptors and DMA linked lists are closely related. The DMA linked list provides a sequence of descriptors, while the DMA descriptors define the specific details of each transfer.

[0031] When performing a DMA read or write, multiple linked lists can be configured so that when the data transfer of a linked list is completed, it will jump to the starting address of the next linked list and continue to transfer data until the next address of the linked list is 0. If the DMA enables the completion interrupt, it will enter the completion interrupt when the DMA send or receive is completed.

[0032] Therefore, the present application provides a data transmission scheme, which first determines whether the length of the data packet to be transmitted is less than the preset length. If it is less than the preset length, it means that the data packet is a small data packet, and the data packet is transmitted through the space of the base address register instead of using the DMA method for transmission. When it is greater than the preset length, the data packet is transmitted through the DMA method, which realizes the use of non-DMA methods for data transmission of small data packets, avoids the problems existing in the DMA method, improves the efficiency of data transmission, and reduces the problems existing in multiple large DMA requests. Improves the stability of transmission.

[0033] The following describes a data transmission method provided by the present application through an embodiment.

[0034] Please refer to Figure 2 , Figure 2 A flowchart of a data transmission method provided in some embodiments of the present application.

[0035] In this embodiment, the method may include:

[0036] S101, determining whether the length of the data packet to be transmitted is less than a preset first length;

[0037] This step is intended to determine whether the length of the data packet to be transmitted is less than a preset length, that is, to determine whether the data packet is a small data packet.

[0038] The preset length may be set based on the experience of a technician, or may be set based on the size of a data packet with a large number of requests in historical transmission data.

[0039] The length of the data packet to be transmitted can be obtained by reading the descriptor of the data packet, or by other means, such as traversal reading, etc. Generally speaking, the method of reading the descriptor is the simplest and most convenient.

[0040] Furthermore, this step may include:

[0041] Determine whether the length of the data packet to be transmitted is less than the minimum packet length of DMA transmission.

[0042] It can be seen that this step may include determining whether the length of the data packet to be transmitted is less than the minimum packet length of DMA transmission. In the DMA transmission process, there is a process of carrying data according to a fixed data packet length. Therefore, there are multiple data packet sizes of different lengths, and the smallest packet length can be selected in this optional solution.

[0043] Furthermore, this step may include:

[0044] The FPGA device determines whether the length of the data packet to be transmitted is less than a preset length.

[0045] It can be seen that this optional solution mainly illustrates that the FPGA device can be used to determine whether the length of the data packet to be transmitted is less than the preset length. Among them, other digital ICs (Integrated Circuits) can also be used.

[0046] Among them, the interface bus of the FPGA device is a standard AXI (Advanced eXtensible Interface, a bus protocol) bus.

[0047] Furthermore, this step may include:

[0048] The length of the data packet is obtained by reading the descriptor of the data packet through the DMA controller.

[0049] S102, if yes, further determine whether there are multiple consecutive small data packets;

[0050] S1021, if not, the data packet is transmitted via DMA.

[0051] That is to say, if the next data packet is not a small data packet, the data packet is transmitted through DMA. In this case, there is only one small data packet between large data packets. Even if it is transmitted through DMA, it will not bring frequent DMA requests and is tolerable. At the same time, this method avoids the operation of the linked list and the migration of data packets, but actually improves the migration efficiency of data packets.

[0052] S1022: If yes, merge multiple consecutive small data into one or more large data packets, and transmit the merged one or more large data packets through DMA.

[0053] See also Figure 3 , Figure 3 A packet conversion flow chart of a data transmission method provided for some embodiments of the present application; merging multiple consecutive small data packets until the next data packet is a large data packet or the merged data packet exceeds a preset second length; it should be noted that the preset second length in this step is generally not equal to the preset first length in the above-mentioned step S101, but as a special case, the preset second length in this step may also be equal to the preset first length in the above-mentioned step S101.

[0054] Based on S101, this step aims to merge multiple consecutive small data packets into one or more large data packets; it should be further explained that the "continuous" here means that the multiple small data packets are logically continuous, but not necessarily continuous in the physical address space. For example, a small data packet to be transmitted and the next data packet to be transmitted are also small data packets, so the two small data packets are logically continuous; however, as a special case of continuity, if multiple logically continuous small data packets happen to be continuous in the address space, it also meets the definition of continuity in this scheme, that is, continuity in the address space is not necessary.

[0055] When the length of the data packet is less than the preset first length, it is necessary to further determine whether the next one or more data packets of the data packet are still small data packets. If the next one or more data packets are still small data packets, multiple logically continuous small data packets are combined into one or more large data packets of appropriate size, and the DMA linked list and DMA descriptor are modified at the same time. That is, the DMA descriptors of the combined one or more large data packets are inserted into the DMA linked list, and the DMA descriptors of the original multiple small data packets are deleted.

[0056] Furthermore, as one of many possible implementations, the step of merging multiple consecutive small data packets into one or more large data packets, and transmitting the merged one or more large data packets through DMA also includes: after merging a large data packet, transmitting the merged data packet through DMA, and then merging the next large data packet.

[0057] Furthermore, as one of many possible implementations, the step of merging multiple consecutive small data packets into one or more large data packets also includes: deleting the DMA descriptors of the multiple consecutive small data packets in the DMA linked list, and inserting the DMA descriptors of the merged one or more large data packets.

[0058] Furthermore, as one of many possible implementations, the step of merging multiple consecutive small data packets into one or more large data packets also includes: sequentially merging multiple consecutive small data packets into a large data packet until a large data packet exceeds a preset second length, and then starting to merge the remaining small data packets into the next large data packet until multiple consecutive small data packets are merged.

[0059] Furthermore, as one of many possible implementations, the step of merging multiple consecutive small data packets into one or more large data packets also includes: migrating the multiple consecutive small data packets to a physically continuous memory area in sequence, and synchronously deleting the DMA descriptors of the migrated small data packets in the DMA linked list.

[0060] As one of many possible implementations, the combined large data packet can be a physically continuous area in the host memory, and the size of the continuous area should be larger than the aforementioned "appropriate size" and have sufficient margin. As one of many possible implementations, the physically continuous area is applied for and managed by the DMA controller. The aforementioned "appropriate size" is not necessarily a fixed value, it can be greater than a certain value, or it can be a range value.

[0061] As one of multiple possible implementations, the physically continuous area may also be located outside the host memory, such as a cache area, a virtual memory, etc.

[0062] As one of the multiple possible implementations, the physically continuous area is located outside the host memory and exists as a relatively independent storage component, which is connected to the memory and the DMA controller but not directly connected to the CPU. In other words, the storage component is used as a dedicated data migration cache area, which is simple and reliable.

[0063] It can be seen that the transmission frequency of small data packets can be reduced through this step, and all data packets are finally transmitted by DMA, which improves the efficiency and stability of data transmission; at the same time, the processing of multiple continuous small data packets in this step is carried out by modifying the linked list of descriptors. The characteristic of the linked list is that it is easy to insert, modify and delete. Therefore, by reading the sizes of multiple continuous data packets in the descriptor of the data packet, calculating the sum of the sizes of the multiple small data packets, and modifying the source address and destination address information, the merging of multiple continuous small data packets can be completed at a low cost, and it will not cause a high cost.

[0064] The circuit components of the DMA controller (Direct Memory Access Controller) mainly include the following parts: Request receiving circuit, which is responsible for receiving DMA request signals from peripheral devices. These requests can start DMA transfers by level triggering or edge triggering. Arbitration logic circuit, when multiple peripheral devices request DMA services at the same time, the arbitration logic circuit is responsible for deciding which device gets control, which usually involves priority judgment and request queue management. Control logic circuit: It controls the data transfer process according to the content of the DMA descriptor and the system's DMA strategy. This includes the generation of control signals such as start transfer, stop transfer, transfer direction, data size and transfer mode. Address generation circuit, which is used to generate source address and destination address. During the transfer process, the address generation circuit may automatically increase the address to achieve continuous data transfer. Counter, which is used to record the amount of data transferred or the number of transfers. When the counter reaches the preset value, the DMA transfer is completed. Data buffer register, which is used to temporarily store data during the transfer process. It can act as a buffer between the memory and the peripheral device, reduce the number of memory accesses, and improve the transmission efficiency. Data transfer circuit, which is responsible for the actual data transfer, including loading data from the source address to the buffer register, transferring data from the buffer register to the target address, and latching data. Interrupt control circuit, when the DMA transfer is completed or an error occurs, the interrupt control circuit will generate an interrupt request to notify the CPU for subsequent processing. Status register, used to store the status information of the DMA controller, such as whether the transfer is completed, whether an error occurs, etc. Interface circuit, used to connect the DMA controller to the system bus, peripheral device interface, etc. This may include address lines, data lines, control lines, etc. Clock circuit, provides the basic clock signal required for the DMA controller to operate. The clock circuit ensures that all operations of the DMA controller are synchronized.

[0065] Please refer to Figure 4 , Figure 4A schematic diagram of the structure of a packet conversion module of a data transmission method provided by some embodiments of the present application. As one of the multiple possible implementations, the packet conversion module in the present application, as a part of the DMA controller circuit, is used to complete the conversion of multiple continuous small data packets into large data packets and modify the descriptors in the DMA linked list. That is to say, in this way, the packet conversion module is implemented by designing a dedicated circuit in the DMA. Obviously, in this way, its essence is implemented by a hardware circuit. Obviously, in this way, the DMA hardware circuit needs to be redesigned, but this way is more efficient, and it also inevitably increases the circuit complexity of the DMA.

[0066] As one of many possible implementations, the packet conversion module in the present application, as an external circuit of the DMA controller, is implemented through hardware programming through FPGA. In this way, it communicates with the DMA controller through a PCIE connection. In this way, there is no need to redesign the DMA circuit, and the existing DMA devices can be fully utilized, but the efficiency is slightly low. As one of many possible implementations, the packet conversion module in the present application is implemented by software, such as firmware in DMA. The advantage of this method is that it does not require redesigning the hardware circuit of DMA, but uses firmware to control the existing DMA circuit to realize the data packet repackaging function, which is slightly less efficient, but the cost is correspondingly lower.

[0067] S103: If not, data transmission of the data packet is performed through DMA.

[0068] Based on S101, this step aims to transmit the data packet by DMA, that is, in other cases, the DMA is used to transmit the data, thus avoiding a large number of requests for small data packets.

[0069] Furthermore, this step may include:

[0070] Data packets are transferred via chained DMA.

[0071] It can be seen that in this optional solution, the data packet is transmitted through the chained DMA mode. This solution is mainly applicable to data transmission in the chained DMA mode.

[0072] Among them, the chained DMA method describes the discrete physical memory blocks to be transferred one by one through multiple descriptors and forms a descriptor table, loads the address of the first descriptor into the descriptor base register of the DMA, and then starts the DMA request. DMA can complete the transfer of n memory blocks at a time.

[0073] As a special case, this solution can also transmit data packets through block DMA.

[0074] Blocking DMA itself does not require a DMA linked list, because blocking DMA usually refers to the transfer of one data block at a time, and the size and destination of this data block are fixed or have been set by the CPU before the transfer. In this case, DMA transfer is single and synchronous, and no linked list is required to manage the transfer of multiple data blocks. However, in some more advanced DMA implementations, even block DMA may use a linked list to manage multiple DMA descriptors, which can achieve more flexible data transfer modes. This linked list is usually called a DMA linked list (DMADescriptor Chain). Each node in the DMA linked list contains one or more DMA descriptors, each of which defines the parameters of a data transfer, such as source address, destination address, transfer length, etc. In order to improve flexibility and efficiency, DMA linked lists are often used in various DMA transfer modes, including block DMA. In these systems, DMA linked lists can be used to implement more complex transfer logic, such as cyclic transfer, conditional transfer, etc.

[0075] The above data transmission method can be used with a PCIE external device provided in this embodiment, including:

[0076] PCIE communication module, used to implement the physical link layer and protocol layer of communication with the host;

[0077] Bus protocol interconnection module, used for interconnection between buses;

[0078] The packet conversion module is used to convert the read and write data of the base address register space to the DMA read and write data interface;

[0079] The storage control interface module is used to convert the storage interface into a standard AXI bus interface.

[0080] The packet conversion module includes:

[0081] An internal management module, used to configure the continuous memory space;

[0082] A packet combination module is used to write multiple consecutive small data packets into a consecutive memory space;

[0083] The linked list modification module is used to modify the descriptor items in the linked list.

[0084] In summary, this solution first determines whether the length of the data packet to be transmitted is less than the preset length. If it is less than the preset length, it means that the data packet is a small data packet. It further determines whether there are multiple consecutive small data packets. If there are multiple consecutive small data packets, the data descriptor in the linked list is modified, and the multiple small data packets are merged into one or more large data packets of appropriate size, and the large data packets are transmitted using DMA; when it is greater than the preset length, the data packet is directly transmitted via DMA. Since the linked list, as a data structure, has the advantages of efficient deletion, insertion and deletion operations, by modifying the pointers and sizes of several consecutive small data packets, the continuous small data are merged into a large data packet, and then the data is still transmitted using DMA, avoiding the problems existing in the frequent DMA transmission of small data packets, improving the efficiency of data transmission, and at the same time reducing the problems caused by multiple large DMA requests, and improving the stability of transmission.

[0085] It should be further explained that in some special cases, such as the distribution of data packet sizes as: large data packet|small data packet|large data packet|small data packet..., that is, large and small data packets are arranged alternately, in this case, it is not necessary to take a data packet merging operation, because in this case, there are no continuous and frequent small data packet transmission requests. In some other special cases, such as the distribution of data packets as small data packet|small data packet|small data packet..., that is, there are multiple continuous small data packets, and the sum of the sizes of multiple continuous small data packets is very large. In this case, it is not suitable to merge all continuous small data packets into a large data packet. In the embodiment of the present application, in this case, multiple continuous small data packets are merged into multiple large data packets of appropriate sizes. Obviously, in this case, the solution in the present application reduces the frequency of DMA requests and improves the stability of data transmission.

[0086] Please refer to Figure 4 , Figure 4 A structural schematic diagram of a packet conversion module of a data transmission method provided in some embodiments of the present application.

[0087] An internal management module, connected to the memory area and the packet combination module, for configuring the continuous memory space;

[0088] The packet combination module is connected with the linked list modification module and the internal management module, and is used to write multiple consecutive small data packets into a consecutive memory space;

[0089] The linked list modification module is used to modify the descriptor items in the linked list.

[0090] It can be seen that this embodiment first determines whether the length of the data packet to be transmitted is less than the preset length. If it is less than the preset length, it means that the data packet is a small data packet. Then it further determines whether there are multiple logically continuous small data packets. If so, the multiple continuous small data packets are converted into a large data packet for transmission by the packet conversion module, instead of directly using the DMA method for transmission. When it is greater than the preset length, the data packet is directly transmitted through the DMA method, which improves the efficiency of data transmission and reduces the problems caused by multiple large DMA requests. The stability of transmission is improved.

[0091] The following is an introduction to the PCIE data transmission devices provided in some embodiments of the present application. The PCIE data transmission devices described below and the PCIE data transmission methods described above can be referenced to each other.

[0092] Please refer to Figure 5 , Figure 5 A structural schematic diagram of a data transmission device provided in some embodiments of the present application.

[0093] In this embodiment, the device may include:

[0094] A data packet detection module is used to determine whether the length of the data packet to be transmitted is less than a preset length, and to determine whether there are multiple consecutive small data packets;

[0095] A data packet merging module, used for merging the plurality of continuous small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets;

[0096] The DMA transmission module is used for transmitting and combining the data packets through DMA.

[0097] It can be seen that this embodiment first determines whether the length of the data packet to be transmitted is less than the preset length. If it is less than the preset length, it means that the data packet is a small data packet. Then it further determines whether there are multiple logically continuous small data packets. If so, the multiple continuous small data packets are converted into a large data packet for transmission by the packet conversion module, instead of directly using the DMA method for transmission. When it is greater than the preset length, the data packet is directly transmitted through the DMA method, which improves the efficiency of data transmission and reduces the problems caused by multiple large DMA requests. The stability of transmission is improved.

[0098] This application also provides an electronic device, please refer to Figure 6 , Figure 6 A schematic diagram of the structure of an electronic device provided in some embodiments of the present application, the electronic device may include:

[0099] Memory for storing computer programs;

[0100] A processor, which is used to implement the steps of any one of the above-mentioned data transmission methods when executing a computer program.

[0101] like Figure 6 , which is a schematic diagram of the composition structure of an electronic device, the electronic device may include: a processor 10, a memory 11, a communication interface 12 and a communication bus 13. The processor 10, the memory 11 and the communication interface 12 all communicate with each other through the communication bus 13.

[0102] In some embodiments of the present application, the processor 10 may be a central processing unit (CPU), an application specific integrated circuit, a digital signal processor, a field programmable gate array, or other programmable logic devices.

[0103] The processor 10 may call a program stored in the memory 11. Specifically, the processor 10 may execute operations in an embodiment of the abnormal IP identification method.

[0104] The memory 11 is used to store one or more programs, which may include program codes, and the program codes include computer operation instructions. In some embodiments of the present application, the memory 11 at least stores programs for implementing the following functions:

[0105] Determining whether the length of the data packet to be transmitted is less than a preset length;

[0106] If yes, further determine whether there are multiple logically continuous small data packets, and if yes, merge the multiple logically continuous small data packets into one or more large data packets through the packet conversion module, and transmit the data through DMA mode;

[0107] If not, the data packet is transmitted via DMA.

[0108] In a possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function, etc.; the data storage area may store data created during use.

[0109] In addition, the memory 11 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.

[0110] The communication interface 12 may be an interface of a communication module, and is used to connect to other devices or systems.

[0111] Of course, it should be noted that Figure 6The structure shown does not constitute a limitation on the electronic device in some embodiments of the present application. In actual applications, the electronic device may include Figure 6 More or fewer components than shown, or combinations of certain components.

[0112] This application also provides a computer-readable storage medium, please refer to Figure 7 , Figure 7 A schematic diagram of the structure of a computer-readable storage medium provided in some embodiments of the present application.

[0113] The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any one of the above-mentioned data transmission methods can be implemented.

[0114] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0115] For an introduction to the computer-readable storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.

[0116] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0117] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0118] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0119] The above is a detailed introduction to a data transmission method, device, electronic device and computer-readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A chained DMA data transmission method, characterized in that: include: Determine whether the length of the data packet to be transmitted is less than a preset first length, if it is less than the preset length, it indicates that the data packet is a small data packet; If not, data transmission of the data packet is performed through DMA; If yes, then further determine whether there are multiple consecutive small data packets: If not, data transmission of the data packet is performed through DMA; If so, multiple consecutive small data packets will be merged into a large data packet in sequence until the large data packet exceeds the preset second length, and then the remaining small data packets will be merged into the next large data packet until the multiple consecutive small data packets are all merged, and the descriptors of the corresponding data packets will be modified, and the merged one or more large data packets will be transmitted via DMA.

2. The chained DMA data transmission method according to claim 1, characterized in that: The step of merging the multiple continuous small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets, and transmitting the merged one or more large data packets through DMA also includes: after merging a large data packet, transmitting the merged data packet through DMA, and then merging the next large data packet.

3. The chained DMA data transmission method according to claim 2, characterized in that: The step of merging the multiple consecutive small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets also includes: deleting the DMA descriptors of the multiple consecutive small data packets in the DMA linked list, and inserting the DMA descriptors of the merged one or more large data packets.

4. The chained DMA data transmission method according to claim 3, characterized in that: The step of merging the multiple continuous small data packets into one or more large data packets and modifying the descriptors of the corresponding data packets also includes: migrating the multiple continuous small data packets to a physically continuous memory area in sequence, and synchronously deleting the DMA descriptors of the migrated small data packets in the DMA linked list.

5. A chained DMA data transmission device, characterized in that: include: A data packet detection module, used to determine whether the length of the data packet to be transmitted is less than a preset first length, if less than the preset length, it means that the data packet is a small data packet, and to determine whether there are multiple consecutive small data packets; A data packet merging module, used to sequentially merge a plurality of continuous small data packets into a large data packet until the large data packet exceeds a preset second length, and then start merging the remaining small data packets into the next large data packet until the plurality of continuous small data packets are all merged, and modify the descriptors of the corresponding data packets; The DMA transmission module is used for transmitting and combining the data packets through DMA.

6. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the chained DMA data transmission method as claimed in any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chained DMA data transmission method according to any one of claims 1 to 4 are implemented.

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