Charge pump circuit and electronic device

Abstract

This disclosure provides a charge pump circuit and an electronic device. The charge pump circuit includes: a first charge pump branch, a second charge pump branch, and a charge transfer control branch; the first charge pump branch includes a first sub-branch and a second sub-branch electrically connected; the second charge pump branch includes a third sub-branch and a fourth sub-branch electrically connected; the first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch is electrically connected to the third sub-branch; the charge transfer control branch is electrically connected to the first sub-branch and the third sub-branch respectively, and is used to transfer a portion of the charge stored in the parasitic capacitance of a second target switch to the parasitic capacitance of a first target switch during a dead time. In this embodiment, when the first target switch switches to the off state, it does not need to be recharged because the parasitic capacitance stores charge, thus reducing switching losses.

Description

Technical Field

[0001] This disclosure relates to the field of control technology, and more particularly to a charge pump circuit and electronic device. Background Technology

[0002] As electronic devices carry increasingly more electrical loads, their battery capacities are also increasing. Therefore, related technologies incorporate charge pump circuits within these electronic devices to charge the batteries.

[0003] For example, in the first stage, the charge pump circuit controls multiple capacitors connected in series, using high voltage and low current to charge the capacitors; in the second stage, the charge pump circuit controls multiple capacitors connected in parallel, using low voltage and high current to charge the battery, achieving a fast charging effect. Based on the above analysis of the working process, during the charging process, the charge pump circuit needs to frequently turn on and off the switching devices, thereby increasing switching losses. Summary of the Invention

[0004] This disclosure provides a charge pump circuit and electronic device to solve the above-mentioned technical problems.

[0005] According to a first aspect of the present disclosure, a charge pump circuit is provided, comprising: a first charge pump branch, a second charge pump branch, and a charge transfer control branch; the first charge pump branch includes a first sub-branch and a second sub-branch that are electrically connected; the second charge pump branch includes a third sub-branch and a fourth sub-branch that are electrically connected; the first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch is electrically connected to the third sub-branch.

[0006] The charge transfer control branch is electrically connected to the first sub-branch and the third sub-branch respectively, and is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead zone period.

[0007] The dead zone period refers to the period during which the switching devices in both the first charge pump branch and the second charge pump branch are in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0008] Optionally, the first sub-branch includes a first switching device, a fourth switching device, and a sixth switching device; the charge transfer control branch includes an inductor;

[0009] The first terminal of the first switching device is electrically connected to the input terminal of the charge pump circuit, and the second terminal of the first switching device is electrically connected to the first terminal of the four switching devices; the second terminal of the fourth switching device is electrically connected to the first terminal of the sixth switching device, and the second terminal of the sixth switching device is electrically connected to the fourth sub-branch.

[0010] The third sub-branch includes a second switching device, a third switching device, and a fifth switching device; the first terminal of the second switching device is electrically connected to the input terminal of the charge pump circuit, the second terminal of the second switching device is electrically connected to the first terminal of the third switching device; the second terminal of the third switching device is electrically connected to the first terminal of the fifth switching device, and the second terminal of the fifth switching device is electrically connected to the second sub-branch.

[0011] During the dead time, in one of the first and second sub-phases, the first terminal of the inductor is electrically connected to the second terminal of the first switching device, and the second terminal of the inductor is grounded; during the other sub-phase of the dead time, the first terminal of the inductor is grounded, and the second terminal of the inductor is electrically connected to the second terminal of the second switching device.

[0012] Optionally, the charge transfer control branch includes a first transfer control switch and a second transfer control switch; a first terminal of the first transfer control switch is electrically connected to a second terminal of the first switching device, and a second terminal of the first transfer control switch is electrically connected to a first terminal of the inductor; a second terminal of the inductor is electrically connected to a first terminal of the second transfer control switch, and a second terminal of the second transfer control switch is grounded; the control terminals of the first transfer control switch and the second transfer control switch are used to receive control signals.

[0013] The first transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the first end of the inductor to the second end of the first switching device;

[0014] The second transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the second terminal of the inductor.

[0015] Optionally, the charge transfer control branch further includes a third transfer control switch and a fourth transfer control switch; the first terminal of the third transfer control switch is electrically connected to the second terminal of the inductor, and the second terminal of the third transfer control switch is electrically connected to the second terminal of the second switching device; the first terminal of the fourth transfer control switch is electrically connected to the first terminal of the inductor, and the second terminal of the fourth transfer control switch is grounded;

[0016] The third transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the second terminal of the inductor to the second terminal of the second switching device;

[0017] The fourth transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the first terminal of the inductor.

[0018] Optionally, the charge transfer control branch further includes a first diode and a second diode; the cathode of the first diode is electrically connected to a first end of the inductor, and the anode of the first diode is grounded; the anode of the second diode is electrically connected to the second charge pump branch, and the cathode of the second diode is electrically connected to a second end of the inductor.

[0019] Optionally, the charge transfer control branch includes a fifth transfer control switch and a sixth transfer control switch; the first terminal of the fifth transfer control switch is electrically connected to the first terminal of the inductor, and the second terminal of the fifth transfer control switch is grounded; the first terminal of the sixth transfer control switch is electrically connected to the second terminal of the inductor, and the second terminal of the sixth transfer control switch is electrically connected to the second terminal of the second switching device.

[0020] The fifth transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the first terminal of the inductor;

[0021] The sixth transfer control switch is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the second terminal of the inductor to the second terminal of the second switching device.

[0022] Optionally, the charge transfer control branch further includes a third diode and a fourth diode; the cathode of the third diode is electrically connected to the second terminal of the inductor, and the anode of the third diode is grounded; the anode of the fourth diode is electrically connected to the first switching device, and the cathode of the fourth diode is electrically connected to the first terminal of the inductor.

[0023] Optionally, at least one of the first transfer control switch, the second transfer control switch, the third transfer control switch, the fourth transfer control switch, the fifth transfer control switch, and the sixth transfer control switch is implemented using a field-effect transistor.

[0024] Optionally, the inductance value of the inductor is less than the target inductance value, which refers to the inductance value that matches the parasitic capacitance resonance of the switching device in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit.

[0025] Optionally, the first charge pump branch and the second charge pump branch constitute a symmetrical charge pump architecture.

[0026] Optionally, the symmetrical charge pump architecture includes at least one of the following: Dixon architecture, series-parallel charging architecture, and cross-charging architecture.

[0027] According to a second aspect of this disclosure, a chip is provided, including a charge pump circuit as described in any of the first aspects.

[0028] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor, a battery, a charging interface, and a charge pump circuit as described in any of the first aspects; the charge pump circuit is electrically connected to the battery and the charging interface respectively; the processor is electrically connected to the charge pump circuit;

[0029] The processor is used to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the on state and the second target switch to the off state within a control cycle;

[0030] The processor is used to control all switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead period;

[0031] The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead time period;

[0032] The charge transfer control branch is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch when a valid control signal is received during the dead zone period.

[0033] And / or,

[0034] The processor, battery, charging interface, and chip as described in the second aspect; the chip is electrically connected to the battery, the charging interface, and the processor, respectively.

[0035] The processor is used to send effective control signals to the first charge pump branch and the second charge pump branch of the charge pump circuit in the chip in each control cycle to switch the second switching device and the first switching device.

[0036] The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead zone period after each control cycle, so as to enable the second switching device and the first switching device to transfer charge.

[0037] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0038] The charge pump circuit provided in this embodiment includes a first charge pump branch, a second charge pump branch, and a charge transfer control branch. The first charge pump branch includes a first sub-branch and a second sub-branch that are electrically connected. The second charge pump branch includes a third sub-branch and a fourth sub-branch that are electrically connected. The first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch is electrically connected to the third sub-branch. The charge transfer control branch is electrically connected to the first sub-branch and the third sub-branch, respectively, and is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time period. The dead time period refers to the period during which the switching devices in the first charge pump branch and the second charge pump branch are both in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle. In this way, by transferring a portion of the charge from the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch in this embodiment, the first target switch can be switched to the off state in the next control cycle without charging because the parasitic capacitance stores charge, thus reducing or eliminating switching losses.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0040] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0041] Figure 2 This is a block diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0042] Figure 3 This is a block diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0043] Figure 4 This is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.

[0044] Figure 5 This is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.

[0045] Figure 6 This is a circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0046] Figure 7 This is an equivalent circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0047] Figure 8 This is an equivalent circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0048] Figure 9 This is an equivalent circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0049] Figure 10 This is a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0051] To address the aforementioned technical problems, embodiments of this disclosure provide a charge pump circuit and an electronic device. Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this disclosure. See also... Figure 1 An electronic device 10 includes a processor 11, a battery 14, a charging interface 12, and a charge pump circuit 13. The charge pump circuit 13 is electrically connected to both the battery 14 and the charging interface 12; the processor 11 is electrically connected to the charge pump circuit 13.

[0052] In one example, the charging interface 12 may include, but is not limited to, a USB Type-C interface, a MicroUSB interface, etc. If it can support charging by the charge pump circuit 13, the corresponding charging interface falls within the protection scope of this disclosure.

[0053] See one example. Figure 2 The charge pump circuit 13 includes a first charge pump branch 21, a second charge pump branch 22, and a charge transfer control branch 23.

[0054] In this example, the first charge pump branch 21 and the second charge pump branch 22 constitute a symmetrical charge pump architecture. The symmetrical charge pump architecture includes at least one of the following: a Dixon architecture, a series-parallel charging architecture, and a cross-charging architecture. For ease of description, in this example, the symmetrical structure is implemented using a cross-charging architecture to facilitate the description of the schemes in subsequent embodiments, but this does not constitute a limitation.

[0055] Understandably, the aforementioned symmetrical charge pump structure can switch between two charge pump branches. The connection point voltage between the two switching devices in the first charge pump branch 21 may be the same as the connection point voltage between the two switching devices in the second charge pump branch 22, thus finding at least one pair of connection points with the same voltage value. When there is a pair of connection points with the same voltage value, the charge transfer control branch 23 is connected to the aforementioned connection point pair; when there are multiple pairs of connection points with the same voltage value, the charge transfer control branch 23 is connected to the connection point pair with the largest voltage value. Understandably, with a constant current, the larger the voltage value, the greater the loss of the switching devices. Therefore, in this example, by connecting the charge transfer control branch 23, the power consumption of the charge pump circuit can be reduced.

[0056] In one example, the first charge pump branch 21 includes an electrically connected first sub-branch 211 and a second sub-branch 212; the second charge pump branch 22 includes an electrically connected third sub-branch 221 and a fourth sub-branch 222; the first sub-branch 211 and the fourth sub-branch 222 are electrically connected, and the second sub-branch 212 is electrically connected to the third sub-branch 221, so that the first charge pump branch 21 and the second charge pump branch 22 constitute a cross-charging architecture; the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture with respect to the first line where the power supply BAT is located.

[0057] The charge transfer control branch 23 is electrically connected to the first sub-branch 211 and the third sub-branch 221 respectively, and is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead zone period.

[0058] It should be noted that the dead zone period refers to the period during which the switching devices in the first charge pump branch 21 and the second charge pump branch 22 are both in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0059] See also Figure 2 The first sub-branch 211 includes a first switching device Q1, a fourth switching device Q4, and a sixth switching device Q6. The first terminal of the first switching device Q1 is electrically connected to the input terminal of the charge pump circuit (which is connected to the power supply BAT), and the second terminal of the first switching device Q1 is electrically connected to the first terminal of the fourth switching device Q4; the second terminal of the fourth switching device Q4 is electrically connected to the first terminal of the sixth switching device Q6, and the second terminal of the sixth switching device Q6 is electrically connected to the fourth sub-branch 222.

[0060] See also Figure 2The second sub-branch 212 includes a first capacitor C1, a third capacitor C3, a seventh switch Q7, an eighth switch Q8, an eleventh switch Q11, a twelfth switch Q12, and a sixteenth switch Q16. The first terminal of the seventh switch Q7 is electrically connected to the third capacitor C3, the twelfth switch Q12, and the third sub-branch 221. The second terminal of the seventh switch Q7 is electrically connected to the second terminal of the first capacitor C1 and the first terminal of the eighth switch Q8. The first terminal of the first capacitor C1 is electrically connected to the second terminal of the first switch Q1 in the first sub-branch 211. The second terminal of the eighth switch Q8 is grounded. The second terminal of the third capacitor C3 is electrically connected to the second terminal of the eleventh switch Q11 and the first terminal of the sixteenth switch Q16. The second terminal of the sixteenth switch Q16 is grounded. The second terminal of the twelfth switch Q12 is electrically connected to the output terminal (VOUTA or VOUTB) of the charge pump circuit and the first terminal of the eleventh switch Q11.

[0061] See also Figure 2 The third sub-branch 221 includes a second switching device Q2, a third switching device Q3, and a fifth switching device Q5; the first terminal of the second switching device Q2 is electrically connected to the input terminal of the charge pump circuit, the second terminal of the second switching device Q2 is electrically connected to the first terminal of the third switching device Q3; the second terminal of the third switching device Q3 is electrically connected to the first terminal of the fifth switching device Q5, and the second terminal of the fifth switching device Q5 is electrically connected to the second sub-branch 212.

[0062] See also Figure 2 The fourth sub-branch 222 includes a second capacitor C2, a fourth capacitor C4, a ninth switch Q9, a tenth switch Q10, a thirteenth switch Q13, a fourteenth switch Q14, and a fifteenth switch Q15. Specifically, the first terminal of the tenth switch Q10 is electrically connected to the first terminal of the fourth capacitor C4, the first terminal of the thirteenth switch Q13, and the second terminal of the sixth switch Q6 in the first sub-branch; the second terminal of the tenth switch Q10 is electrically connected to the first terminal of the ninth switch Q9 and the second terminal of the second capacitor C2; the first terminal of the second capacitor C2 is electrically connected to the second terminal of the second switch Q2; and the second terminal of the ninth switch Q9 is grounded. The second terminal of the thirteenth switch Q13 is electrically connected to the output terminal VOUTB of the charge pump circuit and the first terminal of the fourteenth switch Q14. The second terminal of the fourteenth switch Q14 is electrically connected to the second terminal of the fourth capacitor C4 and the first terminal of the fifteenth switch Q15. The second terminal of the fifteenth switch Q15 is grounded.

[0063] See also Figure 2The charge transfer control branch 23 includes an inductor L1. During the first sub-stage and the second sub-stage of the dead time, the first end of the inductor L1 is electrically connected to the second end of the first switching device Q1, and the second end of the inductor L1 is grounded; during the other sub-stage of the dead time, the first end of the inductor L1 is grounded, and the second end of the inductor L1 is electrically connected to the second end of the second switching device Q2.

[0064] It should also be noted that the inductance value of inductor L1 is less than the target inductance value. The target inductance value refers to the inductance value that resonates with the parasitic capacitance of the switching devices in the first and / or second charge pump branches at the switching frequency of the two charge pump branches in the charge pump circuit. Thus, a smaller inductance value for L1 avoids resonance and prevents prolonged dead time, or in other words, it completes charge transfer without affecting the duration of the dead time in the two charge pump branches, ensuring the normal operation of the charge pump circuit.

[0065] In one embodiment, see Figure 3 The charge pump circuit also includes a fifth capacitor C5. The first terminal of the fifth capacitor C5 is electrically connected to the second terminal of the fourth switching device Q4 and the second terminal of the third switching device Q3, respectively, and the second terminal of the fifth capacitor C5 is grounded. In this case, the first terminal of the fifth capacitor C5 can serve as the second output terminal, and its output voltage is twice the output voltage of the first output terminal VOUT.

[0066] In one embodiment, see further. Figure 3 The charge pump circuit also includes a sixth capacitor C6, a seventeenth switching device Q17, and an eighteenth switching device Q18. The first terminal of the seventeenth switching device Q17 is connected to the second terminal of the eleventh switching device Q11, and the second terminal of the seventeenth switching device Q17 is electrically connected to the first terminals of both the sixth capacitor C6 and the eighteenth switching device Q18. The second terminal of the eighteenth switching device Q18 is electrically connected to the first terminal of the fifteenth switching device Q15. The second terminal of the sixth capacitor C6 is grounded. Thus, the first terminal of the sixth capacitor C6 can be used as a third output terminal, outputting the same voltage as the first output terminal VOUT.

[0067] In one embodiment, see Figure 4The charge transfer control branch 23 includes a first transfer control switch Q20 and a second transfer control switch Q21. The first terminal of the first transfer control switch Q20 is electrically connected to the second terminal of the first switching device Q1, and the second terminal of the first transfer control switch Q20 is electrically connected to the first terminal of the inductor L1. The second terminal of the inductor L1 is electrically connected to the first terminal of the second transfer control switch Q21, and the second terminal of the second transfer control switch Q21 is grounded. The control terminals of the first transfer control switch Q20 and the second transfer control switch Q21 are used to receive control signals. The first transfer control switch Q20 is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the first terminal of the inductor L1 to the second terminal of the first switching device Q1. The second transfer control switch Q21 is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the second terminal of the inductor L1.

[0068] In one embodiment, see further. Figure 4 The charge transfer control branch 23 also includes a third transfer control switch Q22 and a fourth transfer control switch Q23; the first terminal of the third transfer control switch Q22 is electrically connected to the second terminal of the inductor L1, and the second terminal of the third transfer control switch Q22 is electrically connected to the second terminal of the second switching device Q2; the first terminal of the fourth transfer control switch Q23 is electrically connected to the first terminal of the inductor L1, and the second terminal of the fourth transfer control switch Q23 is grounded; the third transfer control switch Q22 is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the second terminal of the inductor L1 to the second terminal of the second switching device Q2; the fourth transfer control switch Q23 is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the first terminal of the inductor L1.

[0069] In one embodiment, see Figure 5 The charge transfer control branch 23 includes a first transfer control switch Q20 and a second transfer control switch Q21, as well as a first diode D1 and a second diode D2. The cathode of the first diode D1 is electrically connected to the first end of the inductor L1, and the anode of the first diode D1 is grounded. The anode of the second diode D2 is electrically connected to the second charge pump branch (specifically, the second end of the second switching device Q2), and the cathode of the second diode D2 is electrically connected to the second end of the inductor L1.

[0070] In one embodiment, see Figure 6The charge transfer control branch 23 includes a fifth transfer control switch Q24 and a sixth transfer control switch Q25; the first terminal of the fifth transfer control switch Q24 is electrically connected to the first terminal of the inductor L1, and the second terminal of the fifth transfer control switch Q24 is grounded; the first terminal of the sixth transfer control switch Q25 is electrically connected to the second terminal of the inductor L1, and the second terminal of the sixth transfer control switch Q25 is electrically connected to the second terminal of the second switching device Q2; the fifth transfer control switch Q24 is used to switch to the on state when a valid control signal is received during the dead time period, so as to ground the first terminal of the inductor L1; the sixth transfer control switch Q25 is used to switch to the on state when a valid control signal is received during the dead time period, so as to electrically connect the second terminal of the inductor L1 to the second terminal of the second switching device Q2.

[0071] In one embodiment, see further. Figure 6 The charge transfer control branch 23 includes a fifth transfer control switch Q24 and a sixth transfer control switch Q25, as well as a third diode D3 and a fourth diode D4. The cathode of the third diode D3 is electrically connected to the second terminal of the inductor L1, and the anode of the third diode D3 is grounded. The anode of the fourth diode D4 is electrically connected to the first switching device Q1, and the cathode of the fourth diode D4 is electrically connected to the first terminal of the inductor L1.

[0072] It should be noted that at least one of the first transfer control switch, the second transfer control switch, the third transfer control switch, the fourth transfer control switch, the fifth transfer control switch, and the sixth transfer control switch is implemented using a field-effect transistor. This allows them to be integrated with the switching devices in each sub-branch of the charge pump circuit onto the same chip or circuit board, and they can also be manufactured using the same process, which helps to reduce the size and cost of the charge pump circuit.

[0073] In this embodiment, combined with Figure 5 The charge pump circuit shown describes the charging and charge transfer processes. It is understood that when the charging interface 12 of the electronic device is electrically connected to an external charging device (i.e., a power supply BAT), the processor 11 can control either the first charge pump branch 21 or the second charge pump branch 22 of the charge pump circuit 13 to charge the battery 14. Figure 2 In this context, capacitor C0 represents battery 14.

[0074] Taking the processor-controlled first charge pump branch 21 as an example, the charging process includes:

[0075] In the first charging stage: Processor 11 controls the first switch Q1, the third switch Q3, the fifth switch Q5, the seventh switch Q7, the ninth switch Q9, the eleventh switch Q11, the thirteenth switch Q13, the fifteenth switch Q15, and the seventeenth switch Q17 to the on state, respectively, and controls the second switch Q2, the fourth switch Q4, the sixth switch Q6, the eighth switch Q8, the tenth switch Q10, the twelfth switch Q12, the fourteenth switch Q14, the sixteenth switch Q16, and the eighteenth switch Q18 to the off state. Furthermore, the first transfer control switch Q20 and the second transfer control switch Q21 are switched to the off state. The equivalent circuit is as follows: Figure 7 As shown.

[0076] The first target switch includes a first switch device Q1, a third switch device Q3, a fifth switch device Q5, a seventh switch device Q7, and a ninth switch device Q9; the second target switch includes a second switch device Q2, a fourth switch device Q4, a sixth switch device Q6, an eighth switch device Q8, and a tenth switch device Q10.

[0077] It should be noted that, Figure 7 The example only illustrates the parasitic capacitances of switching devices Q1 to Q10 involved in charge transfer; the parasitic capacitances of other switching devices are not shown. Assuming a power supply voltage of 20V, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are all equal.

[0078] See Figure 7 The current path includes:

[0079] Path 1

[0080] GND->Q9->C2->Q3->VO1->C5->GND;

[0081] Path 2

[0082] BAT->Q1->C1->Q7->Q5->C5->GND;

[0083] Path 3

[0084] BAT->Q1->C1->Q7->C3->Q11->VOUT;

[0085] Path 4

[0086] BAT->Q1->C1->Q7->C3->Q17->VO2->C6->GND.

[0087] During the battery charging process, the second switch device Q2, the fourth switch device Q4, the sixth switch device Q6, the eighth switch device Q8, and the tenth switch device Q10 are charged, and the voltages after charging are 10V, 10V, 10V, 5V, and 5V respectively.

[0088] Dead Zone

[0089] In one example, the dead time includes a first sub-stage and a second sub-stage, with the first sub-stage preceding the second sub-stage. Specifically, inductor L1 is charged during the first sub-stage, and inductor L2 is discharged during the second sub-stage.

[0090] First sub-stage: The processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to turn on. See below. Figure 8 At this time, the parasitic capacitances of the fourth switch device Q4, the sixth switch device Q6, and the eighth switch device Q8 discharge, and their voltages become 0V; inductor L1 charges, and its voltage rises to 10V. Correspondingly, the parasitic capacitances of the first switch device Q1 and the seventh switch device Q7 charge, and their voltages rise to 10V and 5V, respectively.

[0091] Second sub-stage: The processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the off state, while other switching devices remain unchanged from the state of the first sub-stage. The equivalent circuit is as follows: Figure 9 As shown. See also Figure 9 At this time, the parasitic capacitances of inductor L1, second switch Q2 and tenth switch Q10 discharge, and the voltage becomes 0V; the parasitic capacitances of third switch Q3, fifth switch Q5 and ninth switch Q9 charge, and the voltage rises to 10V, 10V and 5V respectively.

[0092] In the second charging stage: the processor 11 controls the first switch Q1, the third switch Q3, the fifth switch Q5, the seventh switch Q7, the ninth switch Q9, the eleventh switch Q11, the thirteenth switch Q13, the fifteenth switch Q15, and the seventeenth switch Q17 to the off state, and controls the second switch Q2, the fourth switch Q4, the sixth switch Q6, the eighth switch Q8, the tenth switch Q10, the twelfth switch Q12, the fourteenth switch Q14, the sixteenth switch Q16, and the eighteenth switch Q18 to the on state, and the first transfer control switch Q20 and the second transfer control switch Q21 to the off state. The equivalent circuit is as follows: Figure 7 As shown. See also Figure 7 At this time, the darker colored switching device is turned on while the darker colored switching device is turned off.

[0093] It should be noted that the first charge pump branch 21 and the second charge pump branch 22 are symmetrical structures. Therefore, the parasitic capacitance charging and discharging of the switching devices at symmetrical positions are the same as in the previous charging stage. The difference is that, considering that the charge transfer control branch includes the first diode and the second diode, no charge transfer occurs during the control cycle of the second charging stage.

[0094] Thus, in this embodiment, by transferring part of the charge of the parasitic capacitance of the first switching device to the second switching device, the second switching device can be used as the first switching device in the next control cycle without needing to be recharged due to the charge stored in the parasitic capacitance, thereby reducing or eliminating switching losses.

[0095] In some possible embodiments, a chip is also provided, comprising the above-described... Figures 1-9 The example charge pump circuit.

[0096] Figure 10 This is a block diagram illustrating an electronic device according to an exemplary embodiment. For example, the electronic device 1000 may be a smartphone, computer, digital broadcasting terminal, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0097] Reference Figure 10 The electronic device 1000 may include one or more of the following components: processing component 1002, memory 1004, power supply component 1006, multimedia component 1008, audio component 1010, input / output (I / O) interface 1012, sensor component 1014, communication component 1016, and image acquisition component 1018.

[0098] Processing component 1002 typically controls the overall operation of electronic device 1000, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1002 may include one or more processors 1020 to execute computer programs. Furthermore, processing component 1002 may include one or more modules to facilitate interaction between processing component 1002 and other components. For example, processing component 1002 may include a multimedia module to facilitate interaction between multimedia component 1008 and processing component 1002. In one example, processor 1020 may control a charge pump circuit to charge a battery.

[0099] Memory 1004 is configured to store various types of data to support the operation of electronic device 1000. Examples of such data include computer programs for any application or method operating on electronic device 1000, contact data, phone book data, messages, pictures, videos, etc. Memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0100] Power supply component 1006 provides power to various components of electronic device 1000. Power supply component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1000. Power supply component 1006 may include a power chip, which a controller can communicate with to control the power chip to turn a first switching device on or off, thereby enabling or de-energizing the battery to supply power to the motherboard circuitry. In one example, the power supply component 1006 includes a charge pump circuit and / or chip as described above.

[0101] The multimedia component 1008 includes a screen that provides an output interface between the electronic device 1000 and the target object.

[0102] In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input information from a target object. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation.

[0103] Audio component 1010 is configured to output and / or input audio file information. For example, audio component 1010 includes a microphone (MIC) configured to receive external audio file information when electronic device 1000 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio file information may be further stored in memory 1004 or transmitted via communication component 1016. In some embodiments, audio component 1010 also includes a speaker for outputting audio file information.

[0104] I / O interface 1012 provides an interface between processing component 1002 and peripheral interface modules, such as keyboards, click wheels, buttons, etc.

[0105] Sensor assembly 1014 includes one or more sensors for providing state assessments of various aspects of electronic device 1000. For example, sensor assembly 1014 can detect the on / off state of electronic device 1000, the relative positioning of components (e.g., the display screen and keypad of electronic device 1000), changes in position of electronic device 1000 or a component, the presence or absence of contact between a target object and electronic device 1000, the orientation or acceleration / deceleration of electronic device 1000, and temperature changes of electronic device 1000. In this example, sensor assembly 1014 may include magnetic sensors, gyroscopes, and magnetic field sensors, and may also include inertial sensors, image sensors, etc., wherein the magnetic field sensor includes at least one of the following: a Hall sensor, a thin-film magnetoresistive sensor, and a magnetic fluid accelerometer.

[0106] Communication component 1016 is configured to facilitate wired or wireless communication between electronic device 1000 and other devices. Electronic device 1000 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 1016 receives broadcast information or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1016 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0107] In an exemplary embodiment, the electronic device 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital information processors (DSPs), digital information processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0108] In an exemplary embodiment, this disclosure also provides a non-transitory computer-readable storage medium that, when an executable computer program in the storage medium is executed by a processor, enables the implementation of the method described above.

[0109] In an exemplary embodiment, a chip is also provided, the chip including a processor and an interface for reading a computer program through the interface to implement the method described above. The chip can be a conventional CPU (central processing unit) chip, GPU (graphics processing unit) chip, etc., or it can be an acceleration chip specifically designed for artificial intelligence technology, such as an AI (Artificial Intelligence) accelerator.

[0110] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0111] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A charge pump circuit, characterized by, The application relates to a charge pump circuit, comprising: a first charge pump branch, a second charge pump branch and a charge transfer control branch; the first charge pump branch comprises a first sub-branch and a second sub-branch which are electrically connected; the second charge pump branch comprises a third sub-branch and a fourth sub-branch which are electrically connected; the first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch and the third sub-branch are electrically connected; the switch devices in the first charge pump branch and the second charge pump branch are both in an off state during a dead time period; the first sub-branch comprises a first switch device Q1; the third sub-branch comprises a second switch device Q2; the charge transfer control branch is electrically connected with the first switch device Q1 and the second switch device Q2 respectively, and the first switch device Q1 and the second switch device Q2 are connected with a power supply respectively; the switch device in the charge transfer control branch is in an off state during a previous control period when the first charge pump branch and the second charge pump branch work; there are multiple pairs of connection points with the same voltage value in the first sub-branch and the third sub-branch; the charge transfer control branch is electrically connected with the first sub-branch and the third sub-branch respectively, and is connected with a pair of connection points with the maximum voltage value; the charge transfer control branch is used for transferring a part of the stored charge of the parasitic capacitor of a second target switch into the parasitic capacitor of a first target switch during the dead time period; the dead time period refers to a period during which the switch devices in the first charge pump branch and the second charge pump branch are both in an off state, the first target switch refers to a switch device in an on state during a previous control period, and the second target switch refers to a switch device in an off state during the previous control period; the first sub-branch further comprises a fourth switch device and a sixth switch device; the charge transfer control branch comprises an inductor; a first end of the first switch device is electrically connected with an input end of the charge pump circuit, and a second end of the first switch device is electrically connected with a first end of the fourth switch device; a second end of the fourth switch device is electrically connected with a first end of the sixth switch device, and a second end of the sixth switch device is electrically connected with the fourth sub-branch; the third sub-branch further comprises a third switch device and a fifth switch device; a first end of the second switch device is electrically connected with the input end of the charge pump circuit, and a second end of the second switch device is electrically connected with a first end of the third switch device; a second end of the third switch device is electrically connected with a first end of the fifth switch device, and a second end of the fifth switch device is electrically connected with the second sub-branch; during one of a first sub-stage and a second sub-stage of the dead time period, a first end of the inductor is electrically connected with a second end of the first switch device, and a second end of the inductor is grounded; during the other of the first sub-stage and the second sub-stage of the dead time period, the first end of the inductor is grounded, and the second end of the inductor is electrically connected with a second end of the second switch device. ​ 2. The charge pump circuit of claim 1, wherein, The charge transfer control branch comprises a first transfer control switch and a second transfer control switch; a first end of the first transfer control switch is electrically connected with a second end of the first switch device, and a second end of the first transfer control switch is electrically connected with a first end of the inductor; a second end of the inductor is electrically connected with a first end of the second transfer control switch, and a second end of the second transfer control switch is grounded; control ends of the first transfer control switch and the second transfer control switch are used for receiving a control signal; The first transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to electrically connect the first end of the inductor with the second end of the first switch device; The second transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to ground the second end of the inductor.

3. The charge pump circuit of claim 2, wherein, The charge transfer control branch further comprises a third transfer control switch and a fourth transfer control switch; a first end of the third transfer control switch is electrically connected with the second end of the inductor, and a second end of the third transfer control switch is electrically connected with a second end of the second switch device; a first end of the fourth transfer control switch is electrically connected with the first end of the inductor, and a second end of the fourth transfer control switch is grounded; The third transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to electrically connect the second end of the inductor with the second end of the second switch device; The fourth transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to ground the first end of the inductor.

4. The charge pump circuit of claim 2, wherein, The charge transfer control branch further comprises a first diode and a second diode; a cathode of the first diode is electrically connected with the first end of the inductor, and an anode of the first diode is grounded; an anode of the second diode is electrically connected with the second charge pump branch, and a cathode of the second diode is electrically connected with the second end of the inductor.

5. The charge pump circuit of claim 1, wherein, The charge transfer control branch comprises a fifth transfer control switch and a sixth transfer control switch; a first end of the fifth transfer control switch is electrically connected with the first end of the inductor, and a second end of the fifth transfer control switch is grounded; a first end of the sixth transfer control switch is electrically connected with the second end of the inductor, and a second end of the sixth transfer control switch is electrically connected with the second end of the second switch device; The fifth transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to ground the first end of the inductor; The sixth transfer control switch is used for switching to a conducting state when a valid control signal is received in the dead time period, so as to electrically connect the second end of the inductor with the second end of the second switch device.

6. The charge pump circuit of claim 5, wherein, The charge transfer control branch further comprises a third diode and a fourth diode; a cathode of the third diode is electrically connected with the second end of the inductor, and an anode of the third diode is grounded; an anode of the fourth diode is electrically connected with the first switch device, and a cathode of the fourth diode is electrically connected with the first end of the inductor.

7. The charge pump circuit of claim 4 or 5, wherein, At least one of the first transfer control switch, the second transfer control switch, the third transfer control switch, the fourth transfer control switch, the fifth transfer control switch and the sixth transfer control switch is implemented by a field effect transistor.

8. The charge pump circuit of claim 1, wherein, The inductance value of the inductor is less than a target inductance value, which is matched with the parasitic capacitance of the switch device in the first charge pump branch and / or the second charge pump branch when resonating at a switching frequency of two charge pump branches in the charge pump circuit.

9. The charge pump circuit of claim 1, wherein, The first charge pump branch and the second charge pump branch constitute a symmetrical charge pump architecture.

10. The charge pump circuit of claim 9, wherein, The symmetrical charge pump architecture comprises at least one of a Dickson architecture, a series-parallel charging architecture and a cross charging architecture.

11. A chip, characterized by The chip comprises the charge pump circuit according to any one of claims 1-10.

12. An electronic device, comprising: The chip comprises: a processor, a battery, a charging interface and the charge pump circuit according to any one of claims 1-10; the charge pump circuit is electrically connected with the battery and the charging interface respectively; the processor is electrically connected with the charge pump circuit; the processor is configured to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the conducting state and the second target switch to switch to the non-conducting state in a control period; the processor is configured to control all switch devices of the first charge pump branch and the second charge pump branch to switch to the non-conducting state in a dead time period; the processor is further configured to output an effective control signal to the charge transfer control branch of the charge pump circuit in a dead time period; the charge transfer control branch is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control period to the parasitic capacitance of the first target switch when the effective control signal is received in the dead time period.

13. An electronic device, comprising: The chip comprises: a processor, a battery, a charging interface and the chip according to claim 11; the chip is electrically connected with the battery, the charging interface and the processor respectively; the processor is configured to send an effective control signal to the first charge pump branch and the second charge pump branch of the charge pump circuit in the chip to switch the second switch device and the first switch device in each control period; the processor is further configured to output an effective control signal to the charge transfer control branch of the charge pump circuit in a dead time period after each control period to realize the transfer of the charge of the second switch device and the first switch device.

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