Image sensor with improved negative pump voltage stabilization and circuit system thereof

Abstract

The present application relates to an image sensor with improved negative pump voltage stabilization and a circuit system thereof. An image sensor with improved negative pump voltage stabilization and a circuit system thereof are disclosed herein. In one embodiment, a power supply stabilization circuit includes a negative charge pump and a reference voltage generator. The output of the negative charge pump is selectively coupled to a first node of the negative pump stabilization circuit via a first switch, and the output of the reference voltage generator is selectively coupled to a second node of the negative pump stabilization circuit via a second switch. The first node is further selectively coupled to ground via a third switch, and the second node is further selectively coupled to ground via a fourth switch. The first node may be additionally coupled to a first pad, and the second node may be additionally coupled to a second pad. The pads may each be coupled to a capacitor, such as an off-chip capacitor.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors. For example, several embodiments of the present technology relate to CMOS image sensors and circuit systems thereof with improved negative pump voltage stabilization. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like (e.g., resolution, power consumption, dynamic range, etc.) in as many ways as possible, both through device architecture design and image acquisition processing.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge when absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line, which varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted to a digital value to provide information representative of the external scene. Summary of the invention

[0004] One aspect of the present disclosure discloses a negative pump stabilization circuit, comprising: a negative charge pump; a first switch that selectively couples the output of the negative charge pump to a first node; a second switch that selectively couples the first node to ground; a third switch that selectively couples the second node to the output of a reference voltage generator; and a fourth switch that selectively couples the second node to ground, wherein the first node and the second node can be coupled to each other via a capacitor.

[0005] Another aspect of the present disclosure discloses a method for operating a negative pump stabilization circuit, the method comprising: while operating the negative pump stabilization circuit in the first state, precharging a first node of the negative pump stabilization circuit to a reference voltage to establish a voltage difference between the first node and a second node of the negative pump stabilization circuit that is different from the first node; and transitioning the negative pump stabilization circuit from the first state to a second state so that (a) a negative voltage boost occurs at the second node so that the voltage at the second node drops by an amount equal to the voltage difference, and (b) the voltage at the second node is stabilized at a voltage level, wherein at least while the negative pump stabilization circuit is transitioned from the first state to the second state, the second node is coupled to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the figures, wherein the same or similar reference characters are used throughout to refer to the same or similar components unless otherwise specified.

[0007] Figure 1 is a partial schematic block diagram of an image sensor configured in accordance with various embodiments of the present technology.

[0008] Figure 2 is a circuit diagram of a pixel cell configured in accordance with various embodiments of the present technology.

[0009] Figure 3 is a partial schematic block diagram of an imaging system configured in accordance with various embodiments of the present technology.

[0010] Figure 4 is a circuit diagram of a power supply stabilization circuit configured in accordance with various embodiments of the present technology.

[0011] Figure 5A According to various embodiments of the present technology Figure 4 A simplified circuit diagram of a power supply stabilization circuit in a state corresponding to a sleep mode of operation.

[0012] Figure 5B According to various embodiments of the present technology Figure 4 A simplified circuit diagram of a power supply stabilization circuit in a state corresponding to a normal operating mode of operation.

[0013] Figure 6 is corresponding to Figure 4 Power supply stabilization circuit and Figure 5A and 5B A timing diagram of the simplified circuit diagram.

[0014] Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding various aspects of the present technology. In addition, common but well-known elements or methods that are useful or necessary in commercially feasible embodiments are generally not depicted in the figures or described in detail below to avoid unnecessarily obscuring the description of various aspects of the present technology. DETAILED DESCRIPTION

[0015] The present disclosure relates generally to image sensors. For example, several embodiments of the present technology relate to CMOS image sensors and circuit systems thereof with improved negative pump voltage stabilization. In the following description, specific details are set forth to provide a comprehensive understanding of aspects of the present technology. However, those skilled in the relevant art will recognize that the systems, devices, and techniques described herein may be practiced without one or more of the specific details set forth herein or with other methods, components, materials, etc.

[0016] References throughout this specification to an "example" or an "embodiment" indicate that a particular feature, structure, or characteristic described in conjunction with the example or embodiment is included in at least one example or embodiment of the present technology. Thus, the use of the phrases "for example," "as an example," or "an embodiment" herein does not necessarily all refer to the same example or embodiment and is not necessarily limited to the specific example or embodiment discussed. Furthermore, the features, structures, or characteristics of the present technology described herein may be combined in any suitable manner to provide further examples or embodiments of the present technology.

[0017] For ease of description, spatially relative terms (e.g., "below," "beneath," "above," "below," "above," "up," "top," "bottom," "left," "right," "center," "middle," and the like) may be used herein to describe the relationship of one element or feature relative to one or more other elements or features, as shown in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device or system in use or operation in addition to the orientation depicted in the figures. For example, if the device or system shown in the figures is rotated, turned, or flipped about a horizontal axis, an element or feature described as "below one or more other elements or features," "below one or more other elements or features," or "under one or more other elements or features" may be oriented as "above one or more other elements or features." Therefore, the exemplary terms "below" and "under" are non-limiting and may cover both orientations of above and below. The devices or systems may additionally or alternatively be oriented otherwise than as shown in the figures (e.g., rotated 90 degrees about a vertical axis or at other orientations), and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present.

[0018] Throughout this specification, several technical terms are used. These terms have ordinary meanings in the art to which they belong, unless otherwise explicitly defined herein or the context of their use clearly indicates otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] A. Overview

[0020] Many CMOS image sensors enter a sleep mode or state to save power when the image sensor is not in use. When these CMOS image sensors subsequently wake up from the sleep mode to a normal operating mode or state, the voltage generated by the power supply of these image sensors requires time to stabilize to an appropriate voltage level. In one specific example, the power supply of the CMOS image sensor may include a negative charge pump, a capacitor, and a pad electrically positioned between the negative charge pump and the capacitor and coupled in series with the negative charge pump and the capacitor. The capacitor may be further coupled to a positive voltage (e.g., VPOS) or another voltage. When the CMOS image sensor is in the sleep mode, the negative pump voltage NVDD at the pad may be at a first value (e.g., 0V). As the CMOS image sensor transitions to the normal operating mode, the negative pump voltage NVDD at the pad may transition to a second value (e.g., -1.4V). However, the transition of the negative pump voltage NVDD from the first value to the second value is not instantaneous, meaning that there is an amount of time between when the CMOS image sensor wakes up from the sleep mode and when the negative pump voltage NVDD reaches or stabilizes at the second value. This amount of time is referred to herein as the 'NVDD stabilization time' and may be on the order of 2ms in some image sensors. Any image data frames captured during the period before the negative pump voltage NVDD stabilizes to the second value may not accurately represent the external scene being imaged. This may be particularly problematic when attempting to capture an image as quickly as possible after waking the image sensor from a sleep mode (e.g., in order to accurately capture an image corresponding to the moment when the first fireworks burst in the night sky).

[0021] To address these concerns, several embodiments of the present technology are directed to image sensors having power supply stabilization circuits for reducing or minimizing NVDD stabilization time. For example, several embodiments of the present technology are directed to negative pump stabilization circuits, each of which has a negative charge pump and a reference voltage generator. The output of the negative charge pump is selectively coupled to a first node of the negative pump stabilization circuit via a first switch, and the output of the reference voltage generator is selectively coupled to a second node of the negative pump stabilization circuit via a second switch. The first node is further selectively coupled to ground via a third switch, and the second node is further selectively coupled to ground via a fourth switch. The first node may be additionally coupled to a first pad (e.g., a negative pump voltage NVDD pad), and the second node may be additionally coupled to a second pad (e.g., a positive voltage VPOS pad). The pads may each be coupled to a capacitor, such as an off-chip capacitor.

[0022] In a first operating state of the negative pump stabilization circuit (e.g., corresponding to a sleep operating mode of a corresponding power supply and / or imaging system employing the negative pump stabilization circuit), the second node may be coupled to the output of the reference voltage generator via the second switch, and the first node may be coupled to ground via the third switch. Additionally, the first node may be decoupled from the output of the negative charge pump via the third switch, and the second node may be decoupled from ground via the fourth switch. In this manner, the voltage at the second node may rise to the reference voltage output from the reference voltage generator while the first node is grounded (e.g., at 0V). Thus, a pre-charge gap exists or is established between the voltage at the second node and the voltage at the first node while the negative pump stabilization circuit is in the first operating state.

[0023] When the negative pump stabilization circuit subsequently transitions from the first operating state to a second operating state (e.g., corresponding to a normal operating mode of a corresponding power supply and / or imaging system employing the negative pump stabilization circuit), the first node may be decoupled from ground via the third switch and coupled to the output of the negative charge pump via the first switch, and the second node may be decoupled from the output of the reference voltage generator via the second switch and coupled to ground via the fourth switch. As the negative pump stabilization circuit transitions to the second operating state, a negative boost may occur at the first and second nodes to cause the voltage at each of the nodes to quickly drop by an amount equal to the pre-charge gap established in the first operating state. Thus, in an embodiment where ground is equal to 0V, the voltage at the first node may quickly drop to a negative equivalent value of the reference voltage output from the reference voltage generator. Thereafter, the voltage at the first node may stabilize at a negative equivalent value of the reference voltage or continue to stabilize at another voltage value.

[0024] In this manner, the present technique utilizes the negative boost voltage occurring at the first and second nodes to significantly reduce or minimize the NVDD stabilization time. For example, in many cases, the power supply stabilization circuit of the present technique can facilitate achieving an NVDD stabilization time on the order of approximately 170 μs, which represents a NVDD stabilization time that is nearly 10 times faster than the NVDD stabilization time of other power supplies or imagers discussed above. Thus, the present technique facilitates faster capture of accurate images of external scenes when an imaging system and / or a corresponding power supply transitions from a first operating state (e.g., a sleep mode) to a second operating state (e.g., a normal operating mode).

[0025] B. Selected embodiments of image sensors with improved negative pump voltage stabilization and circuit systems thereof

[0026] Figure 1 1 is a partially schematic block diagram of an image sensor 100 configured in accordance with various embodiments of the present technology. As shown, the image sensor 100 includes a pixel array 102, a readout circuit system 106, function logic 108, and a control circuit system 110. The pixel array may be arranged in rows (in Figure 1 Individually identified as rows R1 to Ry) and columns (in Figure 1 1 to 12 (individually identified as columns C1 to Cx in FIG. Figure 1 Pixel cells 112 are each configured to capture image charge in response to incident light received from an external scene and to generate a corresponding analog image charge data signal based at least in part on the captured image charge.

[0027] After each pixel cell 112 has acquired an image charge, a corresponding analog image charge data signal is read out of the pixel array 102 along column bit lines 114 and into the readout circuitry 106. In some embodiments, the analog image charge data signal is read out of the pixel array 102 one row of pixel cells 112 at a time. Alternatively, the analog image charge data signal is read out of the pixel array 102 using other suitable techniques, such as (a) sequentially reading out the pixel cells 112 one by one using a serial readout technique, or (b) simultaneously reading out all or a subset (e.g., multiple rows) of pixel cells 112 using a parallel readout technique.

[0028] When the analog image charge data signal is read into the readout circuitry 106, an analog-to-digital converter (ADC) may be used. Figure 1 102. In some embodiments, the ADC of readout circuitry 106 has an adjustable gain so that the analog image charge data signal can be read out from pixel array 102 using multiple gain settings. Figure 1 Not shown, readout circuitry 106 may additionally or alternatively include amplification circuitry, column readout circuitry, and / or other circuitry.

[0029] The digital representation of the analog image charge data signal may then be transferred from readout circuitry 106 to function logic 108. In some embodiments, function logic 108 is configured to simply store the digital representation as image data. In other embodiments, function logic 108 may be configured to manipulate the image data in addition to storing the image data (e.g., by applying post image effects such as cropping, rotation, red eye removal, brightness adjustment, contrast adjustment, etc.). The image data may be used to render an image of an external scene (e.g., of a person, place, object, etc. within the external scene) from which light incident on pixel cells 112 of pixel array 102 is received.

[0030] As shown, control circuitry 110 is coupled to pixel array 102. In some embodiments, control circuitry 110 controls operating characteristics of pixel array 102. For example, control circuitry 110 may generate transfer signals and / or other control signals (e.g., reset signals) that are used to (a) control the transfer of image charge and / or other signals within each of pixel cells 112 and / or (b) control the readout of analog image charge data signals from pixel array 102. As another example, control circuitry 110 may generate a shutter signal for controlling image acquisition. The shutter signal may be a global shutter signal for enabling all pixel cells 112 of pixel array 102 to simultaneously capture respective image charges (and corresponding analog image charge data signals) during a single acquisition window. Alternatively, the shutter signal may be a rolling shutter signal such that each row, each column, or each other grouping of pixel cells 112 is sequentially enabled to capture respective image charges (and corresponding analog image charge data signals) during consecutive acquisition windows. In some embodiments, the shutter signal may establish an exposure time (e.g., defined as the length of time a shutter remains open, although image sensor 100 may lack a physical shutter). The exposure time may be the same for each image frame, or the exposure time may vary across different image frames.

[0031] In some embodiments, the image sensor 100 may be included in a digital camera, a cell phone, a laptop computer, or the like. Additionally or alternatively, the image sensor 100 may be coupled to other hardware parts, such as a processor (general purpose processor or other processor), a memory element, an output (USB port, a wireless transmitter, an HDMI port, etc.), an illumination device / flash, an electrical input (keyboard, a touch display, a track pad, a mouse, a microphone, etc.), and / or a display. The other hardware parts may deliver instructions to the image sensor 100, extract image data from the image sensor 100, or manipulate the image data supplied by the image sensor 100.

[0032] Figure 2 is a circuit diagram of a pixel unit 212 configured according to various embodiments of the present technology. The pixel 212 may be Figure 1102 of the pixel array 102 or another pixel of the present technology. As shown, the pixel 212 includes a photosensor 216, a transfer transistor 218, a floating diffusion region 220, a reset transistor 222, a source follower transistor 224, and a row select transistor 226. In the illustrated embodiment, the photosensor 216 is a photodiode having an anode coupled to ground (e.g., a negative power supply rail or another reference voltage) and a cathode coupled to the transfer transistor 218. In other embodiments of the present technology, the photosensor 216 may be another suitable type of photosensor or photodetector (e.g., a metal-semiconductor-metal (MSM) photodetector, a phototransistor, a photoconductivity detector, or a phototube). In operation, the photosensor 216 is configured to photogenerate an image charge or photocurrent in response to incident light received from an external scene.

[0033] Transfer transistor 218 selectively couples photosensor 216 to floating diffusion region 220. In particular, transfer transistor 218 includes a gate configured to receive transfer signal TX. When transfer signal TX applied to the gate of transfer transistor 218 is asserted, transfer transistor 218 is activated to transfer photogenerated image charge from photosensor 216 to floating diffusion region 220.

[0034] Reset transistor 222 selectively couples floating diffusion region 220 to a pixel voltage supply. More specifically, reset transistor 222 includes a gate configured to receive a reset signal RST. When reset signal RST is asserted, reset transistor 222 is activated to couple floating diffusion region 220 to the pixel voltage supply, thereby resetting the voltage at floating diffusion region 220.

[0035] The floating diffusion region 220 is further coupled to the gate of a source follower transistor 224. In operation, the source follower transistor 224 is configured to convert the charge at the floating diffusion region 220 into an analog signal at the source of the source follower transistor 224.

[0036] Row select transistor 226 selectively couples the source of source follower transistor 224 to a column bit line (eg, Figure 1 More specifically, row select transistor 226 includes a gate configured to receive a row select signal SEL. With row select signal SEL asserted, row select transistor 226 is activated to pass the analog signal received from source follower transistor 224 to the column bit line via pixel level connection 228.

[0037] In an imaging system utilizing correlated double sampling (CDS), the imaging system uses pixel 212 to obtain a reset level and a signal level. Specifically, after resetting floating diffusion region 220 by asserting reset signal RST, the imaging system reads out the charge at floating diffusion region 220 through pixel-level connection 228 to obtain a corresponding reset level. Additionally, after photosensor 216 photogenerates an image charge and transfers the image charge to floating diffusion region 220 via transfer transistor 218, the imaging system reads out the image charge at floating diffusion region 220 through pixel-level connection 228 to obtain a signal level. Thereafter, the imaging system obtains an image data signal by subtracting the reset level from the signal level to eliminate noise read out in the signal level.

[0038] Figure 3 3 is a partially schematic block diagram of an imaging system 370 configured in accordance with various embodiments of the present technology. As shown, the imaging system 370 includes a power supply 300, a transfer gate (TX) driver 375, and an array 302 of pixels 312. In some embodiments, the array 302 may be Figure 1 102 or another array of the present technology. In these and other embodiments, the pixel 312 may be Figure 1 Pixels 112, Figure 2 212 or other pixels of the present technology. In these and still other embodiments, imaging system 370 may include components other than those shown in the illustrated embodiments. For example, imaging system 370 may include a pixel 212 configured to receive a pixel 212 of the embodiment of the present technology or other pixels ... Figure 1 108) reads out signals from pixels 312 of array 302 (e.g., similar to functional logic 108) Figure 1 As a specific example, imaging system 370 may be incorporated into Figure 1 All or a subset of image sensor 100 .

[0039] In the illustrated embodiment, the TX driver 375 is coupled to the array 302. More specifically, the TX driver 375 includes (a) an input configured to receive an input signal TX_IN and (b) an output coupled to the pixels 312 of the array 302. The input signal TX_IN may be a digital signal. Based at least in part on the input signal TX_IN, the TX driver 375 may generate a transfer signal TX at an output. The output of the TX driver 375 may be coupled to the gate of the transfer transistor of the pixel 312 of the array 302. Thus, the transfer signal TX generated at the output of the TX driver 375 may be applied to the gate of the transfer transistor of the pixel 312 (e.g., with the gate of the transfer transistor). Figure 22 is configured to receive transfer signal TX). Thus, changes in transfer signal TX may be used to control the timing of when pixel 312 of array 302 transfers image charge from its photosensor (not shown) to its floating diffusion region (not shown), as described above with reference to FIG. Figure 2 For example, pixel 312 of array 302 may be configured to transfer image charge from its photosensor to its floating diffusion region at a rising edge or a falling edge of transfer signal TX. In some embodiments, TX driver 375 may be a control circuit system (e.g., Figure 1 part of the control circuit system 110).

[0040] In some embodiments, imaging system 370 includes one or more load capacitors 350. For example, one or more load capacitors 350 may include external capacitances including designed and / or parasitic capacitances. As a specific example, load capacitors 350 may correspond at least in part to off-chip capacitors. Additionally or alternatively, load capacitors 350 may be associated with capacitances of TX driver 375 and / or internal capacitances of power supply 300. In some embodiments, such load capacitances may be generated at least in part by interactions between metal traces in imaging system 370.

[0041] Figure 3 TX driver 375 in is powered by power supply 300. More specifically, TX driver 375 is powered by negative pump voltage NVDD at the output of power supply 300. Figure 3 370 as powering TX driver 375 , but the negative pump voltage NVDD generated by power supply 300 may be used to additionally or alternatively power other components of imaging system 370 .

[0042] In some embodiments, the imaging system 370 may be placed in a first state or sleep mode (e.g., to conserve power when the imaging system 370 is not in use). When the imaging system 370 is in the first state or sleep mode, the negative pump voltage NVDD provided to the TX driver 375 from the power supply 300 may be at a first value (e.g., 0V). As the imaging system 370 transitions to the second state or normal operating mode, the negative pump voltage NVDD provided to the TX driver 375 may transition to a second value (e.g., -1.4V). However, as discussed above, the transition of the negative pump voltage NVDD from the first value to the second value is not instantaneous, which means that there is an NVDD stabilization time representing the amount of time between when the imaging system 370 wakes up from the sleep mode and when the negative pump voltage NVDD reaches or stabilizes at the second value. Any image data frames captured during the NVDD stabilization time and before the negative pump voltage NVDD stabilizes at the second value may not accurately represent the external scene being imaged. For example, the TX driver 375 of the imaging system 370 may be improperly powered during the NVDD stabilization time. Therefore, the transfer signal TX generated at the output of the TX driver 375 may be at an incorrect voltage level to properly capture an image data frame during the NVDD stabilization time. Therefore, for image data frames captured during the NVDD stabilization time, the transfer transistors of at least some of the pixels 312 of the array 302 may not be activated to transfer the image charge generated by the photosensors of those pixels 312 to the corresponding floating diffusion regions of those pixels 312. In turn, the signal levels read out from those pixels 312 for frames captured during the NVDD stabilization time may not accurately represent the light from the external scene incident on the photosensors for those frames, which means that the image data signals corresponding to those signal levels may be darker than the brightness they would have when they were generated and read out in the image data frames captured outside the NVDD stabilization time. This may be particularly problematic when trying to capture an image as quickly as possible after waking up the imaging system 370 from a sleep mode. Thus, reducing the NVDD stabilization time may facilitate faster capture of accurate images of external scenes after the imaging system 370 transitions from a sleep mode to a normal operating mode. Therefore, imaging system 370 and other image sensors / imaging systems configured according to the present technology can employ a power supply stabilization circuit to reduce or minimize the NVDD stabilization time. For example, power supply 300 can employ a power supply stabilization circuit internally. Additionally or alternatively, imaging system 370 can employ a power supply stabilization circuit that is at least partially positioned external to power supply 300.

[0043] Figure 4is a circuit diagram of a power supply stabilization circuit 440 configured in accordance with various embodiments of the present technology. As shown, the power supply stabilization circuit 440 includes a negative charge pump 430, a level shifter 431, an inverting level shifter 432, a first NMOS transistor 433, a second NMOS transistor 434, a first pad 435, a reference voltage generator 436, a first PMOS transistor 437, a third NMOS transistor 438, and a second pad 439. The power supply stabilization circuit 440 is also referred to herein as a negative pump stabilization circuit.

[0044] The negative charge pump 430, the level shifter 431, and the inverting level shifter 432 each include an input configured to receive an enable signal Enable. The negative charge pump 430 includes an output selectively coupled to the first node A via a second NMOS transistor 434. The source of the second NMOS transistor 434 is coupled to the first node A, the drain of the second NMOS transistor 434 is coupled to the output of the negative charge pump 430, and the gate of the second NMOS transistor 434 is coupled to the output of the level shifter 431. The output of the level shifter 431 is further coupled to the gate of the first PMOS transistor 437 and the gate of the third NMOS transistor 438. The inverting level shifter includes an output coupled to the gate of the first NMOS transistor 433. The drain of the first NMOS transistor 433 is coupled to the first node A, and the source of the first NMOS transistor 433 is coupled to ground. The first pad 435 is coupled to the first node A.

[0045] The reference voltage generator 436 is configured to generate a reference voltage VREF at a second node B of the power supply stabilization circuit 440. As discussed in more detail below, the reference voltage VREF may be equal to the absolute value of the voltage output from the negative charge pump 430 or another value. In some embodiments, the reference voltage generator 436 may use a voltage divider to generate the reference voltage VREF. For example, the reference voltage generator 436 may include a voltage divider formed by a second PMOS transistor 441 and a third PMOS transistor 442. The second PMOS transistor 441 may be a PMOS transistor having (a) a source coupled to the analog power supply voltage AVDD and (b) a diode connection of the gate and drain shorted together and coupled to the second node B. Similarly, the third PMOS transistor 442 may be a PMOS transistor having (a) a source coupled to the second node B and (b) a diode connection of the gate and drain shorted together and coupled to ground.

[0046] A drain of the first PMOS transistor 437 is coupled to the second node C, and a source of the first PMOS transistor 437 is coupled to a third node C of the power supply stabilization circuit 440. A source of the third NMOS transistor 438 is coupled to the ground, and a drain of the third NMOS transistor 438 is coupled to the third node C. A second pad 439 is coupled to the third node C.

[0047] The first pad 435 and the second pad 439 can each be coupled to an off-chip capacitor 450. In one example, the off-chip capacitor 450 can include a capacitance on the order of approximately 1 μF to 2 μF. In some embodiments, Figure 4 The off-chip capacitor 450 described in the embodiment may additionally or alternatively include or represent a capacitor corresponding at least in part to a power supply (eg, Figure 3 power supply 300), TX driver (e.g., Figure 3 The load capacitance of the internal capacitance of the TX driver 375) and / or other peripheral / external circuit systems.

[0048] Figure 5A and 5B They are Figure 4 4 is a simplified circuit diagram of the power supply stabilization circuit 440 in different states 560a and 560b. For example, Figure 5A The state 560a of the power supply stabilization circuit 440 described in FIG. 4 may correspond to a sleep mode of operation, and Figure 5B State 560b of the power supply stabilization circuit 440 illustrated in FIG. 4 may correspond to a normal operating mode.

[0049] like Figure 5A and 5B , the first NMOS transistor 433, the second NMOS transistor 434, the first PMOS transistor 437, and the third NMOS transistor 438 are operated as switches whose states (open / closed or activated / deactivated) depend on the state (asserted / unasserted) of the enable signal Enable. For example, the first NMOS transistor 433 is operated to selectively couple (a) the first node A and the first pad 435 to (b) ground; the second NMOS transistor 434 is operated to selectively couple (a) the first node A and the first pad 435 to (b) the output of the negative charge pump 430; the first PMOS transistor 437 is operated to selectively couple (a) the third node C and the second pad 439 to (b) the second node B (e.g., to Figure 4 and the third NMOS transistor 438 is operated to selectively couple (a) the third node C and the second pad 439 to (b) ground.

[0050] Now refer to Figure 6 Discussion Figure 5A and 5B A simplified circuit diagram of the power supply stabilization circuit 440 illustrated in FIG. Figure 6 A timing diagram 690 corresponding to transitioning the power supply stabilization circuit 440 from a sleep mode to a normal operating mode is illustrated. Figure 6 During the time period between time t0 and time t1 in the timing diagram 690 of FIG. Figure 5A 4. The present invention relates to a sleep mode controller 400 that operates in the sleep mode of the state 560a illustrated in FIG. 4. More specifically, the sleep enable signal sleep_en is asserted, while the enable signal Enable is not asserted. When the enable signal Enable is not asserted, the first NMOS transistor 433 and the first PMOS transistor 437 are activated, while the second NMOS transistor 434 and the third NMOS transistor 438 are deactivated. Thus, the first node A is coupled to the ground via the first NMOS transistor 433 so that the negative pump voltage NVDD at the first pad 435 is equal to the ground (e.g., 0V). In addition, the third node C is coupled to the second node B via the first PMOS transistor 437 so that the positive voltage VPOS at the second pad 439 is equal to the positive voltage VPOS generated from the reference voltage generator 436 ( Figure 4 ) outputted a reference voltage VREF. In some embodiments, the positive voltage VPOS at the second pad 439 may be -1.4V when the power supply stabilization circuit 440 operates in the sleep mode.

[0051] exist Figure 6 At time t1 in the timing diagram 690 illustrated in FIG. 1 , the power supply stabilization circuit 440 switches from operating in the sleep mode to operating in the mode corresponding to Figure 5B 4. The first and second PMOS transistors 430 and 435 are connected to the negative charge pump 430 in the state 560b described in FIG. 4. More specifically, the sleep enable signal sleep_en is not asserted, while the enable signal Enable is asserted. When the enable signal Enable is asserted, the second NMOS transistor 434 and the third NMOS transistor 438 are activated, while the first NMOS transistor 433 and the first PMOS transistor 437 are deactivated. Thus, the first node A and the first pad 435 are (a) decoupled from ground and (b) coupled to the output of the negative charge pump 430 via the second NMOS transistor 434. At the same time, the third node C and the second pad 439 are (a) and the second node B (e.g., Figure 4 The positive voltage VPOS at the second pad 439 drops from the reference voltage VREF to ground (e.g., 0V), while the negative pump voltage NVDD at the first pad 435 transitions from ground (e.g., 0V) to a negative equal value of the reference voltage VREF (e.g., -1.4V).

[0052] like Figure 6 As shown in FIG. 4 , the positive voltage VPOS at the second pad 439 and the negative pump voltage NVDD at the first pad 435 experience a negative boost at time t1 equal to the precharge gap between the positive voltage VPOS and the negative pump voltage NVDD just before time t1. Therefore, the NVDD stabilization time of the power supply stabilization circuit 440 can be obtained by Figure 4 ) is set equal to the absolute value of the desired final voltage level at which the negative pump voltage NVDD stabilizes when the power supply stabilization circuit 440 transitions from the sleep mode to the normal operating mode. In other words, the NVDD stabilization time of the power supply stabilization circuit 440 can increase as the difference between (a) the final voltage level at which the negative pump voltage NVDD stabilizes and (b) the negative equivalent value of the reference voltage VREF increases. To illustrate this point, Figure 6 The timing diagram 690 of FIG. 690 is shown as having two line segments 691 and 692 corresponding to the negative pump voltage NVDD. Line segment 691 illustrates that the negative pump voltage NVDD initially drops to a negative equivalent value of the reference voltage VREF and then gradually increases until it stabilizes at a final voltage level greater than the negative equivalent value of the reference voltage VREF at time t2. Line segment 692 illustrates that the negative pump voltage NVDD initially drops to a negative equivalent value of the reference voltage VREF and then gradually decreases until it stabilizes at a final voltage level less than the negative equivalent value of the reference voltage VREF at time t2. In both cases, the NVDD stabilization time (represented in the timing diagram 690 by time t2 minus time t1) is positively correlated to the magnitude of the difference between the final voltage level at which the negative pump voltage NVDD stabilizes and the negative equivalent value of the reference voltage VREF. For this reason, when the voltage level is increased from t2 to t1, the voltage level at which the negative pump voltage NVDD stabilizes is positively correlated to the magnitude of the difference between the final voltage level at which the negative pump voltage NVDD stabilizes and the negative equivalent value of the reference voltage VREF. Figure 4 The negative voltage boost experienced at or near time t1 in timing diagram 690 can be maximized when the reference voltage VREF output by reference voltage generator 436 is equal to the absolute value of the desired final voltage level at which negative pump voltage NVDD stabilizes when transitioning from sleep mode to normal operation mode.

[0053] In many cases, the NVDD stabilization time of the power supply stabilization circuit 440 can be much less than the NVDD stabilization time of other power supplies and / or imagers. For example, in some embodiments, the NVDD stabilization time of the power supply stabilization circuit 440 can be on the order of approximately 170 μs, which represents a nearly 10 times faster NVDD stabilization time than other power supplies or imagers that do not employ the power supply stabilization circuit of the present technique and / or include a NVDD stabilization time on the order of 2 ms. In this manner, the present technique significantly reduces or minimizes the NVDD stabilization time, thereby facilitating faster capture of accurate images of external scenes when the imaging system and / or the corresponding power supply transitions from a sleep mode to a normal operating mode.

[0054] C. in conclusion

[0055] The above detailed description of the embodiments of the present technology is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. Although specific embodiments and examples of the present technology are described above for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the present technology. For example, although the steps are presented in the order given above, alternative embodiments may perform the steps in a different order. In addition, the various embodiments described herein may also be combined to provide further embodiments.

[0056] It will be understood from the foregoing that the specific embodiments of the present technology have been described herein for the purpose of illustration, but the well-known structures and functions are not shown or described in detail to avoid unnecessary ambiguity in the description of the embodiments of the present technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to only represent a single item that is excluded from other items in a list involving two or more items, the use of "or" in this list should be interpreted as including any combination of (a) any single item in the list, (b) all items in the list, or (c) items in the list. In addition, as used herein, the phrase "and / or" as in "A and / or B" refers to only A, only B, and both A and B. In addition, the terms "include", "include", "have" and "with" are used throughout to indicate that at least (several) stated features are included so that any more number of the same features and / or other features of additional types are not excluded. In addition, as used herein, the phrases "based on", "depending on", "as a result of ..." and "in response to" should not be interpreted as a reference to a set of closed conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on" or the phrase "based at least partially on." Moreover, the terms "connected" and "coupled" may be used interchangeably herein and refer to both direct and indirect connections or couplings. For example, element A being "connected" or "coupled" to element B may mean that (i) A is directly "connected" or "coupled" to B and / or (ii) A is indirectly "connected" or "coupled" to B, where the context permits.

[0057] It will also be understood from the foregoing that various modifications may be made without departing from the present disclosure or the present technology. For example, it will be understood by those skilled in the art that the various components of the present technology may be further divided into subcomponents, or various components and functions of the present technology may be combined and integrated. In addition, certain aspects of the present technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments that are not explicitly shown or described herein.

Claims

1. A negative pump stabilization circuit, comprising: Negative charge pump; a first level shifter; a second level shifter different from the first level shifter; a first switch that selectively couples the output of the negative charge pump to a first node; a second switch selectively coupling the first node to ground; a third switch that selectively couples the second node to an output of a reference voltage generator; and a fourth switch selectively coupling the second node to ground, The first node and the second node may be coupled to each other via a capacitor, wherein an output of the first level shifter is coupled to the first switch, the third switch, and the fourth switch such that a signal generated at the output of the first level shifter can be used to control each of the first switch, the third switch, and the fourth switch, and The output of the second level shifter is coupled to the second switch, so that a signal generated at the output of the second level shifter can be used to control the second switch.

2. The negative pump stabilization circuit of claim 1, wherein the first switch comprises an NMOS transistor having a source coupled to the first node and a drain coupled to the output of the negative charge pump.

3. The negative pump stabilization circuit of claim 2, wherein the NMOS transistor further includes a gate coupled to the output of the first level shifter, and wherein the first level shifter includes an input configured to receive an enable signal.

4. The negative pump stabilization circuit of claim 1, wherein the second switch comprises an NMOS transistor having a source coupled to ground and a drain coupled to the first node.

5. The negative pump stabilization circuit of claim 4, wherein the NMOS transistor further includes a gate coupled to the output of the second level shifter, and wherein the second level shifter includes an input configured to receive an enable signal.

6. The negative pump stabilization circuit of claim 1, wherein the third switch comprises a PMOS transistor having a source coupled to the reference voltage generator and a drain coupled to the second node.

7. The negative pump stabilization circuit of claim 6, wherein the PMOS transistor includes a gate coupled to the output of the first level shifter, and wherein the first level shifter includes an input configured to receive an enable signal.

8. The negative pump stabilization circuit of claim 1, wherein the fourth switch comprises an NMOS transistor having a source coupled to ground and a drain coupled to the second node.

9. The negative pump stabilization circuit of claim 8, wherein the NMOS transistor includes a gate coupled to the output of the first level shifter, and wherein the first level shifter includes an input configured to receive an enable signal.

10. The negative pump stabilization circuit of claim 1, wherein the first switch and the fourth switch are configured such that (i) the first switch is open when the fourth switch is open, and (ii) the first switch is closed when the fourth switch is closed.

11. The negative pump stabilization circuit of claim 1, wherein the second switch and the third switch are configured such that (i) the second switch is open when the third switch is open, and (ii) the second switch is closed when the third switch is closed.

12. The negative pump stabilization circuit according to claim 11, wherein the first switch, the second switch, the third switch and the fourth switch are configured so that (i) the first switch and the fourth switch are opened when the second switch and the third switch are closed, and (ii) the first switch and the fourth switch are closed when the second switch and the third switch are opened.

13. A negative pump stabilization circuit according to claim 1, wherein the reference voltage generator includes: (a) a first PMOS transistor having a source coupled to a power supply voltage AVDD and a drain coupled to the output of the reference voltage generator; and (b) a second PMOS transistor having a source coupled to the output of the reference voltage generator and a drain coupled to ground. 14 . The negative pump stabilization circuit according to claim 13 , wherein the first PMOS transistor or the second PMOS transistor is a diode-connected PMOS transistor whose gate is shorted to its drain.

15. A negative pump stabilization circuit according to claim 1, wherein the reference voltage generator is configured to generate a reference voltage at the output of the reference voltage generator, and wherein the reference voltage is equal to the absolute value of the voltage level at which the negative pump voltage NVDD at the first node stabilizes after the negative pump stabilization circuit transitions from a first operating state to a second operating state.

16. The negative pump stabilization circuit according to claim 15, wherein: The first switch and the fourth switch are configured to be opened when the negative pump stabilization circuit operates in the first operation state; The second switch and the third switch are configured to be closed when the negative pump stabilization circuit operates in the first operating state; The first switch and the fourth switch are configured to be closed when the negative pump stabilization circuit operates in the second operating state; and The second switch and the third switch are configured to be opened when the negative pump stabilization circuit operates in the second operation state.

17. The negative pump stabilization circuit according to claim 1, further comprising: a first pad coupled to the first node; and a second pad, coupled to the second node, Wherein the first pad and the second pad can each be coupled to the capacitor.

18. The negative pump stabilization circuit of claim 1, wherein the capacitor is an off-chip capacitor.

19. The negative pump stabilization circuit of claim 1, wherein the second level shifter comprises an inverting level shifter.

20. A method of operating a negative pump stabilization circuit, the method comprising: while operating the negative pump stabilization circuit in a first state, precharging a first node of the negative pump stabilization circuit to a reference voltage to establish a voltage difference between the first node and a second node of the negative pump stabilization circuit different from the first node; and Transitioning the negative pump stabilization circuit from the first state to a second state causes (a) a negative voltage boost to occur at the second node so that the voltage at the second node drops by an amount equal to the voltage difference, and (b) the voltage at the second node stabilizes at a voltage level, wherein transitioning the negative pump stabilization circuit from the first state to the second state includes: using the output of the first level shifter of the negative pump stabilization circuit to (a) decouple the first node from the output of a reference voltage generator, (b) couple the first node to ground, and (c) couple the second node to the output of a negative charge pump, and decoupling the second node from ground using an output of a second level shifter of the negative pump stabilization circuit, the second level shifter being different from the first level shifter, Wherein at least while transitioning the negative pump stabilization circuit from the first state to the second state, the second node is coupled to the first node.

21. The method of claim 20, further comprising generating the reference voltage such that the reference voltage is equal to an absolute value of the voltage level.

22. The method of claim 20, wherein precharging the first node comprises coupling the first node to the output of the reference voltage generator.

23. The method of claim 22, wherein precharging the first node further comprises decoupling the first node from ground.

24. The method of claim 22, wherein precharging the first node further comprises coupling the second node to ground.

25. The method of claim 24, wherein coupling the second node to ground comprises coupling the second node to ground at the same time as coupling the first node to the output of the reference voltage generator.

26. The method of claim 24, wherein precharging the first node further comprises decoupling the second node from the output of the negative charge pump.

27. The method of claim 20, wherein coupling the first node to ground comprises coupling the first node to ground at the same time as coupling the second node to the output of the negative charge pump.

28. The method of claim 20, wherein transitioning the negative pump stabilization circuit from the first state to the second state comprises simultaneously (a) decoupling the first node from the output of the reference voltage generator, (b) coupling the first node to ground, (c) decoupling the second node from ground, and (d) coupling the second node to the output of the negative charge pump.

29. The method according to claim 20 further includes transitioning the negative pump stabilization circuit from the second state to the first state, wherein transitioning the negative pump stabilization circuit from the second state to the first state includes simultaneously (a) decoupling the first node from ground, (b) coupling the first node to the output of the reference voltage generator, (c) decoupling the second node from the output of the negative charge pump, and (d) coupling the second node to ground.

30. The method of claim 20, further comprising coupling the first node to the second node via a capacitor.

31. The method of claim 29, wherein transitioning the negative pump stabilization circuit from the second state to the first state comprises: using the output of the first level shifter to (i) decouple the first node from ground, (ii) couple the first node to the output of the reference voltage generator, and (iii) decouple the second node from the output of the negative charge pump; and The second node is coupled to ground using the output of the second level shifter.

32. The method of claim 20, further comprising transitioning the negative pump stabilization circuit from the second state to the first state, wherein transitioning the negative pump stabilization circuit from the second state to the first state comprises (a) decoupling the first node from ground, and (b) coupling the first node to the output of the reference voltage generator.

33. The method according to claim 20 further includes transitioning the negative pump stabilization circuit from the second state to the first state, wherein transitioning the negative pump stabilization circuit from the second state to the first state includes (a) decoupling the second node from the output of the negative charge pump, and (b) coupling the second node to ground.

34. The method of claim 20, wherein using the output of the second level shifter to decouple the second node from ground comprises using an output of an inverting level shifter to decouple the second node from ground.

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