Solar cell, method for preparing solar cell, and photovoltaic module

Abstract

The present application discloses a solar cell, a method for preparing a solar cell, and a photovoltaic module, belonging to the field of photovoltaic technology. The solar cell includes a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface including a first region and a second region spaced apart and a third region located between the first region and the second region; a first doped layer and a second doped layer, the first doped layer being arranged on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer being arranged on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having a polarity opposite to that of the first doped layer; a dielectric layer and a conductive path layer, the dielectric layer and the conductive path layer being sequentially stacked in the third region in a direction away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting a portion of the first doped layer and a portion of the second doped layer.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a method for preparing a solar cell, and a photovoltaic module. Background Art

[0002] Solar cells can convert solar energy into electricity. Back-contact solar cells, a type of solar cell, have electrodes located on the back of the cell to prevent them from blocking the front of the cell, thereby improving the cell's photoelectric conversion efficiency.

[0003] Existing back-contact solar cells typically include a substrate with a front and back surface. The back surface has a first region, a second region, and a third region disposed between the first and second regions. A first doped layer is stacked in the first region, a second doped layer is stacked in the second region, and a dielectric layer is stacked in the third region. The dielectric layer blocks the first and second doped layers to prevent leakage in the cell and improve the cell's photoelectric conversion efficiency.

[0004] However, existing back-contact solar cells are prone to hot spot problems. Summary of the Invention

[0005] The present application discloses a solar cell, a method for preparing the solar cell, and a photovoltaic module, in order to solve or at least partially solve the problem of hot spots easily occurring in back-contact solar cells in the prior art.

[0006] In order to solve the above technical problems, this application is implemented as follows:

[0007] In a first aspect, the present application discloses a solar cell, comprising: a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region spaced apart and a third region located between the first region and the second region; a first doped layer and a second doped layer, the first doped layer being arranged on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer being arranged on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having an opposite polarity to the first doped layer; a dielectric layer and a conductive path layer, the dielectric layer and the conductive path layer being sequentially stacked on the third region in a direction away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting a portion of the first doped layer and a portion of the second doped layer.

[0008] Optionally, along the thickness direction of the battery cell, the thickness of the dielectric layer is greater than the thickness of the conductive path layer.

[0009] Optionally, along the thickness direction of the battery cell, the thickness of the conductive path layer is greater than the thickness of the dielectric layer.

[0010] Optionally, the dielectric layer and the conductive path layer are made of the same base material; or, the dielectric layer and the conductive path layer are made of different base materials.

[0011] Optionally, the conductive path layer is doped with one element; and / or the conductive path layer is doped with two elements with opposite polarities.

[0012] Optionally, the conductive path layer includes a single doping path layer and a co-doping path layer, wherein the single doping path layer is stacked on the side of the dielectric layer away from the substrate, and the co-doping path layer is stacked on the side of the single doping path layer away from the dielectric layer; the single doping path layer is doped with one element, and the co-doping path layer is doped with two elements with opposite polarities.

[0013] Optionally, the single doping path layer and the co-doping path layer have the same conductivity type.

[0014] Optionally, the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the first doping layer; and / or the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the second doping layer.

[0015] Optionally, along the thickness direction of the cell, the thickness of the conductive path layer is d1, which satisfies 10nm≤d1≤120nm; and / or the element doping concentration of the conductive path layer is greater than 1E18cm - ³ and less than 5E22cm - ³.

[0016] Optionally, the element doping concentration of the dielectric layer is less than 1E13 cm - ³; and / or, along the thickness direction of the battery cell, the thickness of the dielectric layer is d2, satisfying 20nm≤d2≤490nm.

[0017] Optionally, a third doping region is provided in the substrate corresponding to the third region, and the element doping concentration of the third doping region is less than 1E13 cm - ³.

[0018] Optionally, the substrate corresponding to the first region has a first doping region, and the element doping concentration of the first doping region is greater than 1E13 cm -³; and / or, the substrate corresponding to the second region has a second doped region, and the element doping concentration of the second doped region is greater than 1E13cm - ³.

[0019] Optionally, the first doped layer includes a first single-doped layer and a first co-doped layer, the first co-doped layer is doped with two elements with opposite polarities, wherein the first single-doped layer is stacked on the surface of the first region or at least partially embedded in the surface of the first region, the first co-doped layer is stacked on the side of the first single-doped layer away from the substrate, and the conductivity type of the first co-doped layer is opposite to that of the first single-doped layer; the solar cell also includes a first electrode, the first electrode is coupled to the first region of the substrate, the first co-doped layer is provided with a through groove, the first electrode is embedded in the through groove and connected to the first single-doped layer or the first region of the substrate, and there is a gap between the first electrode and the inner wall of the through groove.

[0020] Optionally, the uniformity of the element doping concentration in the first single-doped layer is better than the uniformity of the element doping concentration in the first co-doped layer.

[0021] Optionally, the second doped layer includes a second single-doped layer and a second co-doped layer, and the second co-doped layer is doped with two elements with opposite polarities, wherein the second single-doped layer is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer is stacked on the side of the second single-doped layer away from the substrate, and the second co-doped layer has the same conductivity type as the second single-doped layer.

[0022] Optionally, along the thickness direction of the battery cell, the thickness of the second co-doped layer is greater than the thickness of the first co-doped layer, and the thickness of the first co-doped layer is greater than or equal to the thickness of the co-doped path layer.

[0023] Optionally, the first doping layer has a first concentration gradient co-doping region on a side close to the conductive path layer; and / or the second doping layer has a second concentration gradient co-doping region on a side close to the conductive path layer.

[0024] Optionally, when the first doping layer is a P-type doping layer and the second doping layer is an N-type doping layer, the width of the first gradient concentration co-doping region is greater than the width of the second gradient concentration co-doping region.

[0025] Optionally, a side of the conductive path layer close to the first doping layer has a first depth-gradient co-doping region, and a side of the conductive path layer close to the second doping layer has a second depth-gradient co-doping region.

[0026] In a second aspect, the present application also discloses a method for preparing a solar cell, the method comprising: providing a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region arranged at intervals and a third region located between the first region and the second region; forming a first doping layer on the surface of the first region or in the surface of the first region, and forming a second doping layer on the surface of the second region or in the surface of the second region, the polarity of the first doping layer and the second doping layer being opposite; and stacking a dielectric layer and a conductive path layer in sequence in the third region in a direction away from the substrate, so as to block the first doping layer and the second doping layer through the dielectric layer, and connect part of the first doping layer and part of the second doping layer through the conductive path layer.

[0027] Optionally, the method of forming a first doping layer on the surface of the first region or within the surface of the first region, and forming a second doping layer on the surface of the second region or within the surface of the second region includes: forming a semiconductor layer on the first surface of the substrate, and forming a first doping source layer and a second doping source layer at positions of the semiconductor layer corresponding to the first region and the second region, respectively; heating and advancing the first doping source layer and the second doping source layer so that the first doping layer is formed in the portion of the semiconductor layer corresponding to the first region, and the second doping layer is formed in the portion of the semiconductor layer corresponding to the second region, and the polarities of the first doping layer and the second doping layer are opposite.

[0028] Optionally, the method of sequentially stacking a dielectric layer and a conductive path layer in the third region in a direction away from the substrate includes: forming a semiconductor layer on the first surface of the substrate, and forming a third doping source layer at a position of the semiconductor layer corresponding to the third region; heating and advancing the third doping source layer so that the portion of the semiconductor layer corresponding to the third region forms the stacked dielectric layer and the conductive path layer in sequence in a direction away from the substrate.

[0029] Optionally, the method for forming a first doped layer on the surface of the first region or in the surface of the first region includes: forming a semiconductor layer on the first surface of the substrate, and forming a first doping source layer at a position of the semiconductor layer corresponding to the first region; heating and advancing the first doping source layer so that the portion of the semiconductor layer corresponding to the first region forms a first single doped layer; forming a fourth doping source layer on the first single doped layer; heating and advancing the fourth doping source layer so that the first single doped layer forms a first co-doped layer on the side away from the substrate, and the first single doped layer and the first co-doped layer constitute the first doped layer; the method also includes: providing a through groove on the first co-doped layer, embedding a first electrode in the through groove, and connecting it to the first single doped layer or the first region of the substrate, and there is a gap between the first electrode and the inner wall of the through groove.

[0030] In a third aspect, the present application further discloses a photovoltaic module, which includes the solar cell described in the first aspect.

[0031] The present application discloses a solar cell, a method for preparing a solar cell, and a photovoltaic module. The solar cell includes a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the first surface including a first region and a second region spaced apart and a third region located between the first region and the second region; a first doped layer and a second doped layer, the first doped layer being arranged on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer being arranged on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having a polarity opposite to that of the first doped layer; a dielectric layer and a conductive path layer, the dielectric layer and the conductive path layer being sequentially stacked on the third region in a direction away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting a portion of the first doped layer and a portion of the second doped layer.

[0032] The solar cell disclosed in this application includes a substrate, wherein a first surface of the substrate includes a first region and a second region spaced apart from each other, and a third region located between the first and second regions. A first doped layer is disposed on the surface of the first region or is at least partially embedded within the surface of the first region, and a second doped layer is disposed on the surface of the second region or is at least partially embedded within the surface of the second region. The first doped layer and the second doped layer have opposite polarities, so that current generated by the substrate is collected through the first doped layer and the second doped layer.

[0033] Furthermore, the dielectric layer and the conductive path layer are stacked in sequence in the third region in a direction away from the substrate, so as to block the first doped layer and the second doped layer through the dielectric layer. The dielectric layer can also block the substrate and the conductive path layer to avoid short circuits in the solar cell, ensure the normal operation of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.

[0034] Furthermore, the conductive path layer connects a portion of the first doped layer and a portion of the second doped layer. This configuration enables soft breakdown between the first and second doped layers, preventing the hot spot effect when the solar cell is obscured. Furthermore, while preventing the hot spot effect, it also ensures the photovoltaic conversion efficiency of the solar cell under normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A cross-sectional view of the solar cell described in the embodiment of the present application is shown Figure 1 ;

[0036] Figure 2 A cross-sectional view of the solar cell described in the embodiment of the present application is shown Figure 2 ;

[0037] Figure 3 A cross-sectional view of the solar cell described in the embodiment of the present application is shown Figure 3 ;

[0038] Figure 4 A cross-sectional view of a solar cell according to another embodiment of the present invention Figure 1 ;

[0039] Figure 5 A cross-sectional view of a solar cell according to another embodiment of the present invention Figure 2 ;

[0040] Figure 6 A cross-sectional view of a solar cell according to another embodiment of the present invention Figure 3 ;

[0041] Figure 7 A cross-sectional view of a solar cell according to another embodiment of the present invention Figure 4 ;

[0042] Figure 8 A cross-sectional view of a solar cell according to another embodiment of the present invention is shown. Figure 1 ;

[0043] Figure 9 A cross-sectional view of a solar cell according to another embodiment of the present invention is shown. Figure 2 ;

[0044] Figure 10 A cross-sectional view of a solar cell according to another embodiment of the present invention is shown. Figure 3 ;

[0045] Figure 11 A cross-sectional view of a solar cell according to another embodiment of the present invention is shown. Figure 4 ;

[0046] Figure 12 A flow chart showing the method for preparing a solar cell according to an embodiment of the present application.

[0047] Reference numerals:

[0048] 100: base;

[0049] 101: first doped layer; 1011: first single-doped layer; 1012: first co-doped layer; 1012a: through-groove;

[0050] 102: second doped layer; 1021: second single-doped layer; 1022: second co-doped layer;

[0051] 1031: dielectric layer; 1032: conductive path layer; 1032a: single doping path layer; 1032b: co-doped path layer; 1032c: first depth graded co-doped region;

[0052] 104: interface passivation layer;

[0053] 105: surface passivation layer or anti-reflection layer;

[0054] 106: first electrode;

[0055] 107: second electrode;

[0056] 108: Second concentration gradient co-doping region. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of the present invention.

[0058] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0059] Reference Figure 1, showing a cross-sectional view of the solar cell described in the embodiment of the present application Figure 1 ;reference Figure 2 , showing a cross-sectional view of the solar cell described in the embodiment of the present application Figure 2 ;reference Figure 3 , showing a cross-sectional view of the solar cell described in the embodiment of the present application Figure 3 ;reference Figure 4 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 1 ;reference Figure 5 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 2 ;reference Figure 6 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 3 ;reference Figure 7 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 4 ;reference Figure 8 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 1 ;reference Figure 9 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 2 ;reference Figure 10 , showing a cross-sectional view of a solar cell according to another embodiment of the present application Figure 3 ;reference Figure 11 , a cross-sectional view of a solar cell in another embodiment of the present application Figure 4 .

[0060] like Figures 1 to 11 As shown, an embodiment of the present application discloses a solar cell, which includes a substrate 100, the substrate 100 having a first surface and a second surface arranged opposite to each other, the first surface including a first region and a second region spaced apart and a third region located between the first region and the second region; a first doped layer 101 and a second doped layer 102, the first doped layer 101 being arranged on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer 102 being arranged on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer 102 having an opposite polarity to the first doped layer 101; a dielectric layer 1031 and a conductive path layer 1032, the dielectric layer 1031 and the conductive path layer 1032 being sequentially stacked in the third region in a direction away from the substrate 100, the dielectric layer 1031 blocking the first doped layer 101 and the second doped layer 102, and the conductive path layer 1032 connecting a portion of the first doped layer 101 and a portion of the second doped layer 102.

[0061] Solar cells are the core components of photovoltaic modules, which can convert solar energy into electrical energy. Figures 1 to 11As shown, an embodiment of the present application discloses a solar cell, which can be used in a photovoltaic module to avoid the hot spot effect of the solar cell when the photovoltaic module is blocked, thereby affecting the photoelectric conversion efficiency of the photovoltaic module.

[0062] like Figures 1 to 11 As shown, the solar cell disclosed in the embodiment of the present application includes a substrate 100. The substrate 100 is the core component of the solar cell, which can convert solar energy into electrical energy. For example, the substrate 100 can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer. The crystal type can be single crystal, polycrystalline, etc. Of course, the substrate 100 can also be other types of substrates 100. Here, there are no excessive restrictions on the specific type of the substrate 100. In actual applications, technicians can select a suitable material as the substrate 100 as needed.

[0063] The substrate 100 in the embodiment of the present application has a first surface and a second surface disposed opposite to each other, wherein the first surface is the back side of the cell and the second surface is the front side of the cell. In other words, the solar cell disclosed in the embodiment of the present application is a back-contact solar cell.

[0064] like Figures 1 to 11 As shown, the first surface of the substrate 100 includes a first region and a second region spaced apart from each other, and a third region located between the first and second regions. A first doping layer 101 is disposed on the surface of the first region or at least partially embedded in the surface of the first region, and a second doping layer 102 is disposed on the surface of the second region or at least partially embedded in the surface of the second region. The second doping layer 102 has an opposite polarity to that of the first doping layer 101, so that the current generated by the substrate 100 can be collected through the first doping layer 101 and the second doping layer 102.

[0065] It should be noted that both the first doped layer 101 and the second doped layer 102 may be one or more of polycrystalline silicon, amorphous silicon, microcrystalline silicon, and single crystal silicon. When the first doped layer 101 is a P-type doped layer, the second doped layer 102 is an N-type doped layer. When the first doped layer 101 is an N-type doped layer, the second doped layer 102 is a P-type doped layer. P-type is generally doped with Group IIIA elements, and N-type is generally doped with Group VA elements.

[0066] like Figures 1 to 11As shown, the dielectric layer 1031 and the conductive path layer 1032 are stacked sequentially in the third region in a direction away from the substrate 100. The dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102. The dielectric layer 1031 can also block the substrate 100 and the conductive path layer 1032, thereby preventing short circuits in the solar cell, ensuring normal operation of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0067] It should be noted that the dielectric layer 1031 in the embodiment of the present application includes a semiconductor layer and / or an insulating layer. When the dielectric layer 1031 includes a semiconductor layer and an insulating layer, the insulating layer and the semiconductor layer are sequentially stacked on the surface of the third region in a direction away from the substrate 100. The conductive path layer 1032 is stacked on the side of the semiconductor layer away from the insulating layer. The semiconductor layer includes an intrinsic semiconductor layer and an electrically neutral co-doped semiconductor layer, wherein the intrinsic semiconductor layer includes at least one of intrinsic amorphous silicon, intrinsic polycrystalline silicon, intrinsic single crystal silicon, etc. An electrically neutral co-doped semiconductor layer refers to a semiconductor layer having an element doping concentration not exceeding 1E18cm - ³, a co-doped semiconductor layer that exhibits absolute electrical neutrality, weak positive charge, or weak negative charge. For example, the co-doped semiconductor layer that exhibits electrical neutrality is a polycrystalline silicon layer that is doped with phosphorus and boron elements.

[0068] like Figures 1 to 11 As shown, in the embodiment of the present application, a conductive path layer 1032 is stacked on the side of the dielectric layer 1031 away from the substrate 100. The conductive path layer 1032 connects part of the first doped layer 101 and part of the second doped layer 102, and conducts electricity between the first doped layer 101 and the second doped layer 102 through the conductive path layer 1032. The provision of the conductive path layer 1032 can achieve soft breakdown of the first doped layer 101 and the second doped layer 102, avoiding the hot spot effect when the solar cell is blocked. Moreover, the above-mentioned provision can also ensure the photoelectric conversion efficiency of the solar cell under normal operation while taking into account the hot spot effect.

[0069] Optionally, along the thickness direction of the cell, the thickness of the dielectric layer 1031 is greater than the thickness of the conductive path layer 1032 .

[0070] In the embodiment of the present application, along the thickness direction of the solar cell, the thickness of the dielectric layer 1031 is set to be greater than the thickness of the conductive path layer 1032. This setting makes the dielectric layer 1031 thicker, and the dielectric layer 1031 can ensure electrical isolation between the first doped layer 101 and the second doped layer 102, as well as electrical isolation between the substrate 100 and the conductive path layer 1032, thereby achieving higher photoelectric conversion efficiency when the solar cell is in normal working condition.

[0071] The conductive path layer 1032 in the embodiment of the present application is thinner than the dielectric layer 1031. The conductive path layer 1032 enables soft breakdown between the first doped layer 101 and the second doped layer 102. When the solar cell is blocked, the conductive path layer 1032 can prevent hot spot effects on the solar cell.

[0072] Furthermore, the above-mentioned arrangement can provide a dielectric layer 1031 between the first doped layer 101 and the second doped layer 102 over the entire area of the solar cell, thereby achieving heat spot prevention over the entire area, thereby eliminating the steps and processes for preparing other spacer grooves, making the preparation process of the solar cell simpler and reducing the production cost of the solar cell.

[0073] Optionally, along the thickness direction of the cell, the thickness of the conductive path layer 1032 is greater than the thickness of the dielectric layer 1031 .

[0074] In the embodiment of the present application, the thickness of the conductive path layer 1032 is set to be greater than the thickness of the dielectric layer 1031 along the thickness direction of the cell. This increases the conductive path, and only a small number of anti-hot spot structures are required over the entire cell area to achieve the anti-hot spot effect for the entire cell.

[0075] Specifically, the dielectric layer 1031 and the conductive path layer 1032 can be stacked in sequence on the entire area of at least one third region of the first surface of the substrate 100, or the dielectric layer 1031 and the conductive path layer 1032 can be stacked in sequence on at least a portion of the area of at least one third region of the first surface of the substrate 100.

[0076] It should be noted that the positions of the different conductive path layers 1032 located on the plurality of third regions of the first surface of the substrate 100 may correspond to each other or may be staggered. This application does not impose any specific limitation on this. In actual applications, technicians may configure it as needed.

[0077] Optionally, the dielectric layer 1031 and the conductive path layer 1032 are made of the same base material.

[0078] In the embodiments of the present application, the dielectric layer 1031 and the conductive path layer 1032 are made of the same base material. For example, both the dielectric layer 1031 and the conductive path layer 1032 comprise polysilicon, with doped polysilicon forming the conductive path layer 1032 and undoped polysilicon forming the dielectric layer 1031. Undoped polysilicon may also be referred to as intrinsic polysilicon. Of course, the above specific embodiments are merely examples of the present application and are not intended to limit the present application. In actual applications, technicians may configure the base materials of the dielectric layer 1031 and the conductive path layer 1032 as needed.

[0079] It should be noted that the base materials of the dielectric layer 1031 and the conductive path layer 1032 in the embodiment of the present application are also the same as the base materials of the first doping layer 101 and the second doping layer 102. This arrangement simplifies the cell manufacturing process, namely the cell patterning process, by depositing semiconductor film layers once and then doping them to varying degrees to form the above structure.

[0080] Optionally, the dielectric layer 1031 and the conductive path layer 1032 are made of different base materials.

[0081] The dielectric layer 1031 and the conductive path layer 1032 in the embodiment of the present application may also be made of different base materials. The dielectric layer 1031 may also be an insulating layer. For example, the dielectric layer 1031 may be at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a silicon carbide layer, an intrinsic amorphous silicon layer, an intrinsic polycrystalline silicon layer, an intrinsic single crystal silicon layer, etc. The conductive path layer 1032 may be at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped single crystal silicon layer, etc.

[0082] Optionally, the conductive path layer 1032 is doped with one element; and / or the conductive path layer 1032 is doped with two elements with opposite polarities.

[0083] In the embodiments of the present application, the conductive path layer 1032 may be doped with a single element to enhance its conductivity, achieve soft breakdown of the first doped layer 101 and the second doped layer 102, and prevent hot spot effects when the solar cell is obscured. For example, the conductive path layer 1032 may be doped with only boron, or with only phosphorus.

[0084] Of course, the conductive path layer 1032 can also be doped with two elements of opposite polarity to simplify the cell manufacturing process, facilitate cell manufacturing, and reduce cell manufacturing costs. For example, the conductive path layer 1032 is doped with both boron and phosphorus.

[0085] It should be noted that, when one element is doped into the conductive path layer 1032 , the concentration of the doped element in the conductive path layer 1032 decreases gradually along the direction from the conductive path layer 1032 to the substrate 100 .

[0086] Alternatively, as Figure 2As shown, the conductive path layer 1032 in the embodiment of the present application includes a single-doped path layer 1032a and a co-doped path layer 1032b, wherein the single-doped path layer 1032a is stacked on the side of the dielectric layer 1031 away from the substrate 100, and the co-doped path layer 1032b is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031; the single-doped path layer 1032a is doped with one element, and the co-doped path layer 1032b is doped with two elements with opposite polarities.

[0087] like Figure 2 As shown, in the embodiment of the present application, the conductive path layer 1032 is provided as two layers, one of which is a single-doped path layer 1032a. The single-doped path layer 1032a is stacked on the side of the dielectric layer 1031 away from the substrate 100, and the single-doped path layer 1032a is doped with a single element. The other layer is a co-doped path layer 1032b. The co-doped path layer 1032b is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031, and the co-doped path layer 1032b is doped with two elements of opposite polarity. One of the two elements is the same as the doping element in the single-doped path layer 1032a.

[0088] The above configuration reduces the manufacturing complexity of the cell, simplifies the cell production process, and reduces cell production costs. Furthermore, the above configuration prevents the hot spot effect that occurs when the cell is obscured. Furthermore, while simultaneously preventing the hot spot effect, it also ensures the photoelectric conversion efficiency of the cell under normal operation.

[0089] Optionally, the single-doped path layer 1032 a and the co-doped path layer 1032 b have the same conductivity type.

[0090] In the embodiment of the present application, the conductivity type of the single doping path layer 1032a is set to be the same as the conductivity type of the co-doping path layer 1032b, so that the soft breakdown interface between the first doping layer 101 and the second doping layer 102 is more uniform and the anti-hot spot effect is better.

[0091] Furthermore, setting the conductivity type of the single-doped path layer 1032a to be the same as the conductivity type of the co-doped path layer 1032b can also prevent the soft breakdown layer from being too thick, thereby causing efficiency loss of the cell.

[0092] Optionally, the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the first doping layer 101 ; and / or the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the second doping layer 102 .

[0093] In the embodiment of the present application, the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the first doping layer 101. And / or, the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the second doping layer 102.

[0094] Through the above configuration, the doping concentration of the surface elements of the conductive path layer 1032 can be controlled, so that the conductive path layer 1032 can be made thinner, thereby improving the anti-hot spot effect of the cell and ensuring the photoelectric conversion efficiency of the cell.

[0095] Optionally, along the thickness direction of the cell, the thickness of the conductive path layer 1032 is d1, which satisfies 10nm≤d1≤120nm; and / or the element doping concentration of the conductive path layer 1032 is greater than 1E18cm - ³ and less than 5E22cm - ³.

[0096] In the embodiment of the present application, the thickness of the conductive path layer 1032 is set to d1 along the thickness direction of the cell. Here, d1 is greater than or equal to 10 nm and less than or equal to 120 nm. By setting the thickness of the conductive path layer 1032, the conductive path layer 1032 is relatively thin, thereby ensuring a soft breakdown effect on the cell.

[0097] For example, along the thickness direction of the battery cell, the thickness of the conductive path layer 1032 can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0098] In the embodiment of the present application, the doping concentration of the elements in the conductive path layer 1032 is greater than or equal to 1E18 cm - ³ and less than 5E22cm - By setting the doping concentration of the element in the conductive path layer 1032 to be greater than or equal to 1E18cm - ³ and less than 5E22cm - ³, so that the conductive path layer 1032 can conduct electricity and achieve a soft breakdown effect of the battery cell.

[0099] For example, the element doping concentration in the conductive path layer 1032 may be 1E18 cm - ³、1E20cm - ³、2E18cm - ³、3E18cm - ³、4E18cm - ³、5E18cm - ³、5E22cm -³ etc.

[0100] Optionally, the element doping concentration of the dielectric layer 1031 is less than 1E13 cm - ³; and / or, along the thickness direction of the battery cell, the thickness of the dielectric layer 1031 is d2, satisfying 20nm≤d2≤490nm.

[0101] In the embodiment of the present application, the doping concentration of the elements in the dielectric layer 1031 is set to be less than 1E13 cm - ³, so that the dielectric layer 1031 has insulating properties. The dielectric layer 1031 can block the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and between the substrate 100 and the conductive path layer 1032.

[0102] For example, the doping concentration of the element in the dielectric layer 1031 may be 1E12 cm - ³、1E11cm - ³、1E10cm - ³、1E9cm - ³ etc.

[0103] In the embodiment of the present application, the thickness of the dielectric layer 1031 is set to d2 along the thickness direction of the cell, where d2 is greater than or equal to 20 nm and less than or equal to 490 nm. The dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and between the substrate 100 and the conductive path layer 1032.

[0104] For example, along the thickness direction of the cell, the thickness of the dielectric layer 1031 may be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 490 nm, etc.

[0105] Optionally, the substrate 100 corresponding to the third region has a third doping region, and the element doping concentration of the third doping region is less than 1E13 cm - ³.

[0106] In the embodiment of the present application, the substrate 100 has a third doping region at a position corresponding to the third region, and the doping concentration of the element in the third doping region is set to be less than 1E13 cm -A dielectric layer 1031 is provided between the conductive path layer 1032 and the third doped region of the substrate 100. The dielectric layer 1031 can block the conductive path layer 1032 from the third doped region of the substrate 100, preventing the doping elements in the conductive path layer 1032 from diffusing into the third doped region of the substrate 100, thereby ensuring a higher photoelectric conversion efficiency when the cell is operating normally.

[0107] For example, the doping concentration of the element in the third doping region of the substrate 100 may be 1E12 cm - ³、1E11cm - ³、1E10cm - ³、1E9cm - ³、1E8cm - ³ etc.

[0108] Optionally, the substrate 100 corresponding to the first region has a first doping region, and the element doping concentration of the first doping region is greater than 1E13 cm - ³; and / or, the substrate 100 corresponding to the second region has a second doped region, and the element doping concentration of the second doped region is greater than 1E13cm - ³.

[0109] In the embodiment of the present application, the substrate 100 has a first doping region at a position corresponding to the first region, a second doping region at a position corresponding to the second region, and a third doping region located between the first doping region and the second doping region.

[0110] In the embodiment of the present application, the doping concentration of the element in the first doping region is set to be greater than 1E13 cm - ³, and / or, setting the doping concentration of the element in the second doping region to be greater than 1E13cm - Furthermore, the first doped region and the second doped region have different inward expansion depths in the substrate 100. Through the above arrangement, the solid solubility of different doping elements is matched, enabling effective doping of the first doped layer 101 and the second doped layer 102 and sufficient carrier separation.

[0111] For example, taking the doping elements as boron and phosphorus, the internal diffusion depth of boron in the substrate 100 is deeper, while the internal diffusion depth of phosphorus in the substrate 100 is relatively shallow. In this application, the internal diffusion depth of boron is E17 cm - ³ Cut-off, the depth of phosphorus expansion is E18 cm - ³ Deadline.

[0112] Alternatively, as Figure 6 、 Figure 7 、 Figures 9 to 11As shown, the first doped layer 101 in the embodiment of the present application includes a first single-doped layer 1011 and a first co-doped layer 1012, wherein the first co-doped layer 1012 is doped with two elements of opposite polarities, wherein the first single-doped layer 1011 is superimposed on the surface of the first region or at least partially embedded in the surface of the first region, and the first co-doped layer 1012 is superimposed on the side of the first single-doped layer 1011 away from the substrate 100, and the first co-doped layer 1012 has a conductivity type opposite to that of the first single-doped layer 1011; the solar cell further includes a first electrode 106, which is coupled to the first region of the substrate 100, and the first co-doped layer 1012 is provided with a through-groove 1012a, the first electrode 106 is embedded in the through-groove 1012a and connected to the first single-doped layer 1011 or the first region of the substrate 100, and a gap is formed between the first electrode 106 and the inner wall of the through-groove 1012a.

[0113] like Figure 6 、 Figure 7 、 Figures 9 to 11 As shown, in the embodiment of the present application, the first doped layer 101 is provided as two layers, one of which is a first single-doped layer 1011, and the other is a first co-doped layer 1012, and the first single-doped layer 1011 and the first co-doped layer 1012 have opposite conductivity types. The first single-doped layer 1011 is doped with one element, and the first single-doped layer 1011 is superimposed on the surface of the first region or at least partially embedded in the surface of the first region. The first co-doped layer 1012 is doped with two elements of opposite polarity, and the first co-doped layer 1012 is superimposed on the side of the first single-doped layer 1011 away from the substrate 100. Through the above-mentioned arrangement, the process difficulty of the battery cell can be reduced, the process flow of the battery cell can be simplified, and the manufacturing cost of the battery cell can be reduced.

[0114] The cell disclosed in the embodiment of the present application further includes a first electrode 106, which is coupled to the first region of the substrate 100 to collect carriers generated in the first region of the substrate 100. Specifically, Figure 4 As shown, the first electrode 106 can be embedded in the surface passivation layer or the anti-reflection layer 105 and connected to the first co-doped layer 1012. Figure 5 As shown, the first electrode 106 can also be embedded in the surface passivation layer or anti-reflection layer 105 and the first co-doped layer 1012, and one end of the first electrode 106 is connected to the position of the first single-doped layer 1011 corresponding to the first region. Figure 6 As shown, the first electrode 106 can also be embedded in the surface passivation layer or anti-reflection layer 105, the first co-doped layer 1012 and the first single-doped layer 1011, and one end of the first electrode 106 is connected to the tunneling passivation layer or the surface of the first region of the substrate 100. Through the above arrangement, the first electrode 106 can collect carriers generated in the first region of the substrate 100.

[0115] like Figures 9 to 11 As shown, in an embodiment of the present application, a through groove 1012a can also be provided on the first co-doped layer 1012, and one end of the first electrode 106 is connected to the position corresponding to the first region of the first single-doped layer 1011 through the through groove 1012a, or one end of the first electrode 106 is directly connected to the surface of the first region of the tunnel passivation layer or the substrate 100, and there is a gap between the side wall of the first electrode 106 and the inner wall of the through groove 1012a to reduce the risk of leakage of the battery cell and improve the photoelectric conversion efficiency of the battery cell.

[0116] It should be noted that the configuration of the second electrode 107 in the embodiment of the present application is similar to that of the first electrode 106 , and will not be described in detail herein.

[0117] Optionally, the uniformity of the element doping concentration in the first single-doped layer 1011 is better than the uniformity of the element doping concentration in the first co-doped layer 1012 .

[0118] In the embodiment of the present application, the first single-doped layer 1011 is of the first conductivity type, and the first co-doped layer 1012 is of the second conductivity type. For example, the relevant description is provided. It can be understood that only one type of element is doped in the first single-doped layer 1011, while the first co-doped layer 1012 is doped with both the first element and the second type of element. Among them, the first type of element can be a IIIA group element, such as boron, aluminum, gallium, etc. The second type of element can be a VA group element, such as phosphorus, antimony, arsenic, etc. The thickness of the first single-doped layer 1011 is greater than or equal to 20nm and less than or equal to 490nm, and the thickness of the first co-doped layer 1012 is greater than or equal to 10nm and less than or equal to 480nm.

[0119] In the first co-doped layer 1012, the doping concentration of the first element is substantially uniform along the direction away from the substrate 100, with a concentration uniformity of less than 50%. In the first single-doped layer 1011, the doping concentration of the first element is substantially uniform along the direction away from the substrate 100, with a concentration uniformity of less than 20%. The doping concentration of the first element in the first co-doped layer 1012 and the first single-doped layer 1011 is substantially uniform.

[0120] It should be noted that the uniformity of concentration in the embodiment of the present application = (maximum concentration - minimum concentration) / (maximum concentration + minimum concentration).

[0121] For example, in the embodiment of the present application, in the first single doped layer 1011, the doping concentration of one type of element is in the range of 1E16cm - ³ to 1E21 cm - In the first co-doped layer 1012, the doping concentration of one type of element is in the range of 1E16 cm -³ to 1E21 cm - ³, the doping concentration range of the second type elements is 1E17 cm - ³ to 1E22 cm - ³.

[0122] In the same area, the doping concentration of boron at different depths in the first single-doped layer 1011 is tested. In the first single-doped layer 1011, the doping concentration of boron near the substrate 100 is 6E19 cm - ³, away from the substrate 100, the boron doping concentration is 7E19 cm - ³, the concentration is = (7-6) / (7+6) = 7.7%, less than 20%.

[0123] In the same area, the doping concentration of boron at different depths in the first co-doped layer 1012 is tested. In the first co-doped layer 1012, the doping concentration of boron near the substrate 100 is 7E19 cm - ³, away from the substrate 100, the doping concentration of boron is 3E19 cm - ³, the concentration is = (7-3) / (7+3) = 40%, which is less than 50%.

[0124] In the embodiment of the present application, the uniformity of the element doping concentration in the first single-doped layer 1011 is set to be superior to the uniformity of the element doping concentration in the first co-doped layer 1012. This setting ensures the carrier separation efficiency in the first single-doped layer 1011. Furthermore, this setting ensures that the first single-doped layer 1011 does not affect the passivation effect of the substrate 100.

[0125] Alternatively, as Figures 8 to 11 As shown, the second doped layer 102 in the embodiment of the present application includes a second single-doped layer 1021 and a second co-doped layer 1022. The second co-doped layer 1022 is doped with two elements with opposite polarities. The second single-doped layer 1021 is superimposed on the surface of the second region or at least partially embedded in the surface of the second region. The second co-doped layer 1022 is superimposed on the side of the second single-doped layer 1021 away from the substrate 100. The second co-doped layer 1022 and the second single-doped layer 1021 have the same conductivity type.

[0126] like Figures 8 to 11 As shown, the second doped layer 102 in the embodiment of the present application includes two layers, one of which is a second single-doped layer 1021, in which a single element is doped. The other layer is a second co-doped layer 1022, in which two elements with opposite polarities are doped. The second single-doped layer 1021 and the second co-doped layer 1022 have the same conductivity type.

[0127] like Figures 8 to 11 As shown, the second single-doped layer 1021 is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer 1022 is stacked on the side of the second single-doped layer 1021 away from the substrate 100. Through the above arrangement, the manufacturing difficulty of the battery cell can be reduced, the process flow of the battery cell can be simplified, and the manufacturing cost of the battery cell can be reduced.

[0128] It should be noted that, in the embodiment of the present application, regardless of whether the second single-doped layer 1021 and the second co-doped layer 1022 have the same conductivity type or different conductivity types, the second electrode 107 can be in contact with the second single-doped layer 1021 alone or with the second co-doped layer 1022 alone. Of course, the second electrode 107 can also be in contact with the second single-doped layer 1021 and the second co-doped layer 1022 at the same time. When the second electrode 107 is in contact with the second single-doped layer 1021 and the second co-doped layer 1022 at the same time, the contact formed is better and the reliability of the solar cell is higher.

[0129] Optionally, along the thickness direction of the cell, the thickness of the second co-doped layer 1022 is greater than the thickness of the first co-doped layer 1012 , and the thickness of the first co-doped layer 1012 is greater than or equal to the thickness of the co-doped path layer 1032 b .

[0130] Along the thickness direction of the cell, the thickness of the co-doped path layer 1032b cannot be too thick. This is to ensure the anti-hot spot effect of the cell and the photoelectric conversion efficiency of the cell. The second co-doped layer 1022 will not affect the conductivity type of the second doped layer 102. Therefore, the thickness of the second co-doped layer 1022 can be thicker. The thickness of the first co-doped layer 1012 cannot be too thick. If the thickness of the first co-doped layer 1012 is too thick, it will affect the carrier collection efficiency in the first region. Of course, the thickness of the first co-doped layer 1012 cannot be too thin. If the thickness of the first co-doped layer 1012 is too thin, it will increase the process steps of the cell and require separate processing to form the co-doped path layer 1032b, increasing the manufacturing cost of the cell.

[0131] Based on the above, in the embodiment of the present application, along the thickness direction of the battery cell, the thickness of the second co-doped layer 1022 is set to be greater than the thickness of the first co-doped layer 1012, and the thickness of the first co-doped layer 1012 is set to be greater than or equal to the thickness of the co-doped path layer 1032b.

[0132] Alternatively, as Figure 3 As shown, in the embodiment of the present application, the first doping layer 101 has a first concentration gradient co-doping region (not shown in the figure) on one side close to the conductive path layer 1032; and / or, the second doping layer 102 has a second concentration gradient co-doping region 108 on one side close to the conductive path layer 1032.

[0133] like Figure 3As shown, the region within the first doped layer 101 near the first electrode 106 has a higher doping concentration, facilitating carrier collection and current transmission and collection. In particular, the region below the first electrode 106 within the first doped layer 101 has a higher doping concentration, effectively reducing the metal-semiconductor contact resistance. Conversely, the side of the first doped layer 101 near the conductive path layer 1032 has a lower doping concentration, facilitating Auger recombination and thereby improving the cell's photoelectric conversion efficiency.

[0134] Based on the above, in the embodiment of the present application, a first concentration gradient co-doping region is provided on the side of the first doping layer 101 close to the conductive path layer 1032, and / or a second concentration gradient co-doping region 108 is provided on the side of the second doping layer 102 close to the conductive path layer 1032. This improves the current collection efficiency of the cell and the photoelectric conversion efficiency of the cell.

[0135] Optionally, when the first doping layer 101 is a P-type doping layer and the second doping layer 102 is an N-type doping layer, the width of the first graded concentration co-doping region is greater than the width of the second graded concentration co-doping region 108 .

[0136] When the first doping layer 101 is a P-type doping layer, that is, the first doping layer 101 is doped with boron, and the second doping layer 102 is an N-type doping layer, that is, the second doping layer 102 is doped with phosphorus, the width of the first concentration gradient co-doping region is greater than the width of the second concentration gradient co-doping region 108.

[0137] The above arrangement can improve the carrier transfer efficiency, as well as the current transmission and collection efficiency, without increasing the process difficulty, and reduce the metal-semiconductor contact.

[0138] Of course, the above-mentioned method of setting the first doping layer 101 as a P-type doping layer and the second doping layer 102 as an N-type doping layer is only an individual example of the present application and does not limit the present application. In actual applications, technicians can set the specific doping types of the first doping layer 101 and the second doping layer 102 as needed.

[0139] Optionally, the conductive path layer 1032 has a first depth-gradient co-doped region 1032 c on one side close to the first doping layer 101 , and has a second depth-gradient co-doped region (not shown) on one side close to the second doping layer 102 .

[0140] In the embodiment of the present application, a first deeply graded co-doped region 1032c is provided on the side of the conductive path layer 1032 near the first doped layer 101, and a second deeply graded co-doped region is provided on the side of the conductive path layer 1032 near the second doped layer 102. This increases the depth of the soft breakdown path and reduces the excessive concentration of heat-generating currents in the first doped layer 101 and the second doped layer 102. Furthermore, the temperature of a single soft breakdown point can be reduced, mitigating safety risks.

[0141] A heat generation test was conducted on the solar cells disclosed in the examples of this application. The heat generation test standard was to apply a reverse bias voltage of 15V for 100ms and measure the temperature difference between the front and back of the cell. The highest temperature change after the current was applied was measured as ΔT / °C. The heat generation test results are shown in Table 1 below.

[0142] It should be noted that, in the comparative example, the solar cell is only separated by a space between the first doping layer 101 and the second doping layer 102, and no conductive path layer 1032 and dielectric layer 1031 are provided. Figures 1 to 3 As shown, the solar cell includes a first doping layer 101 and a second doping layer 102 connected via a dielectric layer 1031 and a conductive path layer 1032. Figures 4 to 7 As shown, the solar cell includes a first doped layer 101 and a second doped layer 102 connected via a dielectric layer 1031 and a conductive path layer 1032. The first doped layer 101 includes a first single doped layer 1011 and a first co-doped layer 1012. Figures 8 to 11 As shown, the solar cell includes a first doped layer 101 and a second doped layer 102 connected via a dielectric layer 1031 and a conductive path layer 1032. The first doped layer 101 includes a first single-doped layer 1011 and a first co-doped layer 1012, and the second doped layer 102 includes a second single-doped layer 1021 and a second co-doped layer 1022.

[0143] Table 1 Solar cell heating test results

[0144]

[0145] The test results in Table 1 show that compared to the solar cells disclosed in the comparative example, the solar cells disclosed in Examples 1, 2, and 3 of the present application exhibited lower hot spot test temperatures, a lower proportion of cells exceeding 3°C, and superior hot spot protection. The solar cells with co-doped layers disclosed in Examples 2 and 3 exhibited slightly improved photoelectric conversion efficiency.

[0146] Reference Figure 12 , which shows a flow chart of the battery cell preparation method described in the embodiment of the present application.

[0147] like Figure 12 As shown, the embodiment of the present application discloses a method for preparing a battery cell, which includes:

[0148] 201. Provide a substrate, wherein the substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a first region and a second region spaced apart from each other and a third region located between the first region and the second region.

[0149] The substrate in the embodiments of the present application is a core component of a solar cell that can convert solar energy into electrical energy. For example, the substrate can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer. The crystal type can be single crystal, polycrystalline, etc. Of course, the substrate can also be other types of substrates. Here, there are no excessive restrictions on the specific type of the substrate. In actual applications, technicians can select a suitable material as the substrate as needed.

[0150] It should be noted that in the embodiments of the present application, the substrate needs to be surface treated before providing it. Surface treatment includes steps such as damage removal, stain removal, polishing, and texturing. The substrate in the embodiments of the present application has a first surface and a second surface disposed opposite each other, wherein the first surface is the back surface of the battery cell and the second surface is the front surface of the battery cell.

[0151] That is, the solar cell disclosed in the embodiment of the present application is a back-contact solar cell, wherein the first surface of the substrate has a first region and a second region spaced apart and a third region located between the first region and the second region.

[0152] 202 , forming a first doping layer on the surface of the first region or in the surface of the first region, and forming a second doping layer on the surface of the second region or in the surface of the second region, wherein the polarities of the first doping layer and the second doping layer are opposite.

[0153] It should be noted that both the first doped layer 101 and the second doped layer 102 may be one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. When the first doped layer 101 is a P-type doped layer, the second doped layer 102 is an N-type doped layer. When the first doped layer 101 is an N-type doped layer, the second doped layer 102 is a P-type doped layer. P-type is generally doped with Group IIIA elements, and N-type is generally doped with Group VA elements.

[0154] In the embodiments of the present application, there is no specific limitation on the order in which the first doping layer 101 and the second doping layer 102 are formed. The first doping layer 101 can be formed first, followed by the second doping layer 102. Alternatively, the second doping layer 102 can be formed first, followed by the first doping layer 101. In practical applications, technicians can make this choice as needed.

[0155] Specifically, the method of forming the first doping layer on the surface of the first region or within the surface of the first region and forming the second doping layer on the surface of the second region or within the surface of the second region includes: forming a semiconductor layer on the first surface of the substrate, forming a first doping source layer and a second doping source layer at positions of the semiconductor layer corresponding to the first region and the second region, respectively. Heating and advancing the first doping source layer and the second doping source layer so that the portion of the semiconductor layer corresponding to the first region forms the first doping layer, and the portion of the semiconductor layer corresponding to the second region forms the second doping layer, and the polarities of the first doping layer and the second doping layer are opposite.

[0156] It should be noted that in the embodiments of the present application, laser heating can be used to dope elements into the first doping source layer and the second doping source layer to form the first doping layer and the second doping layer. Of course, the above laser heating is only an example of an embodiment of the present application and does not limit the present application. In actual applications, technicians can select an appropriate doping method as needed.

[0157] In the embodiments of the present application, there are no specific limitations on the specific order of forming the first doping source layer and the second doping source layer, as well as the order in which the first doping source layer and the second doping source layer are heated. For example, in the embodiments of the present application, the first doping source layer can be formed first, then heated to advance the first doping source layer, and then the second doping source layer can be formed, and then heated to advance the second doping source layer. Alternatively, the second doping source layer can be formed first, then the first doping source layer can be formed, and then the first and second doping source layers can be heated in sequence.

[0158] It should be noted that in the embodiment of the present application, before forming the semiconductor layer on the first surface of the substrate, an interface passivation layer 104 can be formed on the first surface of the substrate to protect the substrate. The interface passivation layer 104 in the embodiment of the present application can be a single-layer structure or a multi-layer structure. The interface passivation layer 104 includes one or more of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, a silicon carbide layer, and an amorphous silicon layer.

[0159] Specifically, the method of forming the first doping layer on the surface of the first region or in the surface of the first region includes:

[0160] A semiconductor layer is formed on a first surface of a substrate, and a first doping source layer is formed at a position of the semiconductor layer corresponding to the first region; the first doping source layer is heated and advanced so that the portion of the semiconductor layer corresponding to the first region forms a first single-doped layer; a fourth doping source layer is formed on the first single-doped layer; the fourth doping source layer is heated and advanced so that the first single-doped layer forms a first co-doped layer on a side away from the substrate, the first single-doped layer and the first co-doped layer constituting the first doping layer. In this application, the fourth doping source layer and the second doping source layer may be the same layer.

[0161] By preparing the first doped layer in the above manner, the first doped layer includes a first single-doped layer and a first co-doped layer, which can reduce the process difficulty of the battery cell, simplify the process flow of the battery cell, and reduce the manufacturing cost of the battery cell.

[0162] Of course, the above-mentioned method can also be used to form the second doping layer on the surface of the second region or in the surface of the second region, which will not be described in detail here.

[0163] After heating and advancing the fourth doping source layer so that the first single-doped layer forms a first co-doped layer at a portion away from the substrate, the method further includes:

[0164] A through groove is provided on the first co-doped layer, a first electrode is embedded in the through groove and connected to the first single-doped layer or the first region of the substrate, and a gap is provided between the first electrode and the inner wall of the through groove.

[0165] In an embodiment of the present application, a through groove is provided in the first co-doped layer, a first electrode is embedded in the through groove, and one end of the first electrode is connected to the first single-doped layer or the first region of the substrate, so that the carriers generated in the first region of the substrate are collected by the first electrode.

[0166] It should be noted that, in the embodiment of the present application, there is a gap between the side wall of the first electrode and the inner wall of the through groove, so as to reduce the risk of battery cell leakage and improve the photoelectric conversion efficiency of the battery cell.

[0167] 203 , in a direction away from the substrate, sequentially stack a dielectric layer and a conductive path layer in the third region, so that the dielectric layer blocks the first doped layer and the second doped layer, and the conductive path layer connects part of the first doped layer and part of the second doped layer.

[0168] A solar cell is prepared using the method for preparing a solar cell disclosed in the embodiment of the present application. In the direction away from the substrate, the dielectric layer and the conductive path layer are stacked in sequence in the third region to block the first doped layer and the second doped layer through the dielectric layer. The dielectric layer can also block the substrate and the conductive path layer to avoid short circuiting of the solar cell, ensure the normal operation of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.

[0169] Furthermore, by connecting portions of the first doped layer and the second doped layer via the conductive path layer, the conductive path layer can achieve soft breakdown between the first doped layer and the second doped layer, thereby preventing the hot spot effect when the solar cell is blocked. Furthermore, while taking into account the hot spot effect, it can also ensure the photoelectric conversion efficiency of the cell under normal operation.

[0170] Specifically, the method of sequentially stacking a dielectric layer and a conductive path layer in the third region in a direction away from the substrate includes:

[0171] A semiconductor layer is formed on the first surface of the substrate, and a third doping source layer is formed at a position of the semiconductor layer corresponding to the third region; the third doping source layer is heated and advanced so that a portion of the semiconductor layer corresponding to the third region forms a stacked dielectric layer and a conductive path layer in sequence in a direction away from the substrate.

[0172] The method for preparing a cell disclosed in an embodiment of the present application, after forming the first doping layer, the second doping layer, the dielectric layer, and the conductive path layer, further comprises:

[0173] Residual dopant sources on the cell surface are removed and the cell is cleaned. Etching and other surface modification steps are also required. This etching modification process can modify the doping elements in various areas of the surface, removing surfaces with excessively high or low doping concentrations. Surfaces with excessively high doping concentrations can create Auger recombination zones, while surfaces with low doping concentrations hinder subsequent contact between the surface metal and the electrode. These treatments can improve cell performance.

[0174] After sequentially stacking a dielectric layer and a conductive path layer in the third region in a direction away from the substrate, the method further includes:

[0175] A surface passivation layer is formed on a side of the first doped layer, the second doped layer, and the conductive path layer away from the substrate; a first electrode and a second electrode are formed within the surface passivation layer, the first electrode being electrically connected to the first doped layer, and the second electrode being electrically connected to the second doped layer. The first electrode collects carriers within the first doped layer and transmits the current collected by the first doped layer, while the second electrode collects carriers within the second doped layer and transmits the current collected by the second doped layer.

[0176] As a preferred embodiment, during the surface passivation process, a surface passivation layer or anti-reflection layer can be formed simultaneously on the side of the first doped layer away from the substrate, the side of the second doped layer away from the substrate, and the side of the conductive path layer away from the substrate, so that the structures of the surface passivation layers or anti-reflection layers corresponding to the first region, the second region, and the third region are completely identical.

[0177] It should be noted that the surface passivation layer or anti-reflection layer in the embodiments of the present application may be a single-layer structure or a multi-layer structure. The surface passivation layer or anti-reflection layer includes one or more of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, a silicon carbide layer, an amorphous silicon layer, and a transparent conductive oxide layer (TCO). In the process of preparing the surface passivation layer or the anti-reflection layer, atomic layer deposition (ALD), chemical vapor deposition, for example, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), etc., physical vapor deposition, for example, evaporation, sputtering and other methods can be used to prepare the surface passivation layer or the anti-reflection layer.

[0178] For example, in the process of preparing a surface passivation layer or an anti-reflection layer, an aluminum oxide passivation layer can be first prepared by atomic layer deposition (ALD), and then one or more silicon nitride layers can be formed on the aluminum oxide passivation layer by plasma enhanced chemical vapor deposition (PECVD).

[0179] The first electrode and the second electrode in the embodiment of the present application can be made of metals such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc., can be made of metal nitrides such as TiN, can be made of metal carbides such as TiC, or can be made of metal sulfides. In the embodiment of the present application, there are no excessive restrictions on the specific materials of the first electrode and the second electrode. In actual applications, technicians can select appropriate materials as needed.

[0180] The embodiments of the present application further disclose a photovoltaic module, which includes the solar cell described in the above embodiments.

[0181] It should be noted that in the embodiment of the present application, the solar cell included in the photovoltaic module has the same structure as the solar cell described in the above embodiment, and its beneficial effects are also similar, which will not be repeated here.

[0182] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0183] Although alternative embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including alternative embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0184] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity from another, and do not necessarily require or imply any actual relationship or order between these entities. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or terminal device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the article or terminal device comprising the element.

[0185] The technical solutions provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. At the same time, for those skilled in the art, according to the principles and implementation methods of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A solar cell, characterized in that: include: a substrate having a first surface and a second surface opposite to each other, the first surface including a first region and a second region spaced apart from each other and a third region between the first region and the second region; a first doped layer and a second doped layer, wherein the first doped layer is disposed on a surface of the first region or is at least partially embedded in the surface of the first region, and the second doped layer is disposed on a surface of the second region or is at least partially embedded in the surface of the second region, and the second doped layer has an opposite polarity to the first doped layer; a dielectric layer and a conductive path layer, wherein the dielectric layer and the conductive path layer are sequentially stacked on the third region in a direction away from the substrate, the conductive path layer electrically connecting a portion of the first doped layer and a portion of the second doped layer, the conductive path layer being doped with one element, and / or the conductive path layer being doped with two elements of opposite polarities; In a direction away from the substrate, the dielectric layer electrically isolates a portion of the first doped layer and a portion of the second doped layer, and the dielectric layer electrically isolates the substrate and the conductive path layer.

2. The solar cell according to claim 1, wherein: Along the thickness direction of the battery cell, the thickness of the dielectric layer is greater than the thickness of the conductive path layer.

3. The solar cell according to claim 1, wherein: Along the thickness direction of the battery cell, the thickness of the conductive path layer is greater than the thickness of the dielectric layer.

4. The solar cell according to claim 1, wherein: The dielectric layer and the conductive path layer have the same base material; Alternatively, the dielectric layer and the conductive path layer are made of different base materials.

5. The solar cell according to claim 1, wherein: The conductive path layer includes a single doping path layer and a co-doping path layer, wherein, The single doping path layer is stacked on a side of the dielectric layer away from the substrate, and the co-doping path layer is stacked on a side of the single doping path layer away from the dielectric layer; The single doping path layer is doped with one element, and the co-doping path layer is doped with two elements with opposite polarities.

6. The solar cell according to claim 5, characterized in that: The single doping path layer and the co-doping path layer have the same conductivity type.

7. The solar cell according to claim 1, wherein: The surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the first doping layer; And / or, the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the second doping layer.

8. The solar cell according to claim 1, wherein: Along the thickness direction of the battery cell, the thickness of the conductive path layer is d1, which satisfies 10nm≤d1≤120nm; and / or, The element doping concentration of the conductive path layer is greater than 1E18 cm - ³ and less than 5E22cm - ³.

9. The solar cell according to claim 1, wherein: The element doping concentration of the dielectric layer is less than 1E13 cm - ³; And / or, along the thickness direction of the battery cell, the thickness of the dielectric layer is d2, which satisfies 20nm≤d2≤490nm.

10. The solar cell according to claim 1, wherein: The substrate corresponding to the third region has a third doping region, and the element doping concentration of the third doping region is less than 1E13cm - ³.

11. The solar cell according to claim 1, wherein: The substrate corresponding to the first region has a first doping region, and the element doping concentration of the first doping region is greater than 1E13cm - ³; And / or, the substrate corresponding to the second region has a second doping region, and the element doping concentration of the second doping region is greater than 1E13cm - ³.

12. The solar cell according to any one of claims 1 to 11, characterized in that: The first doped layer includes a first single-doped layer and a first co-doped layer, wherein the first co-doped layer is doped with two elements of opposite polarities, wherein: The first single-doped layer is stacked on the surface of the first region or at least partially embedded in the surface of the first region, and the first co-doped layer is stacked on a side of the first single-doped layer away from the substrate, and the first co-doped layer has a conductivity type opposite to that of the first single-doped layer; The solar cell also includes a first electrode, which is coupled to the first region of the substrate. The first co-doped layer is provided with a through-groove. The first electrode is embedded in the through-groove and connected to the first single-doped layer or the first region of the substrate. There is a gap between the first electrode and the inner wall of the through-groove.

13. The solar cell according to claim 12, wherein: The uniformity of the element doping concentration in the first single-doped layer is better than the uniformity of the element doping concentration in the first co-doped layer.

14. The solar cell according to any one of claims 1 to 11, characterized in that: The second doped layer includes a second single-doped layer and a second co-doped layer, wherein the second co-doped layer is doped with two elements of opposite polarities, wherein: The second single-doped layer is stacked on the surface of the second region or at least partially embedded in the surface of the second region, the second co-doped layer is stacked on the side of the second single-doped layer away from the substrate, and the second co-doped layer has the same conductivity type as the second single-doped layer.

15. The solar cell according to claim 14, characterized in that: Along the thickness direction of the cell, the thickness of the second co-doped layer is greater than the thickness of the first co-doped layer, and the thickness of the first co-doped layer is greater than or equal to the thickness of the co-doped path layer.

16. The solar cell according to claim 1, wherein: The first doping layer has a first concentration gradient co-doping region on a side close to the conductive path layer; And / or, a side of the second doping layer close to the conductive path layer has a second concentration gradient co-doping region.

17. The solar cell according to claim 16, wherein: In a case where the first doping layer is a P-type doping layer and the second doping layer is an N-type doping layer, the width of the first gradient concentration co-doping region is greater than the width of the second gradient concentration co-doping region.

18. The solar cell according to claim 1, wherein: A side of the conductive path layer close to the first doping layer has a first depth-gradient co-doping region, and a side of the conductive path layer close to the second doping layer has a second depth-gradient co-doping region.

19. A method for preparing a solar cell, characterized in that: The method comprises: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface including a first area and a second area spaced apart from each other and a third area located between the first area and the second area; forming a first doping layer on the surface of the first region or in the surface of the first region, and forming a second doping layer on the surface of the second region or in the surface of the second region, wherein the first doping layer and the second doping layer have opposite polarities; A dielectric layer and a conductive path layer are sequentially stacked in the third region in a direction away from the substrate, so that a portion of the first doped layer and a portion of the second doped layer are electrically connected through the conductive path layer, a portion of the first doped layer and a portion of the second doped layer are electrically isolated through the dielectric layer, and the substrate and the conductive path layer are electrically isolated through the dielectric layer; The conductive path layer is doped with one element, and / or the conductive path layer is doped with two elements with opposite polarities.

20. The method for preparing a solar cell according to claim 19, wherein: The method of forming a first doping layer on the surface of the first region or in the surface of the first region and forming a second doping layer on the surface of the second region or in the surface of the second region includes: forming a semiconductor layer on the first surface of the substrate, and forming a first doping source layer and a second doping source layer at positions of the semiconductor layer corresponding to the first region and the second region, respectively; The first doping source layer and the second doping source layer are heated and advanced so that the portion of the semiconductor layer corresponding to the first region forms the first doping layer, and the portion of the semiconductor layer corresponding to the second region forms the second doping layer, and the polarities of the first doping layer and the second doping layer are opposite.

21. The method for preparing a solar cell according to claim 19, wherein: The method of sequentially stacking a dielectric layer and a conductive path layer in the third region in a direction away from the substrate includes: forming a semiconductor layer on the first surface of the substrate, and forming a third doping source layer at a position of the semiconductor layer corresponding to the third region; The third doping source layer is heated and advanced, so that the portion of the semiconductor layer corresponding to the third region forms the stacked dielectric layer and the conductive path layer in sequence along a direction away from the substrate.

22. The method for preparing a solar cell according to claim 19, wherein: The method of forming a first doping layer on the surface of the first region or in the surface of the first region includes: forming a semiconductor layer on the first surface of the substrate, and forming a first doping source layer at a position of the semiconductor layer corresponding to the first region; heating and advancing the first doping source layer so that a portion of the semiconductor layer corresponding to the first region forms a first single-doped layer; forming a fourth doping source layer on the first single-doped layer; heating and advancing the fourth doping source layer so that the first single-doped layer forms a first co-doped layer on a side away from the substrate, wherein the first single-doped layer and the first co-doped layer constitute the first doped layer; The method further comprises: A through-groove is provided on the first co-doped layer, a first electrode is embedded in the through-groove and connected to the first single-doped layer or the first region of the substrate, and a gap is provided between the first electrode and the inner wall of the through-groove.

23. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 18.

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