A low-cost spectrum analysis method for 5G communication systems

Abstract

The present invention discloses a low-cost spectrum analysis method for a 5G communication system, belongs to the field of communication technology, and is used in a time division multiplexing TDD mode, and adopts a method of using a direct memory access system DMA to carry a frequency sweeping module, so as to perform spectrum analysis on 5G NR signals at any time node. First, a register is defined for the relevant control of the frequency sweeping module, and then the data obtained by the frequency sweeping module is processed across clock domains and sent to the XILINX IP core DATAMOVER, and then the data is sent to the double rate synchronous dynamic random access memory DDR inside the operating system PS through the high-performance interface HP, and after being read by PS, it is stored in a text file according to the format, and then the spectrum analysis is performed through the mathematical tool MATLAB.

Description

Technical Field

[0001] The present invention relates to a 5G communication system and belongs to the field of communication technology. In a time division multiplexing (TDD) mode, a method in which a direct memory access system DMA is equipped with a frequency scanning module is adopted to perform spectrum analysis on a 5G NR signal at any time node. Background Art

[0002] In 5G communication systems, no matter debugging or locating problems, the help of spectrum analyzers is indispensable, especially when debugging downlinks. However, the cost of spectrum is very high, and using spectrum analyzers often means expensive capital expenditures. Moreover, when equipment has problems on site, due to limited conditions, it is impossible to use spectrum analyzers to solve the problems. Problems can only be located through some conventional methods, which often results in more time consumption and reduced efficiency. Although the capture and analysis of external DDR greatly improves the efficiency of debugging and locating problems, when the equipment is mass-produced, the larger the number, the more capital expenditures the external DDR will bring. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention aims to provide a low-cost spectrum analysis method for a 5G communication system. In the time division duplexing TDD mode, a method of using a direct memory access system DMA equipped with a frequency sweep module is used to perform spectrum analysis on 5G NR signals at any time node.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: a low-cost spectrum analysis method for a 5G communication system, specifically comprising the following steps:

[0005] Step 1: define registers, including sweep enable signal, sweep time node signal, sweep length signal, sweep position selection signal and processing system write address signal;

[0006] Step 2: Process the in-phase data I and quadrature data Q obtained by frequency scanning across clock domains;

[0007] Step 3: When the ready signal in the command channel from PL to PS of the Xilinx IP core DATAMOVER is captured to be high, the sweep length signal and the processing system write address signal are assigned to the data signal and the corresponding valid signal is sent to the DATAMOVER IP;

[0008] Step 4: After waiting for a while, when the ready signal in the data channel from PL to PS of DATAMOVER IP is captured as high level, according to the AXI_STREAM protocol, the IQ data after the cross-clock domain is completed in step 2 is assigned to the data signal, and the data signal, valid bit indication signal, valid signal and last bit indication signal are sent to DATAMOVERIP;

[0009] Step 5: After PL finishes sending the frequency sweep data, the PL write completion signal is set to a high level, and this signal is output to PS as a rising edge interrupt trigger;

[0010] Step 6: When the PS captures the PL write completion signal, it reads data from the double rate synchronous dynamic random access memory DDR of the PS and stores the read data in a text file .txt according to the format;

[0011] Step 7: After the PS finishes reading the data, the PS read completion signal is set to a high level and output to the PL through the register. When the PL captures the PS read completion signal, the next frequency sweep can be performed;

[0012] Step 8. Perform spectrum analysis on the data of the txt file in step 6 through MATLAB.

[0013] The step 1 is specifically as follows: in the frame structure of the subcarrier with a frequency of 30khz, a complete 10msNR wireless frame is composed of 20 time slots, each slot is composed of 14 symbols, and a sweep enable signal is defined. The sweep operation is performed only when this signal is at a high level; a sweep time node signal is defined, and the starting position of the sweep is adjusted by this signal, that is, the start of the sweep from a specific slot or a symbol is determined; a sweep length signal is defined, and the length of the sweep or the number of IQ data points, that is, the duration of the sweep, is adjusted by this signal. A sweep position selection signal is defined to select the position of the sweep data, such as a certain point on the downlink or uplink; a processing system write address signal is defined to determine the specific address of the PS DDR where the sweep data is stored.

[0014] The step 2 is specifically as follows: by calling the asynchronous first-in-first-out memory FIFO, the input clock is a clock with the same clock frequency as the IQ data, the write enable is started with the rising edge of the sweep enable signal, and the duration of the pull-up is determined by configuring the sweep length signal. The data is the IQ data at the specific link position selected according to the sweep position selection signal. The output clock is a clock with a clock frequency of 100Mhz used by the PS. The read enable is started with the rising edge of the write-full signal output by the FIFO, and the duration of the pull-up is determined by configuring the sweep length signal.

[0015] The step three is specifically as follows: in the direction from PL to PS, continuously capture the ready signal of the DATAMOVER IP command channel. When it is captured as a high level, it indicates that the command channel from PL to PS of the DATAMOVER IP is ready. At this time, the relevant length signal can be sent to the DATAMOVER IP. Since the format of the length signal of the command channel is defined by XILINX, it is 72 bits in total, where: [22:0] indicates the transmission byte length, in bytes.

[23] indicates the burst type that supports bursts, where the value 1 indicates that the burst transmission type is INCR, and the data will be stored in the address that increases starting from the starting address, that is, according to the burst length, each time only the starting address of the current burst needs to be written at the first burst.

[30] indicates whether the frame sent this time is the last frame, where the value 1 indicates that the frame sent this time is the last frame. [N+31:32] indicates the starting address sent, where N indicates the address depth of the memory mapping, which should be a multiple of 8, and the remaining unused bits are filled with 0. Assume that the number of sweep points is 8192, and the signal selected by the sweep selection is 16-bit IQ data of two channels, that is, the length of the data to be sent to DATAMOVERIP is 8192, and the data width is 64 bits. According to the format, the length needs to be set to 8192*64bit / 8byte=65536, which is converted to hexadecimal 10000. The address segment written by PL is divided into 3b00_0000~3bff_ffff, and the sweep length signal is assigned to the data signal according to the format, and the value is 72'h3b80000040810000 in hexadecimal. At the same time, the signal indicating that the signal is valid is sent to DATAMOVER IP.

[0016] The step 4 is specifically as follows: after sending a whole frame of data to the command channel of the DATAMOVER IP, give the command channel enough response time, such as 32 units of time or longer, and then capture the ready signal of the data channel. If this signal is at a high level, send the data that has completed the clock domain conversion in step 2 to the DATAMOVER IP. At the same time, the data to be sent needs to be in accordance with the AXI_STREAM protocol. When the receiver is ready to receive the signal, a high-level ready signal is sent to the sender. At the same time, after the sender receives the high-level ready signal from the receiver, the data, data valid indication, data valid bit indication and the last data indication are sent to the receiver, that is, the data, valid bit indication, valid indication and the last data indication are sent to the DATAMOVERIP.

[0017] The step five is specifically as follows: after PL has sent a whole frame of data to DATAMOVER IP, the PL write completion signal is set to a high level and lasts for one unit clock cycle, and at the same time, this signal is output to PS as a rising edge interrupt trigger, indicating that PL has sent a whole frame of data to DATAMOVER IP. At this time, PS can read data from PSDDR.

[0018] The step six is ​​specifically as follows: when the PS captures the rising edge of the PL write completion signal, the PS reads data from the address corresponding to the PS DDR, and stores the read data in the order of I0, Q0, I1 and Q1 from left to right into the text file .txt.

[0019] The step 7 is as follows: when the PS has finished reading a whole frame of data, the PS read completion signal is pulled high, and the signal is output to the PL through the register. When the PL captures the rising edge of the PS read completion signal, the next frequency sweep can be performed. If the frequency sweep is to be performed, step 1 is entered.

[0020] The step eight is specifically as follows: IQ in the data file is separated, and the frequency resolution of the fast Fourier transform FFT function is used, which depends on the sampling rate of the original signal and the length of the signal. The frequency range is usually half of the sampling rate, which is determined by the Nyquist sampling theorem. The spectrum is plotted using the plot function. For the amplitude spectrum, the absolute value is usually taken and divided by half of the number of points to obtain a double-sided spectrum in dB units.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention adopts TDD mode and realizes frequency sweep analysis at any time node and any length by configuring registers related to the frequency sweep function, thereby enhancing the flexibility of the system.

[0023] 2. The present invention changes the IQ data reported by the frequency scanning from the traditional external DDR chip to the DDR provided by the ARM operating system inside the FPGA, thereby reducing the use cost of the equipment.

[0024] 3. The present invention uses the DDR provided by the ARM operating system inside the FPGA to replace the external DDR chip, which reduces the technical difficulty, reduces the labor cost, and shortens the development cycle.

[0025] 4. When performing frequency domain analysis, the present invention does not rely on a frequency domain instrument, but uses MATLAB analysis instead, thereby reducing the debugging cost in the development stage.

[0026] 5. Compared with the traditional frequency sweeping technology using RAM to capture data, the present invention supports taking more points, making the spectrum analysis more precise and accurate, and ensuring the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an interface diagram of the low-cost spectrum analysis method of the present invention.

[0028] Figure 2 It is a flow chart of the low-cost spectrum analysis method of the present invention. DETAILED DESCRIPTION

[0029] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0030] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0031] See also Figure 1 and Figure 2 , this embodiment includes the following steps:

[0032] Step 1, define registers, including sweep enable signal, sweep time node signal, sweep length signal, sweep position selection signal and processing system write address signal. In the frame structure of the subcarrier with a frequency of 30khz, a complete 10msNR wireless frame consists of 20 time slots, each slot consists of 14 symbols. Define the sweep enable signal. When the sweep operation needs to be performed, set this signal to a high level, and at the same time, it is necessary to meet the condition that the PS is not reading the PS DDR at this time; define the sweep time node signal, and use this signal to adjust the starting position of the sweep. According to the position of the 10ms wireless frame header, the position of the specific slot and symbol in a complete frame can be determined by counting 10ms, that is, configure this signal to determine the start of the sweep from a specific slot or a symbol; define the sweep length signal, and use this signal to adjust the length of the sweep or the number of IQ data points, that is, the duration of the sweep. When the sweep is enabled, capture the rising edge of the sweep enable and keep it at a high level. The total number of unit clock cycles is the value of the configured sweep length. Define the sweep position selection signal, which is used to select the sweep data position. In actual use, it is often necessary to combine different link positions and different antennas to debug or locate problems. According to different needs, by configuring the value of this signal, the sweep operation can be performed from the JESD interface of the uplink, the downsampling rate, the channel filter, the gain adjustment, etc., and the sweep operation can also be performed from the JESD interface of the downlink, the upsampling rate, and the channel filter; define the processing system write address signal, which is used to determine the specific address of the PS DDR where the sweep data is stored. At the same time, when the PS reads data from the PSDDR, it is also based on this address.

[0033] Step 2: Process the in-phase data I and orthogonal data Q obtained by frequency scanning across the clock domain. By calling the asynchronous first-in-first-out memory FIFO, it is divided into two directions: writing and reading. At the same time, this FIFO will output a non-full signal. When its value is 1, it means that the write data does not fill the entire FIFO at this time, and the write operation can continue. When its value is 0, it means that the write data has filled the entire FIFO at this time, and the write operation cannot be performed; when the non-empty signal is output, when its value is 0, it means that there is still data in the FIFO that has not been read out at this time, and the data can continue to be read. When its value is 1, it means that the data in the FIFO has been read and the data cannot be read. The value of the read and write depth setting of the FIFO is consistent with the signal of the frequency sweep length. The write data clock input to the FIFO is a clock with the same clock frequency as the IQ data. The write data enable starts with the rising edge of the frequency sweep enable signal and keeps it at a high level. The total number of unit clock cycles that last is the value of the configured frequency sweep length. The write data is the IQ data at the specific link position selected according to the sweep position selection signal. The input read data clock is the 100Mhz clock frequency used by the PS. The read data enable starts with the rising edge of the write full signal output by the FIFO and keeps it at a high level for a total number of unit clock cycles equal to the value of the configured sweep length.

[0034] Step 3: When the ready signal in the command channel from PL to PS of the Xilinx IP core DATAMOVER is captured at a high level, the sweep length signal and the processing system write address signal are assigned to the data signal and the corresponding valid signal is sent to DATAMOVERIP. In the direction from PL to PS, the ready signal of the DATAMOVER IP command channel is continuously captured. When it is captured at a high level, it indicates that the command channel from PL to PS of the DATAMOVER IP is ready. At this time, the relevant length signal can be sent to DATAMOVERIP. Since the format of the length signal of the command channel is defined by XILINX, it is 72 bits in total, where: [22:0] indicates the transmission byte length in bytes.

[23] indicates the burst type that supports bursts, where the value 1 indicates that the burst transmission type is INCR, and the data will be stored in the address that starts with the starting address, that is, according to the burst length, each time only the starting address of the burst needs to be written at the first burst.

[30] indicates whether the frame sent this time is the last frame, where the value 1 indicates that the frame sent this time is the last frame. [N+31:32] indicates the starting address to be sent, where N indicates the address depth of the memory mapping, which should be a multiple of 8, and the remaining unused bits are filled with 0.

[0035] Assume that the number of sweep points is 8192, and the signal selected by the sweep selection is 16-bit IQ data of two channels, that is, the length of the data to be sent to the DATAMOVER IP is 8192, and the data width is 64 bits. According to the format, the length needs to be set to 8192*64bit / 8byte=65536, which is converted to hexadecimal 10000. The value of the write address signal of the processing system determines the address where the sweep data is stored in the PSDDR. For example, if the address segment is 3b00_0000~3bff_ffff, the sweep length signal is assigned to the data signal according to the format, and the value is 72'h3b80000040810000 in hexadecimal. At the same time, the signal indicating that the signal is valid is sent to the DATAMOVER IP.

[0036] Step 4: After waiting for a while, when the ready signal in the data channel from PL to PS of DATAMOVER IP is captured as high level, according to the AXI_STREAM protocol, the IQ data after the cross-clock domain is completed in step 2 is assigned to the data signal, and the data signal, valid bit indication signal, valid signal and last bit indication signal are sent to DATAMOVERIP. After sending a whole frame of data to the command channel of DATAMOVER IP, give the command channel enough response time, such as 32 units of time or longer, in order to give the command channel enough response time to increase the stability of the system, and then capture the ready signal of the data channel. If this signal is high level, send the data that has completed the clock domain transfer in step 2 to DATAMOVER IP. At the same time, the data to be sent needs to be in accordance with the AXI_STREAM protocol. When the receiver is ready to receive the signal, send the sender a continuous high level ready signal. At the same time, after the sender receives the receiver's high level ready signal, send the data, data valid indication, data valid bit indication and last data indication to the receiver, that is, send the data, valid bit indication, valid indication and last data indication to DATAMOVERIP.

[0037] Step 5. When PL finishes sending the frequency sweep data, the PL write completion signal is set to a high level, and this signal is output to PS as a rising edge interrupt trigger. When PL finishes sending a whole frame of data to DATAMOVER IP, the PL write completion signal is set to a high level and lasts for one unit clock cycle, and this signal is output to PS as a rising edge interrupt trigger, indicating that PL has completed sending a whole frame of data to DATAMOVERIP. At this time, PS can read data from PS DDR.

[0038] Step 6. When the PS captures the PL write completion signal, it reads the data from the PS DDR and stores the read data in the text file .txt according to the format. When the PS captures the rising edge of the PL write completion signal, the PS reads the data from the address corresponding to the PSDDR and stores the read data in the text file .txt in the order of I0, Q0, I1 and Q1 from left to right.

[0039] Step 7. When the PS finishes reading the data, the PS read completion signal is set to a high level and output to the PL through the register. When the PL captures the PS read completion signal, the next frequency sweep can be performed. When the PS finishes reading a whole frame of data, the PS read completion signal is pulled high and output to the PL through the register. When the PL captures the rising edge of the PS read completion signal, the next frequency sweep can be performed. If a frequency sweep is to be performed, proceed to step 1.

[0040] Step 8. Perform spectrum analysis on the data in the txt file in step 6 through MATLAB. Separate the IQ in the data file and use the fast Fourier transform FFT function, whose frequency resolution depends on the sampling rate of the original signal and the length of the signal. The frequency range is usually half of the sampling rate, which is determined by the Nyquist sampling theorem. Use the plot function to draw the spectrum. For the amplitude spectrum, the absolute value is usually taken and divided by half of the number of points to obtain a double-sided spectrum in dB units.

[0041] The above-mentioned implementation modes do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-mentioned implementation modes shall be included in the protection scope of the technical solution.

Claims

1. A low-cost spectrum analysis method for a 5G communication system, characterized in that: The following steps are involved: Step 1: define registers, including sweep enable signal, sweep time node signal, sweep length signal, sweep position selection signal and processing system write address signal; Step 2: Process the in-phase data I and quadrature data Q obtained by frequency scanning across clock domains; The cross-clock domain processing is as follows: by calling the asynchronous first-in-first-out memory FIFO, the input clock is a clock with the same clock frequency as the IQ data, the write enable is started with the rising edge of the sweep enable signal, and the continuous pull-up time is determined by configuring the sweep length signal; the data is the IQ data at the specific link position selected according to the sweep position selection signal; the output clock is a clock with a clock frequency of 100Mhz used by the PS; the read enable is started with the rising edge of the write full signal output by the FIFO, and the continuous pull-up time is determined by configuring the sweep length signal; Step 3: When the ready signal in the command channel from PL to PS of the Xilinx IP core DATAMOVER is captured to be high, the sweep length signal and the processing system write address signal are assigned to the data signal and the corresponding valid signal is sent to the DATAMOVER IP; Step 4: When the ready signal in the data channel from PL to PS of the DATAMOVER IP is captured as high, the IQ data after the clock domain crossing in step 2 is assigned to the data signal according to the AXI_STREAM protocol, and the data signal, valid bit indication signal, valid signal and last bit indication signal are sent to the DATAMOVER IP; Step 5: After PL finishes sending the frequency sweep data, the PL write completion signal is set to a high level, and this signal is output to PS as a rising edge interrupt trigger; Step 6: When the PS captures the PL write completion signal, it reads data from the double rate synchronous dynamic random access memory DDR of the PS and stores the read data in a text file .txt according to the format; Step 7: After the PS finishes reading the data, the PS read completion signal is set to a high level and output to the PL through the register. When the PL captures the PS read completion signal, the next frequency sweep is performed; Step 8. Perform spectrum analysis on the data of the txt file in step 6 through MATLAB.

2. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step one is specifically as follows: in the frame structure of the subcarrier with a frequency of 30khz, a complete 10msNR wireless frame is composed of 20 time slots, each slot is composed of 14 symbols, and a sweep enable signal is defined. The sweep operation is performed only when this signal is at a high level; a sweep time node signal is defined, and the starting position of the sweep is adjusted by this signal, that is, it is determined to start the sweep from a specific slot or a symbol; a sweep length signal is defined, and the length of the sweep or the number of IQ data points, that is, the duration of the sweep, is adjusted by this signal; a sweep position selection signal is defined to select the sweep data position; a processing system write address signal is defined to determine the specific address of the PS DDR where the sweep data is stored.

3. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step three is specifically as follows: in the direction from PL to PS, continuously capture the ready signal of the DATAMOVER IP command channel. When it is captured as a high level, it indicates that the command channel from PL to PS of the DATAMOVER IP is ready, and the relevant length signal can be sent to the DATAMOVER IP at this time. Since the format of the length signal of the command channel is defined by XILINX, it is 72 bits in total, wherein: [22:0] indicates the transmission byte length, in bytes; [23] indicates the burst type that supports bursts, wherein the value 1 indicates that the burst transmission type supported is INCR, and the data will be stored in an address that increases starting from the start address, that is, according to the burst length, each time only the start address of the burst needs to be written at the first burst; [30] indicates whether the frame sent this time is the last frame, wherein the value 1 indicates that the frame sent this time is the last frame; [N+31:32] indicates the starting address sent, wherein N indicates the address depth of the memory mapping, which should be a multiple of 8, and the remaining unused bits are filled with 0.

4. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step 4 is specifically as follows: after sending a whole frame of data to the command channel of the DATAMOVER IP, give the command channel enough response time, and then capture the ready signal of the data channel. If this signal is at a high level, send the data that has completed the clock domain conversion in step 2 to the DATAMOVER IP. At the same time, the data to be sent needs to be in accordance with the AXI_STREAM protocol. When the receiver is ready to receive the signal, a high-level ready signal is sent to the sender. At the same time, after the sender receives the high-level ready signal from the receiver, the data, data valid indication, data valid bit indication and the last data indication are sent to the receiver, that is, the data, valid bit indication, valid indication and the last data indication are sent to the DATAMOVER IP.

5. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step five is specifically as follows: after PL has sent a whole frame of data to DATAMOVER IP, the PL write completion signal is set to a high level and lasts for one unit clock cycle, and at the same time, this signal is output to PS as a rising edge interrupt trigger, indicating that PL has sent a whole frame of data to DATAMOVER IP. At this time, PS can read data from PS DDR.

6. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step six is ​​specifically as follows: when the PS captures the rising edge of the PL write completion signal, the PS reads data from the address corresponding to the PS DDR, and stores the read data in the order of I0, Q0, I1 and Q1 from left to right into the text file .txt.

7. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The specific step seven is: when the PS has read a whole frame of data, the PS read completion signal is pulled high, and the signal is output to the PL through the register; when the PL captures the rising edge of the PS read completion signal, the next frequency sweep can be performed. If the frequency sweep is to be performed, enter step one.

8. The low-cost spectrum analysis method for a 5G communication system according to claim 1, characterized in that: The step eight is specifically as follows: IQ in the data file is separated, and the fast Fourier transform (FFT) function is used, wherein the frequency resolution depends on the sampling rate of the original signal and the length of the signal; the frequency range is half of the sampling rate, and the spectrum is plotted using the plot function, and for the amplitude spectrum, the absolute value is taken and divided by half of the number of points to obtain a double-sided spectrum in dB units.

Images