A driving method of a gate driving circuit and a gate driving circuit

Abstract

The embodiment of the present application provides a driving method of a gate driving circuit and the gate driving circuit. The gate driving circuit comprises a plurality of cascaded shift registers. The working period of the shift register comprises a first stage. At least one shift register comprises: a first output unit, which is turned on in the first stage and outputs an enable signal in the first stage; and a signal processing unit, which transmits a first signal in a first sub-stage and transmits a second signal in a second sub-stage. The absolute value of the voltage value of the first signal is greater than the voltage absolute value of the voltage value of the second signal. The present application makes the enable signal output from the signal processing unit comprise a corner cutting part, which is beneficial to making the waveform of the driving transistor receiving the enable signal earlier and the waveform of the driving transistor receiving the enable signal later both appear a buffer drop trend near the turn-off time, reducing the difference of the turn-off time when the enable signal is output to different positions, and reducing the light flicker.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving method of a gate driving circuit and the gate driving circuit. BACKGROUND

[0002] In a liquid crystal display panel, a plurality of pixel electrodes arranged along a row direction, a driving transistor, and a common electrode located on one side of the pixel electrode in a direction perpendicular to the display panel are included. The gate of the driving transistor is connected to the same scan line. When the liquid crystal display panel emits light, the scan line transmits an enable signal to the gate of the driving transistor. At this time, the driving transistor is turned on, and then the driving transistor writes a data voltage into the pixel electrode connected thereto. An electric field is formed between the pixel electrode and the common electrode to drive liquid crystal molecules to deflect, thereby realizing light emission.

[0003] When the scan line transmits an enable signal to the gate of the driving transistor located in the same row, due to the load on the scan line, the enable signal transmitted by the control signal line will be delayed, that is, the turn-off time of the enable signal transmitted earlier is faster, and the turn-off time of the enable signal transmitted later is slower. It is found that there is a coupling voltage between the scan line connected to the gate of the driving transistor and the pixel electrode when the enable signal is turned off. The coupling voltage between the scan line and the pixel electrode is greatly affected by the speed of turning off the enable signal. It is found that the coupling voltage between the part of the scan line connected to the driving transistor receiving the enable signal earlier and the pixel electrode is greater than the coupling voltage between the part of the scan line connected to the driving transistor receiving the enable signal later and the pixel electrode. The coupling voltage between the scan line connected to the gate of the driving transistor and the pixel electrode affects the potential of the common electrode. The electric field formed between the pixel electrode and the common electrode deviates. Due to the different coupling voltages at different positions, the deviation of the electric field between the pixel electrode and the common electrode at different positions is also different, thereby causing a significant difference in luminance between the pixel electrodes at different positions, resulting in uneven display. SUMMARY

[0004] Therefore, the present application provides a driving method of a gate driving circuit and the gate driving circuit to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a driving method of a gate driving circuit, including a plurality of cascaded shift registers, and the working period of the shift register includes a first stage. At least one shift register includes:

[0006] a first output unit, the first output unit being turned on in the first stage and outputting an enable signal in the first stage;

[0007] The signal processing unit is electrically connected with the input terminal of the first output unit; and the signal processing unit transmits an enable signal to the first output unit in the first stage.

[0008] The first stage includes a first sub-stage and a second sub-stage, and the second sub-stage is performed after the first sub-stage; the signal processing unit transmits a first signal to the input terminal of the first output unit in the first sub-stage, and transmits a second signal to the input terminal of the first output unit in the second sub-stage; and the absolute value of the voltage value of the first signal is greater than the absolute value of the voltage value of the second signal.

[0009] In an implementation form of the first aspect, the signal processing unit includes:

[0010] The first module is electrically connected with the first signal line at the input terminal, and the output terminal of the first module is electrically connected with the input terminal of the first output unit; the first module is turned on in the first sub-stage, and the first clock signal line transmits the first signal in the first sub-stage.

[0011] The second module is electrically connected with the input terminal of the first output unit at the output terminal; the second module is turned on in the second sub-stage, and transmits the second signal to the input terminal of the first output unit.

[0012] In an implementation form of the first aspect, the second module includes a first capacitor and a first transistor, the first terminal of the first transistor is electrically connected with the input terminal of the first output unit, and the second terminal is electrically connected with the first terminal plate of the first capacitor.

[0013] The first transistor is turned on in the second sub-stage, and the first terminal plate of the first capacitor is discharged to the input terminal of the first output unit in the second sub-stage.

[0014] In an implementation form of the first aspect, the second module further includes a second transistor, the first terminal of the second transistor is electrically connected with the ground terminal, and the second terminal is electrically connected with the first terminal plate of the first capacitor.

[0015] The second transistor is turned on in the second sub-stage, and the first terminal plate of the first capacitor is electrically connected with the ground terminal in the second sub-stage.

[0016] In an implementation form of the first aspect, the gate of the first transistor is electrically connected with the first control line, and the gate of the second transistor is electrically connected with the second control line; the first control line and the second control line both transmit the effective level signal in the second sub-stage to control the first transistor and the second transistor to be turned on.

[0017] The first control line transmits the effective level signal in the second sub-stage to control the first transistor to be turned on, and the second control line transmits the effective level signal in the second sub-stage to control the second transistor to be turned on.

[0018] In an implementation form of the first aspect, the signal processing unit further comprises a first charging module, a first end of the first charging module is electrically connected with the first voltage end, and a second end of the first charging module is electrically connected with the first plate of the first capacitor.

[0019] The working period of the shift register further comprises a second stage, the second stage is performed before the second sub-stage; the first charging module is turned on in the second stage and charges the first capacitor.

[0020] In an implementation form of the first aspect, the signal processing unit further comprises a third module, an output end of the third module is electrically connected with the control end of the first module; the third module controls the first module to be turned on in the first sub-stage and turned off in the second sub-stage.

[0021] In an implementation form of the first aspect, the third module comprises a first sub-module and a second sub-module; an input end of the first sub-module is electrically connected with the second voltage end, and an output end of the first sub-module is electrically connected with the control end of the first module; an input end of the second sub-module is electrically connected with the first voltage end, and an output end of the second sub-module is electrically connected with the control end of the first module.

[0022] The first sub-module is turned on in the second sub-stage and controls the first module to be turned off; the second sub-module is turned on in the second stage and controls the first module to be turned on.

[0023] In an implementation form of the first aspect, the signal processing unit further comprises a second charging module, an input end of the second charging module is electrically connected with the first voltage end, and an output end of the second charging module is electrically connected with the first plate of the first capacitor; control ends of the second charging modules comprised by the plurality of signal processing units are electrically connected with the same control line.

[0024] The second charging module is turned on before the first stage and turned off in the second sub-stage.

[0025] In the second aspect, the embodiments of the present application provide a gate drive circuit, which adopts the driving method provided in the first aspect; the gate drive circuit comprises a plurality of cascaded shift registers, at least one shift register comprises:

[0026] A first output unit, the first output unit outputs an enable signal.

[0027] A signal processing unit, comprising a first capacitor, a first transistor and a second transistor, a first electrode of the first transistor is electrically connected with an input end of the first output unit, and a second electrode of the first transistor is electrically connected with a first plate of the first capacitor, a first electrode of the second transistor is electrically connected with a ground end, and a second electrode of the second transistor is electrically connected with the first plate of the first capacitor.

[0028] In an implementation form of the second aspect, a gate of the first transistor and a gate of the second transistor are electrically connected with the same control line.

[0029] In an implementation form of the second aspect, the gate of the first transistor is electrically connected to a first control line, and the gate of the second transistor is electrically connected to a second control line.

[0030] In an implementation form of the second aspect, the signal processing unit further comprises a control transistor, a first electrode of the control transistor being electrically connected to the first signal line, and a second electrode of the control transistor being electrically connected to the input terminal of the first output unit.

[0031] In an implementation form of the second aspect, the signal processing unit further comprises a third transistor and a fourth transistor, a first electrode of the fourth transistor being electrically connected to the first voltage terminal, and a second electrode of the fourth transistor being electrically connected to the gate of the control transistor, and a first electrode of the third transistor being electrically connected to the second voltage terminal, and a second electrode of the third transistor being electrically connected to the gate of the control transistor, and the gate of the third transistor being electrically connected to the same control line as the gate of the first transistor.

[0032] In an implementation form of the second aspect, the signal processing unit further comprises a first charging transistor, a first electrode of the first charging transistor being electrically connected to the first voltage terminal, and a second electrode of the first charging transistor being electrically connected to the first electrode plate of the first capacitor.

[0033] In an implementation form of the second aspect, the signal processing unit further comprises a fourth transistor, a first electrode of the fourth transistor being electrically connected to the first voltage terminal, and a second electrode of the fourth transistor being electrically connected to the gate of the control transistor.

[0034] The gate of the fourth transistor is electrically connected to the same control line as the gate of the first charging transistor.

[0035] In an implementation form of the second aspect, the signal processing unit further comprises a second charging transistor, a first electrode of the second charging transistor being electrically connected to the first voltage terminal, and a second electrode of the second charging transistor being electrically connected to the first electrode plate of the first capacitor, and the gates of the second charging transistors comprised by the plurality of signal processing units are electrically connected to the same control line.

[0036] In a third aspect, an embodiment of the present application provides a display panel, comprising a plurality of scanning lines and the gate driving circuit provided in the second aspect, and the output terminal of the shift register in the gate driving circuit is electrically connected to the scanning lines.

[0037] In a fourth aspect, an embodiment of the present application provides a display device, characterized by comprising the display panel provided in the third aspect.

[0038] In the embodiment of the present application, the difference between the enable signal waveform output from the signal processing unit and the enable signal waveform including the corner cutting part received by the driving transistor in the pixel far from the gate driving circuit in the same pixel row is reduced, which is beneficial to make the driving transistor receiving the enable signal earlier and the driving transistor receiving the enable signal later have a trend of buffer drop near the off time, reduce the difference in off time when the enable signal is output from the near end and the far end of the gate driving circuit, reduce the difference in coupling voltage generated at the near end and the far end of the gate driving circuit, and further reduce the difference in electric field change at the near end and the far end of the gate driving circuit, thereby reducing the influence of brightness unevenness and flicker and improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 A cross-sectional schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure.

[0041] Figure 2 A planar schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure.

[0042] Figure 3 A waveform schematic diagram of a control signal provided by the embodiment of the present application is shown in the figure.

[0043] Figure 4 A schematic diagram of a gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0044] Figure 5 A timing diagram of a gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0045] Figure 6 A schematic diagram of another gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0046] Figure 7 A schematic diagram of another gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0047] Figure 8 A schematic diagram of another gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0048] Figure 9 A timing diagram of another gate driving circuit provided by the embodiment of the present application is shown in the figure.

[0049] Figure 10 A timing diagram of another gate drive circuit provided in an embodiment of the present application;

[0050] Figure 11 A timing diagram of another gate drive circuit provided in an embodiment of the present application;

[0051] Figure 12 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0052] Figure 13 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0053] Figure 14 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0054] Figure 15 A timing diagram of another gate drive circuit provided in an embodiment of the present application;

[0055] Figure 16 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0056] Figure 17 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0057] Figure 18 A schematic diagram of another gate drive circuit provided in an embodiment of the present application;

[0058] Figure 19 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0060] It should be clear that the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0061] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0062] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0063] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0064] It should be understood that although terms such as "first," "second," etc., may be used to describe stages, modules, charging modules, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish stages, modules, charging modules, etc., from each other. For example, without departing from the scope of the embodiments of this application, the first module may also be referred to as the second module, and similarly, the second module may also be referred to as the first module. Through meticulous and in-depth research, the applicant of this case has provided a solution to the problems existing in the prior art.

[0065] Figure 1 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application. Figure 2 A plan view of a display panel provided in an embodiment of this application. Figure 3 This is a waveform diagram of a control signal provided in an embodiment of this application.

[0066] like Figure 1As shown, the display panel in the present application is taken as a liquid crystal display panel as an example for illustration, the liquid crystal display panel includes a plurality of pixels, the gate electrode of the driving transistor Td in the display panel is electrically connected with the scan line Gate, and the gate electrodes of the driving transistors Td in the plurality of pixels in the same row are all electrically connected with the same scan line Gate. When the display panel needs to perform display work, the scan line Gate transmits an enabling signal to the gate electrode of the driving transistor Td, controls the driving transistor Td to be turned on, and after the driving transistor Td is turned on, transmits the data voltage Vdata from the metal electrode (which can be the source electrode or the drain electrode) of the driving transistor Td to the pixel electrode. Further, after the pixel electrode receives the data voltage Vdata, the electric field is formed between the pixel electrodes of different pixels and the common electrode layer, the formed electric field drives the liquid crystal molecules in the pixel to deflect so that the pixel emits light. When the gate electrode of the driving transistor Td in the display panel receives the signal transmitted by the scan line Gate, the coupling voltage is included between the scan line Gate electrically connected with the gate electrode of the driving transistor Td and the pixel electrode, the coupling voltage is generated due to the quick switching between the opening and the closing of the signal transmitted by the scan line Gate to the gate electrode of the driving transistor Td, and the size of the coupling voltage is related to the quickness of the closing of the signal transmitted by the scan line Gate, the faster the closing of the signal transmitted by the scan line Gate, the larger the coupling voltage. The coupling voltage between the part of the scan line Gate electrically connected with the gate electrode of the driving transistor Td and the pixel electrode in the pixel will affect the potential of the part of the common electrode layer corresponding to the pixel position, cause the deviation of the electric field between the pixel electrode and the common electrode layer in the pixel, and thus cause the deviation of the light emitting effect.

[0067] In combination Figure 2 As shown, the non-display area of the display panel 200 includes the gate driving circuit 100, and the control signal generated by the gate driving circuit 100 is output to the liquid crystal display panel. In the display panel 200, the first point and the second point are positions where the same scan line Gate is electrically connected with the gate electrodes of different driving transistors Td, and the control signal transmitted by the same scan line Gate will pass through the first point and the second point. The first point is closer to the gate driving circuit 100 than the second point, that is, the signal transmitted by the scan line Gate will first reach the first point, and the driving transistor Td of the pixel located at the first point will receive the control signal earlier than the driving transistor Td of the pixel located at the second point. In this case, due to the influence of the load on the scan line Gate, the control signal transmitted by the scan line Gate located at the first point and the second point is delayed, and the delay at the second point which is far away from the gate driving circuit 100 is more serious. As shown, Figure 3 As shown, Figure 3 The horizontal axis in the figure represents the time t when the gate electrode of the driving transistor Td receives the control signal, and the vertical axis represents the amplitude A of the control signal received by the gate electrode of the driving transistor.

[0068] The delay in the control signal transmitted by the scan line gate causes the turn-off time of the control signal received by the gate of the driving transistor at point 2 to be longer than that of the control signal received by the gate of the driving transistor at point 1. This can be observed in the control signal waveform at point 2, which shows that when the control signal is turned off, as... Figure 3 As shown in the diagram, the portion outlined by the circular dashed line indicates a beveled transition in the control signal. In this case, the control signal turns off more slowly, while the control signal at point 1 turns off more quickly. From the above, it can be seen that the coupling voltage between the scan line Gate and the pixel electrode corresponding to a pixel is related to the speed at which the control signal received by the gate of the driving transistor Td in that pixel turns off. Taking the pixels at points 1 and 2 in this embodiment as an example: the control signal received by the driving transistor Td at point 1 turns off faster than that received by the driving transistor Td at point 2. Therefore, the coupling voltage between the pixel electrode at point 1 and the scan line Gate is greater than that between the pixel electrode at point 2 and the scan line Gate. The common electrode layer in the display panel 200 receives a common voltage Vcom. The coupling voltage affects the potential stability of the common electrode layer. However, the coupling voltage at point 1 differs from that at point 2, resulting in an inconsistency between the potential Vcom deviation of the common electrode layer at point 1 and that at point 2. For example, if the coupling voltage at point 1 is relatively high, the potential Vcom of the common electrode layer at point 1 will deviate significantly, resulting in a large deviation in the electric field between the pixel electrode and the common electrode layer at point 1, leading to inaccurate brightness output of the pixel at point 1. Conversely, if the coupling voltage at point 2 is relatively low, the potential Vcom of the common electrode layer at point 2 will deviate less, resulting in a smaller deviation in the electric field between the pixel electrode and the common electrode layer at point 2, leading to a smaller deviation in brightness output of the pixel at point 2. Thus, the degree of brightness deviation at point 1 differs from that at point 2, causing inaccurate brightness output of the display panel. Furthermore, since different common electrode layers (Vcom) exist on the display panel surface, but different pixels are provided with the same common voltage, differences in electric field strength between positive and negative frames may also occur, resulting in alternating brightness, i.e., flickering.

[0069] Figure 4 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. Figure 5 This is a timing diagram of a gate driving circuit provided in an embodiment of this application.

[0070] The embodiment of the present application provides a driving method of a gate driving circuit 100, referring to Figure 2 As shown in the figure, the gate driving circuit 100 comprises a plurality of cascaded shift registers VSR, and at least one of the shift registers VSR can be used to output a gate control signal. In the present application, the output end of the shift register VSR is electrically connected with a scanning line Gate, and the output control signal is a scanning signal SG, which is used to control the switch of a driving transistor Td distributed along the row direction. A data signal end writes a data voltage to a pixel electrode through the driving transistor Td.

[0071] In combination with Figure 4 , Figure 5 As shown in the figure, the working period of the shift register VSR comprises a first stage T1, and at least one of the shift registers VSR comprises:

[0072] A first output unit 10, which is turned on in the first stage T1 and outputs an enable signal in the first stage T1. The output end 102 of the first output unit 10 outputs the enable signal, which can be the scanning signal SG used to drive the driving transistor Td to be turned on. In the present application, the enable signal is taken as an example with a high level. In the first stage T1, the first output unit 10 is turned on, and the shift register VSR provides a driving signal for the driving transistor Td.

[0073] A signal processing unit 20, the output end 202 of the signal processing unit 20 is electrically connected with the input end 101 of the first output unit 10, and the signal processed by the signal processing unit 20 can be output to the output end 102 of the first output unit 10 through the output end 202. In the first stage T1, the signal processing unit 20 transmits the enable signal to the first output unit 10. The signal processing unit 20 is a unit for generating the enable signal in the shift register VSR.

[0074] From the above-mentioned background art, when the signal processing unit outputs the enable signal, the enable signal received by the driving transistors located in the same row is prone to delay, and the enable signal received by the gate of the driving transistor located at the first point is turned off faster, and the enable signal received by the gate of the driving transistor located at the second point is turned off slower, that is, the waveform of the enable signal located at the second point shows a slow decreasing trend when turned off, which leads to different coupling voltages at the first point and the second point, and further leads to different degrees of brightness change, resulting in the problems of uneven luminance and flicker of the display panel 200.

[0075] Therefore, in order to reduce the influence of the difference, the present application provides a driving method of the gate driving circuit 100, when the signal processing unit 20 is enabled, the working of the first stage T1 of the signal processing unit 20 is divided into two continuous sub-stages, that is, the first stage T1 includes the continuous first sub-stage T11 and the second sub-stage T12, and the second sub-stage T12 is performed after the first sub-stage T11. The signal processing unit 20 transmits the first signal V1 to the input end 101 of the first output unit 10 in the first sub-stage T11, and the signal processing unit 20 transmits the second signal V2 to the input end 101 of the first output unit 10 in the second sub-stage T12. The absolute value of the voltage value of the first signal V1 is greater than the voltage absolute value of the voltage value of the second signal V2.

[0076] In combination Figure 3 As shown in the figure, the waveform of the enable signal received by the gate of the driving transistor Td at the second point changes slowly when it is turned off, including a part similar to a chamfered corner; the waveform of the enable signal received by the driving transistor Td at the first point changes sharply when it is turned off, almost directly switching from high level to low level. In summary, there is a relatively obvious difference between the waveforms of the enable signals received at the first point and the second point. In order to reduce the influence of the difference, the present application divides the first stage T1 of the enable signal output by the signal processing unit 20 into the first sub-stage T11 and the second sub-stage T12. In the first sub-stage T11, the signal processing unit 20 outputs the first signal V1, which can be consistent with the signal potential for turning on the driving transistor Td as conventionally set. In the second sub-stage T12 within the first stage T1, the falling trend of the enable signal at the second point is imitated, that is, the enable signal appears a decreasing trend in the second sub-stage T12. The signal processing unit 20 outputs the second signal V2 in the second sub-stage T12, and the voltage absolute value of the second signal V2 is smaller than the voltage absolute value of the first signal V1, forming the waveform of the control signal as shown in the figure. Figure 5

[0077] ​In the embodiment of the present application, when the signal processing unit 20 outputs the enable signal in the first stage T1, the signal processing unit 20 outputs the first signal V1 first and then outputs the second signal V2, so that the waveform of the enable signal output from the signal processing unit 20 and the waveform of the enable signal including the corner cutting part received by the driving transistor Td in the pixel far from the gate driving circuit 100 in the same row are different by a small amount, which is beneficial to make the waveform of the driving transistor Td receiving the enable signal earlier and the waveform of the driving transistor Td receiving the enable signal later both have a trend of buffer drop near the off state, reduce the difference in off time when the enable signal is output at the near end and the far end of the gate driving circuit, reduce the difference in coupling voltage generated at the near end and the far end of the gate driving circuit 100, and further reduce the difference in electric field change at the near end and the far end of the gate driving circuit 100, thereby reducing the influence of brightness unevenness and flicker and improving the display effect.

[0078] Figure 6 Another schematic diagram of a gate driving circuit provided by an embodiment of the present application.

[0079] In one embodiment of the present application, as shown in Figure 6 The signal processing unit 20 includes:

[0080] The first module A10 is electrically connected with the first signal line SL1 at the input end A101 and electrically connected with the input end 101 of the first output unit 10 at the output end A102. The first module A10 is turned on in the first sub-stage T11, and the first signal line SL1 transmits the first signal V1 in the first sub-stage T11. The first signal line SL1 can be used to output a voltage signal. The first module A10 is turned on in the first sub-stage T11, and the first module A10 outputs the first signal V1 received from the first signal line SL1 to the output end 102 of the first output unit 10.

[0081] The second module A20 is electrically connected with the input end 101 of the first output unit 10 at the output end A202. The second module A20 is turned on in the second sub-stage T12 and transmits the second signal V2 to the input end 101 of the first output unit 10. The second module A20 is turned on in the second sub-stage T12 and outputs the second signal V2 to the input end 101 of the first output unit 10.

[0082] In the first sub-stage T11, the first module A10 is turned on and the second module A20 is turned off. In the second sub-stage, the second module A20 is turned on and the first module A10 is turned off.

[0083] In the embodiment of the present application, the first module A10 and the second module A20 are respectively set to be started in the first sub-stage T11 and the second sub-stage T12, so that the different first signal V1 and the second signal V2 are continuously output in the first stage T1, which is beneficial to flexibly setting the output of the second signal V2 by using the second module A20, and is beneficial to avoiding the problem of crosstalk caused by using the same module to output, and is beneficial to flexibly setting the first signal V1 and the second signal V2 respectively.

[0084] Figure 7 A schematic diagram of another gate drive circuit provided by an embodiment of the present application.

[0085] In an embodiment of the present application, as shown in Figure 6 , Figure 7 , the second module A20 includes a first capacitor C1 and a first transistor M1, the first electrode of the first transistor M1 is electrically connected with the input end 101 of the first output unit 10, and the second electrode is electrically connected with the first plate C11 of the first capacitor C1.

[0086] The first transistor M1 is turned on in the second sub-stage T12, and the first plate C11 of the first capacitor C1 is discharged to the input end 101 of the first output unit 10 in the second sub-stage T12.

[0087] In the second sub-stage T12, the second module A20 is started, that is, the first transistor M1 is turned on, the first capacitor C1 includes stored charges, and the first plate C11 of the first capacitor C1 is electrically connected with the input end 101 of the first output unit 10. As shown in Figure 5 , optionally, the potential of the first plate C11 formed by the stored charges in the first capacitor C1 is equal to the potential of the second signal V2, so that in the second sub-stage T12, the first output unit 10 receives the second signal V2 through the first transistor M1, and the second signal V2 is generated by discharging the first capacitor C1.

[0088] Figure 8 A schematic diagram of another gate drive circuit provided by an embodiment of the present application, Figure 9 A timing diagram of another gate drive circuit provided by an embodiment of the present application.

[0089] In an embodiment of the present application, as shown in Figure 8 , the second module A20 further includes a second transistor M2, the first electrode of the second transistor M2 is electrically connected with the ground terminal GND, and the second electrode is electrically connected with the first plate C11 of the first capacitor C1.

[0090] The second transistor M2 is turned on in the second sub-stage T12, and the first plate C11 of the first capacitor C1 is electrically connected with the ground terminal GND in the second sub-stage T12.

[0091] In the second sub-stage T12, the second transistor M2 is turned on, and the first plate C11 of the first capacitor C1 is also electrically connected to the ground terminal GND. At this time, the first capacitor C1 forms a performance of discharging to the ground terminal GND. Optionally, the potential of the first plate C11 formed by the stored charge in the first capacitor C1 is equal to the potential when the absolute value of the second signal V2 is maximum. In combination with Figure 9 As shown in the second sub-stage T12, the first transistor M1 and the second transistor M2 are both turned on, and the first plate C11 of the first capacitor C1 is both electrically connected to the input terminal 101 of the first output unit 10 and electrically connected to the ground terminal GND. Thus, the first capacitor C1 forms a performance of discharging to both the input terminal 101 of the first output unit 10 and the ground terminal GND. Therefore, the waveform of the second signal V2 output from the output terminal 102 of the first output unit 10 is a waveform gradually decreasing from the potential when the absolute value of the second signal V2 is maximum.

[0092] In the embodiment of the present application, the first plate C11 of the first capacitor C1 is also electrically connected to the ground terminal GND. Thus, the discharging of the first capacitor C1 to the input terminal 101 of the first output unit 10 in the second sub-stage T12 is gradually decreasing, which is beneficial to make the waveform of the enable signal output by the gate drive circuit 100 more close to the waveform received by the driving transistor Td in the display panel 200 which receives the enable signal later. This is beneficial to further reduce the waveform difference of the enable signal received by the driving transistors Td in the same row of the display panel 200, thereby reducing the influence of the uneven luminance of the display panel 200.

[0093] Figure 10 Another timing diagram of the gate drive circuit provided by the embodiment of the present application.

[0094] In one embodiment of the present application, in combination with Figure 8 、 Figure 10 As shown in the second sub-stage T12, the gate of the first transistor M1 is electrically connected to the first control line S1, and the gate of the second transistor M2 is electrically connected to the second control line S2. The first control line S1 and the second control line S2 both transmit effective level signals in the second sub-stage T12 to control the first transistor M1 and the second transistor M2 to be turned on.

[0095] The first control line S1 transmits an effective level signal in the second sub-stage T12 to control the first transistor M1 to be turned on, and the second control line S2 transmits an effective level signal in the second sub-stage T12 to control the second transistor M2 to be turned on.

[0096] Optionally, in some other implementations, the gates of the first transistor M1 and the second transistor M2 are connected to the same control line.

[0097] In this embodiment, the first control line S1 and the second control line S2 are configured to control the working states of the first transistor M1 and the second transistor M2 respectively, and both the first transistor M1 and the second transistor M2 are configured to be turned off in the first sub-stage T11 and turned on in the second sub-stage T12, which is beneficial to use transistors to achieve discharge control of the first capacitor C1.

[0098] Figure 11 This is a timing diagram of another gate drive circuit provided in an embodiment of this application.

[0099] In one embodiment of this application, reference continues to be made to... Figure 8 As shown, the signal processing unit 20 further includes a first charging module A30. The first terminal A301 of the first charging module A30 is electrically connected to the first voltage terminal VG1, the second terminal A302 is electrically connected to the first plate C11 of the first capacitor C1, and the control terminal A303 is electrically connected to the third control line S3. When the third control line S3 transmits an enable signal, the first charging module A30 is enabled, and the first capacitor C1 receives charging from the first voltage terminal VG1. Optionally, the enable signal transmitted by the third control line S3 is a high-level signal. Optionally, the potential of the first voltage terminal VG1 is set to be the same as the potential of the first signal V1, that is, the potential of the first plate C11 of the first capacitor C1 after charging is the same as the potential of the first signal V1, combined with... Figure 11 The signal processing unit 20 shown outputs a second signal V2 in the second sub-stage T12, which is a signal that gradually decreases from the same potential as the first signal V1.

[0100] like Figure 11 As shown, the working cycle of the shift register VSR also includes a second stage T2. Within the same working cycle, the second stage T2 occurs after the end of the first stage T1 and before the second sub-stage T12 of the next working cycle. At the end of the second sub-stage T12 within the first stage T1, the first capacitor C1 has also completed its discharge. During the second stage T2, the first charging module A30 is activated and charges the first capacitor C1, preparing for the first capacitor C1 to simultaneously discharge to the input terminal 101 of the first output unit 10 and the ground terminal GND when the shift register VSR performs the next second sub-stage T12 in the next working cycle.

[0101] In the embodiment of the present application, the first charging module A30 is arranged to be turned on in the second stage T2 to charge the first capacitor C1, so as to prepare for discharging of the first capacitor C1 in the next second sub-stage T12. In addition, charging the first plate C11 of the first capacitor C1 by the first charging module A30 is equivalent to resetting the first plate C11, which is beneficial to outputting the second signal V2 of the same level by the first output unit 10 and avoiding obvious difference of the second signal V2 outputted in different second sub-stages T12.

[0102] Figure 12 A schematic diagram of another gate drive circuit provided by an embodiment of the present application.

[0103] In an embodiment of the present application, as shown in Figure 12 the signal processing unit 20 further includes a third module A40, and an output end A402 of the third module A40 is electrically connected with a control end A103 of the first module A10; the third module A40 controls the first module A10 to be turned on in the first sub-stage T11 and turned off in the second sub-stage T12.

[0104] The first module A10 is turned on in the first sub-stage T11 and outputs the first signal V1, and the first module A10 is turned off in the second sub-stage T12 and the second module A20 is turned on in the second sub-stage T12.

[0105] In the embodiment of the present application, the third module A40 is arranged to control the switching state of the first module A10, which is beneficial to accurately controlling the switching of the first module A10 and avoiding the first module A10 and the second module A20 being turned on or turned off at the same time, so as to affect the output of the control signal and be beneficial to more stable operation of the gate drive circuit 100 and stable output of the first signal V1 and the second signal V2 with a gradually decreasing trend by the first output unit 10 in the first stage T1.

[0106] Figure 13 A schematic diagram of another gate drive circuit provided by an embodiment of the present application.

[0107] In an embodiment of the present application, as shown in Figure 13 the third module A40 includes a first submodule A40A and a second submodule A40B; an input end A40A1 of the first submodule A40A is electrically connected with the second voltage end VG2, and an output end A40A2 is electrically connected with the control end A103 of the first module A10; an input end A40B1 of the second submodule A40B is electrically connected with the first voltage end VG1, and an output end A40B2 is electrically connected with the control end A103 of the first module A10.

[0108] The first sub-module A40A is turned on and controls the first module A10 to be turned off in the second sub-stage T12, and the second sub-module A40B is turned on and controls the first module A10 to be turned on in the second stage T12.

[0109] From the above, the electric signal output by the second voltage terminal VG2 can control the first module A10 to be turned off, and the electric signal transmitted by the first voltage terminal VG1 can control the first module A10 to be turned on.

[0110] In the second sub-stage T12, the first sub-module A40A in the third module A40 is turned on, the first sub-module A40A outputs the signal of the second voltage terminal VG2 to the control terminal A103 of the first module A10, and the first module A10 is turned off. In the embodiment of the present application, the potential of the first voltage terminal VG1 is greater than the potential of the second voltage terminal VG2 as an example, and the control terminal A103 of the first module A10 receives a low-level signal to be turned off.

[0111] In the second stage T2, the second sub-module A40B in the third module A40 is turned on, the second sub-module A40B outputs the signal of the first voltage terminal VG1 to the control terminal A103 of the first module A10, and the first module A10 is turned on. In the second stage T2, the input terminal A101 of the first module A10 receives the non-enable signal transmitted by the first signal line SL1, the first module A10 outputs the non-enable signal, and then the first output unit 10 outputs the non-enable signal in the second stage T2.

[0112] Until the first sub-stage T11, the second sub-module A40B is continuously turned on, and the first signal line SL1 connected to the input terminal A101 of the first module A10 outputs the first signal V1.

[0113] Figure 14 a schematic diagram of another gate drive circuit provided by an embodiment of the present application, Figure 15 a timing diagram of another gate drive circuit provided by an embodiment of the present application.

[0114] In an embodiment of the present application, as Figure 14As shown, the signal processing unit 20 further includes a second charging module A50, an input end A501 of the second charging module A50 is electrically connected with the first voltage end VG1, an output end A502 of the second charging module A50 is electrically connected with the first plate C11 of the first capacitor C1, and a control end A503 of the second charging module A50 is electrically connected with the fourth control line S4. When the fourth control line S4 transmits an opening signal, the second charging module A50 is opened. Optionally, the opening signal transmitted by the fourth control line S4 is a high-level signal. The second charging module A50 outputs the electrical signal output by the first voltage VG1 to the first capacitor C1, resets the first plate C11 of the first capacitor C1, and prepares for the discharge of the first capacitor C1 in the next second sub-stage T12. In addition, the control ends A503 of the second charging modules A50 included in the plurality of signal processing units 20 are electrically connected with the same control line. Optionally, the first plates C11 of the first capacitors C1 in the plurality of shift registers VSR in the display panel 200 can be simultaneously reset between two adjacent second sub-stages T12.

[0115] As shown in Figure 15 , the second charging module A50 is opened before the first stage T1 and is closed in the second sub-stage T12. Optionally, the second charging module A50 is opened in the initial stage T0 of the shift register VSR, that is, before the shift register VSR starts to output the control signal. The second charging module A50 resets the first plate C11 of the first capacitor C1. Optionally, in the second stage T2, the second charging module A50 is opened to replace the first charging module A30 to charge the first capacitor C1.

[0116] In summary, as shown in Figure 14 , Figure 15 , the working process of the gate drive circuit 100 in the shift register VSR provided in the embodiments of the present application is as follows.

[0117] In the initial stage T0, one of the first charging module A30 and the second charging module A50 is opened to reset the first plate C11 of the first capacitor C1 in the gate drive circuit 100.

[0118] In the first stage T1:

[0119] In the first sub-stage T11, the second sub-module A40B in the third module A40 is opened, the control end A103 of the first module A10 receives the signal output by the first voltage end VG1, the first module A10 is opened, the first module A10 outputs the first signal V1 output by the first signal line SL1 received by the input end A101 to the input end 101 of the first output unit 10, and the enable signal output by the first output unit 10 is the first signal V1.

[0120] In the second sub-stage T12, the first sub-module A40A in the third module A40 is turned on, and the second sub-module A40B is turned off. The control terminal A103 of the first module A10 receives the signal output from the second voltage terminal VG2, and the first module A10 is turned off. The second module A20 is turned on, and the gates of the first transistor M1 and the second transistor M2 in the second module A20 both receive the turn-on signal and are turned on. The first capacitor C1 discharges simultaneously to the input terminal 101 of the first output unit 10 and the ground terminal GND, so that the input terminal of the first output unit 10 receives the gradually decreasing second signal V2.

[0121] In the second stage T2, both the first module A10 and the second module A20 are turned off, and the first charging module A30 is turned on. The first charging module A30 receives the electrical signal output from the first voltage terminal VG1 to charge the first capacitor C1.

[0122] Figure 16 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0123] The shift register VSR also includes a second output unit 30. The input terminal 301 of the second output unit 30 is electrically connected to the second voltage terminal VG2, the output terminal 302 is electrically connected to the output terminal of the shift register VSR, and the control terminal 303 is electrically connected to the control circuit. Furthermore, the control terminal of the first output unit 10 is also electrically connected to the control circuit. The control circuit is used to control the switching states of the first output unit 10 and the second output unit 30.

[0124] Figure 17 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0125] This application provides a gate driving circuit 100, employing the driving method provided in the above embodiments. (See also...) Figure 2 As shown, the gate drive circuit 100 includes multiple cascaded shift registers (VSRs), at least one of which includes:

[0126] First output unit 10, first output unit 10 outputs an enable signal;

[0127] The signal processing unit 20 includes a first capacitor C1, a first transistor M1 and a second transistor M2. The first terminal of the first transistor M1 is electrically connected to the input terminal 101 of the first output unit 10, and the second terminal is electrically connected to the first plate C11 of the first capacitor C1. The first terminal of the second transistor M2 is electrically connected to the ground terminal GND, and the second terminal is electrically connected to the first plate C11 of the first capacitor C1.

[0128] In the second sub-stage T12, the second module A20 is turned on, the first transistor M1 and the second transistor M2 in the second module A20 are both turned on, the first capacitor C1 discharges to the input end 101 of the first output unit 10 and the ground end GND at the same time, and the input end 101 of the first output unit 10 receives the changed second signal V2.

[0129] In an embodiment of the present application, continuing to refer to Figure 17 As shown in the figure, the gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the same control line. Alternatively, the first transistor T1 and the second transistor T2 are both electrically connected to the first control line S1. In the second sub-stage T12, the first transistor M1 and the second transistor M2 are both turned on, and alternatively, the first transistor M1 and the second transistor M2 are of the same type; in the embodiment of the present application, the first transistor M1 and the second transistor M2 are both N-type transistors.

[0130] In the embodiment of the present application, in the second sub-stage T12, the gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the same control line, which is beneficial to simultaneously control the first transistor M1 and the second transistor M2 and ensure that the switching states of the first transistor M1 and the second transistor M2 are the same; and is beneficial to save the control end in the circuit and save the number of wirings.

[0131] Figure 18 Another schematic diagram of a gate drive circuit provided in the embodiment of the present application.

[0132] In an embodiment of the present application, as shown in Figure 18 The gate of the first transistor M1 is electrically connected to the first control line S1, and the gate of the second transistor T2 is electrically connected to the second control line S2.

[0133] The gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to different control lines, which is beneficial to more flexibly control the conduction states of the first transistor M1 and the second transistor M2.

[0134] In an embodiment of the present application, continuing to refer to Figure 17 、 Figure 18 As shown in the figure, the signal processing unit 20 further includes a control transistor M3, the first pole of the control transistor M3 is electrically connected to the first signal line SL1, and the second pole of the control transistor M3 is electrically connected to the input end 101 of the first output unit 10.

[0135] The first module A10 is turned on at the first sub-stage T11, and outputs the first signal V1 transmitted by the first signal line SL1 to the input end 101 of the first output unit 10. Optionally, the first module A10 comprises a control transistor M3, at the first sub-stage T11, the gate of the control transistor M3 receives an enable signal to turn on, the first electrode of the control transistor M3 receives the first signal V1 transmitted by the first signal line SL1, and the second electrode outputs the first signal V1 to the input end 101 of the first output unit 10.

[0136] In one embodiment of the present application, continuing to refer to Figure 18 、 Figure 19 As shown in the figure, the signal processing unit 20 further comprises a third transistor M4 and a fourth transistor M5; the first electrode of the fourth transistor M5 is electrically connected with the first voltage end VG1, and the second electrode is electrically connected with the gate of the control transistor M3.

[0137] At the first sub-stage T11, the control transistor M3 is turned on, and the gate of the control transistor M3 receives an enable signal. Optionally, the second sub-module A40B comprises a fourth transistor M5; the fourth transistor M5 is turned on, the first electrode of the fourth transistor M5 receives a voltage signal transmitted by the first voltage end VG1, and the second electrode outputs the voltage signal to the gate of the control transistor M3. Optionally, the type of the control transistor M3 is N type, and then the control transistor M3 is turned on.

[0138] The first electrode of the third transistor M4 is electrically connected with the second voltage end VG2, the second electrode is electrically connected with the gate of the control transistor M3, and the gate is electrically connected with the same control line as the gate of the first transistor M1.

[0139] At the second sub-stage T12, the first module A10 is turned off, that is, the control transistor M3 is turned off, and the gate of the control transistor M3 receives a turn-off signal. Optionally, the first sub-module A40A comprises a third transistor M4; the third transistor M4 is turned on, the first electrode of the third transistor M4 receives an electric signal output by the second voltage end VG2, and the second electrode outputs the electric signal to the gate of the control transistor M3. Optionally, the type of the control transistor M3 is N type, and then the control transistor M3 is turned off.

[0140] In one embodiment of the present application, continuing to refer to Figure 17 、 Figure 18 As shown in the figure, the signal processing unit 20 further comprises a first charging transistor M6, the first electrode of the first charging transistor M6 is electrically connected with the first voltage end VG1, and the second electrode is electrically connected with the first electrode plate C11 of the first capacitor C1.

[0141] In the second stage T2, the first charging module is turned on to charge the first capacitor C1. Optionally, the first charging module A30 includes a first charging transistor M6; the first charging transistor M6 is turned on, the first pole of the first charging transistor M6 receives the electrical signal output by the first voltage terminal VG1, and the second pole outputs the electrical signal to the first pole plate C11 of the first capacitor C1, thereby completing the charging of the first capacitor C1 and preparing for the discharging of the first capacitor C1 in the next second sub-stage T12.

[0142] In an embodiment of the present application, continuing to refer to Figure 18 、 Figure 19 As shown in the figure, the signal processing unit 20 further includes a fourth transistor M5, the first pole of the fourth transistor M5 is electrically connected with the first voltage terminal VG1, and the second pole is electrically connected with the gate of the control transistor M3.

[0143] The gate of the fourth transistor M5 is electrically connected with the gate of the first charging transistor M6 through the same control line.

[0144] It can be analyzed that the fourth transistor M5 and the first charging transistor M6 can be turned on in the second stage T2 and turned off in the second sub-stage T12, and optionally, the fourth transistor M5 and the first charging transistor M6 are of the same type; therefore, electrically connecting the gate of the fourth transistor M5 with the gate of the first charging transistor M6 through the same control line is conducive to simultaneously controlling the fourth transistor M5 and the first charging transistor M6, thereby saving the number of control terminals in the circuit.

[0145] In an embodiment of the present application, continuing to refer to Figure 17 、 Figure 18 As shown in the figure, the signal processing unit 20 further includes a second charging transistor M7, the first pole of the second charging transistor M7 is electrically connected with the first voltage terminal VG1, and the second pole is electrically connected with the first pole plate C11 of the first capacitor C1; the gates of the second charging transistors M7 included in the plurality of signal processing units 20 are electrically connected with the same control line.

[0146] In the initial stage T0, the second charging modules A50 in the plurality of shift registers VSR are all turned on to reset the first capacitor C1. Optionally, the second charging module A50 includes the second charging transistor M7, and in the initial stage T0, the gates of the second charging transistors M7 in the plurality of shift registers VSR simultaneously receive the enable signal transmitted by the same control line, the second charging transistor M7 is turned on, at this time, the first pole of the second charging transistor M7 receives the electrical signal output by the first voltage terminal VG1, and the second pole outputs the electrical signal to the first pole C11 of the first capacitor C1, thereby completing the reset of the first capacitor C11.

[0147] An embodiment of the present application provides a display panel 200, continuing to refer to Figure 2As shown, the display panel 200 includes a plurality of scan lines Gate and the gate drive circuit 100 provided in the above embodiment, and the output end 102 of the shift register VSR in the gate drive circuit 100 is electrically connected with the scan line Gate. Optionally, the scan line Gate is electrically connected with the gate of the driving transistor Td in the display panel 200, to control the switching state of the driving transistor Td, and further control the light-emitting display of the pixel.

[0148] In the display panel 200, the signal processing unit 20 is configured to output the first signal V1 before the second signal V2 when outputting the enable signal in the first stage T1, so that the enable signal waveform output from the signal processing unit 20 includes the cut-off part and is received by the driving transistor Td in the pixel far from the gate drive circuit 100 in the same row, which is beneficial to make the waveform of the driving transistor Td receiving the enable signal earlier and the waveform of the driving transistor Td receiving the enable signal later both appear the trend of buffer drop near the off time, reduce the difference of the off time when outputting the enable signal at the near end and the far end of the gate drive circuit, reduce the difference of the coupling voltage generated at the near end and the far end of the gate drive circuit 100, and further reduce the difference of the electric field change at the near end and the far end of the gate drive circuit 100, reduce the influence of light-emitting flicker, and improve the display effect.

[0149] Figure 19 A schematic diagram of a display device provided in the embodiment of the present application.

[0150] The embodiment of the present application provides a display device 300, as shown in the figure. Figure 19 The display panel 200 provided in the above embodiment.

[0151] In the display device 300, the signal processing unit 20 is configured to output the first signal V1 before the second signal V2 when outputting the enable signal in the first stage T1, so that the enable signal waveform output from the signal processing unit 20 includes the cut-off part and is received by the driving transistor Td in the pixel far from the gate drive circuit 100 in the same row, which is beneficial to make the waveform of the driving transistor Td receiving the enable signal earlier and the waveform of the driving transistor Td receiving the enable signal later both appear the trend of buffer drop near the off time, reduce the difference of the off time when outputting the enable signal at the near end and the far end of the gate drive circuit, reduce the difference of the coupling voltage generated at the near end and the far end of the gate drive circuit 100, and further reduce the difference of the electric field change at the near end and the far end of the gate drive circuit 100, reduce the influence of light-emitting flicker, and improve the display effect.

[0152] The above only is the preferred embodiment of the present application, and is not used to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A driving method for a gate driving circuit, characterized in that, The gate drive circuit includes multiple cascaded shift registers, and the duty cycle of the shift registers includes a first stage; At least one of the shift registers includes: The first output unit is turned on in the first stage and outputs an enable signal in the first stage; A signal processing unit, the output terminal of which is electrically connected to the input terminal of the first output unit; the signal processing unit transmits the enable signal to the first output unit in the first stage; The first stage includes a first sub-stage and a second sub-stage, with the second sub-stage occurring after the first sub-stage; the signal processing unit transmits a first signal to the input terminal of the first output unit in the first sub-stage, and the signal processing unit transmits a second signal to the input terminal of the first output unit in the second sub-stage, wherein the absolute value of the voltage of the first signal is greater than the absolute value of the voltage of the second signal. The signal processing unit includes: The first module has its input terminal electrically connected to a first signal line and its output terminal electrically connected to the input terminal of the first output unit; the first module is turned on in the first sub-stage and the first clock signal line transmits a first signal in the first sub-stage. The second module has its output terminal electrically connected to the input terminal of the first output unit; the second module is turned on in the second sub-stage and transmits a second signal to the input terminal of the first output unit; the second module includes a first capacitor and a first transistor, the first electrode of the first transistor is electrically connected to the input terminal of the first output unit, and the second electrode is electrically connected to the first plate of the first capacitor; The first transistor is turned on in the second sub-stage and the first plate of the first capacitor discharges to the input terminal of the first output unit in the second sub-stage.

2. The driving method according to claim 1, characterized in that, The second module further includes a second transistor, wherein the first terminal of the second transistor is electrically connected to the ground terminal and the second terminal is electrically connected to the first plate of the first capacitor; The second transistor is turned on in the second sub-stage and the first plate of the first capacitor is electrically connected to the ground terminal in the second sub-stage.

3. The driving method according to claim 2, characterized in that, The gate of the first transistor is electrically connected to the first control line, and the gate of the second transistor is electrically connected to the second control line; both the first control line and the second control line transmit valid level signals in the second sub-stage to control the first transistor and the second transistor to turn on. The first control line transmits an effective level signal in the second sub-stage to control the first transistor to turn on, and the second control line transmits an effective level signal in the second sub-stage to control the second transistor to turn on.

4. The driving method according to claim 1, characterized in that, The signal processing unit further includes a first charging module, wherein a first end of the first charging module is electrically connected to a first voltage terminal and a second end is electrically connected to the first plate of the first capacitor. The shift register's operating cycle also includes a second phase, which occurs before the second sub-phase in the next operating cycle; the first charging module is activated in the second phase and charges the first capacitor.

5. The driving method according to claim 4, characterized in that, The signal processing unit further includes a third module, the output of which is electrically connected to the control terminal of the first module; the third module controls the first module to be turned on in the first sub-stage and turned off in the second sub-stage.

6. The driving method according to claim 5, characterized in that, The third module includes a first submodule and a second submodule; the input terminal of the first submodule is electrically connected to the second voltage terminal, and the output terminal is electrically connected to the control terminal of the first module; the input terminal of the second submodule is electrically connected to the first voltage terminal, and the output terminal is electrically connected to the control terminal of the first module. The first submodule is enabled in the second sub-stage and controls the first module to be disabled; the second submodule is enabled in the second stage and controls the first module to be enabled.

7. The driving method according to claim 1, characterized in that, The signal processing unit further includes a second charging module, the input terminal of which is electrically connected to the first voltage terminal, and the output terminal of which is electrically connected to the first plate of the first capacitor; the control terminals of the second charging modules included in the plurality of signal processing units are electrically connected to the same control line; The second charging module is turned on before the first stage and turned off in the second sub-stage.

8. A gate driving circuit, characterized in that, The gate drive circuit includes multiple cascaded shift registers, at least one of the shift registers including: First output unit, the first output unit outputs an enable signal; The signal processing unit includes a first capacitor, a first transistor, and a second transistor. The first terminal of the first transistor is electrically connected to the input terminal of the first output unit, and the second terminal is electrically connected to the first plate of the first capacitor. The first terminal of the second transistor is electrically connected to the ground terminal, and the second terminal is electrically connected to the first plate of the first capacitor. The shift register's operating cycle includes a first stage, during which the first output unit is enabled and outputs an enable signal; the signal processing unit transmits the enable signal to the first output unit during the first stage. The first stage includes a first sub-stage and a second sub-stage, with the second sub-stage occurring after the first sub-stage; the signal processing unit transmits a first signal to the input terminal of the first output unit in the first sub-stage, and the signal processing unit transmits a second signal to the input terminal of the first output unit in the second sub-stage, wherein the absolute value of the voltage value of the first signal is greater than the absolute value of the voltage value of the second signal. The first transistor is turned on in the second sub-stage and the first plate of the first capacitor discharges to the input terminal of the first output unit in the second sub-stage.

9. The gate driving circuit according to claim 8, characterized in that, The gate of the first transistor and the gate of the second transistor are electrically connected to the same control line.

10. The gate driving circuit according to claim 9, characterized in that, The gate of the first transistor is electrically connected to the first control line, and the gate of the second transistor is electrically connected to the second control line.

11. The gate driving circuit according to claim 8, characterized in that, The signal processing unit further includes a control transistor, wherein the first terminal of the control transistor is electrically connected to the first signal line and the second terminal of the control transistor is electrically connected to the input terminal of the first output unit.

12. The gate driving circuit according to claim 11, characterized in that, The signal processing unit further includes a third transistor and a fourth transistor; the first terminal of the fourth transistor is electrically connected to a first voltage terminal, and the second terminal is electrically connected to the gate of the control transistor; the first terminal of the third transistor is electrically connected to a second voltage terminal, the second terminal is electrically connected to the gate of the control transistor, and the gate of the third transistor is electrically connected to the same control line as the gate of the first transistor.

13. The gate driving circuit according to claim 9 or 12, characterized in that, The signal processing unit further includes a first charging transistor, wherein the first terminal of the first charging transistor is electrically connected to a first voltage terminal and the second terminal is electrically connected to the first plate of the first capacitor.

14. The gate driving circuit according to claim 13, characterized in that, The signal processing unit further includes a fourth transistor, wherein the first terminal of the fourth transistor is electrically connected to the first voltage terminal and the second terminal is electrically connected to the gate of the control transistor. The gate of the fourth transistor is electrically connected to the same control line as the gate of the first charging transistor.

15. The gate driving circuit according to claim 13, characterized in that, The signal processing unit further includes a second charging transistor, the first terminal of which is electrically connected to a first voltage terminal and the second terminal of which is electrically connected to the first plate of the first capacitor; the gates of the second charging transistors included in the plurality of signal processing units are electrically connected to the same control line.

16. A display panel, characterized in that, It includes multiple scan lines and the gate driving circuit as described in claims 8-15, wherein the output terminal of the shift register in the gate driving circuit is electrically connected to the scan lines.

17. A display device, characterized in that, Includes the display panel as described in claim 16.

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