A display panel, a driving method of the display panel, and a display device

Abstract

The application discloses a display panel, a driving method of the display panel and a display device. The display panel comprises a driving circuit. The driving circuit comprises a plurality of shift register units. The shift register unit comprises a driving control module, a stage transmission module and a scanning module. The driving control module comprises a start input end, a scanning control end, a first node and a second node. The stage transmission module comprises a first input end, a second input end, a first level end, a stage transmission clock end and a stage transmission output end. The first input end is electrically connected with the first node, and the second input end is electrically connected with the second node. The stage transmission output end of the i-th shift register unit is electrically connected with the start input end of the j-th shift register unit. The scanning module comprises a third input end, a fourth input end, a second level end, a scanning clock end and a scanning output end. The third input end is electrically connected with the first node. By adopting the technical scheme, the display panel can realize partition frequency display, and the power consumption of the display panel can be reduced under the premise of ensuring display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel, a driving method for the display panel, and a display device. Background Technology

[0002] With the development of display technology, display panels are being used in more and more scenarios, and users' display needs for display panels are becoming more and more diversified.

[0003] Some display areas on the display panel require high-frequency display to ensure smooth video playback, such as the short video display area in short video applications. Other display areas can meet display requirements with low-frequency display, such as static comment areas, menu areas, or black borders. These areas are expected to use low-frequency display to reduce power consumption.

[0004] Currently, all display areas of the display panel have the same refresh rate, which cannot meet the display requirements of zoned frequency refresh. Summary of the Invention

[0005] This invention provides a display panel, a driving method for the display panel, and a display device, enabling the display panel to have a segmented frequency display function and reducing power consumption.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a driving circuit; the driving circuit includes a plurality of cascaded shift register units; The shift register unit includes a drive control module, at least one transmission module, and at least one scanning module; The drive control module includes at least a start input terminal, a scan control terminal, a first node, and a second node; The stage transmission module includes a first input terminal, a second input terminal, a first level terminal, a stage transmission clock terminal, and a stage transmission output terminal; the first input terminal is electrically connected to the first node, and the second input terminal is electrically connected to the second node; the first level terminal is electrically connected to the first fixed potential terminal; wherein, the stage transmission output terminal of the i-th stage shift register unit is electrically connected to the start input terminal of the j-th stage shift register unit, i≠j, and i and j are both positive integers; The scanning module includes a third input terminal, a fourth input terminal, a second level terminal, a scanning clock terminal, and a scanning output terminal; the third input terminal is electrically connected to the first node; and the second level terminal is electrically connected to the first fixed potential terminal.

[0007] According to another aspect of the present invention, a method for driving a display panel is provided for driving the display panel described in the claims; The display panel includes a multi-frequency drive mode; at least a portion of the display frames in the multi-frequency drive mode are first display frames; the first display frame includes a refresh phase and a hold phase; The driving methods include: During the refresh phase, both the stage transmission output terminal and the scan output terminal of the control section shift register unit output valid pulses; During the hold phase, the stage transmission output terminal of the control section shift register unit outputs a valid pulse, while the scan output terminal is at an invalid level.

[0008] According to another aspect of the present invention, a display device is provided, including the above-described display panel.

[0009] The technical solution of this invention, by setting a scanning module in the shift register unit, enables the shift register unit to output a scanning signal for controlling pixel refresh. In consecutive display frames, when the data signals to be written to pixels in some areas are consecutively the same or similar, the scanning module of some shift register units can also stop outputting effective pulses of the scanning signal, reducing the refresh frequency of pixels in some areas, thereby reducing the power consumption of the display panel. In addition, by setting a cascading module in the shift register unit, the shift register unit can output a cascading signal for the shift start input signal. When the scanning module of some shift register units stops outputting effective pulses of the scanning signal, it can ensure that the start input signal of that part of the shift register unit can still continue to shift, so that subsequent shift register units can still be driven and output effective pulses of the scanning signal. Other areas can still refresh at a higher frequency. While reducing the refresh frequency of pixels in some areas, it can also meet the higher refresh frequency requirements for smooth display in some areas, thereby reducing the power consumption of the display panel while ensuring display quality.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention; Figure 5 This is a timing diagram of a driving circuit provided in an embodiment of the present invention; Figure 6 This is a timing diagram of another driving circuit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a switch provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a transmission module provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a scanning module provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of another scanning module provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another scanning module provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another scanning module provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 18 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 20 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention; Figure 23 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 24 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention; Figure 25 This is a schematic diagram of the structure of a global scanning unit provided in an embodiment of the present invention; Figure 26 This is a schematic diagram of the structure of a global reset unit provided in an embodiment of the present invention; Figure 27 This is a flowchart of a driving method for a display panel provided in an embodiment of the present invention; Figure 28 This is a timing diagram of a display panel in multi-frequency driving mode provided by an embodiment of the present invention; Figure 29 This is a flowchart of another display panel driving method provided in an embodiment of the present invention; Figure 30 This is a timing diagram of another display panel in multi-frequency driving mode provided by an embodiment of the present invention; Figure 31 This is a flowchart of another display panel driving method provided in an embodiment of the present invention; Figure 32 This is a timing diagram of another display panel in multi-frequency driving mode provided by an embodiment of the present invention; Figure 33 This is a timing diagram of a shift register unit during the refresh phase provided in an embodiment of the present invention; Figure 34 This is a flowchart of another display panel driving method provided in an embodiment of the present invention; Figure 35 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] As described in the background section, the driving circuit of the display panel can control all pixels to refresh or stop refreshing. During the refresh time of one frame, the refresh frequency of all areas of the display panel is the same. If the refresh frequency of the display panel is reduced, although the power consumption is reduced, it cannot meet the requirements for smooth video display. If a high refresh frequency of all areas of the display panel is required to meet the requirements for smooth video display, it will be detrimental to the low power consumption of the display panel.

[0016] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a driving circuit; the driving circuit includes multiple cascaded shift register units; each shift register unit includes a driving control module, at least one cascaded transfer module, and at least one scanning module; the driving control module includes at least a start input terminal, a scanning control terminal, a first node, and a second node; the cascaded transfer module includes a first input terminal, a second input terminal, a first level terminal, a cascaded transfer clock terminal, and a cascaded transfer output terminal; the first input terminal is electrically connected to the first node, and the second input terminal is electrically connected to the second node; the first level terminal is electrically connected to a first fixed potential terminal; wherein, the cascaded transfer output terminal of the i-th cascaded shift register unit is electrically connected to the start input terminal of the j-th cascaded shift register unit, i ≠ j, and i and j are both positive integers; the scanning module includes a third input terminal, a fourth input terminal, a second level terminal, a scanning clock terminal, and a scanning output terminal; the third input terminal is electrically connected to the first node; the second level terminal is electrically connected to the first fixed potential terminal.

[0017] By employing the above technical solution, by setting a scanning module in the shift register unit, the shift register unit can output a scanning signal for controlling pixel refresh. In consecutive display frames, when the data signals to be written to pixels in some areas are consecutively the same or similar, the scanning modules of some shift register units can also stop outputting valid pulses of the scanning signal, reducing the refresh frequency of pixels in some areas, thereby reducing the power consumption of the display panel. In addition, by setting a cascading module in the shift register unit, the shift register unit can output a cascading signal for the shift start input signal. When the scanning modules of some shift register units stop outputting valid pulses of the scanning signal, it can ensure that the start input signal of those shift register units can still continue to shift, so that subsequent shift register units can still be driven and output valid pulses of the scanning signal. Other areas can still refresh at a higher frequency. While reducing the refresh frequency of pixels in some areas, it can also meet the higher refresh frequency requirements for smooth display in some areas, thereby reducing the power consumption of the display panel while ensuring display quality.

[0018] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0019] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention, for reference. Figure 1 The display panel 001 includes a driving circuit 10, multiple scan lines SL, multiple data lines DL, and multiple pixels P located in the display area AA. At least some of the pixels P located in the same row can be electrically connected to the same scan line SL, and at least some of the pixels P located in the same column can be electrically connected to the same data line DL.

[0020] The driving circuit 10 includes multiple cascaded shift register units 20. The first-stage shift register unit 20 can receive a first start signal as a start input signal. Starting from the second stage, the start input signal of each stage shift register unit 20 comes from the previous stage shift register unit 20, but is not limited to the previous stage shift register unit 20. The scan signals output by each stage shift register unit 20 can be shifted sequentially. The shift register unit 20 is electrically connected to at least one scan line SL to provide a scan signal for the scan line SL. For example, when the scan signal transmitted on the scan line SL is at an active level, the switching device in a row of pixels P electrically connected to the scan line SL can be controlled to open, so that the row of pixels P electrically connected to the scan line SL can receive the data signal transmitted on the data line DL and display it as the corresponding gray level according to the data signal, thereby realizing the refresh of the pixel P electrically connected to the scan line SL.

[0021] In an optional embodiment, the driving circuit 10 further includes a source driving circuit 30, which is electrically connected to multiple data lines DL to provide data signals to the data lines DL. For example, during the pixel refresh time of a row of pixels P, the source driving circuit 30 can provide multiple data signals to the multiple data lines DL, causing the row of pixels P to be displayed as a corresponding grayscale based on the data signals provided by the source driving circuit 30. During the pixel refresh time of the next row of pixels P, the source driving circuit 30 can again provide multiple data signals to the multiple data lines DL, causing the next row of pixels P to be displayed as a corresponding grayscale based on the data signals again provided by the source driving circuit 30.

[0022] It should be noted that, Figure 1 The figure only shows, by way of example, the driving circuit 10 located in the non-display area NA outside the display area AA. In other feasible embodiments, the driving circuit 10 may also be located in the display area AA. In addition, the figure only shows, by way of example, the shift register unit 20 located on the left and lower sides of the display area AA. In other feasible embodiments, the driving circuit 10 may also be located on other sides of the display area AA, or simultaneously on one, three, four, etc., sides of the display area AA. The embodiments of the present invention do not limit the position of the driving circuit 10.

[0023] Figure 2 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. If the display panel 001 is an LED display when it is working, the pixel P may include a write transistor M02, a drive transistor M03, a storage capacitor Cst, and a light-emitting element LED. At this time, the pixel P receives a scan signal from the scan line SL, a data signal from the data line DL, a first power signal PVDD, and a second power signal PVEE, as shown below. Figure 2As shown, the write transistor M02, under the control of the scan signal on the scan line SL, writes the data signal on the data line DL to the gate of the drive transistor M03. The drive transistor M03, according to the data signal, provides a corresponding drive current to the light-emitting element LED to drive the LED to emit light, causing pixel P to display the corresponding grayscale. If the display panel 001 is a liquid crystal display during operation, pixel P may include the write transistor M02, liquid crystal capacitor Clc, storage capacitor Cst, pixel electrode Vp, and common electrode Vcom. In this case, pixel P receives the scan signal from the scan line SL, the data signal from the data line DL, and the common electrode signal, as shown... Figure 3 As shown, the write transistor M02 can write the data signal to the pixel electrode Vp under the control of the scan signal. The liquid crystal capacitor Clc can store the data signal on the pixel electrode Vp. An electric field is formed between the pixel electrode Vp and the common electrode Vcom, which can control the rotation of the liquid crystal molecules (not shown in the figure) and adjust the light flux, so that the pixel P displays the corresponding gray level.

[0024] It should be noted that, Figure 2 and Figure 3 The circuit structure diagram of pixel P is only shown as an example. In other feasible embodiments, pixel P may also include other devices. The embodiments of the present invention do not specifically limit the type of display panel or the specific structure of pixel P.

[0025] Figure 4 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention, with reference to... Figure 4 The shift register unit includes a drive control module 210, at least one stage transfer module 220, and at least one scan module 230. The drive control module 210 includes at least a start input terminal INF, a scan control terminal U2D, a first node N1, and a second node N2. The stage transfer module 220 includes a first input terminal in01, a second input terminal in02, a first level terminal v01, a stage transfer clock terminal NCLK, and a stage transfer output terminal NEXT. The first input terminal in01 is electrically connected to the first node N1, the second input terminal in02 is electrically connected to the second node N2, and the first level terminal v01 is electrically connected to the first fixed potential terminal VGL. The stage transfer output terminal NEXT of the i-th stage shift register unit 20(i) is electrically connected to the start input terminal of the j-th stage shift register unit 20(j), where i ≠ j, and i and j are both positive integers. The scanning module 230 includes a third input terminal in03, a fourth input terminal in04, a second level terminal v02, a scanning clock terminal GCLK, and a scanning output terminal GOUT. The third input terminal in03 is electrically connected to the first node N1; the second level terminal v02 is electrically connected to the first fixed potential terminal VGL.

[0026] Specifically, the start input terminal INF and the scan control terminal U2D of the drive control module 210 can receive the start input signal and the scan control signal, respectively. The drive control module 210 can control the signals of the first node N1 and the second node N2 according to the start input signal and the scan control signal. The first input terminal in01, the second input terminal in02, the first level terminal v01, and the stage transmission clock terminal NCLK of the stage transmission module 220 can receive the signals of the first node N1, the second node N2, the first fixed potential signal, and the stage transmission clock signal, respectively. The stage transmission module 220 can control the stage transmission signal of the stage transmission output terminal NEXT according to the signals of the first node N1, the second node N2, the first fixed potential signal, and the stage transmission clock signal. The third input terminal in03, the second level terminal v02, and the scan clock terminal GCLK of the scanning module 230 receive the signal from the first node N1, the first fixed potential signal, and the scan clock signal, respectively. The scanning module 230 can control the scan signal of the scan output terminal GOUT according to the signal from the first node N1, the signal from the fourth input terminal in04, the first fixed potential signal, and the scan clock signal. The scan output terminal GOUT is electrically connected to the scan line SL.

[0027] For example, the transmission module 220 and the scanning module 230 can receive different signals, and / or the transmission module 220 and the scanning module 230 can have different structures, such that the transmission signal output by the transmission output terminal NEXT of the transmission module 220 and the scanning signal output by the scanning output terminal GOUT of the scanning module 230 can be different.

[0028] Taking a driving circuit comprising z cascaded shift register units 20 as an example, where both the effective level of the transmission signal and the effective level of the scan signal are high. Figure 5 This is a timing diagram of a driving circuit provided in an embodiment of the present invention. (Reference) Figure 4 and Figure 5The display panel 001 includes a multi-frequency drive mode. During at least a portion of the refresh time of the display frame DF in the multi-frequency drive mode, the potentials of the stage transmission signal output by the stage transmission output terminal NEXT and the scan signal output by the scan output terminal GOUT of the same shift register unit 20 can be different. During the refresh time of a display frame DF, each stage transmission output terminal NEXT of the shift register unit 20 can output a valid pulse of the stage transmission signal, and the valid pulses of the stage transmission signal output by each stage shift register unit 20 are shifted sequentially. In the first stage pt1 of the partial display frame DF, both the stage transmission output terminal NEXT and the scan output terminal GOUT of the partial shift register unit 20 can output valid pulses. The valid pulses of the stage transmission signal and the valid pulses of the scan signal are shifted sequentially, so that the pixels P of the partial display area AA can be refreshed row by row. This partial display area AA can be refreshed at a higher frequency. In the second stage pt2 of the partial display frame DF, the stage transmission output terminal NEXT of the partial shift register unit 20 can output valid pulses, but the scan output terminal GOUT of the partial shift register unit 20 stops outputting valid pulses of the scan signal, so that the pixels P of the partial display area AA stops refreshing. This partial display area AA can be refreshed at a lower frequency, thereby realizing the segmented frequency refresh of the display panel 001.

[0029] During the refresh time of a display frame DF, except for the last shift register unit 20, the cascading module 220 of each shift register unit 20 can sequentially output the effective pulse of the cascading signal as the starting input signal of the next shift register unit 20, thereby realizing the sequential shifting of the effective pulse of the starting input signal, that is, realizing the sequential driving of each shift register unit 20. By setting a transmission module 220 in the shift register unit 20, in the multi-frequency drive mode, when the scanning module 230 of some shift register units 20 stops outputting valid pulses of the scanning signal in the second stage pt2 of a display frame DF, the transmission module 220 enables those shift register units 20 to still achieve sequential shifting of the initial input signal; thus, in the first stage pt1 after the second stage pt2 of a display frame DF, the subsequent shift register units 20 can still receive the shifted initial input signal sequentially, that is, the subsequent shift register units 20 can still be driven sequentially, so that the subsequent shift register units 20 can output valid pulses of the scanning signal sequentially, realizing the segmented frequency refresh of the display panel 001.

[0030] In this embodiment of the invention, by incorporating a scanning module within the shift register unit, the shift register unit can output a scanning signal for controlling pixel refresh. In consecutive display frames, when the data signals to be written to pixels in certain areas are consecutively the same or similar, the scanning modules of some shift register units can stop outputting valid pulses of the scanning signal, reducing the refresh frequency of pixels in those areas and thus reducing the power consumption of the display panel. Furthermore, by incorporating a cascading module within the shift register unit, the shift register unit can output a cascading signal for the shift start input signal. When the scanning modules of some shift register units stop outputting valid pulses of the scanning signal, the start input signal of those shift register units can still continue to shift, allowing subsequent shift register units to still be driven and output valid pulses of the scanning signal. Other areas can still refresh at a higher frequency. This reduces the refresh frequency of pixels in some areas while still meeting the higher refresh frequency requirements for smooth display in those areas, thereby reducing the power consumption of the display panel while ensuring display quality.

[0031] Optionally, in the same shift register unit, the cascade clock terminal and the scan clock terminal are not connected.

[0032] Specifically, in the same shift register unit, the stage clock signal received by the stage clock terminal and the scan clock signal received by the scan clock terminal can be different, which allows the stage output signal and the scan output signal to be different in the same shift register unit.

[0033] For example, taking a scenario where all valid voltage levels are high, invalid voltage levels are low, and the first fixed voltage terminal VGL is low, as an example... Figure 6 This is a timing diagram of another driving circuit provided in an embodiment of the present invention, for reference. Figure 4 and Figure 6The display panel 001 includes a multi-frequency drive mode. In the second stage pt2 of the partial display frame DF in the multi-frequency drive mode, the cascading clock signal received by the cascading clock terminal NCLK includes valid pulses, while the scanning clock signal received by the scanning clock terminal GCLK is always at an invalid level. In the second stage pt2, the cascading module 220 of the shift register unit 20 can receive a high-level cascading clock signal and a low-level first fixed potential signal. Under the control of the signals of the first node N1 and the second node N2, at least part of the cascading module 220 of the shift register unit 20 can output a high-level cascading signal. In the second stage pt2, the scanning module 230 of the shift register unit 20 can receive a low-level scanning clock signal and a low-level first fixed potential signal. Under the control of the signals of the first node N1 and the fourth input terminal in04, the scanning module 230 of the shift register unit 20 outputs a low-level scanning signal. In this way, when the scanning module 230 of the same shift register unit 20 stops outputting valid pulses of the scanning signal, the stage transmission module 220 can still output valid pulses of the stage transmission signal normally, ensuring that the initial input signal of the shift register unit 20 can be shifted normally, so that the subsequent stage shift register units 20 can still output valid pulses of the scanning signal, thereby realizing the segmented frequency refresh of the display panel 001.

[0034] In an optional embodiment, in practical applications, the cascading clock terminal NCLK and the scanning clock terminal GCLK of the shift register unit 20 can be electrically connected to the display driver chip (not shown in the figure). By changing the timing design of the display driver chip, it can be made so that in the second stage pt2, the cascading clock signal received by the cascading clock terminal NCLK includes valid pulses, while the scanning clock signal received by the scanning clock terminal GCLK is always at an invalid level.

[0035] In yet another alternative embodiment, Figure 7 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention, for reference. Figure 7 The driving circuit 10 includes multiple output clock lines (GCK1, GCK2), multiple first clock terminals (ACK1, ACK2), multiple switches KK, and a first refresh control terminal Goff1. The input terminal of switch KK is electrically connected to a first clock terminal (ACK1 or ACK2). The output terminal of switch KK is electrically connected to an output clock line (GCK1 or GCK2). Each output clock line can be electrically connected to the scan clock terminal GCLK of multiple shift register units 20. The control terminal KK of the switch is electrically connected to the first refresh control terminal Goff1.

[0036] Specifically, switch KK, under the control of the first refresh control signal at the first refresh control terminal Goff1, controls the transmission path of the scan clock signal to the scan clock terminal GCLK. When switch KK is on, the scan clock terminal GCLK of shift register unit 20 can receive the periodically changing scan clock signal from the first clock terminal (ACK1 or ACK2), and at least some of the scan modules 230 of shift register unit 20 can output valid pulses of the scan signal; when switch KK is off, the scan clock terminal GCLK of shift register unit 20 cannot receive the periodically changing scan clock signal from the first clock terminal (ACK1 or ACK2), and the scan modules 230 of shift register unit 20 cannot output valid pulses of the scan signal, causing pixels in some areas to stop refreshing. This reduces the refresh frequency of only that area without changing the refresh frequency of other areas, achieving segmented frequency distribution.

[0037] For example, the driving circuit 10 also includes multiple shift clock lines (NCK1, NCK2) and multiple second clock terminals (BCK1, BCK2). In practical applications, the first refresh control terminal Goff1, the first clock terminals (ACK1, ACK2), and the second clock terminals (BCK1, BCK2) are all electrically connected to the display driver chip (not shown in the figure). The display driver chip (not shown in the figure) can provide the display panel 001 with a first refresh control signal, a scan clock signal, and a transmission clock signal. The display driver chip (not shown in the figure) can continuously provide the display panel 001 with a periodically changing scan clock signal and a periodically changing transmission clock signal. By providing the display panel 001 with first refresh control signals at different potentials, the switch KK can be turned on / off, thereby indirectly controlling the signal of the scan clock terminal GCLK of the shift register unit 20, thereby realizing the segmentation and frequency division of the display panel 001.

[0038] By setting a switch between the first clock terminal and the output clock line, on the one hand, the design of the clock section in the display driver chip can be simplified, and the clock section of the driver chip can change normally without changing its changing rules, which is conducive to reducing development costs and shortening the development cycle; on the other hand, compared with setting a refresh control module in each shift register unit, multiple shift register units in this application can share a single switch, which is beneficial to the thinning and narrowing of the display panel.

[0039] In an alternative implementation, Figure 8 This is a schematic diagram of a switch provided in an embodiment of the present invention, for reference. Figure 8Switch KK includes a first switching transistor K01 and a second switching transistor K02; the first terminal of the first switching transistor K01 is electrically connected to the first clock terminal ACK1; the second terminal of the first switching transistor K01 is electrically connected to the output clock line GCK1; the first terminal of the second switching transistor K02 is electrically connected to the first fixed potential terminal VGL; the second terminal of the second switching transistor K02 is electrically connected to the output clock line GCK1; the gates of the first switching transistor K01 and the gates of the second switching transistor K02 are both electrically connected to the first refresh control terminal Goff1.

[0040] For example, taking a scenario where the active level is high, the inactive level is low, and the potential of the first fixed potential terminal VGL is low, refer to... Figure 8 The first switching transistor K01 and the second switching transistor K02 are both N-type transistors. The first refresh control terminal Goff1 includes a first sub-control terminal Goff101 and a second sub-control terminal Goff102. The first sub-control terminal Goff101 is electrically connected to the gate of the first switching transistor K01, and the second sub-control terminal Goff102 is electrically connected to the gate of the second switching transistor K02. When the first sub-control terminal Goff101 is high and the second sub-control terminal Goff102 is low, the first switching transistor K01 is turned on and the second switching transistor K02 is turned off. The scan clock signal of the first clock terminal ACK1 can be transmitted to the output clock line GCK1, thereby making the potential of the scan clock terminal GCLK high, and at least part of the shift register unit 20's scan module 230 can output a valid pulse of the scan signal. When the first sub-control terminal Goff101 is low and the second sub-control terminal Goff102 is high, the first switching transistor K01 is turned off and the second switching transistor K02 is turned on. The scan clock signal of the first clock terminal ACK1 cannot be transmitted to the output clock line GCK1, and the potential of the output clock line GCK1 is low, thereby making the potential of the scan clock terminal GCLK low. The shift register unit 20's scan module 230 cannot output a valid pulse of the scan signal, and at least part of the display area stops refreshing. It is understandable that when the channel types of the first switching transistor K01 and the second switching transistor K02 are opposite, the first sub-control terminal Goff101 and the second sub-control terminal Goff102 can be reused.

[0041] By setting a first switching transistor and a second switching transistor in the switch, the first switching transistor can control the transmission path of the scan clock signal from the first clock terminal to the scan clock terminal under the control of the signal from the first sub-control terminal; when the first switching transistor interrupts the transmission path of the scan clock signal, the second switching transistor can reset the output clock line to ensure that the scan clock signal on the output clock line can remain at a low level, so that some shift register units cannot output valid pulses of the scan signal, thereby causing some display areas to stop refreshing and realizing segmented frequency.

[0042] Based on the above embodiments, Figure 9 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 9 In the same shift register unit 20, the fourth input terminal in04 is electrically connected to the second node N2.

[0043] Specifically, in the same shift register unit 20, when the stage transfer clock signal received by the stage transfer clock terminal NCLK is different from the scan clock signal received by the scan clock terminal GCLK, the stage transfer signal output by the stage transfer output terminal NEXT and the scan signal output by the scan output terminal GOUT in the same shift register unit 20 can be different. At this time, the signals received by other signal terminals of the stage transfer module 220 and the scan module 230 can be the same.

[0044] For example, in the same shift register unit 20, the cascading clock signal received by the cascading clock terminal NCLK and the scanning clock signal received by the scanning clock terminal GCLK may be different. The structures of the cascading module 220 and the scanning module 230 may be the same, but are not limited thereto.

[0045] In an optional embodiment, Figure 10 This is a schematic diagram of the structure of a cascading module provided in an embodiment of the present invention, with reference to... Figure 10 The stage transmission module 220 includes a first stage transmission unit 221 and a second stage transmission unit 222. The input terminal of the first stage transmission unit 221 is electrically connected to the first fixed potential terminal VGL, the output terminal of the first stage transmission unit 221 is electrically connected to the stage transmission output terminal NEXT, and the control terminal of the first stage transmission unit 221 is electrically connected to the first input terminal in01. The input terminal of the second stage transmission unit 222 is electrically connected to the stage transmission clock terminal NCLK, the output terminal of the second stage transmission unit 222 is electrically connected to the stage transmission output terminal NEXT, and the control terminal of the second stage transmission unit 222 is electrically connected to the second input terminal in02.

[0046] For example, the first stage transmission unit 221 includes a first stage transmission transistor Tr5, the gate of which is electrically connected to the first node N1, the first terminal of which is electrically connected to the first fixed potential terminal VGL, and the second terminal of which is electrically connected to the stage transmission output terminal NEXT; the second stage transmission unit 222 includes a second stage transmission transistor Tr6, the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the stage transmission clock terminal NCLK, and the second terminal of which is electrically connected to the stage transmission output terminal NEXT.

[0047] In addition, the second stage transmission unit 222 may also include a stage transmission bootstrap capacitor C0 and a stage transmission Zener transistor Tr9. The first terminal of the stage transmission bootstrap capacitor C0 is electrically connected to the gate of the second stage transmission transistor Tr6, and the second terminal of the stage transmission bootstrap capacitor C0 is electrically connected to the stage transmission output terminal NEXT. The first terminal of the stage transmission Zener transistor Tr9 is electrically connected to the second node N2, the second terminal of the stage transmission Zener transistor Tr9 is electrically connected to the first terminal of the stage transmission bootstrap capacitor C0, and the gate of the stage transmission Zener transistor Tr9 is electrically connected to the second fixed potential terminal VGH. Taking the transistors in the stage transmission module 220 as N-type transistors and the second fixed potential terminal VGH as a high level as an example, when the gate of the second stage transmission transistor Tr6 is high, the second stage transmission transistor Tr6 is turned on. When the stage transmission clock signal drives the stage transmission output terminal NEXT to pull up, the stage transmission bootstrap capacitor C0 can couple the gate of the second stage transmission transistor Tr6 high, compensate for the threshold voltage of the second stage transmission transistor Tr6, which is conducive to the complete opening of the second stage transmission transistor Tr6, reduces the signal delay of the stage transmission signal, and improves the accuracy of the stage transmission signal.

[0048] It should be noted that the figure only shows the case where all transistors in the cascade module are N-type transistors. In other alternative embodiments, some or all of the transistors in the cascade module may also be P-type transistors.

[0049] In yet another alternative embodiment, Figure 11 This is a schematic diagram of the structure of a scanning module provided in an embodiment of the present invention, with reference to... Figure 11 The scanning module 230 includes a first scanning unit 231 and a second scanning unit 232. The input terminal of the first scanning unit 231 is electrically connected to a first fixed potential terminal VGL, the output terminal of the first scanning unit 231 is electrically connected to a scan output terminal GOUT, and the control terminal of the first scanning unit 231 is electrically connected to a third input terminal in03. The input terminal of the second scanning unit 232 is electrically connected to a scan clock terminal GCLK, the output terminal of the second scanning unit 232 is electrically connected to a scan output terminal GOUT, and the control terminal of the second scanning unit 232 is electrically connected to a fourth input terminal in04.

[0050] For example, the first scanning unit 231 includes a first scanning transistor Tr5', the gate of which is electrically connected to the first node N1, the first terminal of which is electrically connected to the first fixed potential terminal VGL, and the second terminal of which is electrically connected to the scan output terminal GOUT; the second scanning unit 232 includes a second scanning transistor Tr6', the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the scan clock terminal GCLK, and the second terminal of which is electrically connected to the scan output terminal GOUT.

[0051] In addition, the second scanning unit 232 may also include a scanning bootstrap capacitor C2 and a scanning Zener transistor Tr9'. The first terminal of the scanning bootstrap capacitor C2 is electrically connected to the gate of the second scanning transistor Tr6', and the second terminal of the scanning bootstrap capacitor C2 is electrically connected to the scanning output terminal GOUT. The first terminal of the scanning Zener transistor Tr9' is electrically connected to the second node N2, the second terminal of the scanning Zener transistor Tr9' is electrically connected to the first terminal of the scanning bootstrap capacitor C2, and the gate of the scanning Zener transistor Tr9' is electrically connected to the second fixed potential terminal VGH. Taking the transistors in the scanning module 230 as N-type transistors and the potential of the second fixed potential terminal VGH as an example, when the gate of the second scanning transistor Tr6' is high, the second scanning transistor Tr6' is turned on. When the scanning clock signal drives the scanning signal of the scanning output terminal GOUT to pull up, the scanning bootstrap capacitor C2 can couple the gate of the second scanning transistor Tr6' high, compensate for the threshold voltage of the second scanning transistor Tr6', which is beneficial to the full turn-on of the second scanning transistor Tr6', reduce the signal delay of the scanning signal, and improve the accuracy of the scanning signal.

[0052] It should be noted that the figure only shows an example of the case where all transistors in the scanning module are N-type transistors. In other alternative embodiments, some or all of the transistors in the scanning module may also be P-type transistors.

[0053] Optional, Figure 12 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 12In the same shift register unit 20, the fourth input terminal in04 is electrically connected to the stage transmission output terminal NEXT. The scanning module 230 includes a first scanning unit 231, a second scanning unit 232, and a second refresh control terminal Goff2. The input terminal of the first scanning unit 231 is electrically connected to the first fixed potential terminal VGL; the output terminal of the first scanning unit 231 is electrically connected to the scan output terminal GOUT; the control terminal of the first scanning unit 231 is electrically connected to the third input terminal in03; the input terminal of the second scanning unit 232 is electrically connected to the scan clock terminal GCLK; the output terminal of the second scanning unit 232 is electrically connected to the scan output terminal GOUT; the first control terminal of the second scanning unit 232 is electrically connected to the fourth input terminal in04; and the second control terminal of the second scanning unit 232 is electrically connected to the second refresh control terminal Goff2.

[0054] For example, taking a high level for the effective level and a low level for the invalid level, with the first fixed potential terminal VGL at a low level, in the same shift register unit 20, the first scan unit 231 can pull down the potential of the scan output terminal GOUT under the control of the signal of the first node N1, making the scan signal invalid. The second scan unit 232 can output the scan clock signal of the scan clock terminal GCLK as the scan signal when the stage transmission signal output by the stage transmission terminal NEXT is high and the second refresh control signal of the second refresh control terminal Goff2 is also high. That is, when both the stage transmission signal and the second refresh control signal are at an effective level, the second scan unit 232 can output an effective pulse of the scan clock signal. When any one or both of the stage transmission signal and the second refresh control signal are at an invalid level, the second scan unit 232 stops outputting an effective pulse of the scan clock signal.

[0055] By setting the fourth input terminal in04 to be electrically connected to the stage transmission output terminal NEXT, and the first control terminal of the second scanning unit 232 to be electrically connected to the stage transmission output terminal NEXT, and the second control terminal of the second scanning unit 232 to be electrically connected to the second refresh control terminal Goff2, on the one hand, the potential of the second refresh control terminal Goff2 can be controlled to control whether the shift register unit 20 can output a valid pulse of the scanning signal, thereby controlling whether the pixel electrically connected to the shift register unit 20 can be refreshed, thus realizing the division and frequency separation; on the other hand, when the stage transmission signal of the stage transmission output terminal NEXT is at an effective level, the stage transmission clock terminal NCL The stage clock signal of K charges the stage output terminal NEXT, stabilizing the potential of the stage output terminal NEXT. This ensures that the potential of the first control terminal of the second scanning unit 232 also remains stable. That is, when the potential of the first control terminal of the second scanning unit 232 is at an effective level, the signal of the first control terminal is an active signal (provided by the stage clock signal through the stage output terminal NEXT). This ensures that the first control terminal is at a stable effective level. At this time, whether the shift register unit 20 can output an effective pulse of the scanning signal is only controlled by the second refresh control signal of the second refresh control terminal Goff2, which is beneficial to the accuracy of the scanning signal.

[0056] It is understandable that the refresh control terminals of multiple shift register units can be electrically connected, meaning that the second refresh control terminals of each shift register unit can be electrically connected to the same signal line (not shown in the figure), and the second refresh control signals received by the second refresh control terminals of each shift register unit are the same. By controlling the second refresh control signals received by the second refresh control terminals of each shift register unit to be at an effective level during a certain period of a display frame, it is possible to enable some shift register units to output effective pulses of the scan signal when some shift register units are driven and the cascading module can output effective pulses of the cascading signal, thereby refreshing the pixels in a certain area. Alternatively, by controlling the second refresh control signals received by the second refresh control terminals of each shift register unit to be at an ineffective level during a certain period of a display frame, although some shift register units are driven and the cascading module can output effective pulses of the cascading signal, these shift register units cannot output effective pulses of the scan signal, causing the pixels in a certain area to stop refreshing, thus achieving segmented frequency.

[0057] It is also understandable that whether the shift register unit can output a valid pulse of the scan signal depends on the transmission signal and the second refresh control signal received by the scan module. Other signals received by the scan module do not need to be specially designed. For example, during the refresh time of a display frame, the scan clock signal received by the scan module can always be periodically changing. There is no need to control the scan clock signal to an invalid level during a certain period of time. This is beneficial to simplify the design of the clock part in the display driver chip. The clock part of the driver chip can always change normally without changing its changing rules, which is beneficial to reduce development costs and shorten the development cycle.

[0058] In an optional embodiment, Figure 13 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 12 and Figure 13 In the same shift register unit 20, the number of cascade modules 220 is equal to the number of scan modules 230; one cascade module 220 and one scan module 230 constitute an output group; the scan clock terminal GCLK of the same output group is electrically connected to the cascade clock terminal NCLK.

[0059] Specifically, the scan clock signal at the scan clock terminal GCLK can continuously transition normally. When the scan module 230 needs to stop outputting valid pulses of the scan signal, the second refresh control signal of the second refresh control Goff2 can be set to an invalid level, preventing the scan output terminal GOUT of the scan module 230 from outputting valid pulses. During the refresh time of a display frame, both the cascade clock signal and the scan clock signal include valid pulses that transition normally. For the same output group, the cascade clock signal and the scan clock signal can be completely identical and multiplexed. This reduces the number of clock lines and clock signals, simplifying circuit and timing design.

[0060] For example, refer to Figure 13 The shift register unit 20 includes two cascade modules 220 and two scanning modules 230, i.e. two output groups. The cascade clock terminal NCLK1 and the scanning clock terminal GCLK1 of the first output group can be electrically connected to the same clock line (CK1 or CK3). The cascade clock terminal NCLK2 and the scanning clock terminal GCLK2 of the second output group can be electrically connected to the same clock line (CK2 or CK4).

[0061] In yet another alternative embodiment, Figure 14 This is a schematic diagram of another scanning module provided in an embodiment of the present invention, with reference to... Figure 14The second scan unit 232 includes a refresh control transistor Tr7 and a second scan transistor Tr6'. The gate of the second scan transistor Tr6' is electrically connected to the second terminal of the refresh control transistor Tr7; the first terminal of the second scan transistor Tr6' is electrically connected to the scan clock terminal GCLK; the second terminal of the second scan transistor Tr6' is electrically connected to the scan output terminal GOUT; the first terminal of the refresh control transistor Tr7 is electrically connected to the stage transmission output terminal NEXT; and the gate of the refresh control transistor Tr7 is electrically connected to the second refresh control terminal Goff2.

[0062] For example, taking the scanning module 230 as an example where all transistors are N-type transistors, when the second refresh control terminal Goff2 is high, the refresh control transistor Tr7 is turned on. When the stage transmission signal at the stage transmission output terminal NEXT is high, the gate of the second scanning transistor Tr6' is also high, and the second scanning transistor Tr6' is turned on. When the scan clock signal at the scan clock terminal GCLK jumps high, it can drive the potential of the scan output terminal GOUT to rise, making the scan signal an effective level. When the second refresh control terminal Goff2 is low, the refresh control transistor Tr7 is turned off. When the stage transmission signal at the stage transmission output terminal NEXT is high, the gate of the second scanning transistor Tr6' is still low, and the second scanning transistor Tr6' is turned off. The scan output terminal GOUT cannot output an effective level.

[0063] In addition, the second scanning unit 232 may also include a scanning bootstrap capacitor C2. The first terminal of the scanning bootstrap capacitor C2 is electrically connected to the gate of the second scanning transistor Tr6', and the second terminal of the scanning bootstrap capacitor C2 is electrically connected to the scanning output terminal GOUT. When the scanning clock signal pulls up the scanning output terminal GOUT, the scanning bootstrap capacitor C2 can pull up the gate coupling of the second scanning transistor Tr6', compensating for the threshold voltage of the second scanning transistor Tr6', which is beneficial for the full opening of the second scanning transistor Tr6', reducing the signal delay of the scanning signal, and improving the accuracy of the scanning signal.

[0064] It should be noted that the figure only shows an example of the case where all transistors in the scanning module are N-type transistors. In other alternative embodiments, some or all of the transistors in the scanning module may also be P-type transistors.

[0065] Based on the above implementation methods, Figure 15 This is a schematic diagram of another scanning module provided in an embodiment of the present invention, with reference to... Figure 15The second scanning unit 232 also includes an auxiliary transistor Tr8; the first terminal of the auxiliary transistor Tr8 is electrically connected to the stage transmission output terminal NEXT of the same shift register unit 20; the second terminal of the auxiliary transistor Tr8 is electrically connected to the first terminal of the refresh control transistor Tr7; and the gate of the auxiliary transistor Tr8 is electrically connected to the scan clock terminal GCLK.

[0066] For example, taking the example that all transistors in the scanning module 230 are N-type transistors, when the second refresh control terminal Goff2 is high, the refresh control transistor Tr7 is turned on. At the same time, when the stage transmission signal of the stage transmission output terminal NEXT is high and the scan clock signal of the scan clock terminal GCLK is also high, the auxiliary transistor Tr8 and the second scan transistor Tr6' are both turned on. When the scan clock signal of the scan clock terminal GCLK changes from high to low, the parasitic capacitance coupling of the second scan transistor Tr6' will pull down the gate potential of the second scan transistor Tr6'. At the same time, if the stage transmission output terminal NEXT is directly connected to the first terminal of the refresh control transistor Tr7, and the stage transmission signal of the stage transmission output terminal NEXT also changes from high to low, it will further pull down the gate potential of the second scan transistor Tr6', causing the second scan transistor Tr6' to turn off prematurely. This prevents the potential of the scan output terminal GOUT from being pulled down, which may result in multiple scan lines SL transmitting high scan signals at the same time, and multiple rows of pixels being refreshed simultaneously, leading to abnormal display. By setting an auxiliary transistor Tr8 between the stage transmission output terminal NEXT and the first terminal of the refresh control transistor Tr7, and electrically connecting the gate of the auxiliary transistor Tr8 to the scan clock terminal GCLK, the auxiliary transistor Tr8 can be turned off in advance when the scan clock signal of the scan clock terminal GCLK changes from high level to low level. This avoids affecting the gate potential of the second scan transistor Tr6' when the stage transmission signal of the stage transmission output terminal NEXT changes from high level to low level.

[0067] Furthermore, when the second scan unit 232 includes the scan bootstrap capacitor C2, the second refresh control terminal Goff2 is at a high level, and the refresh control transistor Tr7 is turned on. Simultaneously, when the stage transmission signal at the stage transmission output terminal NEXT is at a high level, and the scan clock signal at the scan clock terminal GCLK is also at a high level, both the auxiliary transistor Tr8 and the second scan transistor Tr6' are turned on. When the scan clock signal drives the scan signal at the scan output terminal GOUT to be pulled up, the scan bootstrap capacitor C2 can pull the gate coupling of the second scan transistor Tr6' high. Thus, when the scan clock signal at the scan clock terminal GCLK changes from high to low, after the parasitic capacitance of the second scan transistor Tr6' pulls down its gate potential, the gate potential of the second scan transistor Tr6' remains relatively high, ensuring that the second scan transistor Tr6' is fully turned on and can promptly pull down the potential of the scan output terminal GOUT.

[0068] Based on the above implementation methods, Figure 16 This is a schematic diagram of another scanning module provided in an embodiment of the present invention, with reference to... Figure 16 The second scanning unit 232 further includes a pull-down transistor Tr10; the gate of the pull-down transistor Tr10 is electrically connected to the first node N1; the first terminal of the pull-down transistor Tr10 is electrically connected to the first fixed potential terminal VGL; and the second terminal of the pull-down transistor Tr10 is electrically connected to the gate of the second scanning transistor Tr6'.

[0069] For example, taking a scenario where the active level is high, the inactive level is low, and the potential of the first fixed potential terminal VGL is low, refer to... Figure 16 When the signal at the first node N1 is high, the first scanning transistor Tr5' and the pull-down transistor Tr10 are turned on, and the gate of the scan output terminal GOUT and the gate of the second scanning transistor Tr6' are low. By setting the pull-down transistor Tr10, it can be turned on when the signal at the first node N1 is high, pulling down the gate potential of the second scanning transistor Tr6' and turning it off. This avoids the second scanning transistor Tr6' having its gate potential always high, causing the first scanning transistor Tr5' and the second scanning transistor Tr6' to be turned on simultaneously, resulting in signal interference and damage to the circuit.

[0070] Optional, Figure 17 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 17 The shift register unit 20 includes n stage transfer modules 220, where n is an integer greater than or equal to 2. Within the same shift register unit 20, the effective pulses of the stage transfer clock signals received by the stage transfer clock terminals NCLK1 and NCLK2 of each stage transfer module 220 do not overlap. Within one clock cycle, the stage transfer clock signal that transitions to an effective pulse on the kth stage is the kth stage transfer clock signal; the stage transfer module 220 receiving the kth stage transfer clock signal is the kth stage transfer module, where k is a positive integer less than or equal to n. The stage transfer output terminal NEXT of the nth stage transfer module 220 of the s-th stage shift register unit 20(s) is electrically connected to the start input terminal INF of the (s+1)-th stage shift register unit 20(s+1), where s is a positive integer.

[0071] The clock period refers to the transition period of multiple cascaded clock signals received in a shift register unit 20, that is, the time period during which multiple cascaded clock signals received in a shift register unit 20 sequentially transition into valid pulses. The valid pulses of multiple cascaded clock signals received by the same shift register unit 20 do not overlap, and the valid pulses of multiple cascaded clock signals received by two adjacent shift register units 20 also do not overlap.

[0072] For example, with n=2, the shift register unit 20 includes two pass modules 220 and two scan modules 230. Figure 18 This is a timing diagram of another shift register unit provided in an embodiment of the present invention, referred to... Figure 17 and Figure 18 The shift register units 20 are cascaded in sequence, and the start input signal of the start input terminal INF is shifted in sequence. The first and second stage transmission modules 220 of the s-th stage shift register unit 20(s) receive the valid pulses of the first and second stage transmission clock signals in sequence, so that the stage transmission output terminals NEXT1 and NEXT2 of the first and second stage transmission modules 220 output valid pulses in sequence. The stage transmission clock signal that the last jump of the output of the s-th stage shift register unit 20(s) becomes a valid pulse is used as the start input signal of the start input terminal INF of the (s+1)-th stage shift register unit 20(s+1), which can realize the sequential shift of the start input signal, that is, realize the sequential driving of each stage shift register unit 20.

[0073] Similarly, the stage transmission clock signal that becomes the last pulse of the output of the (s+1)th stage shift register unit 20 (s+1) can be used as the start input signal of the start input terminal INF of the (s+2)th stage shift register unit 20 (s+2). That is, the stage transmission output terminal NEXT of the nth stage transmission module 220 of the (s+1)th stage shift register unit 20 (s+1) is electrically connected to the start input terminal INF of the (s+2)th stage shift register unit 20 (s+2) (not shown in the figure).

[0074] It should be noted that the display panel can scan in either forward or reverse direction. In forward scanning, the shift register units 20 are arranged sequentially from top to bottom as the first stage, second stage, ..., and last stage, with each stage outputting valid pulses of the stage transmission signal. In reverse scanning, the shift register units 20 are arranged sequentially from bottom to top as the first stage, second stage, ..., and last stage, with each stage outputting valid pulses of the stage transmission signal. Regardless of whether the shift register units 20 are scanned in forward or reverse direction, the stage transmission output terminal NEXT of the stage transmission module 220 that receives the last valid pulse of the stage transmission clock signal from the previous stage is electrically connected to the start input terminal INF of the next stage, thus enabling the sequential driving of each stage of the shift register units 20.

[0075] Optional, Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 19The drive control module 210 includes an input unit 211, a reset unit 212, and an interlock unit 213. The drive control module 210 also includes a reset clock terminal RSTF. The input unit 211 is electrically connected to the start input terminal INF, the scan control terminal U2D, and the second node N2, respectively. The reset unit 212 is electrically connected to the scan control terminal U2D, the reset clock terminal RSTF, the first node N1, and the second fixed potential terminal VGH, respectively. The interlock unit 213 is electrically connected to the first node N1, the second node N2, and the first fixed potential terminal VGL, respectively.

[0076] Specifically, input unit 211 can control the signal of second node N2 to be at an effective level when the potentials of the start input terminal INF and the scan control terminal U2D are both at effective levels; reset unit 212 can control the first node N1 to be at an effective level when the potentials of the scan control terminal U2D and the reset clock terminal RSTF are both at effective levels; interlock unit 213 is used to control the second node N2 to be at an invalid level when the first node N1 is at an effective level, and to control the first node N1 to be at an invalid level when the second node N2 is at an effective level.

[0077] For example, input unit 211 includes a first input transistor Tr13. The first terminal of the first input transistor Tr13 is electrically connected to the scan control terminal U2D, the second terminal of the first input transistor Tr13 is electrically connected to the second node N2, and the gate of the first input transistor Tr13 is electrically connected to the start input terminal INF. Reset unit 212 includes a first reset transistor Tr15 and a reset control transistor Tr4. The gate of the first reset transistor Tr15 is electrically connected to the scan control terminal U2D, the first terminal of the first reset transistor Tr15 is electrically connected to the reset clock terminal RSTF, the second terminal of the first reset transistor Tr15 is electrically connected to the gate of the reset control transistor Tr4, the first terminal of the reset control transistor Tr4 is electrically connected to the second fixed potential terminal VGH, and the second terminal of the reset control transistor Tr4 is electrically connected to the first node N1. The interlocking unit 213 includes a first interlocking transistor Tr1 and a second interlocking transistor Tr3. The first terminal of the first interlocking transistor Tr1 is electrically connected to the second node N2, the gate of the first interlocking transistor Tr1 is electrically connected to the first node N1, and the second terminal of the first interlocking transistor Tr1 is electrically connected to the first fixed potential terminal VGL. The gate of the second interlocking transistor Tr3 is electrically connected to the second node N2, the first terminal of the second interlocking transistor Tr3 is electrically connected to the first node N1, and the second terminal of the second interlocking transistor Tr3 is electrically connected to the first fixed potential terminal VGL.

[0078] In an alternative embodiment, reference continues. Figure 19The drive control module 210 may further include a reverse scan control terminal D2U, an inverting input terminal INB, and an inverting reset clock terminal RSTB; the input unit 211 is also electrically connected to the reverse scan control terminal D2U and the inverting input terminal INB; the reset unit 212 is also electrically connected to the reverse scan control terminal D2U and the inverting reset clock terminal RSTB. The input unit 211 can also control the second node N2 to be at an active level when both the potentials of the reverse scan control terminal D2U and the inverting input terminal INB are active; the reset unit 212 can also control the first node N1 to be at an active level when both the potentials of the reverse scan control terminal D2U and the inverting reset clock terminal RSTB are active.

[0079] For example, continue to refer to Figure 19 The input unit 211 further includes a second input transistor Tr14. The first terminal of the second input transistor Tr14 is electrically connected to the reverse scan control terminal D2U, the second terminal of the second input transistor Tr14 is electrically connected to the second node N2, and the gate of the second input transistor Tr14 is electrically connected to the reverse start input terminal INB. The reset unit 212 further includes a second reset transistor Tr16. The gate of the second reset transistor Tr16 is electrically connected to the reverse scan control terminal D2U, the first terminal of the second reset transistor Tr16 is electrically connected to the reverse reset clock terminal RSTB, and the second terminal of the second reset transistor Tr16 is electrically connected to the gate of the reset control transistor Tr4. Thus, the display panel can achieve both forward and reverse scanning, meeting various application scenarios.

[0080] It should be noted that the figure only shows the case where all transistors in the drive control module are N-type transistors. In other alternative embodiments, some or all of the transistors in the drive control module may also be P-type transistors.

[0081] In yet another alternative embodiment, reference continues to... Figure 19 The drive control module 210 may further include a first storage capacitor C1 and a second storage capacitor C3. The first terminal of the first storage capacitor C1 is electrically connected to a first fixed potential terminal VGL, and the second terminal of the first storage capacitor C1 is electrically connected to a first node N1. The first terminal of the second storage capacitor C3 is electrically connected to the first fixed potential terminal VGL, and the second terminal of the second storage capacitor C3 is electrically connected to a second node N2. The first storage capacitor C1 and the second storage capacitor C3 can store the signals of the first node N1 and the second node N2, respectively. When no new signals are written to the drive control module 210, the first storage capacitor C1 and the second storage capacitor C3 can maintain the stability of the signals of the second node N2 and the first node N1.

[0082] In yet another alternative embodiment, reference continues to... Figure 19The number of cascading modules 220 and the number of scanning modules 230 in the shift register unit 20 can be different. In one embodiment, the shift register unit 20 may include one cascading module 220 and two scanning modules 230. The number of cascading modules 220 is less than the number of scanning modules 230, but this does not affect the fact that the shift register unit 20 outputs multiple scanning signals. In this way, the circuit structure of the shift register unit 20 can be simplified, the number of transistors can be reduced, and it is beneficial to the narrow bezel and thinness of the display panel.

[0083] For example, taking the shift register unit 20 as an example where all transistors are N-type transistors, the first fixed potential terminal VGL is at a low level, and the second fixed potential terminal VGH is at a high level, the following scenario is taken. Figure 20 This is a timing diagram of another shift register unit provided in an embodiment of the present invention, referred to... Figure 19 and Figure 20 In stage t21, both the start input terminal INF and the scan control terminal U2D are at high level, the first input transistor Tr13 is turned on, the signal of the second node N2 is at high level, and the interlock unit 213 can control the signal of the first node N1 to be at low level under the control of the signal of the second node N2; at the same time, the reset clock terminal RSTF is at low level, the reset unit 212 cannot output a high level signal, and the signal of the first node N1 remains at low level. The first stage transmission transistor Tr5 and the first scan transistor Tr5' are turned off, the second stage transmission transistor Tr6 and the second scan transistor Tr6' are turned on, the stage transmission output terminal NEXT outputs the stage transmission clock terminal NCLK at low level, the scan output terminal GOUT1 outputs the scan clock terminal GCLK1 at low level, and the scan output terminal GOUT2 outputs the scan clock terminal GCLK2 at low level.

[0084] During stage t22, both the start input INF and the reset clock RSTF are low. The signal of the second node N2 remains high, and the signal of the first node N1 remains low. The first stage transmission transistor Tr5 and the first scan transistor Tr5' remain off, while the second stage transmission transistor Tr6 and the second scan transistor Tr6' remain on. The stage transmission output NEXT can output the stage transmission clock NCLK at a high level, the scan output GOUT1 can output the scan clock GCLK1 at a high level, and the scan output GOUT2 can output the scan clock GCLK2 at a high level.

[0085] During stage t23, both the reset clock terminal RSTF and the scan control terminal U2D are at high level. The reset unit 212 can output a high-level signal, making the signal of the first node N1 high. Under the control of the signal of the first node N1, the interlock unit 213 can control the signal of the second node N2 to be low. At the same time, the start input terminal INF is low, the input unit 211 cannot output a high-level signal, and the signal of the second node N2 is low. The first stage transmission transistor Tr5 and the first scan transistor Tr5' are turned on, and the second stage transmission transistor Tr6 and the second scan transistor Tr6' are turned off. The stage transmission output terminal NEXT, the scan output terminal GOUT1, and the scan output terminal GOUT2 output the first fixed potential terminal VGL at a low level.

[0086] After stage t23, the start input terminal INF will remain low, and the reset clock terminal RSTF will alternate between high and low levels, causing the signal of the first node N1 to remain high and the signal of the second node N2 to remain low. The stage output terminal NEXT, the scan output terminal GOUT1, and the scan output terminal GOUT2 will remain low until the signal of the start input terminal INF changes to high again. Only then will the signal of the second node N2 change to high. At the same time, under the action of the reset unit 212 and the interlock unit 213, the stage output terminal NEXT, the scan output terminal GOUT1, or the scan output terminal GOUT2 may output high again.

[0087] For example, Figure 21 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, for reference. Figure 21 When multiple shift register units 20 are cascaded, the start input terminal INF of the first-stage shift drive unit 01 can receive a first start signal as the start input signal, and the inverting input terminal INB of the last-stage shift drive unit 20 can receive a second start signal as the inverting input signal. Except for the first-stage and last-stage shift drive units 20, the start input terminals INF of other stages of shift drive units 20 are electrically connected to the stage output terminal NEXT of the previous-stage shift register unit 20. The stage output terminal NEXT of the current-stage shift register unit 20 can be electrically connected to the start input terminal INF of the next-stage shift register unit 20. The inverting input terminal INB of the current-stage shift register unit 20 is electrically connected to the stage output terminal NEXT of the next-stage shift register unit 20, and the stage output terminal NEXT of the current-stage shift register unit 20 can be electrically connected to the inverting input terminal INB of the previous-stage shift register unit 20.

[0088] The scan control terminal U2D of each shift register unit 20 is electrically connected, and the reverse scan control terminal D2U of each shift register unit 20 is electrically connected. When the shift register unit 20 performs the forward scan driving process, the potential of the scan control terminal U2D of each shift register unit 20 can all be at an active level, and the potential of the reverse scan control terminal D2U can all be at an inactive level. Thus, the signal of the second node N2 in the current shift drive unit 20 is not affected by the stage transmission signal of the stage transmission output terminal NEXT of the next-level shift drive unit 20. When the shift register unit 20 performs the reverse scan driving process, the potential of the scan control terminal U2D of each shift register unit 20 can all be at an inactive level, and the potential of the reverse scan control terminal D2U can all be at an active level. Thus, the signal of the second node N2 in the current shift drive unit 20 is not affected by the stage transmission signal of the stage transmission output terminal NEXT of the previous-level shift drive unit 20.

[0089] The reverse reset clock terminal RSTB, the stage transfer clock terminal NCLK, and the reset clock terminal RSTF of the same shift register unit 20 are different clock signals. For example, for the h-th stage shift register unit 20, the reverse reset clock terminal RSTB, the stage transfer clock terminal NCLK, and the reset clock terminal RSTF can be electrically connected to the shift clock lines NCK2, NCK3, and NCK4, respectively; for the h+1-th stage shift register unit 20, the reverse reset clock terminal RSTB, the stage transfer clock terminal NCLK, and the reset clock terminal RSTF can be electrically connected to the shift clock lines NCK3, NCK4, and NCK5, respectively. K1 is electrically connected; for the (h+2)th level shift register unit 20, the reverse reset clock terminal RSTB, the stage transfer clock terminal NCLK, and the reset clock terminal RSTF can be electrically connected to the shift clock lines NCK4, NCK1, and NCK2, respectively; for the (h+3)th level shift register unit 20, the reverse reset clock terminal RSTB, the stage transfer clock terminal NCLK, and the reset clock terminal RSTF can be electrically connected to the shift clock lines NCK1, NCK2, and NCK3, respectively; wherein, the effective pulses on the shift clock lines NCK1, NCK2, NCK3, and NCK4 are shifted sequentially, and h is a positive integer. Furthermore, the inverted reset clock terminal RSTB of the h-th stage shift register unit 20 can be electrically connected to the inverted reset clock terminal RSTB of the h+4-th stage shift register unit 20; the stage transfer clock terminal NCLK of the h-th stage shift register unit 20 can be electrically connected to the stage transfer clock terminal NCLK of the h+4-th stage shift register unit 20; and the reset clock terminal RSTF of the h-th stage shift register unit 20 can be electrically connected to the reset clock terminal RSTF of the h+4-th stage shift register unit 20.

[0090] The scan clock signals GCLK1 and GCLK2 of the same shift register unit 20 are also different clock signals. For example, for the h-th stage shift register unit 20, the scan clock signals GCLK1 and GCLK2 can be electrically connected to the output clock lines GCK1 and GCK2, respectively; for the h+1-th stage shift register unit 20, the scan clock signals GCLK1 and GCLK2 can be electrically connected to the output clock lines GCK3 and GCK4, respectively; wherein, the effective pulses on the output clock lines GCK1, GCK2, GCK3, and GCK4 are shifted sequentially, and h is a positive integer. In addition, the scan clock signal GCLK1 of the h-th stage shift register unit 20 can be electrically connected to the scan clock signal GCLK1 of the h+2-th stage shift register unit 20; the scan clock signal GCLK2 of the h-th stage shift register unit 20 can be connected to the scan clock signal GCLK2 of the h+2-th stage shift register unit 20.

[0091] Optional, Figure 22 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, for reference. Figure 22 The drive control module 210 includes a scan control unit 214 and an enable control unit 215. The drive control module 210 also includes an enable clock terminal Nset and a third node N3. The scan control unit 214 is electrically connected to the start input terminal INF, the scan control terminal U2D, and the third node N3, respectively. The scan control unit 214 is used to receive the start input signal from the start input terminal INF and the scan control signal from the scan control terminal U2D, and control the signal of the third node N3. The enable control unit 215 is electrically connected to the enable clock terminal Nset, the third node N3, the second fixed potential terminal VGH, the first node N1, and the second node N2, respectively. The enable control unit 215 is used to receive the enable clock signal from the enable clock terminal Nset, the signal from the third node N3, and the second fixed potential signal from the second fixed potential terminal VGH, and control the signals of the first node N1 and the second node N2.

[0092] Specifically, the scan control unit 214 can control the signal of the third node N3 to be at an active level when both the potentials of the start input terminal INF and the scan control terminal U2D are active; the scan control unit 214 can also control the signal of the third node N3 to be inactive when the potential of the scan control terminal U2D is active and the start input terminal INF is inactive. The enable control unit 215 can control the signal of the first node N1 to be either active or inactive, and control the signal of the second node N2 to be either active or inactive, under the control of the signal of the third node N3 and the enable clock signal of the enable clock terminal Nset.

[0093] In an alternative embodiment, reference continues. Figure 22The scan control unit 214 includes a first scan control transistor Tr17; the gate of the first scan control transistor Tr17 is electrically connected to the scan control terminal U2D, the first terminal of the first scan control transistor Tr17 is electrically connected to the start input terminal INF, and the second terminal of the first scan control transistor Tr17 is electrically connected to the third node N3.

[0094] Specifically, when the potential of the scan control terminal U2D is at an effective level, the first scan control transistor Tr17 is turned on, and the potential of the third node N3 is the same as the potential of the start input terminal INF, thus realizing forward scan drive. By setting the gate of the first scan control transistor Tr17 to be connected to the scan control terminal U2D and the first terminal of the first scan control transistor Tr17 to be connected to the start input terminal INF, the potential of the third node N3 can follow the change of the start input signal of the start input terminal INF, so as to avoid the potential of the third node N3 floating and always being at an effective level, affecting the driving process of the shift register unit 20.

[0095] Furthermore, the drive control module 210 may also include a reverse scan control terminal D2U and an inverting input terminal INB; the scan control unit 214 further includes a second scan control transistor Tr18; the gate of the second scan control transistor Tr18 is electrically connected to the reverse scan control terminal D2U, the first terminal of the second scan control transistor Tr18 is electrically connected to the inverting input terminal INB, and the second terminal of the second scan control transistor Tr18 is electrically connected to the third node N3. When the potential of the reverse scan control terminal D2U is at an active level, the potentials of the second scan control transistor Tr18 and the third node N3 are the same as the potential of the inverting input terminal INB, thus enabling reverse scan drive.

[0096] In yet another alternative embodiment, reference continues to... Figure 22 The enable control unit includes a first enable transistor Tr01, a second enable transistor Tr02, and a third enable transistor Tr03. The gate of the first enable transistor Tr01 is electrically connected to the enable clock terminal Nset, the first terminal of the first enable transistor Tr01 is electrically connected to the third node N3, and the second terminal of the first enable transistor Tr01 is electrically connected to the gate of the second enable transistor Tr02 at the second node N2. The first terminal of the second enable transistor Tr02 is electrically connected to the enable clock terminal Nset, and the second terminal of the second enable transistor Tr02 is electrically connected to the second terminal of the third enable transistor Tr03 at the first node N1. The gate of the third enable transistor Tr03 is electrically connected to the enable clock terminal Nset, and the first terminal of the third enable transistor Tr03 is electrically connected to the second fixed potential terminal VGH.

[0097] Specifically, when the signal of the third node N3 and the potential of the enable clock terminal Nset are both at valid levels, the signal of the second node N2 is at a valid level; when the signal of the second node N2 is at a valid level, the potential of the first node N1 is the same as the potential of the enable clock terminal Nset; when the signal of the second node N2 is at an invalid level, the signal of the first node N1 is at a valid level. By setting a scan control unit 214 and an enable control unit 215 in the drive control module 210, and by setting only the first enable transistor Tr01, the second enable transistor Tr02, and the third enable transistor Tr03 in the scan control unit 215, control of the first node N1 and the second node N2 can be achieved, reducing the number of transistors and facilitating the narrow bezel and thinness of the display panel.

[0098] For example, taking the shift register unit 20 as an example where all transistors are N-type transistors, the first fixed potential terminal VGL is at a low level, and the second fixed potential terminal VGH is at a high level, the following scenario is taken. Figure 23 This is a timing diagram of another shift register unit provided in an embodiment of the present invention, referred to... Figure 22 and Figure 23 During stage t31, both the start input terminal INF and the scan control terminal U2D are at a high level, the first scan control transistor Tr17 is turned on, and the signal of the third node N3 is at a high level. At the same time, the enable clock signal of the enable clock terminal Nset is also at a high level, the first enable transistor Tr01, the second enable transistor Tr02 and the third enable transistor Tr03 are all turned on, the signals of the first node N1 and the second node N2 are both at a high level, the first stage transmission transistor Tr5, the first scan transistor Tr5', the second stage transmission transistor Tr6 and the second scan transistor Tr6' are all turned on. At this time, the stage transmission clock terminal NCLK is at a low level, the stage transmission output terminal NEXT outputs a low level, the scan clock terminals GCLK1 and GCLK2 are at a low level, and the scan output terminals GOUT1 and GOUT2 output a low level.

[0099] In stage t32, the start input signal of the start input terminal INF becomes low, the potential of the scan control terminal U2D remains high, the first scan control transistor Tr17 is turned on, and the signal of the third node N3 is low; at the same time, the enable clock signal of the enable clock terminal Nset is low, the first enable transistor Tr01 and the third enable transistor Tr03 are turned off, making the second node N2 still high, the second enable transistor Tr02 is turned on, the first node N1 is low, the first stage transmission transistor Tr5 and the first scan transistor Tr5' are turned off, the second stage transmission transistor Tr6 and the second scan transistor Tr6' are turned on, at this time the stage transmission clock terminal NCLK is high, the stage transmission output terminal NEXT can output the high level of the stage transmission clock terminal NCLK, the scan clock terminals GCLK1 and GCLK2 are high in sequence, and the scan output terminals GOUT1 and GOUT2 can output valid pulses in sequence.

[0100] During stage t33, the potentials of the start input terminal INF and the scan control terminal U2D remain unchanged, the signal of the third node N3 is still low, the enable clock signal of the enable clock terminal Nset becomes high, the first enable transistor Tr01 and the third enable transistor Tr03 are turned on, the first node N1 becomes high, and the second node N2 becomes low; the first stage transmission transistor Tr5 and the first scan transistor Tr5' are turned on, the second stage transmission transistor Tr6 and the second scan transistor Tr6' are turned off, and the stage transmission output terminal NEXT, the scan output terminal GOUT1 and the scan output terminal GOUT2 output the first fixed potential terminal VGL at a low level.

[0101] After stage t33, the start input INF will remain low, the signal of the third node N3 will remain low, and the enable clock signal of the enable clock Nset will alternate between high and low levels, causing the signal of the first node N1 to remain high and the signal of the second node N2 to remain low. The stage output NEXT, scan output GOUT1, and scan output GOUT2 will remain low until the signal of the start input INF changes to high again. Only then will the signal of the third node N3 change to high. At the same time, under the action of the first enable transistor Tr01, the second enable transistor Tr02, and the third enable transistor Tr03, the stage output NEXT, scan output GOUT1, or scan output GOUT2 may output a high level.

[0102] It should be noted that the figure only shows the case where all transistors in the drive control module are N-type transistors. In other alternative embodiments, some or all of the transistors in the drive control module may also be P-type transistors.

[0103] In one embodiment, in the same shift register unit 20, the effective pulse of the start input signal received by the start input terminal INF overlaps with the effective pulse of the enable clock signal received by the enable clock terminal Nset, and the effective pulse of the enable clock signal received by the enable clock terminal Nset does not overlap with the effective pulse of the cascade clock signal of the cascade clock terminal NCLK.

[0104] By setting the effective pulse of the start input signal received by the start input terminal INF to overlap with the effective pulse of the enable clock signal received by the enable clock terminal Nset, the start input terminal INF can be made to be at an effective level. When the third node N3 is also at an effective level (stage t31), the effective level of the third node N3 can be transmitted to the second node N2, ensuring that the potential of the start input terminal INF can affect the potential of the second node N2, thereby driving the shift register unit 20. By setting the effective pulse of the enable clock signal received by the enable clock terminal Nset to not overlap with the effective pulse of the stage transmission clock signal of the stage transmission clock terminal NCLK, it can be ensured that when the first node N1 and the second node N2 are both at an effective level (stage t31), the stage transmission clock signal of the stage transmission clock terminal NCLK is at an invalid level, avoiding signal collision at the stage transmission output terminal NEXT and damage to the circuit.

[0105] In another embodiment, in the same shift register unit 20, the effective pulse of the enable clock signal received by the enable clock terminal Nset does not overlap with the effective pulse of the cascade clock signal of the scan clock terminal GCLK, so as to ensure that when the first node N1 and the second node N2 are both at an effective level (t31 stage), the scan clock signal of the scan clock terminal GCLK is at an invalid level, thus avoiding signal collision at the scan output terminal GOUT and damage to the circuit.

[0106] Based on the above embodiment, the stage clock terminal NCLK of the s-th stage shift register unit 20(s) is electrically connected to the enable clock terminal Nset of the p-th stage shift register unit 20(p), s≠p, and s and p are both positive integers.

[0107] For example, Figure 24 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, for reference. Figures 22-24 Each stage of the shift register unit 20 outputs a valid pulse of the stage transmission signal at its NEXT terminal. The valid pulses of the stage transmission clock signal received by the stage transmission clock terminals NCLK of adjacent shift register units 20 are shifted sequentially. The enable clock terminal Nset of the current stage shift register unit 20 can be electrically connected to the stage transmission clock terminal NCLK of the previous stage shift register unit 20 on the same clock line. The enable clock signal of the current stage shift register unit 20 reuses the stage transmission clock signal of the previous stage shift register unit 20. This reduces the number of clock lines in the driving circuit 10, contributing to a narrower bezel and thinner display panel.

[0108] In another optional embodiment, the shift register unit 20 includes n cascade modules 220 and m scanning modules 230; where n < m.

[0109] Specifically, the m scanning modules 230 of the shift register unit 20 can be electrically connected to m scan lines, which helps to reduce the number of shift register units 20 in the drive circuit 10 and reduce the space occupied by the drive circuit 10; by setting n cascading modules 220, n < m, it also helps to reduce the space occupied by the shift register units 20 and the number of clock lines, further reducing the space occupied by the drive circuit 10; in addition, combined with Figure 22 The circuit structure of the drive control module 210 shown has fewer clock signals required, which helps to further reduce the number of clock lines.

[0110] refer to Figures 22-24 n=1, the display panel includes a first shift clock line NCK1 and a second shift clock line NCK2; the enable clock terminal Nset of the 2s-1 stage shift register unit 20 (2s-1) is electrically connected to the first shift clock line NCK1, and the stage transmission clock terminal NCLK is electrically connected to the second shift clock line NCK2; the enable clock terminal Nset of the 2s stage shift register unit 20 (2s) is electrically connected to the second shift clock line NCK2, and the stage transmission clock terminal NCLK is electrically connected to the first shift clock line NCK1; where s is a positive integer.

[0111] Specifically, the drive control module 210 of the shift register unit 20 is electrically connected to only one clock terminal (enable clock terminal Nset), and only needs to receive one clock signal (enable clock signal). This enable clock terminal Nset can be electrically connected to the cascade clock terminals NCLK of other shift register units 20. The enable clock signal can reuse the cascade clock signals of other shift register units 20. When the shift register unit 20 includes only one cascade module 220, the shift register unit 20 includes only one cascade clock terminal NCLK. In this case, combined with the enable clock... The signal reuses the stage transmission clock signal of other stage shift register units 20. The shift register unit 20 only needs to receive two stage transmission clock signals. Therefore, the display panel can be equipped with only two shift clock lines for transmitting stage transmission clock signals. The enable clock terminal Nset of adjacent stage shift register units 20 is electrically connected to different shift clock lines. The stage transmission clock terminal NCLK of adjacent stage shift register units 20 is electrically connected to different shift clock lines. The enable clock terminal Nset and the stage transmission clock terminal NCLK of the same stage shift register unit 20 are also electrically connected to different shift clock lines.

[0112] It is understandable that when the shift register unit 20 includes a cascade module 220, regardless of how many scanning modules 230 the shift register unit includes, the display panel can be equipped with only two shift clock lines for transmitting the cascade clock signal, and there is no need to set up an additional enable clock line for transmitting the enable clock signal. This can achieve the driving of the drive control module 210 and the cascade module 220 in the multi-level shift register unit 20, which helps to simplify the wiring connection of the drive circuit.

[0113] In yet another alternative embodiment, reference continues to... Figures 22-24 The display panel also includes m first output clock lines (GCK1, GCK2) and m second output clock lines (GCK3, GCK4); the m scanning modules of the 2s-1 stage shift register unit are electrically connected to the m first output clock lines (GCK1, GCK2) one by one; the m scanning modules of the 2s stage shift register unit are electrically connected to the m second output clock lines (GCK3, GCK4) one by one.

[0114] Specifically, the display panel may include two shift clock lines for transmitting stage clock signals and 2m output clock lines for transmitting scan clock signals. The valid pulses of the stage clock signals on the first shift clock line and the second shift clock line alternate sequentially. In one cycle of all scan clock signals, the valid pulses of the 2m scan clock signals on the 2m output clock lines shift sequentially without overlapping. The shift register unit 20 is electrically connected to the m scan lines SL. When the shift register unit 20 can output m scan signals, and all m scan signals include valid pulses, the valid pulses of the m scan signals output by the shift register unit 20 shift sequentially. The last valid pulse of the m scan signals output by the 2s-1 stage shift register unit is located before the first valid pulse of the m scan signals output by the 2s stage shift register unit.

[0115] Optionally, the driving circuit also includes a global scanning unit, which is used to control the first node of each shift register unit to be invalid and the signals of the stage transmission output terminal and the scan output terminal of each shift register unit to be valid under the control of the first global control signal.

[0116] Specifically, when the first global control signal is at an active level, the global scan unit transmits an invalid level to the first node of each shift register unit, and transmits an active level to the stage transmission output terminal and scan output terminal of each shift register unit, so that the switching devices in all pixels are turned on, and all pixels can receive the data signal transmitted on the data line. In this way, all pixels can be controlled to reach the same state, and global refresh can be achieved.

[0117] For example, in practical applications, if the display panel experiences an abnormal power outage or enters a low-power sleep mode, it can provide an effective level of the first global control signal to the global scanning unit of the driving circuit, causing all pixels to write zero-grayscale data signals and all pixels to stop emitting light, thereby reducing power consumption and saving energy. When the display panel is a liquid crystal display, it can provide an effective level of the first global control signal to the global scanning unit of the driving circuit, causing all pixels to write zero-grayscale data signals and controlling the liquid crystal to be in an unbiased state, which can avoid liquid crystal polarization and improve display quality.

[0118] In an optional embodiment, Figure 25 This is a schematic diagram of the structure of a global scanning unit provided in an embodiment of the present invention, with reference to... Figure 25 The global scanning unit 40 includes a first scanning transistor Tr21, a second scanning transistor Tr22, and a third scanning transistor Tr23. The gates of the first scanning transistor Tr21, the second scanning transistor Tr22, and the third scanning transistor Tr23 are all electrically connected to the first global control terminal GAS to receive the first global control signal. The first terminal of the first scanning transistor Tr21 is electrically connected to the first fixed potential terminal VGL, and the second terminal of the first scanning transistor Tr21 is electrically connected to the first node N1 of each shift register unit 20. The first terminal of the second scanning transistor Tr22 is electrically connected to the second fixed potential terminal VGH, and the second terminal of the second scanning transistor Tr22 is electrically connected to the stage transmission output terminal NEXT of each shift register unit 20. The first terminal of the third scanning transistor Tr23 is electrically connected to the second fixed potential terminal VGH, and the second terminal of the third scanning transistor Tr23 is electrically connected to the scan output terminal GOUT of each shift register unit 20.

[0119] For example, consider a scenario where all valid voltage levels are high, all invalid voltage levels are low, and the first fixed voltage terminal VGL is low while the second fixed voltage terminal VGH is high. When the first global control signal of the first global control terminal GAS is high, the first scan transistor Tr21, the second scan transistor Tr22, and the third scan transistor Tr23 are turned on, causing the potential of the first node N1 of each shift register unit 20 to be low at the first fixed voltage terminal VGL. This prevents the stage transmission output terminal NEXT and the scan output terminal GOUT of each shift register unit 20 from outputting the low level of the first fixed voltage terminal VGL. Furthermore, it also causes the stage transmission output terminal NEXT and the scan output terminal GOUT of each shift register unit 20 to be high. Thus, the switching devices in all pixels can be turned on, and the same data signal can be written.

[0120] It is understood that when a shift register unit 20 includes multiple cascade modules 220, the global scan unit 40 may include multiple second scan transistors Tr22; when a shift register unit 20 includes multiple scan modules 230, the global scan unit 40 may include multiple third scan transistors Tr23.

[0121] In one embodiment, the second scanning transistor Tr22 can be reused as the third scanning transistor Tr23.

[0122] Optionally, the driving circuit also includes a global reset unit; the global reset unit is used to control the signals at the stage transmission output and scan output of each shift register unit to an invalid level under the control of the second global control signal.

[0123] Specifically, when the second global control signal is at an active level, the global reset unit transmits an invalid level to the stage transmission output and scan output of each shift register unit, so that the switching devices in all pixels are turned off and all pixels stop receiving data signals transmitted on the data lines. In this way, the scan signals output by all shift register units can be simultaneously reset to an invalid level, thus achieving a global reset.

[0124] For example, in practical applications, before and / or after the driving circuit operates, the display panel can provide an effective level of the second global control signal to the global reset unit of the driving circuit, so that all pixels stop writing data signals. This can prevent signal abnormalities at some stage transmission outputs and scan outputs, which would affect the display effect. In addition, the display panel may also include detection units such as gesture detection units and touch detection units. When the detection units are working, in order to avoid signal interference, all clock signals need to jump to an invalid level, which may prevent the signals at some stage transmission outputs and scan outputs of shift register units from being reset. By providing an effective level of the second global control signal to the global reset unit of the driving circuit, the signals at all stage transmission outputs and scan outputs of shift register units can be reset, that is, the driving circuit is controlled not to work. This prevents the driving circuit from interfering with the stage transmission signal, scan signal and data signal when the detection unit is working, causing abnormal pixel refresh and writing of abnormal data signals, which would affect the display and driving functions of the display panel.

[0125] In an optional embodiment, Figure 26 This is a schematic diagram of a global reset unit provided in an embodiment of the present invention, with reference to... Figure 26The global reset unit 50 includes a fourth scan transistor Tr24 and a fifth scan transistor Tr25; the gates of both the fourth scan transistor Tr24 and the fifth scan transistor Tr25 are electrically connected to the second global control terminal Greset to receive the second global control signal; the first terminals of both the fourth scan transistor Tr24 and the fifth scan transistor Tr25 are electrically connected to the first fixed potential terminal VGL; the second terminal of the fourth scan transistor Tr24 is electrically connected to the stage transmission output terminal NEXT of each shift register unit 20; and the second terminal of the fifth scan transistor Tr25 is electrically connected to the scan output terminal GOUT of each shift register unit 20.

[0126] For example, all valid levels are high, all invalid levels are low, and the potential of the first fixed potential terminal VGL is low. When the second global control signal at the second global control terminal Greset is high, the fourth scan transistor Tr24 and the fifth scan transistor Tr25 are turned on, causing the stage transmission output terminal NEXT and the scan output terminal GOUT of each shift register unit 20 to be low, controlling all pixels to be turned off and stopping the writing of data signals.

[0127] It is understood that when a shift register unit 20 includes multiple cascade modules 220, the global reset unit 50 may include multiple fourth scan transistors Tr24; when a shift register unit 20 includes multiple scan modules 230, the global reset unit 50 may include multiple fifth scan transistors Tr25.

[0128] In one embodiment, the fourth scan transistor Tr24 can be reused as the fifth scan transistor Tr25.

[0129] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display panel, which can be used to drive the display panel provided in any embodiment of the present invention. Figure 27 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, see reference. Figure 27 The driving methods include: S1001. During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses.

[0130] S1002. During the holding phase, the stage transmission output terminal of the shift register unit of the control section outputs a valid pulse, while the scan output terminal is at an invalid level.

[0131] The display panel includes a multi-frequency driving mode, in which different areas of the display panel have different refresh rates. For example, the display area includes a low-frequency display area and a high-frequency display area, and the refresh rate of pixels in the low-frequency display area is lower than that of pixels in the high-frequency display area. At least a portion of the display frames in the multi-frequency driving mode are designated as the first display frame. In the first display frame, pixels in the low-frequency display area are not refreshed, maintaining the grayscale of the previous display frame, while pixels in the high-frequency display area are refreshed to the grayscale of the current display frame. The first display frame includes a refresh phase and a hold phase. The refresh phase refers to the phase where the driving circuit can output valid pulses of the scan signal to control at least a portion of the pixels to refresh; the hold phase refers to the phase where the driving circuit cannot output valid pulses of the scan signal, but can control at least a portion of the pixels to stop refreshing, maintaining the grayscale of the previous display frame. In both the refresh and hold phases, shift register units are driven.

[0132] For example, taking a high level as the active level and a low level as the inactive level, Figure 28 This is a timing diagram of a display panel in multi-frequency driving mode according to an embodiment of the present invention, with reference to... Figure 28 During the refresh phase tf of the first display frame DA01, by controlling the NEXT output terminal and GOUT scan output terminal of the partial shift register unit 20 to output valid pulses, the partial shift register unit 20 can control the refresh of a portion of pixels, enabling the pixels P to be refreshed at a higher frequency. At the same time, the partial shift register unit 20 can sequentially output valid pulses of the transmission signal, realizing the sequential shifting of the valid pulses of the initial input signal, that is, realizing the sequential driving of the partial shift register unit 20, enabling the partial shift register unit 20 to sequentially output valid pulses of the scan signal, realizing line-by-line scanning.

[0133] During the holding phase tk of the first display frame DA01, by controlling the output of the stage transmission of a partial shift register unit to output a valid pulse and the scan output to be at an invalid level, the partial shift register unit 20 can control a portion of pixels to stop refreshing, allowing the pixels P to be refreshed at a lower frequency, thus achieving multi-frequency driving. At the same time, the partial shift register unit 20 can still output valid pulses of the stage transmission signal sequentially, realizing the sequential shifting of the valid pulses of the initial input signal, so that the subsequent stage shift register units 20 can still receive the shifted initial input signal sequentially, that is, the subsequent stage shift register units 20 can still be driven sequentially, so that the subsequent stage shift register units 20 can be driven sequentially, and output valid pulses of the scan signal sequentially, thus realizing the segmented frequency refresh of the display panel 001.

[0134] In this embodiment of the invention, during the refresh phase, both the stage transmission output terminal and the scan output terminal of a portion of the shift register units output valid pulses, enabling some pixels to refresh at a higher frequency, thus meeting the higher refresh frequency requirements for smooth display in certain areas. During the hold phase, by controlling the stage transmission output terminal of a portion of the shift register units to output valid pulses while the scan output terminal is at an invalid level, the scan output terminal of the portion of the shift register units can be controlled to stop outputting valid pulses of the scan signal, reducing the refresh frequency of pixels in certain areas and thereby reducing the power consumption of the display panel. Simultaneously, when the scan output terminal of a portion of the shift register units stops outputting valid pulses of the scan signal, the stage transmission module of that portion of the shift register units can still output valid pulses, ensuring that the initial input signal of that portion of the shift register units can continue to shift, allowing subsequent stage shift register units to still be driven sequentially and output valid pulses of the scan signal sequentially. This reduces the refresh frequency of pixels in certain areas while still meeting the higher refresh frequency requirements for smooth display in certain areas, thereby reducing the power consumption of the display panel while ensuring display quality.

[0135] In an optional embodiment, in the first display frame, a portion of the shift register unit is a first shift register unit, and a portion of the shift register unit is a second shift register unit. During the refresh phase, controlling both the stage transmission output terminal and the scan output terminal of the portion of the shift register unit to output valid pulses includes: during the refresh phase, controlling both the stage transmission output terminal and the scan output terminal of the first shift register unit to be at an invalid level, and both the stage transmission output terminal and the scan output terminal of the second shift register unit to output valid pulses. During the hold phase, controlling the stage transmission output terminal of the portion of the shift register unit to output valid pulses, and the scan output terminal to be at an invalid level, includes: during the hold phase, controlling the stage transmission output terminal of the first shift register unit to output valid pulses, the scan output terminal of the first shift register unit to be at an invalid level, and both the stage transmission output terminal and the scan output terminal of the second shift register unit to be at an invalid level.

[0136] For details, please refer to Figure 28The first shift register unit 201 refers to the shift register unit 20 electrically connected to the pixel located in the low-frequency display area A01, and the second shift register unit 202 refers to the shift register unit 20 electrically connected to the pixel located in the high-frequency display area A02. The refresh phase tf is the phase driven by the second shift register unit 202. During the refresh phase tf, the second shift register unit 202 receives a valid pulse from the start input signal. By controlling the stage transmission output terminal NEXT and the scan output terminal GOUT of the second shift register unit 202 to output valid pulses, the pixel located in the high-frequency display area A02 can write data signals and be refreshed. During the refresh phase tf, the first shift register unit 201 does not receive a valid pulse from the start input signal, the first shift register unit 201 is not driven, and the stage transmission output terminal NEXT and the scan output terminal GOUT of the first shift register unit A01 are both at invalid levels.

[0137] The hold phase tk is the phase driven by the first shift register unit 201. During the hold phase tk, the first shift register unit 201 receives a valid pulse from the start input signal. By controlling the NEXT output terminal of the first shift register unit 201 to output a valid pulse, the scan output terminal GOUT is at an invalid level, so that the pixels located in the low-frequency display area A01 cannot write data signals, and the pixels located in the low-frequency display area A02 retain the grayscale of the previous display frame. During the hold phase tk, the second shift register unit 202 does not receive a valid pulse from the start input signal, the second shift register unit 202 is not driven, and both the NEXT output terminal and the scan output terminal GOUT of the second shift register unit 202 are at invalid levels. The pixels located in the high-frequency display area A02 can write data signals before and / or after the refresh phase tf of the same first display frame DA01 during the hold phase tk, and are refreshed.

[0138] Thus, regardless of whether it is the refresh phase tf or the hold phase tk, the stage transmission output terminal NEXT of each shift register unit 20 can output valid pulses of the stage transmission signal. Although the scan output terminal GOUT of the first shift register unit 201 is always at an invalid level in the first display frame DA01, and the scan output terminal GOUT of the second shift register unit 202 can output valid pulses, the stage transmission output terminals NEXT of both the first shift register unit 201 and the second shift register unit 202 can output valid pulses of the stage transmission signal. This allows the initial input signals of the first shift register unit 201 and the second shift register unit 202 to be shifted normally without affecting the sequential shift of the initial input signals between the first shift register unit 201 and the second shift register unit 202. Each shift register unit 20 can be driven sequentially, so that the scan output terminal GOUT of each shift register unit 20 can selectively output valid pulses according to the driving method. According to the driving method of the display panel, in the first display frame DA01, the first shift register unit 201 can be any shift register unit 20, and the second shift register unit 202 can also be any shift register unit 20. According to actual needs, in the first display frame DA01, which shift register units 20 can be the first shift register unit 201 where the scan signal is always at an invalid level, and which shift register units 20 can be the second shift register unit 202 that can output valid pulses of the scan signal, can be selected according to actual needs. That is, according to actual needs, which areas are high-frequency display areas A02, where the pixels of high-frequency display areas A02 can be refreshed at a high frequency, and which areas are low-frequency display areas A01, where the pixels of low-frequency display areas A01 can be refreshed at a low frequency, so as to achieve zoned frequency, thereby reducing the power consumption of the display panel while ensuring display quality.

[0139] Based on the above embodiments, continue to refer to Figure 28 The multi-frequency drive mode includes a second display frame DA02; the multi-frequency drive mode includes multiple drive cycles; the drive cycle includes the second display frame DA02 and the first display frame DA01; in the same drive cycle, the second display frame DA02 is located before the first display frame DA01; the drive method also includes: in the second display frame DA02, controlling the stage transmission output terminal NEXT and the scan output terminal GOUT of the first shift register unit 201 to output valid pulses, and controlling the stage transmission output terminal NEXT and the scan output terminal GOUT of the second shift register unit 202 to output valid pulses.

[0140] Specifically, in the same display cycle, in the second display frame DA02, the scan output terminals GOUT of both the first shift register unit 201 and the second shift register unit 202 can output valid pulses. Pixels located in the high-frequency display area A02 and pixels located in the low-frequency display area A01 can both receive valid pulses of the scan signal, enabling pixels located in the high-frequency display area A02 and pixels located in the low-frequency display area A01 to rewrite data signals. In the first display frame DA01, only the scan output terminal GOUT of the second shift register unit 202 can output valid pulses. Pixels located in the high-frequency display area A02 can rewrite data signals, while pixels located in the low-frequency display area A01 do not rewrite data signals, allowing pixels located in the low-frequency display area A01 to continue maintaining the grayscale of the second display frame DA02.

[0141] For example, taking a display cycle that includes a second display frame DA02 and a first display frame DA01 as an example, continue to refer to Figure 28 Pixels located in the high-frequency display area A02 can have their data signals rewritten in every display frame, while pixels located in the low-frequency display area A01 only have their data signals rewritten in the second display frame DA02. The refresh rate of pixels located in the high-frequency display area A02 is twice that of pixels located in the low-frequency display area A01, and the refresh rate of pixels located in the low-frequency display area A01 is reduced to half the refresh rate of pixels located in the high-frequency display area A02.

[0142] It is understandable that when the display cycle includes one second display frame DA02 and d first display frames DA01, the refresh frequency of the pixel located in the low-frequency display area A01 is reduced to 1 / (d+1) of the refresh frequency of the pixel located in the high-frequency display area A02; where d is a positive integer.

[0143] Optional, Figure 29 This is a flowchart of another display panel driving method provided in an embodiment of the present invention, see reference. Figure 29 The driving methods include: S2001. During the refresh phase, both the cascade clock signal at the cascade clock terminal and the scan clock signal at the scan clock terminal of the control shift register unit include valid pulses.

[0144] S2002. During the holding phase, the stage clock signal at the stage clock terminal of the control shift register unit includes a valid pulse, and the scan clock signal at the control scan clock terminal is an invalid level.

[0145] For example, taking a high level as the active level and a low level as the inactive level, Figure 30 This is a timing diagram of another display panel in multi-frequency driving mode provided by an embodiment of the present invention, for reference. Figure 30During the refresh phase tf, the cascade clock terminal NCLK of each shift register unit 20 can receive valid pulses of the cascade clock signal, the scan clock terminal GLK can receive valid pulses of the scan clock signal, and the cascade output terminal NEXT and the scan output terminal GOUT of the driven second shift register unit 202 can output valid pulses, enabling some pixels to be refreshed. During the hold phase tk, the cascade clock terminal NCLK of each shift register unit 20 can receive valid pulses of the cascade clock signal, the scan clock signal of the scan clock terminal GLK is invalid, the cascade output terminal NEXT of the driven first shift register unit 201 can output valid pulses, and the scan output terminal GOUT outputs invalid levels, causing some pixels to stop refreshing and maintain the grayscale of the previous display frame. Thus, by controlling the scan clock signal of the scan clock terminal GCLK of each shift register unit 20, the potential of the scan signal of the scan output terminal GOUT of the shift register unit 20 can be controlled, achieving segmentation and frequency division. This helps reduce the signals required by the display panel and the corresponding signal connections, and simplifies timing and circuitry.

[0146] For example, in practical applications, the cascading clock terminal NCLK and the scanning clock terminal GCLK of the shift register unit 20 can be electrically connected to the display driver chip (not shown in the figure), and the cascading clock signal of the cascading clock terminal NCLK and the scanning clock signal of the scanning clock terminal GCLK of each stage of the shift register unit 20 can be controlled by the display driver chip.

[0147] Optionally, the scanning module 230 includes a second refresh control terminal Goff2. Figure 31 This is a flowchart of another display panel driving method provided in an embodiment of the present invention, see reference. Figure 31 The driving methods include: S3001. During the refresh phase, both the cascade clock signal at the cascade clock terminal and the scan clock signal at the scan clock terminal of the control shift register unit include valid pulses, and the second refresh control terminal is at the enable level.

[0148] S3002. During the holding phase, both the cascade clock signal at the cascade clock terminal and the scan clock signal at the scan clock terminal of the control shift register unit include valid pulses, and the second refresh control terminal is at an enabled level.

[0149] Specifically, the second refresh control terminal Goff2 is the enable terminal of the scanning module 230. When the signals received by other ports of the scanning module 230 are the same, the potential of the scanning output terminal GOUT can be controlled by controlling the potential of the second refresh control terminal Goff2.

[0150] For example, taking the active and enable levels as high levels, the inactive and disabled levels as low levels, and the potential of the first fixed potential terminal VGL as low level as an example. Figure 32 This is a timing diagram of another display panel in multi-frequency driving mode provided by an embodiment of the present invention, for reference. Figure 32 During the refresh phase tf, the second refresh control terminal Goff2 of each shift register unit 20 is enabled at a high level, and the scanning module 230 of the second shift register unit 202 driven by it can output the scanning clock signal of the scanning clock terminal GCLK as a scanning signal, so that the pixels electrically connected to the second shift register unit 202 can be refreshed; during the hold phase tk, the second refresh control terminal Goff2 of each shift register unit 20 is disabled at a low level, and the scanning module 230 of the first shift register unit 201 driven by it can output the low level of the first fixed potential terminal VGL as a scanning signal, so that some pixels electrically connected to the first shift register unit 201 stop refreshing and hold the grayscale of the previous display frame.

[0151] Thus, the potential of the scan signal at the scan output terminal GOUT of the shift register unit 20 can be controlled simply by controlling the potential of the second refresh control terminal Goff2, achieving frequency division and no special design is required for other signals. For example, the scan clock signal received by the scan module 230 can always be periodically changing, without needing to control the scan clock signal to an invalid level during a certain period of time. This simplifies the design of the clock section in the display driver chip, allowing the clock section of the driver chip to change normally without changing its changing rules, which helps reduce development costs and shorten the development cycle.

[0152] For example, the second refresh control terminal Goff2 of all scanning modules 230 of all shift register units 20 can be electrically connected to the same signal line, which can be electrically connected to a display driver chip (not shown in the figure). The potential of the second refresh control terminal Goff2 of each scanning module 230 of each shift register unit 20 can be controlled by the display driver chip.

[0153] Optionally, the shift register unit includes m scanning modules; m is an integer greater than or equal to 2; during the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses, including: during the refresh phase, providing a stage transmission clock signal to the stage transmission clock terminal of the shift register unit, and providing m scan clock signals to the m scan clock terminals of the shift register unit; wherein, during the refresh phase, the valid pulses of the multiple scan clock signals provided to the same shift register unit do not overlap; in the same shift register unit, the valid pulse of the stage transmission clock signal provided to the stage transmission clock terminal overlaps with the valid pulse of at least one scan clock signal.

[0154] For example, taking m=2 and the effective level as high level as an example, Figure 33 This is a timing diagram of a shift register unit during the refresh phase according to an embodiment of the present invention. (Refer to...) Figure 33 During the refresh phase, the effective pulses of the transmission clock signal NCLK at the transmission clock terminal of the transmission module 220 can overlap with the effective pulses of the scan clock signals GCLK1 and GCLK2 at the scan clock terminals. When the transmission output terminal NEXT of the transmission module 220 outputs the effective pulses of the transmission clock terminal NCLK, the scan output terminals GOUT1 and GOUT2 of the scan module 230 can also output the effective pulses of the scan clock terminals GCLK1 and GCLK2. By setting the effective pulse of the cascading clock signal to overlap with the effective pulse of at least one scanning clock signal, during the refresh phase, the time period of the cascading clock signal output by the cascading module 220 at the cascading clock terminal NCLK and the time period of the scanning clock signal output by the scanning module 230 at the scanning clock terminal GCLK1 or GCLK2 can overlap. In this way, when the cascading module 220 stops outputting the cascading clock signal at the cascading clock terminal NCLK, the scanning module 230 can output a complete effective pulse, and when the scanning module 230 stops outputting the scanning clock signal at the scanning clock terminal GCLK1 or GCLK2, the cascading module 220 can output a complete effective pulse. This avoids a large difference in the effective time periods between the effective pulses of the cascading clock signal and the effective pulses of the scanning clock signal, which would prevent the cascading module 220 or the scanning module 230 from outputting a complete effective pulse.

[0155] Optionally, the driving circuit also includes a global reset unit; the global reset unit is used to control the signals at the stage transmission output and scan output of each shift register unit to be at an invalid level under the control of the second global control signal. Figure 34 This is a flowchart of another display panel driving method provided in an embodiment of the present invention, see reference. Figure 34 The driving methods include: S4001. During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses.

[0156] S4002. During the holding phase, the stage transmission output terminal of the shift register unit in the control section outputs a valid pulse, while the scan output terminal is at an invalid level.

[0157] Between the refresh phase and the hold phase, S4003 controls the second global control signal to switch to an active level.

[0158] For example, during the hold phase, to stop the output of valid pulses from the scan output terminals of some shift register units, it is necessary to change the potential of some signals supplied to the shift register units. This may affect the operation of the shift register units, such as the process of resetting the potential of the scan output terminals of some shift register units from an effective level to an ineffective level. This could prevent the potential of the scan output terminals of some shift register units from returning to an ineffective level, resulting in multiple rows of pixels being written with data signals simultaneously, leading to abnormal display. By controlling the second global control signal to switch to an effective level between the refresh and hold phases, the potentials of the stage transmission output terminals and scan output terminals of each shift register unit can be reset to an ineffective level, preventing the potential of the scan output terminals of the shift register units from failing to return to an ineffective level and causing display abnormalities.

[0159] Furthermore, the display panel also includes a gesture detection circuit (not shown in the figure); the first display frame also includes a detection phase, which is located between the refresh phase and the hold phase; between the refresh phase and the hold phase, the second global control signal is controlled to switch to an active level, including: during the detection phase, controlling the gesture detection circuit to operate, and controlling the cascade clock and scan clock terminals of all shift register units to be at an inactive level, and the second global control signal switching to an active level.

[0160] For example, during the detection phase, the gesture detection circuit outputs a gesture detection signal. The gesture detection signal needs to change rapidly and continuously to detect gestures. To avoid signal interference, all clock signals need to be pulled low. This may cause the potential of the stage transmission signal at the stage transmission output end of the shift register unit and the scan signal at the scan output end to not be pulled low. By switching the second global control signal to an active level, the stage transmission signal at the stage transmission output end of the shift register unit and the scan signal at the scan output end can be reset to an inactive level to avoid abnormal display.

[0161] In one embodiment, the driving method further includes: between the refresh phase and the hold phase, and before the detection phase, controlling the stage transmission clock and scan clock terminals of all shift register units to be at invalid levels, and the second global control signal to switch to an active level. This allows for a rapid reset of the stage transmission signal at the stage transmission output terminal and the scan signal at the scan output terminal after the refresh phase or hold phase ends, improving the display effect.

[0162] The display panel driving method provided in the embodiments of the present invention can be used with any of the display panels provided in the embodiments of the present invention, and has the corresponding technical features and beneficial effects of the display panel. For the contents not described in detail in the embodiments of the display panel driving method, please refer to the description of the display panel above, and will not be repeated here. Similarly, the display panel of the embodiments of the present invention also has functional modules and beneficial effects that can execute the display panel driving method provided in the embodiments of the present invention. For the contents not described in detail in the embodiments of the display panel, please refer to the description of the display panel driving method above, and will not be repeated here.

[0163] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 35 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 35 The display device 002 includes the display panel 001 provided in any embodiment of the present invention. The display device 002 provided in the embodiments of the present invention can be... Figure 35 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0164] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: The driving circuit includes multiple cascaded shift register units. The shift register unit includes a drive control module, at least one transmission module, and at least one scanning module; The drive control module includes at least a start input terminal, a scan control terminal, a first node, and a second node; The stage transmission module includes a first input terminal, a second input terminal, a first level terminal, a stage transmission clock terminal, and a stage transmission output terminal; the first input terminal is electrically connected to the first node, and the second input terminal is electrically connected to the second node; the first level terminal is electrically connected to a first fixed potential terminal; wherein, the stage transmission output terminal of the i-th stage shift register unit is electrically connected to the starting input terminal of the j-th stage shift register unit, i≠j, and i and j are both positive integers; The scanning module includes a third input terminal, a fourth input terminal, a second level terminal, a scanning clock terminal, and a scanning output terminal; the third input terminal is electrically connected to the first node; The second voltage level terminal is electrically connected to the first fixed voltage terminal; The display panel includes a multi-frequency driving mode. In the multi-frequency driving mode, at least a portion of the display frames have a partial refresh time, and the potentials of the stage transmission signal output from the stage transmission output terminal and the scan signal output from the scan output terminal of the same shift register unit are different.

2. The display panel according to claim 1, characterized in that, In the same shift register unit, the cascade clock terminal and the scan clock terminal are not connected.

3. The display panel according to claim 2, characterized in that, The driving circuit includes multiple output clock lines, multiple first clock terminals, multiple switches, and a first refresh control terminal; The input terminal of the switch is electrically connected to the first clock terminal; the output terminal of the switch is electrically connected to the output clock line, and the output clock line is electrically connected to the scan clock terminals of at least two of the shift register units; the control terminal of the switch is electrically connected to the first refresh control terminal.

4. The display panel according to claim 3, characterized in that, The switch includes a first switching transistor and a second switching transistor; The first terminal of the first switching transistor is electrically connected to the first clock terminal; the second terminal of the first switching transistor is electrically connected to the output clock line. The first terminal of the second switching transistor is electrically connected to the first fixed potential terminal; the second terminal of the second switching transistor is electrically connected to the output clock line. The gates of the first switching transistor and the second switching transistor are both electrically connected to the first refresh control terminal.

5. The display panel according to claim 2, characterized in that, In the same shift register unit, the fourth input terminal is electrically connected to the second node; The scanning module includes a first scanning unit and a second scanning unit; The input terminal of the first scanning unit is electrically connected to the first fixed potential terminal; the output terminal of the first scanning unit is electrically connected to the scanning output terminal; the control terminal of the first scanning unit is electrically connected to the third input terminal. The input terminal of the second scanning unit is electrically connected to the scanning clock terminal; the output terminal of the second scanning unit is electrically connected to the scanning output terminal; and the control terminal of the second scanning unit is electrically connected to the fourth input terminal.

6. The display panel according to claim 1, characterized in that, In the same shift register unit, the fourth input terminal is electrically connected to the stage output terminal; The scanning module includes a first scanning unit, a second scanning unit, and a second refresh control terminal; The input terminal of the first scanning unit is electrically connected to the first fixed potential terminal; the output terminal of the first scanning unit is electrically connected to the scanning output terminal; the control terminal of the first scanning unit is electrically connected to the third input terminal. The input terminal of the second scanning unit is electrically connected to the scanning clock terminal; the output terminal of the second scanning unit is electrically connected to the scanning output terminal; the first control terminal of the second scanning unit is electrically connected to the fourth input terminal; and the second control terminal of the second scanning unit is electrically connected to the second refresh control terminal.

7. The display panel according to claim 6, characterized in that, In the same shift register unit, the number of the cascading modules is equal to the number of the scanning modules; one cascading module and one scanning module constitute an output group; The scan clock terminal of the same output group is electrically connected to the cascade clock terminal.

8. The display panel according to claim 5 or 6, characterized in that, The first scanning unit includes a first scanning transistor; The gate of the first scanning transistor is electrically connected to the first node; the first electrode of the first scanning transistor is electrically connected to the first fixed potential terminal; and the second electrode of the first scanning transistor is electrically connected to the scanning output terminal.

9. The display panel according to claim 6, characterized in that, The second scanning unit includes a refresh control transistor and a second scanning transistor; The gate of the second scanning transistor is electrically connected to the second terminal of the refresh control transistor; the first terminal of the second scanning transistor is electrically connected to the scan clock terminal; and the second terminal of the second scanning transistor is electrically connected to the scan output terminal. The first terminal of the refresh control transistor is electrically connected to the stage output terminal; the gate of the refresh control transistor is electrically connected to the second refresh control terminal.

10. The display panel according to claim 9, characterized in that, The second scanning unit also includes an auxiliary transistor; The first terminal of the auxiliary transistor is electrically connected to the stage output terminal; the second terminal of the auxiliary transistor is electrically connected to the first terminal of the refresh control transistor; and the gate of the auxiliary transistor is electrically connected to the scan clock terminal.

11. The display panel according to claim 9, characterized in that, The second scanning unit also includes a pull-down transistor; The gate of the pull-down transistor is electrically connected to the first node; the first terminal of the pull-down transistor is electrically connected to the first fixed potential terminal; and the second terminal of the pull-down transistor is electrically connected to the gate of the second scanning transistor.

12. The display panel according to claim 1, characterized in that, The transmission module includes a first-level transmission unit and a second-level transmission unit; The input terminal of the first-stage transmission unit is electrically connected to the first fixed potential terminal; the output terminal of the first-stage transmission unit is electrically connected to the stage transmission output terminal; the control terminal of the first-stage transmission unit is electrically connected to the first input terminal. The input terminal of the second-stage transmission unit is electrically connected to the clock terminal of the stage transmission unit; the output terminal of the second-stage transmission unit is electrically connected to the output terminal of the stage transmission unit; and the control terminal of the second-stage transmission unit is electrically connected to the second input terminal.

13. The display panel according to claim 1, characterized in that, The shift register unit includes n of the cascade modules; n is an integer greater than or equal to 2; In the same shift register unit, the effective pulses of the transmission clock signals received by the transmission clock terminals of each transmission module do not overlap, and within one clock cycle, the transmission clock signal that becomes an effective pulse at the kth stage is the kth stage transmission clock signal; the transmission module that receives the kth stage transmission clock signal is the kth stage transmission module; k is a positive integer less than or equal to n; The nth-level transmission output terminal of the s-th-level shift register unit is electrically connected to the starting input terminal of the (s+1)-th-level shift register unit; s is a positive integer.

14. The display panel according to claim 1, characterized in that, The drive control module includes an input unit, a reset unit, and an interlock unit; the drive control module also includes a reset clock terminal; The input unit is electrically connected to the starting input terminal, the scanning control terminal, and the second node, respectively. The reset unit is electrically connected to the scan control terminal, the reset clock terminal, the first node, and the second fixed potential terminal, respectively. The interlocking unit is electrically connected to the first node, the second node, and the first fixed potential terminal, respectively.

15. The display panel according to claim 1, characterized in that, The drive control module includes a scan control unit and an enable control unit; the drive control module also includes an enable clock terminal and a third node; The scanning control unit is electrically connected to the starting input terminal, the scanning control terminal, and the third node, respectively; the scanning control unit is used to receive the starting input signal from the starting input terminal and the scanning control signal from the scanning control terminal, and to control the signal of the third node; The enable control unit is electrically connected to the enable clock terminal, the third node, the second fixed potential terminal, the first node, and the second node, respectively. The enable control unit is used to receive the enable clock signal from the enable clock terminal, the signal from the third node, and the second fixed potential signal from the second fixed potential terminal, and to control the signals from the first node and the second node.

16. The display panel according to claim 15, characterized in that, The scanning control unit includes a first scanning control transistor; The gate of the first scan control transistor is electrically connected to the scan control terminal; the first electrode of the first scan control transistor is electrically connected to the start input terminal; and the second electrode of the first scan control transistor is electrically connected to the third node.

17. The display panel according to claim 15, characterized in that, The enabling control unit includes a first enabling transistor, a second enabling transistor, and a third enabling transistor; The gate of the first enabling transistor is electrically connected to the enabling clock terminal; the first terminal of the first enabling transistor is electrically connected to the third node; the second terminal of the first enabling transistor and the gate of the second enabling transistor are electrically connected to the second node. The first terminal of the second enabling transistor is electrically connected to the enabling clock terminal; the second terminal of the second enabling transistor and the second terminal of the third enabling transistor are electrically connected to the first node; The gate of the third enabling transistor is electrically connected to the enabling clock terminal; the first terminal of the third enabling transistor is electrically connected to the second fixed potential terminal.

18. The display panel according to claim 15, characterized in that, The shift register unit includes n of the cascading modules and m of the scanning modules; where n < m; The stage clock terminal of the s-th stage shift register is electrically connected to the enable clock terminal of the p-th stage shift register, where s ≠ p, and both s and p are positive integers.

19. The display panel according to claim 18, characterized in that, n=1； The display panel further includes a first shift clock line and a second shift clock line; The enable clock terminal of the 2s-1 stage shift register unit is electrically connected to the first shift clock line, and the stage clock terminal is electrically connected to the second shift clock line. The enable clock terminal of the second-stage shift register unit is electrically connected to the second shift clock line, and the cascade clock terminal is electrically connected to the first shift clock line. Where s is a positive integer.

20. The display panel according to claim 19, characterized in that, The display panel also includes m first output clock lines and m second output clock lines; The m scanning modules of the 2s-1 level shift register unit are electrically connected one-to-one with the m first output clock lines; The m scanning modules of the second-stage shift register unit are electrically connected one-to-one with the m second output clock lines.

21. The display panel according to claim 1, characterized in that, The driving circuit also includes a global scanning unit; The global scanning unit is used to control the first node of each shift register unit to an invalid level under the control of the first global control signal, and to control the signals of the stage transmission output terminal and the scan output terminal of each shift register unit to an active level.

22. The display panel according to claim 21, characterized in that, The global scanning unit includes a first scanning transistor, a second scanning transistor, and a third scanning transistor; The gates of the first scanning transistor, the second scanning transistor, and the third scanning transistor all receive the first global control signal; The first terminal of the first scanning transistor is electrically connected to the first fixed potential terminal, and the second terminal of the first scanning transistor is electrically connected to the first node of each of the shift register units. The first terminal of the second scanning transistor is electrically connected to the second fixed potential terminal, and the second terminal of the second scanning transistor is electrically connected to the stage transmission output terminal of each of the shift register units. The first terminal of the third scanning transistor is electrically connected to the second fixed potential terminal, and the second terminal of the third scanning transistor is electrically connected to the scanning output terminal of each of the shift register units.

23. The display panel according to claim 1, characterized in that, The driving circuit also includes a global reset unit; The global reset unit is used to control the signals at the stage transmission output terminal and the scan output terminal of each of the shift register units to an invalid level under the control of the second global control signal.

24. The display panel according to claim 23, characterized in that, The global reset unit includes a fourth scanning transistor and a fifth scanning transistor; The gates of both the fourth and fifth scanning transistors receive the second global control signal; the first terminals of both the fourth and fifth scanning transistors are electrically connected to the first fixed potential terminal. The second terminal of the fourth scanning transistor is electrically connected to the stage transmission output terminal of each of the shift register units; The second terminal of the fifth scanning transistor is electrically connected to the scanning output terminal of each of the shift register units.

25. A driving method for a display panel, characterized in that, For driving the display panel according to any one of claims 1-24; The display panel includes a multi-frequency driving mode; at least a portion of the display frames in the multi-frequency driving mode are first display frames; the first display frame includes a refresh phase and a hold phase; The driving method includes: During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses; During the holding phase, the stage transmission output terminal of the shift register unit in the control section outputs a valid pulse, while the scan output terminal is at an invalid level.

26. The driving method for a display panel according to claim 25, characterized in that, In the first display frame, some of the shift register units are first shift register units, and some of the shift register units are second shift register units; During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses, including: During the refresh phase, the stage transmission output terminal and the scan output terminal of the first shift register unit are both at invalid levels, while the stage transmission output terminal and the scan output terminal of the second shift register unit both output valid pulses. During the holding phase, the stage transmission output terminal of the shift register unit in the control section outputs a valid pulse, while the scan output terminal is at an invalid level, including: During the holding phase, the stage output terminal of the first shift register unit is controlled to output a valid pulse, the scan output terminal of the first shift register unit is at an invalid level, and both the stage output terminal and the scan output terminal of the second shift register unit are at invalid levels.

27. The driving method for a display panel according to claim 26, characterized in that, The multi-frequency drive mode includes a portion of the display frames as second display frames; the multi-frequency drive mode includes multiple drive cycles; the drive cycle includes the second display frame and the first display frame; In the same driving cycle, the second display frame is located before the first display frame; The driving method further includes: In the second display frame, the first shift register unit's stage transmission output terminal and the scan output terminal both output valid pulses, and the second shift register unit's stage transmission output terminal and the scan output terminal both output valid pulses.

28. The driving method for a display panel according to claim 25, characterized in that, During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses, including: During the refresh phase, both the cascading clock signal at the cascading clock terminal and the scanning clock signal at the scanning clock terminal of the shift register unit include valid pulses. During the holding phase, the stage transmission output terminal of the shift register unit in the control section outputs a valid pulse, while the scan output terminal is at an invalid level, including: During the holding phase, the cascading clock signal controlling the cascading clock terminal of the shift register unit includes a valid pulse, and the scanning clock signal controlling the scanning clock terminal is at an invalid level.

29. The driving method for a display panel according to claim 25, characterized in that, The scanning module includes a second refresh control terminal; During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses, including: During the refresh phase, both the cascading clock signal at the cascading clock terminal and the scanning clock signal at the scanning clock terminal of the shift register unit include valid pulses, and the second refresh control terminal is at an enable level. During the holding phase, the stage transmission output terminal of the shift register unit in the control section outputs a valid pulse, while the scan output terminal is at an invalid level, including: During the holding phase, both the cascading clock signal at the cascading clock terminal and the scanning clock signal at the scanning clock terminal of the shift register unit include valid pulses, and the second refresh control terminal is at an enabled level.

30. The driving method for a display panel according to claim 25, characterized in that, The shift register unit includes m scanning modules; m is an integer greater than or equal to 2; During the refresh phase, both the stage transmission output terminal and the scan output terminal of the shift register unit in the control section output valid pulses, including: During the refresh phase, a cascading clock signal is provided to the cascading clock terminal of the shift register unit, and m scanning clock signals are provided to the m scanning clock terminals of the shift register unit. During the refresh phase, the effective pulses of the multiple scan clock signals supplied to the same shift register unit do not overlap; within the same shift register unit, the effective pulses of the cascade clock signal supplied to the cascade clock terminal overlap with at least one effective pulse of the scan clock signal.

31. The driving method for a display panel according to claim 25, characterized in that, The driving circuit also includes a global reset unit; The global reset unit is used to control, under the control of the second global control signal, the signals of the stage transmission output terminal and the scan output terminal of each of the shift register units to be at an invalid level; The driving method further includes: Between the refresh phase and the hold phase, the second global control signal is controlled to transition to an active level.

32. The driving method for a display panel according to claim 31, characterized in that, The display panel also includes a gesture detection circuit; The first display frame further includes a detection phase, which is located between the refresh phase and the hold phase; Between the refresh phase and the hold phase, controlling the second global control signal to transition to an active level includes: During the detection phase, the gesture detection circuit is controlled to operate, and the cascade clock terminal and the scan clock terminal of all shift register units are controlled to be at an invalid level, and the second global control signal jumps to an active level.

33. A display device, characterized in that, Includes the display panel as described in any one of claims 1-24.

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