Chip isolation packaging structure and method

Abstract

The present invention relates to the field of chip packaging, and in particular to a chip isolation packaging structure and method, comprising two adjacently stacked dielectric substrates; the lower surface of the upper dielectric substrate includes a downward metal dam, and the upper surface of the lower dielectric substrate includes an upward metal dam; the upward metal dam corresponds to the position of the downward metal dam and is interconnected to form a chip isolation cavity; an isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the lower surface of the downward metal dam and / or the upper surface of the upward metal dam; the upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating. The present invention uses patterned electroplating to set metal dams in both the upward and downward directions to form a chip packaging cavity, which has good shielding performance and can also serve as a support structure between the upper and lower layers, thereby improving the structural stability of the overall package, high flexibility, simple process, and improved space utilization.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a chip isolation packaging structure and method. Background Art

[0002] With the advancement of RF technology, microsystem packaging is becoming increasingly smaller and more functional. However, device shielding and isolation between components are hindering product performance. To address these issues, there are two approaches: global and local. Global approaches primarily involve using technical partitions to divide the cavity on the substrate and repackaging multiple independent SIPs (system-in-package) into new SIPs. These approaches have low space utilization. Local approaches primarily involve wrapping the chip with bond wires and forming shielded cavities using substrate slots and vias. These approaches undoubtedly increase the number of substrate layers and process complexity, while also providing limited isolation and application scenarios.

[0003] Therefore, how to balance the miniaturization of the chip system-level packaging with a simple packaging process, a high product yield and excellent isolation effect is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip isolation packaging structure and method to solve the problem in the prior art that as the system-level packaging volume becomes smaller and smaller, the packaging process becomes more and more complicated, the finished product yield becomes lower and lower, and the isolation effect becomes worse and worse.

[0005] In order to solve the above technical problems, the present invention provides a chip isolation packaging structure, comprising two adjacently stacked dielectric substrates;

[0006] The lower surface of the dielectric substrate located above includes a downward metal dam, and the upper surface of the dielectric substrate located below includes an upward metal dam; the upward metal dam corresponds to the downward metal dam in position and is connected to each other to form a chip isolation cavity;

[0007] The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the lower surface where the downward metal dam is located and / or the upper surface where the upward metal dam is located;

[0008] The upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating.

[0009] Optionally, in the chip isolation package structure, the isolation chip is electrically connected to an external circuit via a signal line of a redistribution layer on the surface of the isolation chip;

[0010] The metal dam corresponding to the surface where the isolation chip is located is used as an opening dam, and the opening dam is provided with an isolation electroplating growth area at a position corresponding to the signal line.

[0011] Optionally, in the chip isolation packaging structure, there is only one opening dam in a single chip isolation cavity;

[0012] A ratio of a height of the opening dam to a total height of the corresponding chip isolation cavity is smaller than a preset first threshold.

[0013] Optionally, in the chip isolation packaging structure, a chip isolation cavity consisting of a plurality of the upward metal dams and the downward metal dams is provided between two adjacent layers of the dielectric substrate.

[0014] Optionally, in the chip isolation packaging structure, the dielectric substrate is an aluminum nitride ceramic substrate.

[0015] Optionally, in the chip isolation packaging structure, the upward metal dam and the downward metal dam in the same chip isolation cavity are welded together.

[0016] Optionally, in the chip isolation packaging structure, the upward metal dam and / or the downward metal dam is a metal copper dam.

[0017] Optionally, in the chip isolation packaging structure, the lower surface of the upper dielectric substrate includes a downward airtight dam, and the upper surface of the lower dielectric substrate includes an upward airtight dam.

[0018] The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber;

[0019] The chip isolation cavity is arranged in the airtight isolation chamber.

[0020] Optionally, in the chip isolation packaging structure, a single airtight isolation chamber includes a plurality of chip isolation cavities.

[0021] Optionally, in the chip isolation packaging structure, the lower surface of the upper dielectric substrate includes downward-pointing metal needles, and the upper surface of the lower dielectric substrate includes upward-pointing metal needles;

[0022] The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other;

[0023] The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle and the downward metal needle;

[0024] The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating.

[0025] Optionally, in the chip isolation packaging structure, the chip isolation packaging structure includes N stacked dielectric substrates; N is not less than 3;

[0026] The dielectric substrate at the top layer includes the downward metal dam, the dielectric substrate at the bottom layer includes the upward metal dam, and the dielectric substrate at the middle layer includes the upward metal dam and the downward metal dam. All the metal dams constitute the N-1 layer chip isolation cavity.

[0027] A chip isolation packaging structure includes two first packaging units;

[0028] The first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating;

[0029] The first surfaces of the two first packaging units are arranged opposite to each other, so that the metal dams of the two first surfaces are positioned correspondingly and connected to each other to form a chip isolation cavity;

[0030] The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the first surface;

[0031] The metal dam is a metal structure obtained by patterned electroplating.

[0032] A chip isolation packaging method, comprising:

[0033] The isolation chip is disposed in a metal dam of a first packaging unit; the first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating;

[0034] Arranging the first surfaces of the two first packaging units to face each other, with the metal dams of the two first packaging units positioned correspondingly;

[0035] The metal dams of the two first packaging units are welded together so that the two opposite metal dams form a chip isolation cavity; the chip isolation cavity includes at least one isolation chip.

[0036] A chip isolation packaging structure includes a second packaging unit and two first packaging units;

[0037] The first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating;

[0038] The second packaging unit includes a dielectric substrate and metal dams disposed on a first surface and a second surface of the dielectric substrate;

[0039] The first surfaces of the two first packaging units are arranged opposite to each other, and the second packaging unit is arranged between the two first packaging units;

[0040] The metal dams on the surfaces of adjacent packaging units are arranged in a corresponding position and are interconnected to form a chip isolation cavity;

[0041] The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the surface of the dielectric substrate;

[0042] The metal dam is a metal structure obtained by patterned electroplating.

[0043] A chip isolation packaging method, comprising:

[0044] The isolation chip is disposed within the metal dam of the first packaging unit and / or the second packaging unit; the first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; the second packaging unit includes a dielectric substrate and metal dams disposed on the first and second surfaces of the dielectric substrate;

[0045] The second packaging unit is stacked with two of the first packaging units, wherein the first surfaces of the two first packaging units are arranged opposite to each other, the second packaging unit is stacked between the two first packaging units, and the metal dams on the oppositely arranged surfaces of adjacent packaging units are positioned correspondingly;

[0046] The metal dams at corresponding positions on adjacent packaging units are welded together so that two opposite metal dams form a chip isolation cavity; the chip isolation cavity includes at least one isolation chip.

[0047] The chip isolation packaging structure provided by the present invention includes two adjacent layers of dielectric substrates; the lower surface of the upper dielectric substrate includes a downward metal dam, and the upper surface of the lower dielectric substrate includes an upward metal dam; the upward metal dam corresponds to the position of the downward metal dam and is interconnected to form a chip isolation cavity; the isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the lower surface where the downward metal dam is located and / or the upper surface where the upward metal dam is located; the upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating. The present invention uses patterned electroplating to set metal dams in both the upward and downward directions to form a chip packaging cavity, which not only has good shielding performance, but also can serve as a support structure between the upper and lower layers, improving the overall structural stability of the package. At the same time, the patterned electroplating setting is highly flexible, the process is simple, the finished product yield is high, and compared with existing related technologies, it occupies less space, which can further improve space utilization. The present invention also provides a chip isolation packaging structure and method with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 A schematic structural diagram of a specific embodiment of the chip isolation packaging structure provided by the present invention;

[0050] Figure 2 A schematic structural diagram of a specific embodiment of the chip isolation packaging structure provided by the invention;

[0051] Figure 3 A schematic diagram of the partial structure of a specific embodiment of the chip isolation packaging structure provided by the invention;

[0052] Figure 4 A partial top view of a specific embodiment of the chip isolation packaging structure provided by the invention;

[0053] Figure 5 A schematic diagram of the partial structure of a specific embodiment of the chip isolation packaging structure provided by the invention;

[0054] Figure 6 A partial front view of a specific embodiment of the chip isolation packaging structure provided by the invention;

[0055] Figure 7A schematic diagram of a partial structure of another specific embodiment of the chip isolation packaging structure provided by the invention;

[0056] Figure 8 A schematic diagram of a partial structure of another specific embodiment of the chip isolation packaging structure provided by the invention;

[0057] Figure 9 A schematic flow chart of a specific implementation of the chip isolation packaging method provided by the invention;

[0058] Figure 10 A schematic flow chart of another specific implementation of the chip isolation packaging method provided by the invention.

[0059] In the figure, it includes 01-dielectric substrate, 01a-first dielectric substrate, 01b-second dielectric substrate, 01'-topmost dielectric substrate, 01''-bottommost dielectric substrate, 01'''-middle dielectric substrate, 02-upward metal dam, 02a-first upward metal dam, 02b-second upward metal dam, 03-downward metal dam, 03a-first downward metal dam, 03b-second downward metal dam, 04-isolation chip, 04a-first isolation chip, 04b-second isolation chip, 05-upward airtight dam, 06-downward airtight dam, 07-solder, 08-bonding wire, 09-metal via, 10-solder ball, 11-surface mount chip, 12a-first redistribution layer, 12b-second redistribution layer, 12c-third redistribution layer, 12d-fourth redistribution layer, 13-upward metal needle, 14-downward metal needle, 15-signal line. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0061] The core of the present invention is to provide a chip isolation packaging structure, a structural diagram of a specific embodiment of which is shown in FIG. Figure 1 As shown, it is called the specific embodiment 1, including two adjacently stacked dielectric substrates 01;

[0062] The lower surface of the dielectric substrate 01 located above includes a downward metal dam 03, and the upper surface of the dielectric substrate 01 located below includes an upward metal dam 02; the upward metal dam 02 corresponds to the downward metal dam 03 and is connected to each other to form a chip isolation cavity;

[0063] The isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is arranged on the lower surface of the downward metal dam 03 and / or the upper surface of the upward metal dam 02;

[0064] The upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating.

[0065] The dielectric substrate 01 is an aluminum nitride ceramic substrate. Aluminum nitride ceramic substrates have advantages such as good thermal conductivity, strong sealing, and high stability. Of course, they can be adjusted according to actual conditions, but high-temperature co-fired ceramic dielectric materials are preferred because of their high thermal conductivity and low thermal expansion coefficient, good thermal conductivity and structural stability.

[0066] In the present invention, the metal dam half-cavity structure itself serves as a cover plate structure, which not only meets the airtightness requirements but also eliminates the sealing process. At the same time, it efficiently utilizes the upper and lower spaces of the structure, improves space utilization, and helps to reduce the volume of the microsystem. The half-cavity structure design has great advantages in equipment upgrades, module maintenance, and optional configuration. Different chips can be placed inside the half-cavity structure according to different needs to form half-cavity structure semi-finished products with different functions, which can be arbitrarily combined according to specific needs, with high reconfigurability. At the same time, the standardized and unified design can improve the design efficiency of engineers, simplify assembly complexity, improve production efficiency, and reduce costs.

[0067] Furthermore, the upward metal dam 02 and the downward metal dam 03 in the same chip isolation cavity are connected by welding. Welding connection is more secure, has better sealing performance, and is relatively simple to process. Specifically, the welding connection is performed by soldering. Of course, other connection methods can also be used according to specific circumstances, and the present invention is not limited here.

[0068] Specifically, the upward metal dam 02 and / or the downward metal dam 03 are copper dams. Copper has good deposition performance and a simple electroplating process, achieving both high production rates and a dense structure. Of course, other metal dam materials can also be used depending on the actual situation.

[0069] As a preferred embodiment, the lower surface of the dielectric substrate 01 located at the top includes a downward airtight dam 06, and the upper surface of the dielectric substrate 01 located at the bottom includes an upward airtight dam 05;

[0070] The upward airtight dam 05 and the downward airtight dam 06 are located in corresponding positions and are connected to each other to form an airtight isolation chamber;

[0071] The chip isolation cavity is arranged in the airtight isolation chamber.

[0072] In this preferred embodiment, in addition to the upward metal dam 02 and the downward metal dam 03 that constitute the chip isolation cavity, the downward airtight dam 06 and the upward airtight dam 05 are additionally provided on the dielectric substrate 01. The airtight dam is a dam that encloses the metal dam and leaves no openings after the upper and lower parts are connected. This ensures the stability of the atmosphere in the airtight isolation chamber after the connection, improves the isolation effect, and further provides support for the packaging structure, thereby achieving better device operation stability.

[0073] Furthermore, a single airtight isolation chamber can include multiple chip isolation cavities. Chips of a type susceptible to external interference can be uniformly placed in corresponding areas of the dielectric substrate 01, which are then sealed using the upward airtight dam 05 and the downward airtight dam 06, thereby simplifying the packaging structure and improving packaging efficiency. Of course, preferably, the upward airtight dam 05 and the downward airtight dam 06 are installed simultaneously with the upward metal dam 02 and the downward metal dam 03.

[0074] Furthermore, the lower surface of the dielectric substrate 01 located above includes downward-pointing metal needles 14, and the upper surface of the dielectric substrate 01 located below includes upward-pointing metal needles 13;

[0075] The downward metal needle 14 corresponds to the upward metal needle 13 in position and is connected to each other;

[0076] The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle 13 and the downward metal needle 14;

[0077] The upward metal needle 13 and the downward metal needle 14 are metal structures obtained by pattern electroplating.

[0078] In this preferred embodiment, the upward metal needles 13 and the downward metal needles 14 are obtained by pattern electroplating technology, which not only realizes the signal connection between the two dielectric substrates 01 in the stacking direction, but also allows the upward metal needles 13, the downward metal needles 14 and the metal dam to be set at the same time, greatly shortening the packaging time.

[0079] The chip isolation packaging structure provided by the present invention includes two adjacently stacked dielectric substrates 01; the lower surface of the upper dielectric substrate 01 includes a downward metal dam 03, and the upper surface of the lower dielectric substrate 01 includes an upward metal dam 02; the upward metal dam 02 corresponds to the position of the downward metal dam 03 and is interconnected to form a chip isolation cavity; the isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is arranged on the lower surface where the downward metal dam 03 is located and / or the upper surface where the upward metal dam 02 is located; the upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating. The present invention uses patterned electroplating to set metal dams in both the upward and downward directions to form a chip packaging cavity, which not only has good shielding performance, but also can serve as a support structure between the upper and lower layers, thereby improving the structural stability of the overall package. At the same time, the patterned electroplating setting is highly flexible, the process is simple, and the finished product yield is high. Compared with existing related technologies, it occupies less space and can further improve space utilization.

[0080] The following is a brief introduction Figure 2 、 Figure 3 and Figure 4 Each structure in Figure 2 This is a cross-sectional view showing the structural diagram of a complete BGA (ball grid array) package formed after two adjacent stacked dielectric substrates are assembled.

[0081] Figure 3 To display only Figure 2 A schematic cross-sectional view of the first dielectric substrate 01a and the structure thereon, Figure 4 for Figure 3The top view of the structure corresponds to the following: the first isolation chip 04a is placed on the ground circuit of the second redistribution layer 12b and is connected to the pad on the second redistribution layer 12b through the bonding wire 08; the second isolation chip 04b is placed on the ground circuit of the second redistribution layer 12b and is connected to the pad on the second redistribution layer 12b through the bonding wire 08; the first upward metal dam 02a is integrated with the first dielectric substrate 01a, enclosing the first isolation chip 04a that needs to be shielded, and slots are opened at the input and output ports to leave space for signal routing; the second upward metal dam 02b is integrated with the first dielectric substrate 01a, enclosing the second isolation chip 04a that needs to be shielded 4b is surrounded, and grooves are opened at the input and output ports to reserve space for signal routing; the corresponding metal via 09 is located in the first dielectric substrate 01a in the form of a through hole, connecting the first redistribution layer 12a and the second redistribution layer 12b; the upward metal needle 13 is located on the signal circuit of the second redistribution layer 12b, and transmits the signal vertically; the solder 07 is located on the top surface of the first upward metal dam 02a, the second upward metal dam 02b, the upward metal needle 13, and the upward airtight dam 05; the upward airtight dam 05 is integrated with the first dielectric substrate 01a and is located at the outermost edge of the entire upper surface of the substrate; the solder ball 10 is connected to the pad on the first redistribution layer 12a.

[0082] like Figure 5 To display only Figure 2 Schematic diagram of a cross-section of the second dielectric substrate 01b and the structure thereon, wherein the third isolation chip 04c is placed on the ground circuit of the third redistribution layer 12c and is connected to the pad on the third redistribution layer 12c via a bonding wire 08; the first downward metal dam 03a is integrated with the second dielectric substrate 01b and is located on the lower surface of the second dielectric substrate 01b, with a relative position and shape of Figure 1 The first upward metal dam 02a is the same as the first upward metal dam 02a; the second downward metal dam 03b is integrated with the second dielectric substrate 01b, enclosing the third isolation chip 04c that needs to be shielded, and slotting the input and output ports to leave space for signal routing; the second downward metal dam 03b is located on the lower surface of the second dielectric substrate 01b, and its relative position and shape are the same as Figure 1 The second upward metal dam 02b is the same as the second upward metal dam 02b in FIG. The package structure may also include another surface-mount chip 11, which is bonded to the signal circuit of the third redistribution layer 12c. The downward metal pins 14 are located on the signal circuit of the third redistribution layer 12c, transmitting signals vertically. The downward airtight dam 06 is integral with the second dielectric substrate 01b and is located at the outermost edge of the entire substrate's lower surface. The fourth redistribution layer 12d has no structure.

[0083] Preferably, between two adjacent layers of the dielectric substrate 01 , there is a chip isolation cavity consisting of a plurality of the upward metal dams 02 and the downward metal dams 03 .

[0084] You can also refer to Figure 2 A plurality of chip isolation cavities can be provided between a pair of adjacent dielectric substrates 01, and of course more isolation chips 04 can be provided, thereby increasing the chip laying density and further expanding the versatility of the present invention.

[0085] On the basis of the first embodiment, the metal dam is further improved to obtain the second embodiment, the corresponding partial structure diagram of which is shown as follows: Figure 6 As shown, it includes two adjacently stacked dielectric substrates 01;

[0086] The lower surface of the dielectric substrate 01 located above includes a downward metal dam 03, and the upper surface of the dielectric substrate 01 located below includes an upward metal dam 02; the upward metal dam 02 corresponds to the downward metal dam 03 and is connected to each other to form a chip isolation cavity;

[0087] The isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is arranged on the lower surface of the downward metal dam 03 and / or the upper surface of the upward metal dam 02;

[0088] The upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating;

[0089] The isolation chip 04 is electrically connected to the external circuit via the signal line 15 of the redistribution layer on the surface;

[0090] The metal dam corresponding to the surface where the isolation chip 04 is located is used as an opening dam, and the opening dam is provided with an isolation electroplating growth area at a position corresponding to the signal line 15 .

[0091] The difference between this embodiment and the above embodiment is that, in this embodiment, the area where the signal line 15 is provided is left blank, and the rest of the structure is the same as that of the above embodiment, which will not be described in detail here.

[0092] This specific embodiment describes that the isolation chip 04 is connected to the external circuit via the redistribution layer on the surface of the dielectric substrate 01 on which it is located. Therefore, when patterning the corresponding metal dam, the corresponding signal line 15 used for signal transmission needs to be kept out of the way to prevent the signal line 15 from contacting the metal dam and causing a ground short circuit, thereby causing signal interference. Therefore, this specific embodiment further defines the metal dam corresponding to the surface on which the isolation chip 04 is located (for example, if the isolation chip 04 is located on the upper surface of the underlying dielectric substrate 01, the corresponding metal dam is the upward metal dam 02). An isolation plating growth area is added to the corresponding metal dam. The isolation plating growth area is an area on the dielectric substrate 01 through which the signal line 15 passes. When patterning the corresponding metal dam, the isolation plating growth area is avoided. In other words, the metal dam is not plated and grown in the isolation plating growth area. This reserves an opening area for the signal line 15 to pass through without adding additional steps. Figure 6 A front view of a chip isolation cavity with an open dam.

[0093] Furthermore, there is only one opening dam in a single chip isolation cavity;

[0094] The ratio of the height of the opening dam to the total height of the corresponding chip isolation cavity is less than a preset first threshold. It should be noted that since only the metal dam corresponding to the surface where the isolation chip 04 is located needs to reserve the isolation electroplating growth area, and there is no need to reserve the isolation electroplating growth area on the other dielectric substrate 01, the lower the height of the metal dam on the surface where the isolation chip 04 is located, the smaller the opening between the chip isolation cavity and the outside world, and the better the packaging effect. Therefore, the first threshold can be set in advance to make the metal dam where the isolation electroplating growth area exists as low as possible to achieve a better packaging effect. The range of the first threshold can be 0.3 to 0.5, including endpoint values, such as any one of 0.30, 0.44 or 0.50. Of course, it can also be adjusted according to actual conditions, and the present invention is not limited here.

[0095] On the basis of the specific embodiment 1, the number of the dielectric substrate 01 and the metal dam thereon are further limited to obtain the specific embodiment 3, and the corresponding partial structure diagram thereof is as follows: Figure 7 As shown, it includes two adjacently stacked dielectric substrates 01;

[0096] The lower surface of the dielectric substrate 01 located above includes a downward metal dam 03, and the upper surface of the dielectric substrate 01 located below includes an upward metal dam 02; the upward metal dam 02 corresponds to the downward metal dam 03 and is connected to each other to form a chip isolation cavity;

[0097] The isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is arranged on the lower surface of the downward metal dam 03 and / or the upper surface of the upward metal dam 02;

[0098] The upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating;

[0099] The chip isolation packaging structure includes N stacked dielectric substrates 01; N is not less than 3;

[0100] The dielectric substrate 01 at the top layer includes the downward metal dam 03, the dielectric substrate 01 at the bottom layer includes the upward metal dam 02, and the dielectric substrate 01 at the middle layer includes the upward metal dam 02 and the downward metal dam 03. All the metal dams constitute the N-1 layer chip isolation cavity.

[0101] The difference between this embodiment and the above embodiment is that in this embodiment, more layers of dielectric substrate 01 are provided and the metal dam is modified accordingly. The rest of the structure is the same as the above embodiment and will not be described in detail here.

[0102] The most commonly used method for three-dimensional multi-chip stacking in related technologies is to use a multi-layer substrate with slots cut into it and then mount the chips at the bottom of the slots. However, if a large number of chips are to be embedded, numerous slots must be cut into the substrate, compromising the substrate's structural stability. Furthermore, multiple layers of substrate must be crimped together to accommodate vertical signal routing and chip embedding. This complicates the multi-layer substrate structure and significantly increases assembly difficulty. For the currently more commonly used multi-chip stack based on pure silicon, the greater the number of layers, the more pronounced the brittleness and poor insulation properties of the silicon material become, and the silicon material itself is more difficult to process. Subsequently, POP (Package on Package) packaging emerged, but when multiple packages are vertically stacked using solder balls, their structural stability deteriorates accordingly. Furthermore, multi-layer solder ball bonding complicates assembly, creating gaps between the solder balls and poor signal transmission between layers. Furthermore, to enhance the shielding of the package, most often metal walls and covers are used to enclose the entire board structure, increasing the assembly process.

[0103] Please refer to Figure 7 In this specific embodiment, metal dams are provided in both the upper and lower directions of multiple dielectric substrates 01 at non-edge positions, thereby ensuring the performance of multi-chip stacking while improving the integration of chip stacking and the shielding effect, and effectively improving the efficiency, maintainability, optionality, and reconfigurability of product assembly. Figure 7 In the figure, multiple columns of ellipsis represent the dielectric substrate 01 in the middle layer which is omitted. In addition, Figure 7In the figure, 01' represents the topmost dielectric substrate, 01'' represents the bottommost dielectric substrate, and 01''' represents the middle dielectric substrate.

[0104] Figure 8 Taken out separately Figure 7 A dielectric substrate 01''' in a middle layer can be obtained by using a dielectric substrate 01'' in a top layer, a dielectric substrate 01'' in a bottom layer and a plurality of dielectric substrates 01'' in a middle layer. Figure 7 The structure in .

[0105] The present invention also provides a chip isolation packaging structure, a structural diagram of a specific embodiment of which can be found in Figures 1 to 6 , referred to as specific implementation mode 4, including two first packaging units;

[0106] The first packaging unit includes a dielectric substrate 01 and a metal dam provided on a first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating;

[0107] The first surfaces of the two first packaging units are arranged opposite to each other, so that the metal dams of the two first surfaces are positioned correspondingly and connected to each other to form a chip isolation cavity;

[0108] The isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is disposed on the first surface;

[0109] The metal dam is a metal structure obtained by patterned electroplating.

[0110] Please refer to Figures 1 to 6 , Figures 1 to 6 The above chip isolation packaging structure is described. The chip isolation cavity in the above text is surrounded by two metal dams arranged opposite to each other. Figure 1 and Figure 2 02 and 03 are used to represent two metal dams.

[0111] For further explanation of the chip isolation packaging structure in this specific embodiment, please refer to the specific embodiment one and specific embodiment two in the previous text. This specific embodiment can be regarded as another way of expressing specific embodiment one and specific embodiment two, and will not be elaborated here.

[0112] The chip isolation packaging structure provided by the present invention includes two first packaging units; the first packaging unit includes a dielectric substrate 01 and a metal dam disposed on the first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating; the first surfaces of the two first packaging units are arranged relative to each other, so that the metal dams on the two first surfaces are positioned correspondingly and interconnected to form a chip isolation cavity; the isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is disposed on the first surface; the metal dam is a metal structure obtained by patterned electroplating. The present invention uses patterned electroplating to set metal dams in both upward and downward directions to form a chip packaging cavity. This not only has excellent shielding performance, but also serves as a support structure between the upper and lower layers, improving the overall structural stability of the package. At the same time, the patterned electroplating setting is highly flexible, the process is simple, and the finished product yield is high. Compared with existing related technologies, it occupies less space and can further improve space utilization.

[0113] The present invention also provides a chip isolation packaging method, a flow chart of a specific embodiment of the method is as follows: Figure 9 As shown, it is called the fifth specific implementation method, including:

[0114] S101: placing an isolation chip in a metal dam of a first packaging unit; the first packaging unit comprises a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating.

[0115] S102: Arrange the first surfaces of the two first packaging units opposite to each other, with the metal dams of the two first packaging units positioned correspondingly.

[0116] S103: welding the metal dams of the two first packaging units together so that the two opposing metal dams form a chip isolation cavity; the chip isolation cavity includes at least one isolation chip.

[0117] The chip isolation packaging method of the fifth embodiment provided by the present invention can be compared with the fourth embodiment mentioned above. It is essentially the method for manufacturing the chip isolation packaging structure described in the fourth embodiment, and will not be elaborated here.

[0118] The chip isolation packaging method provided by the present invention comprises: placing an isolation chip 04 within a metal dam of a first packaging unit; the first packaging unit comprises a dielectric substrate 01 and a metal dam disposed on a first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating; the first surfaces of two first packaging units are disposed opposite each other, with the metal dams of the two first packaging units positioned correspondingly; the metal dams of the two first packaging units are welded together, so that the two opposing metal dams form a chip isolation cavity; the chip isolation cavity includes at least one isolation chip 04. The chip isolation packaging method provided in this specific embodiment, after the two metal dams are disposed opposite each other, is directly fixed by welding, rapidly completing the packaging of the isolation chip 04, significantly improving packaging efficiency and reducing packaging difficulty.

[0119] The present invention also provides a chip isolation packaging structure, a structural diagram of a specific embodiment of which can be found in Figure 7 and Figure 8 , referred to as specific embodiment six, including a second packaging unit and two first packaging units;

[0120] The first packaging unit includes a dielectric substrate 01 and a metal dam provided on a first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating;

[0121] The second packaging unit includes a dielectric substrate 01 and metal dams disposed on a first surface and a second surface of the dielectric substrate 01;

[0122] The first surfaces of the two first packaging units are arranged opposite to each other, and the second packaging unit is arranged between the two first packaging units;

[0123] The metal dams on the surfaces of adjacent packaging units are arranged in a corresponding position and are interconnected to form a chip isolation cavity;

[0124] The isolation chip 04 is located in the chip isolation cavity, and the isolation chip 04 is arranged on the surface of the dielectric substrate 01;

[0125] The metal dam is a metal structure obtained by patterned electroplating.

[0126] Please refer to Figures 7 and 8 , Figures 7 and 8The above-mentioned chip isolation packaging structure is described. The chip isolation cavity is surrounded by two metal dams arranged opposite to each other. The two metal dams are represented by 02 and 03 in the figure. In this specific embodiment, it is assumed that the first packaging unit has a metal dam only on the first surface, and the second packaging unit has the metal dam on both the front and back surfaces, that is, on the first and second surfaces. Figure 8 This is a schematic structural diagram of a single second packaging unit.

[0127] For further description of the chip isolation packaging structure in this specific embodiment, please refer to the specific embodiment three in the previous text. This specific embodiment can be regarded as another way of expressing the specific embodiment three, and will not be elaborated here.

[0128] The chip isolation packaging structure provided by the present invention includes a second packaging unit and two first packaging units; the first packaging unit includes a dielectric substrate 01 and a metal dam disposed on the first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating; the second packaging unit includes a dielectric substrate 01 and metal dams disposed on the first and second surfaces of the dielectric substrate 01; the first surfaces of the two first packaging units are arranged opposite each other, and the second packaging unit is arranged between the two first packaging units; the metal dams on the oppositely disposed surfaces of adjacent packaging units are positioned correspondingly and interconnected to form a chip isolation cavity; the isolation chip 04 is located in the chip isolation cavity and is disposed on the surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating. The present invention uses patterned electroplating to set metal dams in both upward and downward directions to form a chip packaging cavity, which not only has excellent shielding performance but also serves as a support structure between upper and lower layers, improving the structural stability of the entire package. At the same time, the patterned electroplating configuration is highly flexible, the process is simple, and the finished product yield is high. Compared with existing related technologies, it occupies less space and can further improve space utilization.

[0129] The present invention also provides a chip isolation packaging method, a flow chart of a specific embodiment of the method is as follows: Figure 10 As shown, it is called the seventh specific implementation method, including:

[0130] S201: Disposing an isolation chip within a metal dam of a first packaging unit and / or a second packaging unit; the first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; the second packaging unit includes a dielectric substrate and metal dams disposed on the first and second surfaces of the dielectric substrate.

[0131] S202: stacking the second packaging unit and the two first packaging units, wherein the first surfaces of the two first packaging units are arranged opposite to each other, the second packaging unit is stacked between the two first packaging units, and the positions of the metal dams on the oppositely arranged surfaces of adjacent packaging units correspond to each other.

[0132] S203: welding corresponding metal dams on adjacent packaging units to form a chip isolation cavity with two opposing metal dams; the chip isolation cavity includes at least one isolation chip.

[0133] The chip isolation packaging method of the seventh embodiment provided by the present invention can be compared with the sixth embodiment mentioned above. It is essentially the method for manufacturing the chip isolation packaging structure described in the sixth embodiment, and will not be elaborated here.

[0134] The chip isolation packaging method provided by the present invention comprises placing an isolation chip 04 within the metal dams of a first packaging unit and / or a second packaging unit; the first packaging unit comprises a dielectric substrate 01 and a metal dam disposed on the first surface of the dielectric substrate 01; the metal dam is a metal structure obtained by patterned electroplating; the second packaging unit comprises a dielectric substrate 01 and metal dams disposed on the first and second surfaces of the dielectric substrate 01; the second packaging unit is stacked with two of the first packaging units, wherein the first surfaces of the two first packaging units are disposed opposite each other, the second packaging unit is stacked between the two first packaging units, and the metal dams on the opposite surfaces of adjacent packaging units correspond to each other; the corresponding metal dams on the adjacent packaging units are welded together, so that the two opposing metal dams form a chip isolation cavity; the chip isolation cavity contains at least one isolation chip 04. This specific embodiment inserts one or more second packaging units, each with metal dams on both surfaces, between the first packaging units to form a stacked packaging structure. After stacking multiple packaging structures, adjacent metal dams can be quickly welded, thereby ensuring packaging density while improving packaging efficiency.

[0135] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0136] It should be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0137] The above is a detailed introduction to the chip isolation packaging structure and method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications may be made to the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A chip isolation packaging structure, characterized in that: comprising two adjacently stacked dielectric substrates; The lower surface of the dielectric substrate located above includes a downward metal dam, and the upper surface of the dielectric substrate located below includes an upward metal dam; the upward metal dam corresponds to the downward metal dam in position and is connected to each other to form a chip isolation cavity; The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the lower surface where the downward metal dam is located and / or the upper surface where the upward metal dam is located; The upper metal dam and the lower metal dam are metal structures obtained by patterned electroplating; The lower surface of the dielectric substrate located above includes a downward airtight dam, and the upper surface of the dielectric substrate located below includes an upward airtight dam. The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber; The chip isolation cavity is arranged in the airtight isolation chamber; The lower surface of the dielectric substrate located above includes downward-pointing metal needles, and the upper surface of the dielectric substrate located below includes upward-pointing metal needles; The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other; The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle and the downward metal needle; The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating; The downward airtight dam, the downward metal needles and the downward metal dam are simultaneously provided by a single electroplating process; the upward metal dam, the upward metal needles and the upward metal dam are simultaneously provided by a single electroplating process.

2. The chip isolation packaging structure according to claim 1, wherein: The isolation chip is electrically connected to the external circuit via a signal line of a redistribution layer on the surface where the isolation chip is located; The metal dam corresponding to the surface where the isolation chip is located is used as an opening dam, and the opening dam is provided with an isolation electroplating growth area at a position corresponding to the signal line.

3. The chip isolation packaging structure according to claim 2, wherein: There is only one opening dam in a single chip isolation cavity; A ratio of a height of the opening dam to a total height of the corresponding chip isolation cavity is smaller than a preset first threshold.

4. The chip isolation packaging structure according to claim 1, wherein: A chip isolation cavity composed of a plurality of upward metal dams and downward metal dams is provided between two adjacent dielectric substrates.

5. The chip isolation packaging structure according to claim 1, wherein: A single airtight isolation chamber includes a plurality of chip isolation cavities.

6. The chip isolation packaging structure according to any one of claims 1 to 5, characterized in that: The chip isolation packaging structure includes N stacked dielectric substrates; N is not less than 3; The dielectric substrate at the top layer includes the downward metal dam, the dielectric substrate at the bottom layer includes the upward metal dam, and the dielectric substrate at the middle layer includes the upward metal dam and the downward metal dam. All the metal dams constitute the N-1 layer chip isolation cavity.

7. A chip isolation packaging structure, characterized in that: comprising two first packaging units; The first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; The first surfaces of the two first packaging units are arranged opposite to each other, so that the metal dams of the two first surfaces are positioned correspondingly and connected to each other to form a chip isolation cavity; The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the first surface; The metal dam is a metal structure obtained by patterned electroplating; The lower surface of the dielectric substrate located above includes a downward airtight dam, and the upper surface of the dielectric substrate located below includes an upward airtight dam. The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber; The chip isolation cavity is arranged in the airtight isolation chamber; The lower surface of the dielectric substrate located above includes downward-pointing metal needles, and the upper surface of the dielectric substrate located below includes upward-pointing metal needles; The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other; The redistribution layer on the lower surface is electrically connected to the redistribution layer on the upper surface via the upward metal needle and the downward metal needle; The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating; The downward airtight dam, the downward metal needles and the downward metal dam are simultaneously provided by a single electroplating process; the upward metal dam, the upward metal needles and the upward metal dam are simultaneously provided by a single electroplating process.

8. A chip isolation packaging method, characterized in that: include: The isolation chip is disposed in a metal dam of a first packaging unit; the first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; Arranging the first surfaces of the two first packaging units to face each other, with the metal dams of the two first packaging units positioned correspondingly; welding the metal dams of the two first packaging units together so that the two opposing metal dams form a chip isolation cavity; The chip isolation cavity includes at least one isolation chip; The lower surface of the dielectric substrate located above includes a downward airtight dam, and the upper surface of the dielectric substrate located below includes an upward airtight dam. The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber; The chip isolation cavity is arranged in the airtight isolation chamber; The lower surface of the dielectric substrate located above includes downward-pointing metal needles, and the upper surface of the dielectric substrate located below includes upward-pointing metal needles; The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other; The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle and the downward metal needle; The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating; The downward airtight dam, the downward metal needles and the downward metal dam are simultaneously provided by a single electroplating process; the upward metal dam, the upward metal needles and the upward metal dam are simultaneously provided by a single electroplating process.

9. A chip isolation packaging structure, characterized in that: comprising a second packaging unit and two first packaging units; The first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; The second packaging unit includes a dielectric substrate and metal dams disposed on a first surface and a second surface of the dielectric substrate; The first surfaces of the two first packaging units are arranged opposite to each other, and the second packaging unit is arranged between the two first packaging units; The metal dams on the surfaces of adjacent packaging units are arranged in a corresponding position and are interconnected to form a chip isolation cavity; The isolation chip is located in the chip isolation cavity, and the isolation chip is arranged on the surface of the dielectric substrate; The metal dam is a metal structure obtained by patterned electroplating; The lower surface of the dielectric substrate located above includes a downward airtight dam, and the upper surface of the dielectric substrate located below includes an upward airtight dam. The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber; The chip isolation cavity is arranged in the airtight isolation chamber; The lower surface of the dielectric substrate located above includes downward-pointing metal needles, and the upper surface of the dielectric substrate located below includes upward-pointing metal needles; The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other; The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle and the downward metal needle; The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating; The downward airtight dam, the downward metal needles and the downward metal dam are simultaneously provided by a single electroplating process; the upward metal dam, the upward metal needles and the upward metal dam are simultaneously provided by a single electroplating process.

10. A chip isolation packaging method, characterized in that: include: The isolation chip is disposed within the metal dam of the first packaging unit and / or the second packaging unit; the first packaging unit includes a dielectric substrate and a metal dam disposed on a first surface of the dielectric substrate; the metal dam is a metal structure obtained by patterned electroplating; the second packaging unit includes a dielectric substrate and metal dams disposed on the first and second surfaces of the dielectric substrate; The second packaging unit is stacked with two of the first packaging units, wherein the first surfaces of the two first packaging units are arranged opposite to each other, the second packaging unit is stacked between the two first packaging units, and the metal dams on the oppositely arranged surfaces of adjacent packaging units are positioned correspondingly; Welding the corresponding metal dams on adjacent packaging units together so that two opposing metal dams form a chip isolation cavity; The chip isolation cavity includes at least one isolation chip; The lower surface of the dielectric substrate located above includes a downward airtight dam, and the upper surface of the dielectric substrate located below includes an upward airtight dam. The upward airtight dam and the downward airtight dam are located in corresponding positions and are connected to each other to form an airtight isolation chamber; The chip isolation cavity is arranged in the airtight isolation chamber; The lower surface of the dielectric substrate located above includes downward-pointing metal needles, and the upper surface of the dielectric substrate located below includes upward-pointing metal needles; The downward metal needle and the upward metal needle are positioned correspondingly and connected to each other; The redistribution layer on the lower surface is electrically connected to the flush wiring layer on the upper surface via the upward metal needle and the downward metal needle; The upward metal needle and the downward metal needle are metal structures obtained by pattern electroplating; The downward airtight dam, the downward metal needles and the downward metal dam are simultaneously provided by a single electroplating process; the upward metal dam, the upward metal needles and the upward metal dam are simultaneously provided by a single electroplating process.

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