A data processing method and a data processing device

Abstract

The embodiment of the present application discloses a data processing method and a data processing device. The method is specifically as follows: inner code encoding is performed on n first data streams respectively to obtain n second data streams. The n second data streams include n inner code codewords respectively from the n second data streams, the n inner code codewords include n / m codeword sets, each codeword set includes m inner codewords, and each inner codeword includes N bits. Bit interleaving is performed on the n / m codeword sets to obtain n / m target bit sets. The m×N bits in each target bit set are mapped to obtain m×N / L modulation symbols respectively, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, and the L bits of the modulation symbol come from L inner codewords respectively. If the L bits of the modulation symbol all come from the information bits of the inner code codeword, then any two bits in the modulation symbol come from two different positions of two different inner codewords.

Description

[0001] This application claims the priority of the Chinese patent application filed with the China Patent Office on June 24, 2022, with application number 202210727137.1 and invention name “A data processing method and data processing device”, and the Chinese patent application filed with the China Patent Office on July 22, 2022, with application number 202210867882.6 and invention name “A data processing method and data processing device”, and the priority of the Chinese patent application filed with the China Patent Office on April 4, 2023, with application number 202310382561.1 and invention name “A data processing method and data processing device”, all of which are incorporated into this application by application. Technical Field

[0002] The present application relates to the field of communications, and in particular to a data processing method and a data processing device. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing in the direction of large capacity, packetization, and intelligence. Using forward error correction (FEC) coding to correct the transmitted data can solve transmission errors and recover the original data sent by the sender from the received data.

[0004] Currently, a cascade FEC transmission scheme is proposed, in which the transmitting device and the transmitting processing module are connected through an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted, and sends the data after the first FEC encoding to the transmitting processing module. The transmitting processing module performs a second FEC encoding on the data after the first FEC encoding, and modulates and maps the bit sequence after the second FEC encoding to generate a corresponding modulation symbol sequence, and finally transmits the generated symbol sequence to the receiving end through the optical transmission network. After the receiving end demodulates and decodes the received modulation symbol sequence, it can obtain the information sent by the transmitting end.

[0005] Usually, cascade coding interleaving is added before the second FEC coding to shuffle the order of the data after the first FEC coding to enhance the error correction performance of the overall FEC scheme. In addition, during the actual transmission of the modulation symbol sequence, the transmission link is affected by burst factors, which will cause errors in several consecutive symbols in the modulation symbol sequence, and the receiving end receives the modulation symbol sequence affected by the burst factors. Due to the large number of consecutive errors, it is difficult to accurately correct errors through the FEC code, resulting in a high bit error rate for information transmission. Summary of the invention

[0006] The embodiment of the present application provides a data processing method and a data processing device, so that the cascade FEC transmission scheme has a strong anti-burst capability and can be applied to more transmission scenarios, especially to actual coherent transmission scenarios where the channel has colored noise.

[0007] In a first aspect, the present application provides a data processing method. The method comprises the following steps. First, inner code encoding is performed on n first data streams respectively to obtain n second data streams. Among them, the n first data streams are all outer code encoded, and both the inner code encoding and the outer code encoding are FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. Afterwards, bit interleaving is performed on the n / m codeword sets to obtain n / m target bit sets. Among them, each target bit set includes m×N bits. Furthermore, the m×N bits in each target bit set are mapped to obtain m×N / L modulation symbols to obtain a total of n×N / L modulation symbols. Wherein, each L bits are mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L inner code words respectively. If the L bits mapped to a modulation symbol all come from information bits of an inner code word, then any two bits of the L bits mapped to a modulation symbol come from two different positions of two different inner code words.

[0008] In this implementation, a cascade FEC transmission scheme is adopted, that is, the data stream is successively coded by the outer code and coded by the inner code. On this basis, the present application designs a method of bit interleaving and mapping, so that the bits in the outer code word and the bits in the inner code word are discretely and evenly mapped to the modulation symbol, so that the cascade FEC transmission scheme has a strong burst resistance capability, especially for burst errors with a short length, which can be directly corrected by the inner code decoding, and can be applied to more transmission scenarios, especially for actual coherent transmission scenarios where the channel has colored noise.

[0009] In some possible implementations, N is divisible by L, the N bits of each inner codeword are respectively mapped to N modulation symbols, the N bits of the inner codeword include L first bit subsets, the bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and the bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols. For example, a modulation symbol includes bit position b0, bit position b1, ..., bit position b L-1 , the N bits of the inner code word are mapped to bit b0, bit b1, ..., bit b L-1The number of bits is N / L. It should be understood that the probability of errors in the above L bits during transmission is not necessarily equal, and mapping the bits of an inner code word more evenly to the modulation symbols can improve the burst resistance of the cascade FEC scheme in actual transmission.

[0010] In some possible implementations, bit interleaving a codeword set to obtain a target bit set includes: performing a first position transformation on the K information bits of each inner codeword in the codeword set to obtain a first bit set. Performing a second position transformation on the bits at the same position in the first bit set to obtain a target bit set. Taking the codeword set as a bit matrix as an example, the first position transformation can be understood as a position transformation of the bits located in each row, and the second position transformation can be understood as a position transformation of the bits located in each column. This implementation provides a specific implementation method for bit interleaving, so that the present scheme has a strong anti-burst capability.

[0011] In some possible implementations, performing a first position transformation on the K information bits of each inner codeword in the codeword set includes: performing a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set. This implementation provides a specific implementation method for the first position transformation, which has a good practical effect.

[0012] In some possible implementations, the codeword set and the first bit set are both represented as bit matrices, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits. The bits at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

[0013] In some possible implementations, the first position change satisfies a first condition, and the first condition includes:

[0014]

[0015] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≤i<m.

[0016] In some possible implementations, each identical position in the first bit set includes m / L second bit subsets, and each second bit subset includes L bits. Performing a second position transformation on the bits at the identical position in the first bit set includes: performing an upward cyclic shift or a downward cyclic shift on each identical position of the m / L second bit subsets in the first bit set. This implementation provides a specific implementation method for the second position transformation, which has a good practical effect.

[0017] In some possible implementations, the second position change satisfies a second condition, and the second condition includes:

[0018]

[0019] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents rounding down, Y%Z represents the remainder after the integer Y is divided by the integer Z, θ is a non-zero integer greater than -L and less than L, 0≤i<m, 0≤j<N.

[0020] In some possible implementations, the second position change satisfies a third condition, and the third condition includes:

[0021]

[0022] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. It means rounding down, Y%Z means the remainder after dividing the integer Y by the integer Z, Y^Z means the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0023] In some possible implementations, the second position change satisfies a fourth condition, and the fourth condition includes:

[0024] H3[i][j]=H2[i^(j%L)][j]

[0025] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0026] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0027] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the fifth condition, which includes:

[0028]

[0029] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, It means rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0030] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the sixth condition, which includes:

[0031]

[0032] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0≤t<m×N, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, It means rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0033] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, which includes:

[0034]

[0035] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, and 0≤i<m.

[0036] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, which includes:

[0037]

[0038] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0≤t<m×N, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m.

[0039] In some possible implementations, mapping the m×N bits in each target bit set to obtain m×N / L modulation symbols includes: mapping every L consecutive bits located at the same position in each target bit set to a modulation symbol to obtain m×N / L modulation symbols.

[0040] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and the m / L modulation symbols obtained by mapping the m bits at the same position in each target bit set are continuous in the modulation symbol stream. Wherein, when the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are a column of m bits in the bit matrix; when the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are continuous m bits in the one-dimensional array.

[0041] In some possible embodiments, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, each target bit set is represented as a bit matrix including m rows and N columns of bits, the m bits located in one column of each target bit set are mapped to obtain m / L first modulation symbols, each consecutive T first modulation symbols among the m / L first modulation symbols are continuous in the modulation symbol stream, the m bits located in another column of each target bit set are mapped to obtain m / L second modulation symbols, each consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, one column is adjacent to another column, consecutive T first modulation symbols among the m / L first modulation symbols and consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, and m / L is divisible by T.

[0042] In some possible implementations, the n first data streams are all processed by identification locking and channel de-skew, and when W×L bits in W consecutive modulation symbols are all information bits of an inner code word, the W×L bits come from more than 2 outer code code words encoded by an outer code, where W≥2.

[0043] In some possible implementations, each modulation symbol is a dual polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes 2 bits.

[0044] In a second aspect, the present application provides a data processing method. The method comprises the following steps. First, inner code encoding is performed on n first data streams respectively to obtain n second data streams. Among them, the n first data streams are all outer code encoded, and both the inner code encoding and the outer code encoding are FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. Afterwards, bit interleaving is performed on the n / m codeword sets to obtain n / m target bit sets. Among them, each target bit set includes m×N bits, and bit interleaving includes position transformation of the K information bits of each inner codeword in the codeword set. Then, the m×N bits in each target bit set are mapped to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, and m is divisible by L. The L bits mapped to a modulation symbol come from L r Inner code words, L r Each of the inner code words has L c bits are mapped to modulation symbols. The 2L bits mapped to 2 consecutive modulation symbols come from 2L r Inner code words, L = L r ×L c ,L c >1.

[0045] In some possible implementations, performing position transformation on the K information bits of each inner codeword in the codeword set includes: performing a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0046] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0047] In some possible implementations, the position change satisfies a target condition, and the target condition includes:

[0048]

[0049] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position change, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position change, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≤i<m.

[0050] In some possible implementations, each target bit set includes m rows and N columns of bits, and each L bit in the target bit set r Line L c A total of L bits in a column are mapped to one modulation symbol.

[0051] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

[0052] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping. c The bit mapping of the columns yields m / L r The first modulation symbol, m / L r Each of the T consecutive first modulation symbols in the first modulation symbols is continuous in the modulation symbol stream. c The bit mapping of the columns yields m / L r The second modulation symbol, m / L r Every consecutive T second modulation symbols in the modulation symbol stream are consecutive. c Column and other L c Adjacent rows, m / L r The first modulation symbols of the continuous T first modulation symbols are m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0053] In some possible implementations, each modulation symbol is a dual polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes 2 bits.

[0054] In a third aspect, the present application provides a data processing device. The data processing device includes: a coding module, a bit interleaving module and a bit mapping module. The coding module is used to: perform inner code encoding on n first data streams respectively to obtain n second data streams. Among them, the n first data streams are all encoded with outer codes, and both the inner code encoding and the outer code encoding are forward error correction FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. The bit interleaving module is used to: bit interleave n / m codeword sets respectively to obtain n / m target bit sets, each target bit set includes m×N bits; the bit mapping module is used to: map the m×N bits in each target bit set respectively to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L inner code words respectively. If the L bits mapped to a modulation symbol all come from the information bits of the inner code word, then any two bits of the L bits mapped to a modulation symbol come from two different positions of two different inner code words.

[0055] In some possible implementations, N is divisible by L, the N bits of each inner code word are respectively mapped to N modulation symbols, the N bits of the inner code word include L first bit subsets, the bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and the bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols.

[0056] In some possible implementations, the bit mapping module is specifically configured to: perform a first position transformation on the K information bits of each inner codeword in the codeword set to obtain a first bit set, and perform a second position transformation on the bits at the same position in the first bit set to obtain a target bit set.

[0057] In some possible implementations, the bit mapping module is specifically configured to: perform a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0058] In some possible implementations, the codeword set and the first bit set are both represented as bit matrices, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits. The bits at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

[0059] In some possible implementations, the first position change satisfies a first condition, and the first condition includes:

[0060]

[0061] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≤i<m.

[0062] In some possible implementations, each identical position in the first bit set includes m / L second bit subsets, and each second bit subset includes L bits. The bit mapping module is specifically configured to perform upward cyclic shift or downward cyclic shift on each identical position of the m / L second bit subsets in the first bit set.

[0063] In some possible implementations, the second position change satisfies a second condition, and the second condition includes:

[0064]

[0065] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents rounding down, Y%Z represents the remainder after the integer Y is divided by the integer Z, θ is a non-zero integer greater than -L and less than L, 0≤i<m, 0≤j<N.

[0066] In some possible implementations, the second position change satisfies a third condition, and the third condition includes:

[0067]

[0068] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. It means rounding down, Y%Z means the remainder after dividing the integer Y by the integer Z, Y^Z means the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0069] In some possible implementations, the second position change satisfies a fourth condition, and the fourth condition includes:

[0070] H3[i][j]=H2[i^(j%L)][j]

[0071] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0072] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0073] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the fifth condition, which includes:

[0074]

[0075] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, It means rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0076] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the sixth condition, which includes:

[0077]

[0078] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0≤t<m×N, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, It means rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0079] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, which includes:

[0080]

[0081] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, and 0≤i<m.

[0082] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, which includes:

[0083]

[0084] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0≤t<m×N, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m.

[0085] In some possible implementations, the bit mapping module is specifically configured to: map every L consecutive bits located at the same position in each target bit set to a modulation symbol to obtain m×N / L modulation symbols.

[0086] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and the m / L modulation symbols obtained by mapping the m bits at the same position in each target bit set are continuous in the modulation symbol stream. Wherein, when the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are a column of m bits in the bit matrix. When the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are continuous m bits in the one-dimensional array.

[0087] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each target bit set is represented as a bit matrix including m rows and N columns of bits. The m bits located in one column of each target bit set are mapped to obtain m / L first modulation symbols, and each consecutive T first modulation symbols of the m / L first modulation symbols are continuous in the modulation symbol stream. The m bits located in another column of each target bit set are mapped to obtain m / L second modulation symbols, and each consecutive T second modulation symbols of the m / L second modulation symbols are continuous in the modulation symbol stream. One of the columns is adjacent to another of the columns, and consecutive T first modulation symbols of the m / L first modulation symbols and consecutive T second modulation symbols of the m / L second modulation symbols are continuous in the modulation symbol stream, and m / L is divisible by T.

[0088] In some possible implementations, the n first data streams are all processed by identification locking and channel de-skew, and when W×L bits in W consecutive modulation symbols are all information bits of an inner code word, the W×L bits come from more than 2 outer code code words encoded by an outer code, where W≥2.

[0089] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, and each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes 2 bits.

[0090] In a fourth aspect, the present application provides a data processing device. The data processing device includes: a coding module, a bit interleaving module and a bit mapping module. The coding module is used to: perform inner code encoding on n first data streams respectively to obtain n second data streams. Among them, the n first data streams are all encoded by outer code, and the inner code encoding and the outer code encoding are both forward error correction FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. The bit interleaving module is used to: perform bit interleaving on the n / m codeword sets respectively to obtain n / m target bit sets. Each target bit set includes m×N bits, and the bit interleaving includes position transformation of the K information bits of each inner codeword in the codeword set. The bit mapping module is used to map the m×N bits in each target bit set to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L r Inner code words, L r Each of the inner code words has Lc bits are mapped to modulation symbols, and the 2L bits mapped to 2 consecutive modulation symbols come from 2L r Inner code words, L = L r ×L c ,L c >1.

[0091] In some possible implementations, the bit interleaving module is specifically configured to: perform a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0092] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0093] In some possible implementations, the position change satisfies a target condition, and the target condition includes:

[0094]

[0095] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position change, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position change, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≤i<m.

[0096] In some possible implementations, each target bit set includes m rows and N columns of bits, and each L bit in the target bit set r Line L c A total of L bits in a column are mapped to one modulation symbol.

[0097] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

[0098] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping. c The bit mapping of the columns yields m / L r The first modulation symbol, m / L r Each of the T first modulation symbols in the target bit set is located in the other L c The bit mapping of the columns yields m / Lr The second modulation symbol, m / L r Every consecutive T second modulation symbols in the modulation symbol stream are consecutive. c Column and other L c Adjacent rows, m / L r The first modulation symbols of the continuous T first modulation symbols are m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0099] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, and each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes 2 bits.

[0100] In a fifth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain one second data stream, so as to obtain a total of n2 second data streams. n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to one PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. Perform inner code encoding on the m first bit sets respectively to obtain m inner code code words, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, each inner code code word includes 1 first bit set and 1 check bit set participating in the inner code encoding, totaling N bits, N=K+P, each check bit set includes P bits, and P is an integer greater than or equal to 1. Perform cyclic shift on the m inner code code words respectively to obtain m third bit sets, each third bit set includes 1 second bit set obtained by cyclic shifting the first bit set and 1 check bit set. Polling obtains 2 bits from each third bit set to obtain a fourth bit set, the fourth bit set includes m×N bits, a total of m×K bits from the m second bit sets in the fourth bit set are continuous, and a total of m×P bits from the m check bit sets in the fourth bit set are continuous. It should be understood that each second data stream includes multiple fourth bit sets, and each fourth bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0101] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0102] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0103] In some possible implementations, the m inner code words and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

[0104] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0105]

[0106] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before cyclic shift to the left, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m,

[0107] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0108]

[0109] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤δ i <K.

[0110] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, where the third condition includes:

[0111]

[0112] Wherein, M3[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0113] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0114] {0,30,60,90,110,20,50,80};

[0115] {0,30,90,60,110,20,80,50};

[0116] {0,60,30,90,110,50,20,80};

[0117] {0,60,90,30,110,50,80,20};

[0118] {0,90,30,60,110,80,20,50};

[0119] {0,90,60,30,110,80,50,20}.

[0120] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0121] [0,30,60,90,10,40,70,100};

[0122] [0,30,90,60,10,40,100,70};

[0123] {0,60,30,90,10,40,40,100};

[0124] {0,60,90,30,10,70,100,40};

[0125] {0,90,30,60,10,100,40,70};

[0126] {0,90,60,30,10,100,70,40}.

[0127] In a sixth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain one second data stream, so as to obtain a total of n2 second data streams. n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to one PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. Cyclic shift is performed on the m first bit sets to obtain m second bit sets, and inner code coding is performed on the m first bit sets to obtain m check bit sets, both the inner code coding and the outer code coding are forward error correction FEC coding, each second bit set includes K bits, each check bit set includes P bits, and P is an integer greater than or equal to 1. Polling is performed to obtain 2 bits from each second bit set to obtain a total of m×K continuous bits, and polling is performed to obtain 2 bits from each check bit set to obtain a total of m×P continuous bits, so as to obtain a third bit set including m×N bits, N=K+P. It should be understood that each second data stream includes multiple third bit sets, each third bit set contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each third bit set are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each third bit set are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from m second bit sets and / or m check bit sets.

[0128] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0129] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0130] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0131] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0132]

[0133] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j<K, 0≤i<m,

[0134] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0135] M2[i][j]=M1[i][(j-δ i )% K]

[0136] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j<K, 0≤i<m, 0≤δ i <K.

[0137] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0138] {0,30,60,90,110,20,50,80};

[0139] {0,30,90,60,110,20,80,50};

[0140] {0,60,30,90,110,50,20,80};

[0141] {0,60,90,30,110,50,80,20};

[0142] {0,90,30,60,110,80,20,50};

[0143] {0,90,60,30,110,80,50,20}.

[0144] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0145] {0,30,60,90,10,40,70,100};

[0146] {0,30,90,60,10,40,100,70};

[0147] {0,60,30,90,10,40,40,100};

[0148] {0,60,90,30,10,70,100,40};

[0149] {0,90,30,60,10,100,40,70};

[0150] {0,90,60,30,10,100,70,40}.

[0151] In a seventh aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and coding each n1 first data streams in the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams. n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving coding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. Cyclic shifting is performed on the m first bit sets to obtain m second bit sets, each second bit set includes K bits. The m second bit sets are respectively inner-coded to obtain m inner-code codewords, and both the inner-code coding and the outer-code coding are forward error correction FEC coding, and each inner-code codeword includes 1 second bit set and 1 check bit set participating in the inner-code coding, totaling N bits, N=K+P, and each check bit set includes P bits, and P is an integer greater than or equal to 1. Polling obtains 2 bits from each inner-code codeword to obtain a third bit set, and the third bit set includes m×N bits, and a total of m×K bits from the m second bit sets in the third bit set are continuous, and a total of m×P bits from the m check bit sets in the third bit set are continuous. It should be understood that each second data stream includes multiple third bit sets, and each third bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to the continuous m PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner-code codewords.

[0152] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0153] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0154] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0155] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0156]

[0157] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K,

[0158] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0159] M2[i][j]=M1[i][(j-δ i )% K]

[0160] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K, 0≤δ i <K.

[0161] In some possible implementations, the m inner code words are represented as a bit matrix including m rows and N columns, and the m inner code words and the third bit set satisfy a third condition, and the third condition includes:

[0162]

[0163] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words. Indicates the third bit set bits, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0164] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0165] {0,30,60,90,110,20,50,80};

[0166] {0,30,90,60,110,20,80,50};

[0167] {0,60,30,90,110,50,20,80};

[0168] {0,60,90,30,110,50,80,20};

[0169] {0,90,30,60,110,80,20,50};

[0170] {0,90,60,30,110,80,50,20}.

[0171] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0172] {0,30,60,90,10,40,70,100};

[0173] {0,30,90,60,10,40,100,70};

[0174] {0,60,30,90,10,40,40,100};

[0175] {0,60,90,30,10,70,100,40};

[0176] {0,90,30,60,10,100,40,70};

[0177] {0,90,60,30,10,100,70,40}.

[0178] In an eighth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain one second data stream, so as to obtain a total of n2 second data streams. n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to one PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. The m first bit sets are respectively inner-coded to obtain m inner-code codewords. Both the inner-code coding and the outer-code coding are forward error correction FEC coding. Each inner-code codeword includes a first bit set and a check bit set participating in the inner-code coding, totaling N bits, N=K+P, each check bit set includes P bits, and P is an integer greater than or equal to 1. The m inner-code codewords are respectively interleaved to obtain a second bit set, the second bit set includes m×N bits, and the first bit set in the second bit set is bits satisfy the first condition or the second condition, 0≤i<m, 0≤j<N.

[0179] The first condition includes:

[0180]

[0181] in, Indicates the first bit in the second bit set bits, represents the first codeword in the i-th inner code bits, C i [j] represents the jth bit in the i-th inner code word.

[0182] The second condition includes:

[0183]

[0184] in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ i )% K bits, C i [j] represents the jth bit in the i-th inner code word.

[0185] It should be understood that each second data stream includes multiple second bit sets, and each second bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0186] In some possible implementations, K=120, m=8, The value of satisfies the first value item Any item in include:

[0187] {0,30,60,90,110,20,50,80};

[0188] {0,30,90,60,110,20,80,50};

[0189] {0,60,30,90,110,50,20,80};

[0190] {0,60,90,30,110,50,80,20};

[0191] {0,90,30,60,110,80,20,50};

[0192] {0,90,60,30,110,80,50,20};

[0193] δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0194] {0,30,60,90,10,40,70,100};

[0195] {0,30,90,60,10,40,100,70};

[0196] {0,60,30,90,10,40,40,100};

[0197] {0,60,90,30,10,70,100,40};

[0198] {0,90,30,60,10,100,40,70};

[0199] {0,90,60,30,10,100,70,40}.

[0200] In a ninth aspect, the present application provides a data processing device, which includes: an interleaving coding module and a bit mapping module. The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams in the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is used to: map each 2 bits in the n2 second data streams to 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically used to: obtain a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. Perform inner code encoding on the m first bit sets respectively to obtain m inner code code words, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, each inner code code word includes 1 first bit set and 1 check bit set participating in the inner code encoding, totaling N bits, N=K+P, each check bit set includes P bits, and P is an integer greater than or equal to 1. Perform cyclic shift on the m inner code code words respectively to obtain m third bit sets, each third bit set includes 1 second bit set obtained by cyclic shifting the first bit set and 1 check bit set. Polling obtains 2 bits from each third bit set to obtain a fourth bit set, the fourth bit set includes m×N bits, a total of m×K bits from the m second bit sets in the fourth bit set are continuous, and a total of m×P bits from the m check bit sets in the fourth bit set are continuous. It should be understood that each second data stream includes multiple fourth bit sets, and each fourth bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0201] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0202] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0203] In some possible implementations, the m inner code words and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

[0204] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0205]

[0206] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before cyclic shift to the left, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m,

[0207] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0208]

[0209] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤δ i <K.

[0210] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, where the third condition includes:

[0211]

[0212] Wherein, M3[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0213] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0214] [0,30,60,90,110,20,50,80};

[0215] [0,30,90,60,110,20,80,50};

[0216] {0,60,30,90,110,50,20,80};

[0217] {0,60,90,30,110,50,80,20};

[0218] {0,90,30,60,110,80,20,50};

[0219] {0,90,60,30,110,80,50,20}.

[0220] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0221] {0,30,60,90,10,40,70,100};

[0222] {0,30,90,60,10,40,100,70};

[0223] {0,60,30,90,10,40,40,100};

[0224] {0,60,90,30,10,70,100,40};

[0225] {0,90,30,60,10,100,40,70};

[0226] {0,90,60,30,10,100,70,40}.

[0227] In a tenth aspect, the present application provides a data processing device, which includes: an interleaving coding module and a bit mapping module. The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams in the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is used to: map each 2 bits in the n2 second data streams to 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically used to: obtain a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. Cyclic shift is performed on the m first bit sets to obtain m second bit sets, and inner code coding is performed on the m first bit sets to obtain m check bit sets, both the inner code coding and the outer code coding are forward error correction FEC coding, each second bit set includes K bits, each check bit set includes P bits, and P is an integer greater than or equal to 1. Polling is performed to obtain 2 bits from each second bit set to obtain a total of m×K continuous bits, and polling is performed to obtain 2 bits from each check bit set to obtain a total of m×P continuous bits, so as to obtain a third bit set including m×N bits, N=K+P. It should be understood that each second data stream includes multiple third bit sets, each third bit set contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each third bit set are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each third bit set are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from m second bit sets and / or m check bit sets.

[0228] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0229] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0230] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0231] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0232]

[0233] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j<K, 0≤i<m,

[0234] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0235] M2[i][j]=M1[i][(j-δ i )% K]

[0236] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j<K, 0≤i<m, 0≤δ i <K.

[0237] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0238] {0,30,60,90,110,20,50,80};

[0239] {0,30,90,60,110,20,80,50};

[0240] {0,60,30,90,110,50,20,80};

[0241] {0,60,90,30,110,50,80,20};

[0242] {0,90,30,60,110,80,20,50};

[0243] {0,90,60,30,110,80,50,20}.

[0244] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0245] {0,30,60,90,10,40,70,100};

[0246] {0,30,90,60,10,40,100,70};

[0247] {0,60,30,90,10,40,40,100};

[0248] {0,60,90,30,10,70,100,40};

[0249] {0,90,30,60,10,100,40,70};

[0250] {0,90,60,30,10,100,70,40}.

[0251] In the eleventh aspect, the present application provides a data processing device, which includes: an interleaving coding module and a bit mapping module. The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams in the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is used to: map each 2 bits in the n2 second data streams to a PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically used to: obtain a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. The m first bit sets are respectively cyclically shifted to obtain m second bit sets, each second bit set includes K bits. The m second bit sets are respectively inner-coded to obtain m inner-code codewords, and both the inner-code coding and the outer-code coding are forward error correction FEC coding, and each inner-code codeword includes 1 second bit set and 1 check bit set participating in the inner-code coding, totaling N bits, N=K+P, and each check bit set includes P bits, and P is an integer greater than or equal to 1. Polling obtains 2 bits from each inner-code codeword to obtain a third bit set, and the third bit set includes m×N bits, and a total of m×K bits from the m second bit sets in the third bit set are continuous, and a total of m×P bits from the m check bit sets in the third bit set are continuous. It should be understood that each second data stream includes multiple third bit sets, and each third bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to the continuous m PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner-code codewords.

[0252] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0253] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0254] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0255] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0256]

[0257] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K,

[0258] In some possible implementations, the second bit set is cyclically shifted rightward by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0259] M2[i][j]=M1[i][(j-δ i )% K]

[0260] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K, 0≤δ i <K.

[0261] In some possible implementations, the m inner code words are represented as a bit matrix including m rows and N columns, and the m inner code words and the third bit set satisfy a third condition, and the third condition includes:

[0262]

[0263] Among them, M ＜ [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words. Indicates the third bit set bits, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0264] In some possible implementations, K=120, m=8, the i-th second bit set is cyclically shifted to the left from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in include:

[0265] {0,30,60,90,110,20,50,80};

[0266] {0,30,90,60,110,20,80,50};

[0267] {0,60,30,90,110,50,20,80};

[0268] {0,60,90,30,110,50,80,20};

[0269] {0,90,30,60,110,80,20,50};

[0270] {0,90,60,30,110,80,50,20}.

[0271] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted rightward by δ from the i-th first bit set. i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0272] {0,30,60,90,10,40,70,100};

[0273] {0,30,90,60,10,40,100,70};

[0274] {0,60,30,90,10,40,40,100};

[0275] {0,60,90,30,10,70,100,40};

[0276] {0,90,30,60,10,100,40,70};

[0277] {0,90,60,30,10,100,70,40}.

[0278] In a twelfth aspect, the present application provides a data processing device, which includes: an interleaving coding module and a bit mapping module. The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams in the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is used to: map each 2 bits in the n2 second data streams to 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically used to: obtain a0 first bit sets from each first data stream of the n1 first data streams, so as to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each first bit set includes K bits, and n1, a0 and K are all integers greater than 1. The m first bit sets are respectively inner-coded to obtain m inner-code codewords. Both the inner-code coding and the outer-code coding are forward error correction FEC coding. Each inner-code codeword includes a first bit set and a check bit set participating in the inner-code coding, totaling N bits, N=K+P, each check bit set includes P bits, and P is an integer greater than or equal to 1. The m inner-code codewords are respectively interleaved to obtain a second bit set, the second bit set includes m×N bits, and the first bit set in the second bit set is bits satisfy the first condition or the second condition, 0≤i<m, 0≤j<N.

[0279] The first condition includes:

[0280]

[0281] in, Indicates the first bit in the second bit set bits, represents the first codeword in the i-th inner code bits, C i [j] represents the jth bit in the i-th inner code word.

[0282] The second condition includes:

[0283]

[0284] in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ i )% K bits, C i [j] represents the jth bit in the i-th inner code word.

[0285] It should be understood that each second data stream includes multiple second bit sets, and each second bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0286] In some possible implementations, K=120, m=8, The value of satisfies the first value item Any item in include:

[0287] {0,30,60,90,110,20,50,80};

[0288] {0,30,90,60,110,20,80,50];

[0289] [0,60,30,90,110,50,20,80};

[0290] {0,60,90,30,110,50,80,20};

[0291] {0,90,30,60,110,80,20,50};

[0292] {0,90,60,30,110,80,50,20};

[0293] δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0294] {0,30,60,90,10,40,70,100};

[0295] {0,30,90,60,10,40,100,70};

[0296] {0,60,30,90,10,40,40,100};

[0297] {0,60,90,30,10,70,100,40};

[0298] {0,90,30,60,10,100,40,70};

[0299] {0,90,60,30,10,100,70,40].

[0300] In the embodiment of the present application, a cascade FEC transmission scheme is adopted, that is, the data stream is successively coded by the outer code and the inner code. On this basis, the present application designs a method of bit interleaving and mapping, so that the bits in the outer code word and the bits in the inner code word are discretely and evenly mapped to the modulation symbol, so that the cascade FEC transmission scheme has a strong burst resistance capability, especially for burst errors with a short length, which can be directly corrected by inner code decoding, and can be applied to more transmission scenarios, especially for actual coherent transmission scenarios where the channel has colored noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0301] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0302] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown;

[0303] Figure 3 A flowchart of a data processing method provided in an embodiment of the present application;

[0304] Figure 4 A schematic diagram of cyclically shifting the bits of each row to the left in an embodiment of the present application;

[0305] Figure 5 A schematic diagram of performing upward cyclic shifting on the bits in each column in an embodiment of the present application;

[0306] Figure 6 A schematic diagram of position transformation of bits in each column in an embodiment of the present application;

[0307] Figure 7 This is a first schematic diagram of mapping bits in an embodiment of the present application;

[0308] Figure 8 This is a second schematic diagram of mapping bits in an embodiment of the present application;

[0309] Fig. 9 This is a third schematic diagram of mapping bits in an embodiment of the present application;

[0310] Fig.10 This is a fourth schematic diagram of mapping bits in an embodiment of the present application;

[0311] Fig.11 A schematic diagram of performing inner code encoding and interleaving modulation mapping on a data stream in an embodiment of the present application;

[0312] FIG. 12( a ) is a schematic diagram of a first operation flow of a transmission end processing module in an embodiment of the present application;

[0313] FIG12( b ) is a schematic diagram of a second operation flow of the transmitting end processing module in an embodiment of the present application;

[0314] FIG. 12( c ) is a schematic diagram of a third operation flow of the transmitting end processing module in an embodiment of the present application;

[0315] FIG12( d ) is a schematic diagram of a fourth operation flow of the transmitting end processing module in an embodiment of the present application;

[0316] Fig.13 This is a schematic diagram of a 1×800G interface scenario in an embodiment of the present application;

[0317] Fig.14 This is a schematic diagram of a 2×400G interface scenario in an embodiment of the present application;

[0318] Fig.15 This is another schematic diagram of a 1×800G interface scenario in an embodiment of the present application;

[0319] Fig.16 This is a first schematic diagram of cascade interleaving in an embodiment of the present application;

[0320] Fig.17 This is a schematic diagram of the first structure of the convolution interleaver in the embodiment of the present application;

[0321] Fig.18 This is a second schematic diagram of cascade interleaving in an embodiment of the present application;

[0322] Fig.19 This is a schematic diagram of the second structure of the convolution interleaver in the embodiment of the present application;

[0323] Fig. 20 This is a third schematic diagram of cascade interleaving in the embodiment of the present application;

[0324] Fig.21 This is a schematic diagram of the third structure of the convolution interleaver in the embodiment of the present application;

[0325] Fig. 22 This is a schematic diagram of the fourth structure of the convolution interleaver in the embodiment of the present application;

[0326] Fig.23 This is a fifth structural schematic diagram of a convolution interleaver in an embodiment of the present application;

[0327] Fig.24 This is a schematic diagram of a data processing flow in an embodiment of the present application;

[0328] Fig.25 A schematic diagram of the structure of a data processing device in an embodiment of the present application;

[0329] Fig.26Another flowchart of the data processing method provided in the embodiment of the present application;

[0330] Fig. 27 A schematic diagram of a first implementation method of interleaving coding processing;

[0331] Fig.28 A schematic diagram of a second implementation of interleaving coding processing;

[0332] Fig.29 A schematic diagram of a third implementation of interleaving coding processing;

[0333] Fig.30 A schematic diagram of a fourth implementation of interleaving coding processing;

[0334] Fig.31 A fifth embodiment of the interleaved coding process is shown;

[0335] Fig.32 A sixth embodiment of interleaving coding processing is shown;

[0336] Fig.33 A seventh embodiment of the interleaved coding process is shown;

[0337] Fig.34 A schematic diagram of an eighth implementation of interleaving coding processing;

[0338] Fig.35 A ninth embodiment of the interleaved coding process is shown;

[0339] Fig.36 A schematic diagram of a tenth implementation of interleaving coding processing;

[0340] Fig.37 A schematic diagram of an eleventh implementation of interleaving coding processing;

[0341] Fig.38 A schematic diagram of a twelfth implementation of interleaving coding processing;

[0342] Fig.39 This is another structural schematic diagram of the data processing device in the embodiment of the present application;

[0343] Fig.40 Another structural diagram of the data processing device in the embodiment of the present application. DETAILED DESCRIPTION

[0344] The embodiment of the present application provides a data processing method and a data processing device. The cascade FEC transmission scheme has a strong anti-burst capability and can be applied to more transmission scenarios, especially to actual coherent transmission scenarios where the channel has colored noise. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate, so that the embodiments described in this application can be implemented in an order other than the content described in this application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0345] Figure 1 Schematic diagram of a communication system used in the embodiment of the present application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04 and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). Among them, the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected through the AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules (optical modules), electrical modules, connectors (connectors) or other modules that process data during data transmission. For example, the processing module can be an 800LR module (800LR module, a coherent optical module). Furthermore, the transmitting device 01, the transmitting processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0346] Figure 2 for Figure 1 The following is a schematic diagram of a data transmission process in a communication system. Figure 2As shown, in the process of transmitting data from the transmitting device 01 to the receiving device 05, the transmitting device 01 is used to perform outer code encoding on the data, and then transmit the outer code encoded data to the transmitting end processing module 02. The transmitting end processing module 02 is used to perform inner code encoding on the outer code encoded data to obtain outer code encoded and inner code encoded data, and transmit the outer code encoded and inner code encoded data to the channel transmission medium 03. The channel transmission medium 03 is used to transmit the outer code encoded and inner code encoded data to the receiving end processing module 04. The receiving end processing module 04 is used to perform inner code decoding on the outer code encoded and inner code encoded data, and transmit the inner code decoded data to the receiving end device 05. The receiving end device 05 is used to perform outer code decoding on the inner code decoded data.

[0347] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance of the execution subject operating the data relative to the channel transmission medium 03. The execution subject operating the inner code is closer to the channel transmission medium, and the execution subject operating the outer code is farther away from the channel transmission medium. In the embodiment of the present application, after the data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 through the transmitting end processing module 02, and then transmitted from the channel transmission medium 03 to the receiving end device 05 through the receiving end processing module 04. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting end processing module 02, and the data decoded by the receiving end device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving end processing module 04. Therefore, the data encoded by the transmitting end device 01 is called the data encoded by the outer code, the data encoded by the transmitting end processing module 02 is called the data encoded by the inner code, the data decoded by the receiving end device 05 is called the data decoded by the outer code, and the data decoded by the receiving end processing module 04 is called the data decoded by the inner code. In a possible implementation, the above inner code encoding and outer code encoding are both in the form of FEC encoding, thereby forming a cascade FEC transmission scheme. For example, the transmitting device 01 can use RS code for outer code encoding, and the transmitting processing module 02 can use Hamming code for inner code encoding. For another example, the transmitting device 01 can use RS code for outer code encoding, and the transmitting processing module 02 can use Bose–Chaudhuri–Hocquenghem (BCH) code for inner code encoding.

[0348] It should be noted that the above content is an illustrative description of the application scenarios of the data processing method provided in the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. A person of ordinary skill in the art can know that as business needs change, the application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0349] Figure 3 A flow chart of a data processing method provided in an embodiment of the present application. It should be understood that the method is a data processing performed on a data stream after being encoded by an outer code, which can be specifically implemented by the above-mentioned transmitting end processing module 02.

[0350] 301. Perform inner code encoding on n first data streams respectively to obtain n second data streams.

[0351] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n first data streams, where n is an integer greater than 1. The above-mentioned first data processing may include alignment lock, lane de-skew processing, lane reorder processing, or concatenated interleaving processing, etc. The above-mentioned n first data streams are all data streams encoded by outer code. For example, the outer code encoding can use RS code, and the n data streams after outer code encoding can include multiple RS code words. In practical applications, other encoding methods can also be used for outer code encoding. For the convenience of description, RS code words are uniformly used below to represent the code words generated after outer code encoding. It should be noted that the outer code length value in this application is counted in units of outer code symbols, where a symbol can include one or more bits. For example, the outer code is a KP4 RS (544, 514) code, the code length is 544 symbols, and one outer code symbol contains 10 bits.

[0352] The inner code encoder performs inner code encoding on each K bits in each first data stream, and then adds P check bits to obtain a total of N bits of inner code codewords. Here, the K bits can be called the inner code information sequence, and K+P=N. Usually, K is a multiple of 10, and these K bits correspond to K / 10 outer code symbols. In some scenarios, the K / 10 outer code symbols corresponding to the K information bits come from K / 10 different outer code codewords.

[0353] It should be understood that each second data stream encoded by the inner code contains at least one inner code word. An inner code word is obtained from each second data stream to obtain a total of n inner code words, and these n inner code words include n / m code word sets, namely code word set 0, code word set 1, ..., code word set n / m-1. Each code word set includes m inner code words. Code word set h (0≤h<n / m) includes code word m×h, code word m×h+1, ..., code word m×h+m-1. Among them, n is divisible by m.

[0354] It should be noted that the above codeword set is only a concept introduced for the convenience of description. In practical applications, the second data stream is a whole and has no divisions. Each codeword set can be regarded as a plurality of bits in the second data stream.

[0355] 302. Perform bit interleaving on n / m codeword sets respectively to obtain n / m target bit sets.

[0356] It should be understood that the number of bits in the codeword set and the target bit set is m×N bits. This step is to transform the positions of the bits in the codeword set to obtain the target bit set. As an example, the target bit set can be expressed as a bit matrix of m rows and N columns. As another example, the target bit set can also be expressed as a one-dimensional array including m×N bits. It should be noted that, taking the codeword set as a bit matrix as an example, the bit interleaving provided in the present application includes but is not limited to transforming the positions of the bits in each row of the codeword set (referred to as row transformation), transforming the positions of the bits in each column of the codeword set (referred to as column transformation), and exchanging the positions of the bits in each row and each column of the codeword set (referred to as row and column transformation). Among them, the row and column transformation includes row transformation first and then column transformation, column transformation first and then row transformation, and simultaneous transformation of rows and columns. The following will introduce bit interleaving in detail in combination with several specific implementation methods.

[0357] For simplicity of description, the m×N codeword bits in the codeword set h (0≤h<n / m) are represented by a first matrix H1 with m rows and N columns, where each row of the first matrix H1 includes N bits of an inner codeword. The bits in the i-th (0≤i<m)-th row and j-th (0≤j<N)-th column of the first matrix H1 are denoted as H1[i][j]. More specifically, H1[i][j] represents the j-th bit of the i-th inner codeword in the codeword set h, and also represents the j-th bit in the codeword m×h+i from the second data stream m×h+i. It should be noted that n / m codeword sets correspond to n / m first matrices H1, that is, the codeword set h (0≤h<n / m) corresponds to the h-th first matrix H1. For simplicity of description below, the h-th first matrix H1 is simply described as the first matrix H1.

[0358] The total K bits from the 0th column to the K-1th column of each row in the first matrix H1 correspond to the K-length information bits of an inner code word; the total m×K bits from the 0th column to the K-1th column of the first matrix H1 correspond to the m×K information bits of m inner code words. Similarly, the total P bits from the Kth column to the N-1th column of each row in the first matrix H1 correspond to the P-length check bits of an inner code word; the total m×P bits from the Kth column to the N-1th column of the first matrix H1 correspond to the m×P check bits of m inner code words.

[0359] The following first introduces the specific methods of independently implementing row transformation and column transformation.

[0360] Implementation method 1 of bit interleaving: row transformation (also called first position transformation).

[0361] Specifically, the first position of the K information bits of each inner code word in the code word set is exchanged. Alternatively, it can also be described as "performing a first position change on the K information bits in each row of the first matrix H1". In a possible implementation, the first position change is specifically to perform a left circular shift or a right circular shift on the K information bits in each row of the first matrix H1. Taking the left circular shift as an example, the K information bits in the i-th (0≤i<m) row of the first matrix H1 are circularly shifted left by i×Δ bits, where the non-zero integer Δ is the row offset constraint factor. It should be noted that for the K information bits (u0,u1,u2,u3,…,u K-2 ,u K-1 ), cyclically shift i×Δ bits to the left to obtain K bits after shift (u (i×Δ)％K ,u (1+i×Δ)％K ,u (2+i×Δ)％K ,…,u (K-2+i×Δ)％K ,u (K-1+i×Δ)％K ).

[0362] Figure 4 FIG. 1 is a schematic diagram of cyclically shifting the information bits of each row to the left in an embodiment of the present application. Figure 4 As shown in the example (a), taking K = 8 and cyclic shifting 2 bits to the left as an example, the 8 information bits (u i,0 ,u i,1 ,u i,2 ,u i,3 ,u i,4 ,u i,5 ,u i,6 ,u i,7 ) is cyclically shifted 2 bits to the left to become (u i,2 ,u i,3 ,u i,4 ,u i,5 ,u i,6 ,u i,7 ,u i,0 ,u i,1 ).like Figure 4 As shown in the example (b), taking Δ=2 as an example, the 8 information bits in the i-th row are cyclically shifted to the left by i×2 bits, for example, the 8 information bits in the 0th row are cyclically shifted to the left by 0 bits, the 8 information bits in the 1st row are cyclically shifted to the left by 2 bits, and the 8 information bits in the 2nd row are cyclically shifted to the left by 4 bits. In this way, the cyclic shift is performed to realize the first position transformation of the K information bits in each row of the first matrix H1.

[0363] More specifically, the first position transformation using a circular shift is introduced through the following formulas.

[0364] As an example, the first position transformation adopts a left circular shift to satisfy formula (1.1):

[0365]

[0366] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤i<m. Generally, the row offset constraint factor Δ is a multiple of 10 and 0<Δ<K.

[0367] It should be noted that cyclically shifting the K information bits to the left by i×Δ bits is equivalent to cyclically shifting the K information bits to the left by (i×Δ)%K bits. That is, the above formula (1.1) can be written as the following formula (1.2):

[0368]

[0369] For the K information bits in the i-th row of the first matrix H1, a cyclic shift of i×Δ bits is performed to the left to obtain the K bits in the 0th column to the K-1th column in the i-th row of the second matrix H2. Equivalently, for the K information bits in the 0th column to the K-1th column in the i-th row of the first matrix H1, a cyclic shift of i×(K-Δ) bits is performed to the right to obtain the K bits in the 0th column to the K-1th column in the i-th row of the second matrix H2. Figure 4 As shown in the example of (a), K=8, a cyclic shift of the information bits to the left by 2 bits is equivalent to a cyclic shift to the right by 6 bits.

[0370] As another example, the first position transformation adopts a rightward circular shift to satisfy formula (1.3):

[0371]

[0372] Among them, the integer α is a multiple of K, when 0≤i<m and 0≤j<K is a non-negative integer, an integer Typically, the row offset constraint factor is a multiple of 10 and Other parameters that are the same as those in the above formula (1.1) are not repeated here.

[0373] In some specific formula expressions, for simplicity of description, formula (1.3) will be abbreviated to formula (1.4):

[0374]

[0375] It should also be noted that the above cyclic shift of the K information bits from the 0th column to the K-1th column of each row in the first matrix H1 only operates on the information bits in the first matrix H1. Therefore, it can also be described as: cyclic shifting the K information bits from the 0th column to the K-1th column of each row in the first matrix H1 to obtain a fourth matrix H4 with m rows and K columns. Specifically, the left cyclic shift is used for the first position transformation to satisfy formula (3.1):

[0376] H4=H1[i][(j+i×Δ)%K]

[0377] The meanings of the parameters in formula (3.1) are similar to those in formula (1.1) and will not be repeated here.

[0378] Implementation method 2 of bit interleaving: column transformation (also called second position transformation).

[0379] It should be noted that the column transformation introduced in this implementation is described on the basis of obtaining the second matrix H2 by row transformation of the first matrix H1. In some possible scenarios, this implementation can also be used to perform column transformation on the first matrix H1, which will not be described here.

[0380] Specifically, the bits at the same position in the second matrix H2 are subjected to a second position transformation to obtain a third matrix H3. It should be understood that the bits at the same position in the second matrix H2 can be understood as the m bits at the same column in the second matrix H2, that is, the positions of the m bits at the same column are transformed. Alternatively, the bits at the same position in the second matrix H2 can also be understood as the G×m bits at the same G column in the second matrix H2, where G is an integer greater than 1, that is, the upper and lower positions are transformed with the G bits at the same G column in each row as a unit. For ease of explanation, the same column at the same position is used as an example for introduction below.

[0381] In one possible implementation, the second matrix H2 is divided into m / L first sub-matrices, and each first sub-matrix contains L rows and N columns. In each first sub-matrix, the L bits in each column are circularly shifted upward or downward to achieve a position change of the bits in each first sub-matrix. Taking the upward circular shift as an example, the L bits in the j-th (0≤j<N) column of each first sub-matrix are circularly shifted upward by θ×(j%L) bits, where the non-zero integer θ is the column offset constraint factor. Here, the L bits in the j-th (0≤j<N) column of each first sub-matrix are circularly shifted upward by θ×(j%L) bits, which is also equivalent to an upward circular shift of θ×j bits, which is known to those skilled in the art and will not be described in detail here. For the L bits Circularly shift upward by θ×(j%L) to obtain L bits after the shift

[0382] Figure 5 FIG. 1 is a schematic diagram of performing an upward cyclic shift on the L bits in each column of each first sub-matrix in an embodiment of the present application. Figure 5 As shown in the example (a), taking L = 8 and cyclic shifting upward by 2 bits as an example, the 8 bits in the jth column Circularly shift upward by 2 bits to obtain 8 bits after shifting like Figure 5 As shown in the example (b), taking θ=2 as an example, the 8 bits in the jth column are cyclically shifted upward by 2×(j%8) bits, for example, the 8 bits in the 0th column are cyclically shifted upward by 0 bits, the 8 bits in the 1st column are cyclically shifted upward by 2 bits, and the 8 information bits in the 2nd column are cyclically shifted upward by 4 bits. In this way, the cyclic shift is performed to realize the second position transformation of the bits located at the same position in the second matrix H2.

[0383] More specifically, the second position transformation using a circular shift is introduced through the following formulas.

[0384] As an example, the second position transformation adopts upward circular shift to satisfy formula (2.1):

[0385]

[0386] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents rounding down, Y%Z represents the remainder after integer Y is divided by integer Z, 0≤i<m, 0≤j<N. The non-zero integer θ is the column offset constraint factor. Usually, the column offset constraint factor 0<θ<L.

[0387] It should be understood that the above formula (2.1) can also be written as:

[0388] For the L bits in the jth column of the first submatrix in the second matrix H2, performing an upward cyclic shift of θ×(j%L) bits is equivalent to performing a downward cyclic shift of (L-θ)×(j%L) bits. Figure 5 As shown in the example of (a), L=8, a cyclic shift upward by 2 bits is equivalent to a cyclic shift downward by 6 bits.

[0389] As another example, the second position transformation adopts downward circular shift to satisfy formula (2.2):

[0390]

[0391] Among them, the integer β is a multiple of L, when all 0≤i<m and 0≤j<N is a non-negative integer, an integer Typically, the column offset constraint factor Other parameters that are the same as those in the above formula (2.1) are not repeated here.

[0392] In some specific formula expressions, for simplicity of description, formula (2.2) will be abbreviated to formula (2.3):

[0393]

[0394] In another possible implementation, different from the above-mentioned upward circular shift or downward circular shift, the second position transformation satisfies formula (2.4):

[0395]

[0396] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. It means rounding down, Y%Z means the remainder after dividing the integer Y by the integer Z, Y^Z means the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0397] Figure 6 FIG. 1 is a schematic diagram of changing the position of the bits in each column in an embodiment of the present application. Figure 6 As shown, when m=8, L=8, the second position transformation method that satisfies the above formula (2.4) is shown. i,jRepresented as the bit of the i-th row and j-th column of the second symbol matrix H2. Each consecutive 8 columns of the second matrix H2, namely the 8*kth column to the 8*k+7th column, are interleaved and mapped to the consecutive 8 columns of the third symbol matrix, namely the 8*kth column to the 8*k+7th column, in the manner shown in the figure.

[0398] It should be noted that when the integer L is a power of 2, the above second position transformation can also satisfy formula (2.5):

[0399] H3[i][j]=H2[i^(j%L)][j]

[0400] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by the XOR operation of the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i<m, 0≤j<N.

[0401] It should also be noted that the first position transformation is only a position transformation of the information bits, while the second position transformation is a position transformation of both the information bits and the check bits. For the fourth matrix H4 with m rows and K columns only for the information bits, the second position transformation can be expressed in another way as follows:

[0402] Specifically, the fourth matrix H4 with m rows and K columns and the first matrix H1 with m rows and N columns from the Kth column to the N-1th column are divided into a plurality of second sub-matrices, each of which contains L rows and N columns. The L bits in each column of each second sub-matrix are position-transformed to obtain a third matrix H3 with m rows and N columns.

[0403] A specific implementation method is to cyclically shift the L bits in the jth (0≤j<N) column of each second submatrix upward by θ×(j%L) bits. More specifically, for 0≤i<m, the second position transformation can also satisfy formula (4.1):

[0404]

[0405] Where the integer θ is the column offset constraint factor. Formula (4.1) can also be simplified as:

[0406]

[0407] Another specific implementation method is that, for 0≤i<m, the second position transformation can also satisfy formula (4.2):

[0408]

[0409] When L is a power of 2, for 0≤i<m, the second position transformation can also satisfy formula (4.3):

[0410]

[0411] It should be understood that the above describes the specific methods of implementing row transformation and column transformation independently, that is, bit interleaving includes two steps. In some possible scenarios, the above row transformation and column transformation can also be implemented by one step, and this implementation method is described in detail below.

[0412] Implementation method 3 of bit interleaving: row transformation and column transformation are implemented through one step operation.

[0413] In a specific implementation, for 0≤i<m, bit interleaving satisfies formula (5):

[0414]

[0415] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, and θ is a non-zero integer greater than -L and less than L.

[0416] Formula (5) can also be simplified as:

[0417]

[0418] In another specific implementation, for 0≤i<m, bit interleaving satisfies formula (6):

[0419]

[0420] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z.

[0421] When L is a power of 2, for 0≤i<m, bit interleaving satisfies formula (7):

[0422]

[0423] It should be noted that when the integer Δ is a multiple of 10, and one outer code symbol in the outer code word contains 10 bits, the K information bits can be considered as K / 10 symbols, where each symbol corresponds to 10 information bits. Cyclic shifting the K information bits in the i-th (0≤i<m) row of the first matrix H1 by i×Δ bits can be considered as cyclic shifting the K / 10 symbols in the i-th (0≤i<m) row of the first matrix H1. The specific implementation method is known to those skilled in the art and will not be described in detail here.

[0424] When specific values ​​of parameters such as Δ, θ, m, and L are given, the interleaving correspondence of bit interleaving the first matrix H1 to obtain the third matrix H3 can be described by a table. The specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0425] When specific values ​​of parameters such as Δ, θ, m, and L are given, the above formula (5) or (6) can be simply transformed into other formulas. For example, when m=L, formula (5) can be simplified as follows:

[0426]

[0427] Formula (6) can be transformed as follows:

[0428]

[0429] or

[0430]

[0431] It should be understood that the specific implementation methods of other simple transformations are known to ordinary technicians in this field and will not be repeated here.

[0432] It should be noted that the above codeword set, bit matrix, and submatrix are concepts introduced only for the convenience of description. In practical applications, the data stream is a whole and there is no division. Each codeword set, bit matrix, and submatrix can be regarded as one or more bits in the data stream. In addition, in practical applications, the above-mentioned first matrix, second matrix, third matrix, fourth matrix, etc. may not be presented in the form of a matrix. For example, the first matrix H1 is presented as a first bit set, and the first bit set includes m first bit subsets, and each first bit subset includes a row and N columns of bit elements corresponding to the first matrix H1.

[0433] It should be noted that in the above implementation, the target bit set after bit interleaving of m codewords is represented by a third matrix H3 with m rows and N columns. In addition, the target bit set can also be represented by a one-dimensional array, denoted as array A, which contains m×N bits. The tth (0≤t<m×N) bit in array A is denoted as A[t]. The array A containing m×N bit elements obtained by bit interleaving the first matrix H1 can also be represented in the following way.

[0434] As an example, for 0≤i<m, bit interleaving satisfies formula (8):

[0435]

[0436] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the bit interleaving is performed, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving is performed, 0≤tvm×N, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, and θ is a non-zero integer greater than -L and less than L.

[0437] As another example, for 0≤ivm, bit interleaving satisfies formula (9):

[0438]

[0439] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z.

[0440] When L is a power of 2, for 0≤i<m, bit interleaving satisfies formula (10):

[0441]

[0442] 303. Map the m×N bits in each target bit set respectively to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols.

[0443] In this embodiment, m is divisible by L. Each L bits in the target bit set is mapped to a modulation symbol, that is, a modulation symbol includes L bits. The L bits in each modulation symbol come from L inner code words respectively. In addition, if the L bits mapped to the modulation symbol all come from information bits of the inner code word, any two bits of the L bits mapped to the modulation symbol come from two different positions of two different inner code words.

[0444] It should be understood that the n×N / L modulation symbols obtained by mapping all target bit sets can be expressed as a modulation symbol stream. Alternatively, the m×N / L modulation symbols obtained by mapping each target bit set can be expressed as a modulation symbol stream to obtain a total of n / m modulation symbol streams. The modulation symbol stream can also be sent to the channel transmission medium for transmission after other data processing. Other data processing may include polarization distribution or DSP framing processing.

[0445] In a possible implementation, when N is divisible by L, the N bits of each inner codeword are respectively mapped to N modulation symbols, and the N bits of the inner codeword include L first bit subsets, bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols. For example, a modulation symbol includes bit position b0, bit position b1, ..., bit position b L-1 , the N bits of the inner code word are mapped to bit b0, bit b1, ..., bit b L-1 The number of bits is N / L. It should be understood that the probability of errors in the above L bits during transmission is not necessarily equal, and mapping the bits of an inner code word more evenly to the modulation symbols can improve the burst resistance of the cascade FEC scheme in actual transmission.

[0446] It should be noted that in some possible scenarios, the n first data streams are all processed by identification locking and channel correction. When W×L bits in W consecutive modulation symbols are all information bits of the inner code word, the W×L bits come from more than 2 outer code code words encoded by the outer code, where W≥2.

[0447] In some implementations applied to coherent optical communications, the above modulation method is dual-polarization quadrature amplitude modulation (DP-QAM), such as DP-QPSK or DP-16QAM. For DP-QPSK modulation, one DP-QPSK modulation symbol corresponds to L = 4 bits; for DP-16QAM modulation, one DP-16QAM modulation symbol corresponds to L = 8 bits.

[0448] In some implementations applied to direct-detection optical communications, the above modulation method is pulse amplitude modulation (PAM), such as PAM4. Under PAM4 modulation, one PAM4 modulation symbol corresponds to L=2 bits.

[0449] The specific implementation of the mapping is introduced below by taking the target bit set represented by the third matrix H3 as an example.

[0450] Mapping implementation method 1:

[0451] Every L consecutive bits of the m bits in each column of the third matrix H3 are mapped to a modulation symbol. Each third matrix H3 is mapped to m×N / L modulation symbols.

[0452] In a possible implementation, the m / L modulation symbols obtained by mapping the m bits in each column of the third matrix H3 are continuous in the modulation symbol stream. That is, the m / L modulation symbols obtained by mapping each column in the third matrix H3 are used as continuous m / L modulation symbols in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping N columns in the third matrix H3 are used as continuous m×N / L modulation symbols in the modulation symbol stream.

[0453] Figure 7 This is a first schematic diagram of mapping bits in an embodiment of the present application. Figure 7 As shown, when m / L=2, the third matrix H3 maps each column to 2 modulation symbols, and these 2 modulation symbols are represented by S(0,j) and S(1,j) respectively, where 0≤j<N.

[0454] In another possible implementation, the m bits located in column B of the third matrix H3 are mapped to obtain m / L first modulation symbols, and each consecutive T first modulation symbols among the m / L first modulation symbols are continuous in the modulation symbol stream. The m bits located in column C of the third matrix H3 are mapped to obtain m / L second modulation symbols, and each consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream. Among them, column B is adjacent to column C, consecutive T first modulation symbols among the m / L first modulation symbols and consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, and m / L is divisible by T.

[0455] Figure 8 This is a second schematic diagram of mapping bits in an embodiment of the present application. Figure 8 As shown, when m / L=4 and T=2, each column of the third matrix H3 is mapped to 4 modulation symbols, represented by S(0,j), S(1,j), S(2,j), S(3,j), where 0≤j<N. It can be seen that the first T modulation symbols of the m / L modulation symbols obtained by mapping each column of the third matrix H3 are used as the continuous T modulation symbols in the modulation symbol stream, and accordingly, the total T×N modulation symbols in N columns are used as the continuous T×N modulation symbols in the modulation symbol stream. The next T modulation symbols of the m / L modulation symbols obtained by mapping each column of the third matrix H3 are used as the continuous T modulation symbols in the modulation symbol stream, and accordingly, the total T×N modulation symbols in N columns are used as the next continuous T×N modulation symbols in the modulation symbol stream. By analogy, continuous m×N / L modulation symbols in the modulation symbol stream can be obtained.

[0456] Mapping implementation method 2:

[0457] The L bits in each modulation symbol come from L r Inner code words, L r Each of the inner code words has L c A total of L bits r ×L c bits are mapped to one modulation symbol, and the 2L bits in two consecutive modulation symbols come from 2L r Inner code words, 2L r Each of the inner code words has L c bits are mapped to two consecutive modulation symbols, L = L r ×L c ,L c >1. That is, the third matrix H3 has r L in the row c Total L r ×L c = L bits are mapped into one modulation symbol, where L c> 1. For example, bit b0, bit b1, ..., bit b of a modulation symbol L-1 The corresponding L inner code bits come from L r different inner code words, and each inner code word provides L c bits. For the third matrix H3, each L c Total number of columns m×L c bits are mapped to m / L r Each third matrix H3 is mapped to m×N / L modulation symbols, and continuous m×N / L modulation symbols are obtained in the modulation symbol data stream.

[0458] In a possible implementation, the third matrix H3 is c m / L obtained by column mapping r modulation symbols as continuous m / L in the modulation symbol stream r modulation symbols, and the m×N / L modulation symbols obtained by mapping to N columns are used as continuous m×N / L modulation symbols in the modulation symbol stream.

[0459] Fig. 9 This is a third schematic diagram of mapping bits in the embodiment of the present application. Fig. 9 As shown, when When each L in the third matrix H3 c The total number of columns mapped is m×L c The bitmap is modulation symbols, represented by S(0,j) and S(1,j), where 0≤j<N / L c .

[0460] In another possible implementation, the bits in column B in the third matrix H3 are mapped to obtain m / L r The first modulation symbol, m / L r Each consecutive T first modulation symbols in the first modulation symbols are continuous in the modulation symbol stream. The bit mapping in the C column of each target bit set is obtained by m / L r The second modulation symbol, m / L r Each consecutive T second modulation symbols in the second modulation symbols are consecutive in the modulation symbol stream. Wherein, column B includes L c Column C also includes L c Column, Column B is adjacent to Column C, m / L r The first modulation symbols of the continuous T first modulation symbols are m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0461] Fig.10This is a fourth schematic diagram of mapping bits in the embodiment of the present application. Fig.10 As shown, when When T=2, each L in the third matrix H3 c The total number of columns mapped is m×L c The bitmap is modulation symbols, represented by S(0,j), S(1,j), S(2,j), S(3,j), where 0≤j<N / L c It can be seen that c m / L obtained by column mapping r The first T modulation symbols of the modulation symbols are used as the continuous T modulation symbols in the first modulation symbol stream. Accordingly, the total number of N columns is T×N / L. c modulation symbols as consecutive T×N / L in the modulation symbol stream c modulation symbols. c m / L obtained by column mapping r The next T modulation symbols in the modulation symbols are used as the consecutive T modulation symbols in the first modulation symbol stream. Accordingly, the total number of N columns is T×N / L. c modulation symbols as the next consecutive T×N / L in the modulation symbol stream c By analogy, m×N / L continuous modulation symbols in the modulation symbol stream can be obtained.

[0462] In the embodiment of the present application, a cascade FEC transmission scheme is adopted, that is, the data stream is successively coded by the outer code and the inner code. On this basis, the present application designs a method of bit interleaving and mapping, so that the bits in the outer code word and the bits in the inner code word are discretely and evenly mapped to the modulation symbol, so that the cascade FEC transmission scheme has a strong burst resistance capability, especially for burst errors with a short length, which can be directly corrected by inner code decoding, and can be applied to more transmission scenarios, especially for actual coherent transmission scenarios where the channel has colored noise.

[0463] The above is described below in conjunction with some specific embodiments. Figure 3 The process of the described data processing method is further introduced.

[0464] Embodiment 1: The target bit set is represented by a bit matrix, n=32, m=16, K=160, L=8.

[0465] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts BCH (176, 160), that is, the code word bit length N=176, the information bit length K=160, and the check bit length P=16. The 160 information bits of each inner code word come from 16 symbols of 16 different outer code RS code words.

[0466] The 32 codewords after the above inner code encoding are divided into h = 2 codeword sets, each codeword set contains m = 16 BCH (176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 352 DP-16QAM symbols can be obtained from the 16 BCH (176, 160) codewords in each codeword set.

[0467] The above 16 BCH (176, 160) codewords with a total of 2816 bits are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 16 rows and 176 columns, and its interleaving correspondence is: for 0≤i<16, there is

[0468]

[0469] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, a non-zero integer θ is a column offset constraint factor, and a non-zero integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, 150. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0470] The third matrix H3 with 16 rows and 176 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols respectively. A specific implementation method is that rows 0-7 in each column are mapped to a DP-16QAM symbol, and rows 8-15 are mapped to another DP-16QAM symbol. Each third matrix H3 is mapped to 352 DP-16QAM symbols. The 2 DP-16QAM symbols mapped in each column are used as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols mapped in 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0471] Every 16 codewords in the above 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0472] In this embodiment, when colored noise exists in the actual transmission and the width is 4 DP-16QAM symbols, 32 error bits can be dispersed to multiple inner codes BCH (176, 160), and the number of error bits corresponding to each inner code is no more than 2. Considering that the inner code BCH (176, 160) can correct 2 bits, the colored noise of the 2-3 DP-16QAM symbol width can be effectively corrected by the inner code. In addition, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can resist burst errors with a length greater than 1500 bits. That is, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits. By adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0473] Embodiment 2: The target bit set is represented as an array, n=32, m=16, K=160, L=8.

[0474] Based on the scheme of Example 1, 16 BCH (176, 160) codewords with a total of 2816 bits are represented by a first matrix H1 with 16 rows and 176 columns. The data obtained after bit interleaving is not represented by a third matrix H3 with 16 rows and 176 columns as shown in Example 1, but by an array A with a length of 2816 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2816 bits, and its interleaving correspondence is: for 0≤i<16, there is

[0475]

[0476] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, 150. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0477] By mapping every 8 consecutive bits in the first array A containing 2816 bits to a DP-16QAM symbol, 352 DP-16QAM symbols can be obtained as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0478] Every 16 codewords in the above 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0479] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 1 are respectively equal to the values ​​of Δ and θ in Example 2, the 32 codewords in Example 2 are bit interleaved and mapped to obtain the same 704 DP-16QAM symbols as those in Example 2.

[0480] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0481] Embodiment 3: The target bit set is represented by a bit matrix, n=32, m=8, K=160, L=8.

[0482] Based on the scheme of Example 1, the 32 codewords after inner code encoding are not divided into 2 codeword sets as shown in Example 1, but are divided into 4 codeword sets, each of which contains m = 8 BCH (176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 8 BCH (176, 160) codewords in each codeword set can obtain 176 DP-16QAM symbols.

[0483] The above 8 BCH (176, 160) codewords with a total of 1408 bits are represented by a first matrix H1 with 8 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 176 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0484]

[0485] It can be simplified to

[0486]

[0487] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, 150. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0488] The third matrix H3 of 8 rows and 176 columns contains 8 bits in each column. The 8 bits in each column are mapped to one DP-16QAM symbol. Each third matrix H3 is mapped to 176 DP-16QAM symbols. The 176 DP-16QAM symbols obtained by mapping the 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0489] Every 8 codewords in the above 32 codewords are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0490] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise of up to 2 DP-16QAM symbol widths, and can resist burst errors of length greater than 2000 bits.

[0491] Embodiment 4: The target bit set is represented as an array, n=32, m=8, K=160, L=8.

[0492] Based on the solution of Embodiment 3, 8 BCH (176, 160) codewords with a total of 1408 bits are represented by a first matrix H1 with 8 rows and 176 columns. The data obtained after bit interleaving is not represented by a third matrix H3 with 8 rows and 176 columns as shown in Embodiment 1, but by an array A with a length of 1408 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 1408 bits, and its interleaving correspondence is: for 0≤i<8, there is

[0493]

[0494] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, 150. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0495] By mapping every 8 consecutive bits in the first array A containing 1408 bits to a DP-16QAM symbol, 176 DP-16QAM symbols can be obtained as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0496] Every 8 code words in the above 32 code words are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 code words are mapped to a total of 704 DP-16QAM symbols after bit interleaving.

[0497] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 4 are respectively equal to the values ​​of Δ and θ in Example 3, the 32 codewords in Example 4 are bit interleaved and mapped to obtain the same 704 DP-16QAM symbols as those in Example 3.

[0498] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise of up to 2 DP-16QAM symbol widths, and can resist burst errors of length greater than 2000 bits.

[0499] Embodiment 5: The target bit set is represented by a bit matrix, n=32, m=32, K=160, L=8.

[0500] Based on the scheme of Example 1, the 32 codewords after inner code encoding are not divided into 2 codeword sets as shown in Example 1, but 32 codewords are used as a codeword set, including m=32 BCH(176,160) codewords. Considering DP-16QAM modulation, each L=8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 32 BCH(176,160) codewords can obtain 704 DP-16QAM symbols.

[0501] The above 32 BCH (176, 160) codewords with a total of 5632 bits are represented by a first matrix H1 with 32 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 32 rows and 176 columns, and its interleaving correspondence is: for 0≤i<32, there is

[0502]

[0503] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, 140. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0504] The third matrix H3 with 32 rows and 176 columns has 32 bits in each column. The 32 bits in each column are mapped to 4 DP-16QAM symbols. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, constituting 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0505] A specific implementation method is that the first T=1 DP-16QAM symbol of the 4 DP-16QAM symbols mapped in each column (that is, the 0th DP-16QAM symbol mapped in each column), and a total of 176 DP-16QAM symbols in 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream; the next T=1 DP-16QAM symbol of the 4 DP-16QAM symbols mapped in each column (that is, the 1st DP-16QAM symbol mapped in each column), and a total of 176 DP-16QAM symbols in 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; and so on, a total of 704 consecutive DP-16QAM symbols in the first modulation symbol stream can be obtained.

[0506] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise of up to 2 DP-16QAM symbol widths, and can resist burst errors of length greater than 2000 bits.

[0507] Embodiment 6: The target bit set is represented by a bit matrix, 2 symbols in each column are output continuously, n=32, m=32, K=160, L=8.

[0508] Based on the scheme of Example 5, 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, constituting 704 continuous DP-16QAM symbols in the first modulation symbol stream. This embodiment provides another specific implementation method: the first 2 DP-16QAM symbols of the 4 DP-16QAM symbols mapped in each column (i.e., the 0th and 1st DP-16QAM symbols mapped in each column), 176 columns of a total of 352 DP-16QAM symbols are used as 352 continuous DP-16QAM symbols in the first modulation symbol stream; the last 2 DP-16QAM symbols of the 4 DP-16QAM symbols mapped in each column (i.e., the 2nd and 3rd DP-16QAM symbols mapped in each column), 176 columns of a total of 352 DP-16QAM symbols are used as the next 352 continuous DP-16QAM symbols in the first modulation symbol stream; finally, 704 continuous DP-16QAM symbols in the first modulation symbol stream are obtained.

[0509] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0510] Embodiment 7: The target bit set is represented by a bit matrix, 2 symbols are output continuously in each column, n=16, m=16, K=160, L=8.

[0511] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 16 second data streams. The inner code encoding adopts BCH (176, 160), that is, the code word bit length N=176, the information bit length K=160, and the check bit length P=16. The 160 information bits of each inner code word come from 16 symbols of 16 different outer code RS code words.

[0512] The above 16 inner codewords are regarded as a codeword set, including m=16 BCH(176,160) codewords. Considering DP-16QAM modulation, each L=8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 16 BCH(176,160) codewords can obtain 352 DP-16QAM symbols.

[0513] The above 16 BCH (176, 160) codewords with a total of 2816 bits are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 16 rows and 176 columns, and its interleaving correspondence is: for 0≤i<16, there is

[0514]

[0515] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160<Δ<160, an integer θ is a column offset constraint factor, and a non-zero integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, 140. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0516] The third matrix H3 with 16 rows and 176 columns mentioned above contains 16 bits in each column. The 16 bits in each column are mapped to 2 DP-16QAM symbols. A specific implementation method is that rows 0-7 in each column are mapped to one DP-16QAM symbol, and rows 8-15 are mapped to another DP-16QAM symbol. The 16 codewords are mapped to a total of 352 DP-16QAM symbols after bit interleaving, constituting 352 consecutive DP-16QAM symbols in the first modulation symbol stream. A specific implementation method is that the 2 DP-16QAM symbols mapped in each column are used as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols mapped in 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0517] It should be noted that the 2816-bit interleaved data obtained by bit interleaving the above-mentioned first matrix H1 is represented by a third matrix H3 with 16 rows and 176 columns, and can also be represented by an array of length 2816 bits, as shown in Example 2 and Example 4. The specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0518] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0519] It should be noted that the operation flow of the transmitting processing module can also be as shown in Figure 12(b), where the channel data stream after identification locking does not undergo channel de-skew processing and is directly sent to the channel reordering. When the client-side interface is 2-way 400G, the RS symbols in any of the channel data streams 0-15 and the RS symbols in any of the channel data streams 16-31 sent to the convolutional interleaving come from two different RS outer code words. In this 2×400G interface scenario, the transmitting processing module adopts the operation flow as shown in Figure 12(c) or Figure 12(d) without performing the channel reordering operation, and can still ensure that the 160 information bits in the inner code word correspond to 16 RS symbols from 16 different outer code RS code words. At this time, the delay of the overall cascade FEC solution can be reduced, but its ability to resist burst errors will be weakened. Whether to perform channel de-skew processing and channel reordering in the transmitting processing module can be determined according to the actual transmission scenario.

[0520] Embodiment 8: The target bit set is represented by a bit matrix, 4 symbols in each column are output continuously, n=8, m=8, K=120, L=2.

[0521] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=8 first data streams. The 8 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 8 second data streams. The inner code encoding adopts Hamming code Hamming (128, 120), that is, the code word bit length N=128, the information bit length K=120, and the check bit length P=8. The 120 information bits of each inner code word come from 12 symbols of 12 different outer code RS code words.

[0522] The above 8 inner codewords are regarded as a codeword set, including m=8 Hamming (128, 120) codewords. Considering PAM4 modulation, each L=2 bits are mapped to a PAM4 symbol. After bit interleaving and mapping, 8 Hamming (128, 120) codewords can obtain 512 PAM4 symbols.

[0523] The above 8 Hamming (128, 120) codewords with a total of 1024 bits are represented by a first matrix H1 with 8 rows and 128 columns, where each row of the first matrix H1 includes 128 bits of an inner code Hamming (128, 120) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 128 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0524]

[0525] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<120, a non-zero integer θ is a column offset constraint factor, and integer θ = 1. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, and 100.

[0526] The third matrix H3 of the above 8 rows and 176 columns contains 8 bits in each column. The 8 bits in each column are mapped to 4 PAM4 symbols. A specific implementation method is that the 2 bits in the 0th to 1st rows in each column are mapped to a PAM4 symbol, the 2 bits in the 2nd to 3rd rows are mapped to another PAM4 symbol, the 2 bits in the 4th to 5th rows are mapped to another PAM4 symbol, and the 2 bits in the 6th to 7th rows are mapped to another PAM4 symbol. The 8 codewords are mapped to a total of 512 PAM4 symbols after bit interleaving, constituting 512 consecutive PAM4 symbols in the first modulation symbol stream. A specific implementation method is that the 4 PAM4 symbols mapped in each column are used as 4 consecutive PAM4 symbols in the first modulation symbol stream, and the 512 PAM4 symbols mapped in 128 columns are used as 512 consecutive PAM4 symbols in the first modulation symbol stream.

[0527] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise of up to 4 PAM4 symbol widths, and can resist burst errors with a length greater than 1200 bits.

[0528] Embodiment 9: The target bit set is represented by a bit matrix, 4 symbols in each column are output continuously, n=32, m=8, K=120, L=2.

[0529] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from a plurality of synchronous client lanes to obtain n=32 first data streams. Fig.11 Schematic diagram of performing inner code encoding and interleaving modulation mapping on a data stream in an embodiment of the present application. Fig.11As shown, 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts Hamming code Hamming (128, 120), that is, the code word bit length N = 128, the information bit length K = 120, and the check bit length P = 8. The 120 information bits of each inner code word come from 12 symbols of 12 different outer code RS code words. The 32 second data streams are divided into 4 second data stream groups, each group contains 8 second data streams, and each second data stream group is interleaved and modulated to obtain a modulation symbol stream, and a total of 4 modulation mapping streams are obtained. The 4 modulation mapping data streams will be transmitted through 4 different channels. The 4 different channels shown can be 4 different wavelengths, or 4 different optical fibers, etc.

[0530] A Hamming (128, 120) codeword is obtained from each of the above second data streams, and a total of 8 Hamming (128, 120) codewords with a total of 1024 bits are represented by a first matrix H1 with 8 rows and 128 columns, wherein each row of the first matrix H1 includes 128 bits of an inner code Hamming (128, 120) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 128 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0531]

[0532] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<120, a non-zero integer θ is a column offset constraint factor, and the integer θ=1. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110.

[0533] Another interleaving mapping relationship is:

[0534]

[0535] The third matrix H3 of 8 rows and 176 columns contains 8 bits in each column. The 8 bits in each column are mapped to 4 PAM4 symbols. A specific implementation method is that the 2 bits in the 0th to 1st rows in each column are mapped to one PAM4 symbol, the 2 bits in the 2nd to 3rd rows are mapped to another PAM4 symbol, the 2 bits in the 4th to 5th rows are mapped to another PAM4 symbol, and the 2 bits in the 6th to 7th rows are mapped to another PAM4 symbol. After bit interleaving, the 8 codewords are mapped to a total of 512 PAM4 symbols, constituting 512 consecutive PAM4 symbols in the first modulation symbol stream.

[0536] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascaded FEC scheme as a whole can effectively resist colored noise of up to 8 PAM4 symbol widths on each channel, and can resist burst errors with a length greater than 1100 bits.

[0537] It should be noted that the operation flow of the transmitting end processing module can also be as shown in Figure 12(b), where the channel data stream after identification locking does not undergo channel de-skew processing and is directly sent to channel reordering. In this case, the latency of the overall cascade FEC solution can be reduced, but its ability to resist burst errors will be weakened. Whether to perform channel de-skew processing and channel reordering in the transmitting end processing module can be determined according to the actual transmission scenario.

[0538] Embodiment 10: The target bit set is represented by a bit matrix, n=32, m=8, K=160, L=8, L r =4,L c =2.

[0539] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts BCH (176, 160), that is, the code word bit length N=176, the information bit length K=160, and the check bit length P=16. The 160 information bits of each inner code word come from 16 symbols of 16 different outer code RS code words.

[0540] The 32 codewords after inner code encoding are divided into 4 codeword sets, each of which contains m = 8 BCH (176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 8 BCH (176, 160) codewords in each codeword set can obtain 176 DP-16QAM symbols.

[0541] The above 8 BCH (176, 160) codewords with a total of 1408 bits are represented by a first matrix H1 with 8 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 176 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0542]

[0543] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<160, and an integer is a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, 150.

[0544] The third matrix H3 with 8 rows and 176 columns has 8 bits per column. r =4,L c =2. A total of 8 bits in 2 columns in every 4 rows are mapped to a DP-16QAM symbol. The 2 modulation symbols obtained by mapping every 2 columns in the third matrix H3 are used as 2 consecutive modulation symbols in the first modulation symbol stream, and the 176 modulation symbols obtained by mapping 176 columns are used as 176 consecutive modulation symbols in the first modulation symbol stream, as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0545] Every 8 codewords in the above 32 codewords are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0546] Embodiment 11: The target bit set is represented by a bit matrix, n=32, m=16, K=160, L=8, L r =4,L c =2.

[0547] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts BCH (176, 160), that is, the code word bit length N=176, the information bit length K=160, and the check bit length P=16. The 160 information bits of each inner code word come from 16 symbols of 16 different outer code RS code words.

[0548] The 32 codewords after inner code encoding are divided into 2 codeword sets, each codeword set contains m = 16 BCH (176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 352 DP-16QAM symbols can be obtained from the 16 BCH (176, 160) codewords in each codeword set.

[0549] The above 16 BCH (176, 160) codewords with a total of 1408 bits are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 16 rows and 176 columns, and its interleaving correspondence is: for 0≤i<16, there is

[0550]

[0551] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<160, and an integer is a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, 150.

[0552] The third matrix H3 with 16 rows and 176 columns contains 16 bits per column. r =4,L c = 2. A total of 8 bits in 2 columns in every 4 rows are mapped to a DP-16QAM symbol. 4 DP-16QAM symbols are obtained by mapping every 2 columns in the third matrix H3.

[0553] The first two DP-16QAM symbols of the 4 DP-16QAM symbols mapped from every 2 columns in the third matrix H3 (i.e., the 0th and 1st DP-16QAM symbols mapped from each column), and a total of 176 DP-16QAM symbols in 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream; the last two DP-16QAM symbols of the 4 DP-16QAM symbols mapped from every 2 columns (i.e., the 2nd and 3rd DP-16QAM symbols mapped from every 2 columns), and a total of 176 DP-16QAM symbols in 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; finally, 352 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.

[0554] Every 16 codewords in the above 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0555] Embodiment 12: The target bit set is represented by a bit matrix, n=32, m=16, K=110, L=8.

[0556] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts BCH (126, 110), that is, the code word bit length N=126, the information bit length K=110, and the check bit length P=16. The 110 information bits of each inner code word come from 11 symbols of 11 different outer code RS code words.

[0557] The 32 codewords after the inner code encoding are divided into h = 2 codeword sets, each of which contains m = 16 BCH (126, 110) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 252 DP-16QAM symbols can be obtained from the 16 BCH (126, 110) codewords in each codeword set.

[0558] The above 16 BCH (126, 110) codewords with a total of 2016 bits are represented by a first matrix H1 with 16 rows and 126 columns, where each row of the first matrix H1 includes 126 bits of an inner code BCH (126, 110) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 16 rows and 126 columns, and its interleaving correspondence is: for 0≤i<16, there is

[0559]

[0560] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -110<Δ<110, a non-zero integer θ is a column offset constraint factor, and a non-zero integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, and 100. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0561] The third matrix H3 with 16 rows and 126 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols respectively. A specific implementation method is that rows 0-7 in each column are mapped to a DP-16QAM symbol, and rows 8-15 are mapped to another DP-16QAM symbol. Each third matrix H3 is mapped to 252 DP-16QAM symbols. The 2 DP-16QAM symbols mapped in each column are used as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 252 DP-16QAM symbols mapped in 176 columns are used as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0562] Every 16 codewords in the above 32 codewords are mapped to 252 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0563] In this embodiment, when colored noise exists in the actual transmission and the width is 4 DP-16QAM symbols, 32 error bits can be dispersed to multiple inner codes BCH (126, 110), and the number of error bits corresponding to each inner code is no more than 2. Considering that the inner code BCH (126, 110) can correct 2 bits, the colored noise of the 2-3 DP-16QAM symbol width can be effectively corrected by the inner code. In addition, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can resist burst errors with a length greater than 1200 bits. That is, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits. By adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0564] Embodiment 13: The target bit set is represented as an array, n=32, m=16, K=110, L=8.

[0565] Based on the scheme of Example 12, 16 BCH (126, 110) codewords with a total of 2016 bits are represented by a first matrix H1 with 16 rows and 126 columns. The data obtained after bit interleaving is not represented by the third matrix H3 with 16 rows and 126 columns as shown in Example 1, but by an array A with a length of 2016 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2016 bits, and its interleaving correspondence is: for 0≤i<16, there is

[0566]

[0567] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -110<Δ<110, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100. A typical value of the integer θ is θ=7, and another typical value is θ=1. In particular, for 0≤i<16, there is

[0568]

[0569] By mapping every 8 consecutive bits in the first array A containing 2016 bits to a DP-16QAM symbol, 252 DP-16QAM symbols can be obtained as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0570] Every 16 codewords in the above 32 codewords are mapped to 252 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0571] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 11 are respectively equal to the values ​​of Δ and θ in Example 12, the 32 codewords in Example 11 are bit interleaved and mapped to obtain the same 504 DP-16QAM symbols as those in Example 12.

[0572] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0573] Embodiment 14: The target bit set is represented by a bit matrix, n=32, m=8, K=110, L=8, L r =4,L c =2.

[0574] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts BCH (126, 110), that is, the code word bit length N=126, the information bit length K=110, and the check bit length P=16. The 110 information bits of each inner code word come from 11 symbols of 11 different outer code RS code words.

[0575] The 32 codewords after inner code encoding are divided into 4 codeword sets, each of which contains m = 8 BCH (126, 110) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 8 BCH (126, 110) codewords in each codeword set can obtain 126 DP-16QAM symbols.

[0576] The above 8 BCH (126, 110) codewords with a total of 1008 bits are represented by a first matrix H1 with 8 rows and 126 columns, where each row of the first matrix H1 includes 126 bits of an inner code BCH (126, 110) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 126 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0577]

[0578] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -100<Δ<100, and a non-zero integer Δ is a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100.

[0579] The third matrix H3 with 8 rows and 126 columns has 8 bits per column. r =4,L c =2. A total of 8 bits in 2 columns in every 4 rows are mapped to a DP-16QAM symbol. The 2 modulation symbols obtained by mapping every 2 columns in the third matrix H3 are used as 2 consecutive modulation symbols in the first modulation symbol stream, and the 126 modulation symbols obtained by mapping 126 columns are used as 126 consecutive modulation symbols in the first modulation symbol stream, as 126 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0580] Every 8 codewords in the above 32 codewords are mapped to 126 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0581] Embodiment 15: The target bit set is represented by a bit matrix, n=16, m=16, K=120, L=8.

[0582] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 16 second data streams. The inner code encoding adopts BCH (136, 120), that is, the code word bit length N=136, the information bit length K=120, and the check bit length P=16. The 120 information bits of each inner code word come from 12 symbols of 12 different outer code RS code words.

[0583] The 16 codewords after the inner code encoding are used as h = 1 codeword set, which contains m = 16 BCH (136, 120) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 272 DP-16QAM symbols can be obtained from the 16 BCH (136, 120) codewords in each codeword set.

[0584] The above 16 BCH (136, 120) codewords with a total of 2176 bits are represented by a first matrix H1 with 16 rows and 136 columns, where each row of the first matrix H1 includes 136 bits of an inner code BCH (136, 120) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 16 rows and 136 columns, and its interleaving correspondence is: for 0≤i<16, there is

[0585]

[0586] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -120<Δ<120, a non-zero integer θ is a column offset constraint factor, and a non-zero integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110. A typical value of the integer θ is θ=7, and another typical value is θ=1.

[0587] The third matrix H3 with 16 rows and 136 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols respectively. A specific implementation method is that rows 0-7 in each column are mapped to a DP-16QAM symbol, and rows 8-15 are mapped to another DP-16QAM symbol. Each third matrix H3 is mapped to 272 DP-16QAM symbols. The 2 DP-16QAM symbols mapped in each column are used as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 272 DP-16QAM symbols mapped in 136 columns are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0588] In this embodiment, when there is colored noise in the actual transmission and the width is 4 DP-16QAM symbols, 32 error bits can be dispersed to multiple inner codes BCH (136, 120), and the number of error bits corresponding to each inner code is no more than 2. Considering that the inner code BCH (136, 120) can correct 2 bits, the colored noise of the 2-3 DP-16QAM symbol width can be effectively corrected by the inner code. In addition, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can resist burst errors with a length greater than 1200 bits. That is, by adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits. By adopting the designed bit interleaving and mapping method, the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0589] Embodiment 16: The target bit set is represented as an array, n=16, m=16, K=120, L=8.

[0590] Based on the scheme of Example 15, 16 BCH (136, 120) codewords with a total of 2176 bits are represented by a first matrix H1 with 16 rows and 136 columns. The data obtained after bit interleaving is not represented by the third matrix H3 with 16 rows and 136 columns as shown in Example 1, but by an array A with a length of 2176 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2176 bits, and its interleaving correspondence is: for 0≤i<16, there is

[0591]

[0592] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -120<Δ<120, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110. A typical value of the integer θ is θ=7, and another typical value is θ=1. In particular, for 0≤i<16, there is

[0593]

[0594] By mapping every 8 consecutive bits in the first array A containing 2176 bits to a DP-16QAM symbol, 272 DP-16QAM symbols can be obtained as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0595] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0596] Embodiment 17: The target bit set is represented by a bit matrix, n=16, m=8, K=120, L=8, L r =4,L c =2.

[0597] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 16 second data streams. The inner code encoding adopts BCH (136, 120), that is, the code word bit length N=136, the information bit length K=120, and the check bit length P=16. The 120 information bits of each inner code word come from 12 symbols of 12 different outer code RS code words.

[0598] The 16 codewords after inner code encoding are divided into 2 codeword sets, each codeword set contains m = 8 BCH (126, 110) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 8 BCH (136, 120) codewords in each codeword set can obtain 136 DP-16QAM symbols.

[0599] The above 8 BCH (136, 120) codewords with a total of 1088 bits are represented by a first matrix H1 with 8 rows and 136 columns, where each row of the first matrix H1 includes 136 bits of an inner code BCH (136, 120) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 8 rows and 136 columns, and its interleaving correspondence is: for 0≤i<8, there is

[0600]

[0601] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<120, and an integer is a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110.

[0602] The third matrix H3 with 8 rows and 136 columns has 8 bits per column. r =4,L c =2. A total of 8 bits in 2 columns in every 4 rows are mapped to a DP-16QAM symbol. The 2 modulation symbols obtained by mapping every 2 columns in the third matrix H3 are used as 2 consecutive modulation symbols in the first modulation symbol stream, and the 136 modulation symbols obtained by mapping 136 columns are used as 136 consecutive modulation symbols in the first modulation symbol stream, as 136 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0603] Every 8 codewords in the above 16 codewords are mapped to 136 DP-16QAM symbols after bit interleaving. The 16 codewords are mapped to a total of 272 DP-16QAM symbols after bit interleaving, which are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0604] Embodiment 18: The target bit set is represented by a bit matrix, n=12, m=12, K=160, L=8, L r =4,L c =2.

[0605] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=12 first data streams. The 12 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 12 second data streams. The inner code encoding adopts BCH (176, 160), that is, the code word bit length N=176, the information bit length K=160, and the check bit length P=16. The 160 information bits of each inner code codeword come from 16 symbols of 16 different outer code RS codewords.

[0606] The 12 codewords after inner code encoding are used as a codeword set, which contains m = 12 BCH (176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, 264 DP-16QAM symbols can be obtained from the 12 BCH (176, 160) codewords in each codeword set.

[0607] The above 12 BCH (176, 160) codewords with a total of 2112 bits are represented by a first matrix H1 with 12 rows and 176 columns, where each row of the first matrix H1 includes 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit interleaved to obtain a third matrix H3 with 12 rows and 176 columns, and its interleaving correspondence is: for 0≤i<12, there is

[0608]

[0609] in, represents a round-down operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0<Δ<160, and an integer is a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, 150.

[0610] The third matrix H3 with 12 rows and 176 columns contains 8 bits per column. r =4,L c =2. A total of 8 bits in 2 columns in every 4 rows are mapped to a DP-16QAM symbol. The 3 modulation symbols obtained by mapping every 2 columns in the third matrix H3 are used as 3 consecutive modulation symbols in the first modulation symbol stream, and the 264 modulation symbols obtained by mapping 176 columns are used as 264 consecutive DP-16QAM modulation symbols in the first modulation symbol stream.

[0611] It should be noted that the above embodiments are all for Figure 3The operation steps in the data processing method shown are introduced. In practical applications, Figure 2 The operations performed by the sending end processing module 02 include but are not limited to: Figure 3 The data processing method shown is described below with reference to some specific implementation methods to introduce other operations performed by the sending end processing module 02.

[0612] Implementation method 1: Operation process of applying the transmitting end processing module to the 1×800G interface scenario.

[0613] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n first data streams, where n is an integer greater than 1. The above-mentioned first data processing may include alignment lock, lane de-skew processing, lane reorder processing, or concatenated interleaving processing. This embodiment provides specific details of the first data processing.

[0614] FIG12(a) is a schematic diagram of the first operation flow of the transmitting end processing module in the embodiment of the present application. As shown in FIG12(a), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, multiple channel data streams encoded with an outer code can be obtained, and alignment markers are used to perform alignment lock and lane de-skew to obtain aligned multiple channel data streams. Then, the data of multiple channels are subjected to lane reordering according to the alignment marker, so that the data of multiple channels can be arranged in a specified order. The channel data streams after channel reordering are sent to the cascade interleaver to scramble the data order to obtain n first data streams, and are respectively sent to the inner code encoder for inner code encoding. After the data streams encoded with the inner code are subjected to the designed bit interleaving and mapping to obtain modulation symbols, the data are processed and then sent to the channel transmission medium for transmission. The data processing may include polarization distribution or DSP framing, etc. Here n is a positive integer greater than 1.

[0615] It should be noted that the lane de-skew and lane reorder in Figure 12(a) are both optional. Figure 12(b) is a schematic diagram of the second operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(b), the channel data stream after alignment lock does not undergo channel de-skew processing and is directly sent to channel reordering. Figure 12(c) is a schematic diagram of the third operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(c), the channel data stream after alignment lock undergoes channel de-skew processing and is directly sent to cascade interleaving without channel reordering. Figure 12(d) is a schematic diagram of the fourth operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(d), the channel data stream after alignment lock does not undergo channel de-skew processing or channel reordering and is directly sent to cascade interleaving. It should be noted that, as shown in the flow of the transmitting end processing module in FIG. 12(b) and FIG. 12(d), the channel data stream after alignment lock does not undergo channel de-skew processing, and the data in each channel data stream is required to be aligned based on the outer code symbol. More specifically, taking KP4 as an example for outer code encoding, the number of deviation bits between any two channel data streams is a multiple of 10, that is, the data in the channel data stream is aligned based on the KP4 RS symbol.

[0616] Fig.13 This is a schematic diagram of a 1×800G interface scenario in an embodiment of the present application. Fig.13 As shown, the transmitting device uses a schematic diagram of 32 physical coding sublayer (PCS) channel data streams of a 1×800G interface. The transmitting device performs KP4 RS (544,514) code encoding on the 1-channel 800GbE service data stream to be transmitted to obtain 32 PCS lane data streams. In PCS lane data streams 0-15, each data stream is separated by 68 symbols, totaling 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS lane data stream come from different RS code words, and the two symbols at the same position of two adjacent PCS lane data streams come from different RS code words. Similarly, in PCS lane data streams 16-31, each data stream is separated by 68 symbols, totaling 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS channel data stream come from different RS code words, and the two symbols at the same position of two adjacent PCS channel data streams come from different RS code words. After being processed by the PMA, the 32 PCS channel data streams are sent to the transmitting end processing module through the connection unit interface 800GAUI-8.

[0617] Based on the data processing diagram of the transmitting processing module shown in FIG12(a) above, the transmitting processing module uses the known alignment marker of the PCS channel to perform alignment lock on the channel data stream. The known alignment markers of the 32 channels here are different (see Ethernet Technology Consortium 800G Specification). The transmitting processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. The 32 channel data are then lane reordered according to the alignment marker so that the 32 channel data can be arranged in a specified order. One order is to follow Fig.13 The same channel data stream is sorted from top to bottom from 0 to 31. The 32 PCS channel data streams after channel reordering are sent to the cascade interleaver to scramble the data order to obtain n first data streams, and are sent to the inner code encoder for inner code encoding. The n second data streams after inner code encoding are subjected to the designed bit interleaving and mapping, and then data processing is performed and sent to the channel transmission medium for transmission. It should be noted that the value of n here can be equal to 32 or 16.

[0618] It should be noted that the operation flow of the transmitting end processing module can also be as shown in Figure 12(b), where the channel data stream after identification locking does not undergo channel de-skew processing and is directly sent to the channel for reordering. In this case, the delay of the overall cascade FEC solution can be reduced, but its ability to resist burst errors will be weakened. Whether to perform channel de-skew processing in the transmitting end processing module can be determined according to the actual transmission scenario.

[0619] Implementation method 2: Operational process of applying the transmitting end processing module to a 2×400G interface scenario.

[0620] Fig.14 This is a schematic diagram of a 2×400G interface scenario in an embodiment of the present application. Fig.14As shown in the figure, the transmitting device uses a schematic diagram of 32 PCS channel data streams of the 2×400G interface. The transmitting device encodes the 2 400GbE service data streams to be transmitted with KP4 RS (544,514) outer code to obtain 2 channels of 32 PCS channel data streams in total, each of which includes 16 PCS channel data streams. Each data stream in PCS channel data streams 0-15 or PCS channel data streams 16-31 is separated by 68 symbols, totaling 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS channel data stream come from different RS code words, and the two symbols at the same position of the two adjacent PCS channel data streams come from different RS code words. After being processed by the PMA, the 32 PCS channel data streams are sent to the transmitting processing module through the connection unit interface 2×400GAUI-4.

[0621] Based on the data processing schematic diagram of the transmitting end processing module shown in FIG. 12 (a) above, the transmitting end processing module uses the known alignment markers of PCS lanes 0-15 or PCS lanes 16-31 to perform alignment lock on the 16-channel data streams. Here, PCS lanes 0-15 can be considered as PCS lanes 0-15 in the 0th 400G, and PCS lanes 16-31 can be considered as PCS lanes 0-15 in the 1st 400G. The known alignment markers of the 16 lanes in the 0th 400G are the same as the known alignment markers of the 16 lanes in the 1st lane. The transmitting end processing module then performs lane de-skew processing on the 32-channel data streams to obtain aligned 32-channel data streams. Then, according to the alignment markers of PCS lanes 0-15 or PCS lanes 16-31, the data of the 16 lanes are lane reordered so that the data of the 16 lanes can be arranged in a specified order. Finally, the data of the 32 lanes can be arranged in a specified order. One order is to follow Fig.14 The same channel data stream is sorted from top to bottom from 0 to 31. The 32 PCS channel data streams after channel reordering are sent to the cascade interleaver to scramble the data order to obtain n first data streams, and are sent to the inner code encoder for inner code encoding. The n second data streams after inner code encoding are subjected to the designed bit interleaving and mapping, and then data processing is performed and sent to the channel transmission medium for transmission. It should be noted that the value of n here can be equal to 32 or 16.

[0622] It should be noted that the operation flow of the transmitting processing module can also be as shown in Figure 12(b), where the channel data stream after identification and locking does not undergo channel de-skew processing and is directly sent to the channel reordering. Furthermore, considering that the client-side interface is 2-way 400G, the RS symbols in any of the channel data streams 0-15 and the RS symbols in any of the channel data streams 16-31 sent to the convolutional interleaving come from two different RS outer code words. In this 2×400G interface scenario, the transmitting processing module can also adopt the operation flow as shown in Figure 12(c) or Figure 12(d) without performing the channel reordering operation. In this case, the latency of the overall cascade FEC solution can be reduced, but its ability to combat burst errors will be weakened. Whether to perform channel de-skew processing and channel reordering in the transmitting processing module can be determined based on the actual transmission scenario.

[0623] Implementation method 3: Operation flow of applying the transmitting end processing module to another 1×800G interface scenario.

[0624] Fig.15 FIG. 1 is another schematic diagram of a 1×800G interface scenario in an embodiment of the present application. Fig.15 As shown, the transmitting device uses a schematic diagram of 8 channel data streams of a 1×800G interface. The transmitting device performs KP4 RS (544,514) code outer code encoding on the 1-channel 800GbE service data stream to be transmitted to obtain 8 channel data streams. Each data stream in channel data streams 0-8 is separated by 136 symbols, totaling 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each channel data stream come from different RS code words, and the two symbols at the same position of two adjacent channel data streams come from different RS code words. After being processed by the PMA, the 8 channel data streams are sent to the transmitting end processing module through the connection unit interface 800GAUI-8. It should be noted that in some specific implementations, the above 8 channel data streams are called 8 PCS channel data streams; in other specific implementations, the above 8 channel data streams are called 8 FEC channel data streams. No specific limitation is made here.

[0625] Based on the data processing diagram of the transmitting end processing module shown in FIG12(a) above, the transmitting end processing module uses the known alignment marker of the channel to perform alignment lock on the channel data stream. Here, the known alignment markers of the 8 channels are different. The transmitting end processing module then performs lane de-skew processing on the 8 channel data streams to obtain 8 aligned channel data streams. Then, the data of the 8 channels is reordered according to the alignment marker so that the data of the 8 channels can be arranged in a specified order. One order is to follow Fig.15The same channel data stream is sorted from top to bottom from 0 to 7. The 8 channel data streams after channel reordering are sent to the cascade interleaver to scramble the data order to obtain n first data streams, and are sent to the inner code encoder for inner code encoding. The n second data streams after inner code encoding are subjected to the designed bit interleaving and mapping, and then data processing is performed and sent to the channel transmission medium for transmission. Usually, the value of n here is 8.

[0626] It should be noted that the operation flow of the transmitting end processing module can also be as shown in Figure 12(b), where the channel data stream after identification and locking does not undergo channel de-skew processing and is directly sent to channel reordering. The transmitting end processing module can also adopt the operation flow as shown in Figure 12(c) or Figure 12(d) without performing channel reordering. In this case, the delay of the overall cascade FEC solution can be reduced, but its ability to resist burst errors will be weakened. Whether to perform channel de-skew processing and channel reordering in the transmitting end processing module can be determined according to the actual transmission scenario.

[0627] Implementation method 4: An operation flow of applying the transmitting end processing module to cascade interleaving in a 1×800G or 2×400G interface scenario.

[0628] Based on the above implementation 1 or 2, this embodiment provides a specific implementation of a cascade interleaver, which shuffles the data order of 32 PCS channel data streams after channel reordering to obtain n=32 first data streams. The specific structure of the cascade interleaver is introduced below.

[0629] Fig.16 This is a first schematic diagram of cascade interleaving in the embodiment of the present application. Fig.16 As shown, 4 outer code RS symbols are obtained from each of the 32 PCS channel data streams, for a total of 128 symbols, each of which contains 10 bits. The 128 RS symbols before channel permutation can be represented by a matrix of 32 rows and 4 columns, and the 4 symbols in the rth row come from PCS channel data stream r. The 128 RS symbols after permutation can also be represented by a matrix of 32 rows and 4 columns. Among the 32 rows and 4 columns of symbols after channel permutation, the symbol in the 0th column and the rth row (0≤r<32) comes from the symbol in the 0th column and the rth row before channel permutation, the symbol in the 1st column and the rth row comes from the symbol in the 1st column and the rth row before channel permutation; the symbol in the 2nd column and the rth row The sign of the row comes from the 2nd column before channel permutation. The symbol of the row, column 2 The sign of the row comes from the 2nd column before channel permutation. The symbol of the row; the 3rd column The sign of the row comes from the 3rd column before channel permutation. The symbol of the row, column 3 The sign of the row comes from the 3rd column before channel permutation. Line symbol.

[0630] Fig.16 As shown in FIG. 1 , a total of 128 RS symbols in 32 rows and 4 columns are subjected to channel permutation to obtain 128 RS symbols after 32 rows and 4 columns permutation. The channel permutation relationship can be expressed by a formula. The 128 RS symbols in 32 rows and 4 columns after permutation, the symbol in the r0th row and c0th column comes from the symbol in the 128 RS symbols in 32 rows and 4 columns before permutation. The 32 data streams after channel permutation are sent to the convolution interleaver to interleave and disrupt the data order.

[0631] Fig.17 Schematic diagram of the first structure of the convolution interleaver in the embodiment of the present application. Fig.17 As shown, the convolution interleaver used in this embodiment includes 4 delay lines. These 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 4 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 12Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 4Q symbols, and the delay value of delay line 3 is 0 symbols, that is, no delay. Fig.17 C shown r () represents an RS symbol in the data stream r90≤r<32) after channel permutation. For example, C r (16t), C r (16t+1), C r (16t+2), C r (16t+3) represents the 4 RS symbols currently input to delay line 0 in channel data stream r and C r (16t-48Q), C r (16t-48Q+1), C r (16t-48Q+2), C r (16t-48Q+3) are the 4 RS symbols output by delay line 0; C r (16t+4), C r (16t+5), C r (16t+6), C r (16t+7) represents the next 4 RS symbols input to delay line 1 in the channel data stream and C r (16t-32Q+4), C r (16t-32Q+5), C r (16t-32Q+6), C r(16t-32Q+7) are the 4 RS symbols output by delay line 1; C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) indicates that the next 4 RS symbols in the channel data stream are input to delay line 2 and C r (16t-16Q+8), C r (16t-16Q+9), C r (16t-16Q+10), C r (16t-16Q+11) are the 4 RS symbols output by delay line 2; C r (16t+12), C r (16t+13), C r (16t+14), C r (16t+15) represents the 4 RS symbols in the channel data stream that are subsequently input to delay line 3 and C r (16t+12), C r (16t+13), C r (16t+14), C r (16t+15) are the 4 RS symbols output by delay line 3. When 16Q+4≥68, i.e., Q≥4, the C output by convolution interleaving is r (16t-48Q), C r (16t-48Q+1), C r (16t-48Q+2), C r (16t-48Q+3), C r (16t-32Q+4),

[0632] C r (16t-32Q+5), C r (16t-32Q+6), C r (16t-32Q+7), C r (16t-16Q+8), C r (16t-16Q+9),

[0633] C r (16t-16Q+10), C r (16t-16Q+11), C r (16t+12), C r (16t+13), C r (16t+14), C r(16t+15) A total of 16 RS symbols come from 16 different RS code words. In this embodiment, Q=4 is used, the delay value of delay line 0 is 48 RS symbols (i.e., 480-bit delay), the delay value of delay line 1 is 32 RS symbols (i.e., 320-bit delay), the delay value of delay line 2 is 16 RS symbols (i.e., 160-bit delay), and the delay value of delay line 3 is 0, i.e., no delay.

[0634] Implementation method 5: The transmitting end processing module is applied to another operation flow of cascade interleaving in a 1×800G or 2×400G interface scenario.

[0635] Based on the above implementation 1 or 2, this embodiment provides another specific implementation of the cascade interleaver, which shuffles the data order of the 32 PCS channel data streams after channel reordering to obtain n=16 first data streams. The specific structure of the cascade interleaver is introduced below.

[0636] Fig.18 This is a second schematic diagram of cascade interleaving in the embodiment of the present application. Fig.18 As shown, 32 PCS channel data streams are respectively subjected to convolution interleaving processing to obtain 32 third data streams, and then 32 third data streams are multiplexed every 2 to obtain 1 first data stream, so that 16 first data streams are obtained in total.

[0637] Fig.19 Schematic diagram of the second structure of the convolution interleaver in the embodiment of the present application. Fig.19 As shown, the convolution interleaver used in this embodiment includes 4 delay lines. These 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, that is, no delay. As shown in FIG. Fig.19 C shown r () represents an RS symbol in the channel data stream r (0≤r<32). For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (8t-24Q), C r (8t-24Q+1) are the two RS symbols output by delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and Cr (8t-16Q+2), C r (8t-16Q+3) are the two RS symbols output by delay line 1; C r (8t+4), C r (8t+5) indicates that the next two RS symbols in the channel data stream are input to delay line 2 and C r (8t-8Q+4), C r (8t-8Q+5) are the two RS symbols output by delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols in the channel data stream that are subsequently input to delay line 3 and C r (8t+6), C r (8t+7) are the two RS symbols output by delay line 3. When 8Q+2≥68, i.e., Q≥9, the convolution interleaving output C r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+60, C r (8t+7) A total of 8 RS symbols come from 8 different RS code words. In this embodiment, Q=9 is used, the delay value of delay line 0 is 54 RS symbols (i.e., 540-bit delay), the delay value of delay line 1 is 36 RS symbols (i.e., 360-bit delay), the delay value of delay line 2 is 18 RS symbols (i.e., 180-bit delay), and the delay value of delay line 3 is 0, i.e., no delay.

[0638] After the above convolution interleaving process, 32 third data streams are obtained, and every 2 of them are multiplexed to obtain 1 first data stream, so that 16 first data streams are obtained in total. Fig.18 As shown, multiplexing p (0≤p<16) multiplexes 8 consecutive RS symbols in the third data stream p and 8 consecutive RS symbols in the third data stream p+15 into 16 consecutive symbols in the first data stream p. The above 16 consecutive symbols come from 16 RS symbols in 16 different outer code RS code words. A specific implementation method is that the 8 consecutive RS symbols C in the third data stream p are multiplexed into 16 consecutive symbols in the first data stream p. p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) Cp (7) and the 8 consecutive RS symbols C in the third data stream p+16 p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Multiplex into 16 consecutive symbols C in the first data stream p p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) C p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Another specific implementation method is that 8 consecutive RS symbols C in the third data stream p p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) and the 8 consecutive RS symbols C in the third data stream p+16 p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Multiplex into 16 consecutive symbols C in the first data stream p p (0), C p+16 (0), C p (1) C p+16 (1) C p (2) C p+16 (2) C p (3) C p+16 (3) C p (4) Cp+16 (4) C p (5) C p+16 (5) C p (6) C p+16 (6) C p (7) C p+16 (7). Here, for the 16 output symbols C p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) and C p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 The specific order of arrangement of (7) is not limited.

[0639] Implementation method 6: Another operation flow of applying the transmitting end processing module to cascade interleaving in a 1×800G interface scenario.

[0640] Based on the above implementation mode 3, this embodiment provides another specific implementation mode of the cascade interleaver, which shuffles the data order of the 8 channel data streams after channel reordering to obtain n=8 first data streams. The specific structure of the cascade interleaver is introduced below.

[0641] Fig. 20 FIG. 3 is a third schematic diagram of cascade interleaving in the embodiment of the present application. Fig. 20 As shown, 8 channel data streams are respectively subjected to convolution interleaving processing to obtain 8 first data streams.

[0642] Fig.21 FIG. 1 is a schematic diagram of the third structure of the convolution interleaver in the embodiment of the present application. Fig.21As shown, the convolution interleaver used in this embodiment includes 6 delay lines. The 6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 10Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 6Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 2Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay. As shown Fig.21 C shown r () represents an RS symbol in the data stream r (0≤r<8) after channel permutation. For example, C r (12t), C r (12t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (12t-60Q), C r (12t-60Q+1) are the two RS symbols output by delay line 0; C r (12t+2), C r (12t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (12t-48Q+2), C r (12t-48Q+30 is the 2 RS symbols output by delay line 1; and so on, C r (12t+10), C r (12t+11) indicates the next two RS symbols input to delay line 2 in the channel data stream and C r (12t+100, C r (12t+110 is the 2 RS symbols output by delay line 2. When 12Q+2≥68, i.e. Q≥6, the output C r (12t-60Q0, C r (12t-60Q+10, C r (12t-48Q+20,

[0643] C r (12t-48Q+3), C r (12t-36Q+4), C r (12t-36Q+5), C r (12t-24Q+6), C r (12t-24Q+7),

[0644] C r (12t-12Q+8), Cr (12t-12Q+9), C r (12t+10), C r (12t+11) A total of 12 RS symbols come from 12 different RS code words. In this embodiment, Q=6 is used, the delay value of delay line 0 is 60 RS symbols (i.e., 600-bit delay), the delay value of delay line 1 is 48 RS symbols (i.e., 480-bit delay), the delay value of delay line 2 is 36 RS symbols (i.e., 360-bit delay), the delay value of delay line 3 is 24 RS symbols (i.e., 240-bit delay), the delay value of delay line 4 is 12 RS symbols (i.e., 120-bit delay), and the delay value of delay line 5 is 0, i.e., no delay.

[0645] Implementation method 7: The transmitting end processing module is applied to another operation flow of cascade interleaving in a 1×800G or 2×400G interface scenario.

[0646] Based on the above-mentioned implementation mode 4, this embodiment provides another structural schematic diagram of a convolutional interleaver. Fig. 22 FIG. 4 is a schematic diagram of the fourth structure of the convolution interleaver in the embodiment of the present application. Fig. 22 As shown, the convolution interleaver used in this embodiment includes three delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 4 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 8Q symbols, the delay value of delay line 1 is 4Q symbols, and the delay value of delay line 2 is 0 symbols, that is, no delay. Fig. 22 C shown r () represents an RS symbol in the data stream r (0≤r<32) after channel permutation. For example, C r (16t), C r (16t+1), C r (16t+2), C r (16t+3) represents the 4 RS symbols currently input to delay line 0 in channel data stream r and C r (16t-24Q), C r (16t-24Q+1), C r (16t-24Q+2), C r (16t-24Q+3) are the 4 RS symbols output by delay line 0; C r (16t+4), C r (16t+5), C r (16t+6), C r (16t+7) represents the next 4 RS symbols input to delay line 1 in the channel data stream and Cr (16t-12Q+4), C r (16t-12Q+5), C r (16t-12Q+6), C r (16t-12Q+7) are the 4 RS symbols output by delay line 1; C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) indicates that the next 4 RS symbols in the channel data stream are input to delay line 2 and C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) are the 4 RS symbols output by delay line 2. When 12Q+4≥68, i.e., Q≥6, the C output by the convolution interleaving r (16t-24Q), C r (16t-24Q+1), C r (16t-24Q+2), C r (16t-24Q+3), C r (16t-12Q+4),

[0647] C r (16t-12Q+5), C r (16t-12Q+6), C r (16t-12Q+7), C r (16t+8), C r (16t+9), C r (16t+10),

[0648] C r (16t+11) A total of 12 RS symbols come from 12 different RS code words. In this embodiment, Q=6 is used, the delay value of delay line 0 is 48 RS symbols (i.e., 480-bit delay), the delay value of delay line 1 is 24 RS symbols (i.e., 240-bit delay), and the delay value of delay line 2 is 0, i.e., no delay.

[0649] Implementation method 8: Another operation flow of applying the transmitting end processing module to cascade interleaving in a 1×800G or 2×400G interface scenario.

[0650] Based on the above implementation mode 5, this embodiment provides another structural diagram of a convolutional interleaver. Fig.23 Schematic diagram of the fifth structure of the convolution interleaver in the embodiment of the present application. Fig.23As shown, the convolution interleaver used in this embodiment includes three delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, that is, no delay. Fig.23 C shown r () represents an RS symbol in the channel data stream r (0≤r<32). For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (6t-12Q), C r (6t-12Q+1) are the two RS symbols output by delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (6t-6Q+2), C r (6t-6Q+3) are the two RS symbols output by delay line 1; C r (6t+4), C r (6t+5) indicates that the next two RS symbols in the channel data stream are input to delay line 2 and C r (6t+4), C r (6t+5) are the two RS symbols output by delay line 2; when 6Q+2≥68, i.e., Q≥11, the convolution interleaving output C r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r (6t+5) A total of 6 RS symbols come from 6 different RS code words. In this embodiment, Q=11 is used, the delay value of delay line 0 is 44 RS symbols (i.e., 440-bit delay), the delay value of delay line 1 is 22 RS symbols (i.e., 220-bit delay), and the delay value of delay line 2 is 0, i.e., no delay.

[0651] After the above convolution interleaving process, 32 third data streams are obtained, and every 2 of them are multiplexed to obtain 1 first data stream, so that 16 first data streams are obtained in total. Fig.18As shown, multiplexing p (0≤p<16) multiplexes 6 consecutive RS symbols in the third data stream p and 6 consecutive RS symbols in the third data stream p+15 into 12 consecutive symbols in the first data stream p. The above 12 consecutive symbols come from 12 RS symbols in 12 different outer code RS code words.

[0652] It should be noted that, in some practical applications, different bit interleaving and mapping methods can be selected according to different transmission scenarios. Fig.24 This is a schematic diagram of a data processing flow in an embodiment of the present application. Fig.24 As shown, V types of bit interleaving and mapping processing modules are provided, where V is an integer greater than 1. The V types of bit interleaving and mapping processing modules shown have different anti-burst capabilities. In a specific application, n first data streams are encoded by inner code to obtain n second data streams, and one of the bit interleaving and mapping processing modules is selected according to the actual transmission scenario to bit interleave and map the data in the second data stream to obtain multiple modulation symbols. It should be understood that Fig.24 The internal code encoding module in is used to perform Figure 3 In step 301 of the illustrated embodiment, Fig.24 Each bit interleaving and mapping processing module is used to perform Figure 3 The specific implementation of steps 302 and 303 in the illustrated embodiment will not be repeated here. As an example, the above-mentioned embodiments 1-11 provide a total of 11 different bit interleaving and mapping methods. Fig.24 11 bit interleaving and mapping processing modules can be provided accordingly, so that the required bit interleaving and mapping processing modules can be selected according to the actual transmission scenario to implement the bit interleaving and mapping method in the corresponding embodiment.

[0653] The above introduces the data processing method provided in the embodiment of the present application. The following introduces the data processing device provided in the embodiment of the present application.

[0654] Fig.25 FIG. 1 is a schematic diagram of a structure of a data processing device in an embodiment of the present application. Fig.25 As shown, the data processing device includes a coding module 101, a bit interleaving module 102 and a bit mapping module 103. The coding module 101 is used to perform the above Figure 3 The operation of step 301 in the data processing method shown in FIG. 1 is performed by the bit interleaving module 102. Figure 3 The operation of step 302 in the data processing method shown in FIG. 1 is performed by the bit mapping module 103. Figure 3 The operation of step 303 in the data processing method shown in the figure can be specifically referred to the relevant introduction in the above data processing method, which will not be repeated here.

[0655] It should be understood that the device provided in the present application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system. In addition, each functional unit in each embodiment of the present application can be integrated in a processing unit, or it can be each independent physical unit, or two or more functional units can be integrated in a processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0656] It should be noted that Figure 3 In the data processing method, the n inner code words come from n second data streams, wherein an inner code word is obtained from each second data stream, and then the n inner code words are bit interleaved. In some specific applications, multiple inner code words can also be obtained from each data stream and bit interleaved. Fig.26 Another flow chart of the data processing method provided in the embodiment of the present application. It should be understood that the method is a data processing performed on the data stream after being encoded by the outer code, which can be specifically implemented by the above-mentioned sending end processing module 02.

[0657] 401. Perform interleaving coding on each n1 first data streams among the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, where n2=n0 / n1, and n1 is an integer greater than 0.

[0658] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0 first data streams, where n0 is an integer greater than 1. The above-mentioned first data processing may include alignment lock, lane de-skew processing or lane alignment processing, lane reorder processing, or symbol mux processing, etc. The above-mentioned n0 first data streams are all data streams encoded by outer code. For example, the outer code encoding can adopt RS code, and the n data streams after outer code encoding can include multiple RS code words. For example, the outer code is the adopted KP4 RS (544,514) code, the code length is 544 symbols, and one outer code symbol contains 10 bits.

[0659] The following describes the specific operation of performing interleaving coding on the n1 first data streams to obtain a second data stream. The interleaving coding process includes operations such as inner code coding, cyclic shift, and polling readout.

[0660] Fig. 27 FIG. 1 is a schematic diagram of a first implementation method of interleaving coding processing. Fig. 27 As shown in (a), the interleaved coding process first performs inner code coding, then performs cyclic shift, and then performs polling reading. It should be understood that each first data stream contains at least a0 first bit sets, each first bit set contains K bits, where the integer a0>1. For the n1 first data streams, a0 first bit sets are obtained from each first data stream, respectively, to obtain a total of m=n1×a0 first bit sets, which contain a total of n1×a0×K bits.

[0661] like Fig. 27 As shown in (b), the inner code encoding performs inner code encoding on each of the first bit sets containing K bits in the m first bit sets, and adds P check bits to obtain an inner code codeword containing N bits, and a total of m inner code codewords are obtained. Here, the first bit set containing K bits can be called an inner code information sequence, and K+P=N. The P check bits are also called a check bit set. One of the inner code codewords contains one of the first bit sets and one of the check bits. That is to say, the m inner code codewords contain m first bit sets and m check bit sets. Usually, K is an integer multiple of 10. It should be noted that in the present application materials, the inner code codeword is also referred to as a codeword.

[0662] It should be noted that convolution interleaving is usually performed before inner code encoding, in order to make the K information bits correspond to more KP4 outer code symbols, such as K / 10 outer code symbols, and make the corresponding outer code symbols come from more outer code code words, so as to achieve better overall cascade FEC performance. For example, K=120, the 120 information bits correspond to 12 KP4 outer code symbols, and come from 12 outer code code words.

[0663] It should be noted that in some scenarios requiring low latency, convolution interleaving is usually not performed before inner code encoding. The K information bits correspond to K / 10 outer code symbols, and the number of outer code words from which the corresponding outer code symbols come is less than K / 10. For example, K=120, the 120 information bits correspond to 12 KP4 outer code symbols, and the 12 KP4 symbols come from 4 outer code words.

[0664] like Fig. 27 As shown in (b), for the information bit sequences of m inner code words, that is, m first bit sets, the cyclic shift cyclically shifts each first bit set to the left. bits or cyclically shifted δ bits to the right to obtain a second bit set containing K bits. Each second bit set is combined with the P-length check bits in its corresponding inner code word to obtain a third bit set containing N bits. It should be noted that the third bit set containing N bits is obtained by cyclically shifting the information bit sequence (first bit set) containing K bits in the inner code codeword and combining it with the check bits containing P bits in the inner code codeword. For the sake of simplicity of description, the present application material simply describes the third bit set containing N bits as being obtained by cyclically shifting the inner code codeword containing N bits.

[0665] Taking the left cyclic shift as an example, for the first bit set (u0,u1,u2,u3,…,u K-2 ,u K-1 ), circular shift to the left bits, and obtain the second bit set containing K bits after shifting Where Y%Z represents the remainder after dividing the integer Y by the integer Z. Usually, the offset constraint factor for the left circular shift is is an integer multiple of 10, and

[0666] Taking the right cyclic shift as an example, for the first bit set (u0,u1,u2,u3,…,u K-2 ,u K-1 ), cyclically shift right by δ bits to obtain the second bit set (u (-δ)％K ,u (1-δ0％K ,u (2-δ)％K ,…,u (K-2-δ)％K ,u (K-1-δ)％K ), where Y%Z represents the remainder after the integer Y is divided by the integer Z. Usually, the offset constraint factor δ of the right cyclic shift is an integer multiple of 10, and 0≤δ<K.

[0667] It should be noted that the first bit set is cyclically shifted to the left bits to obtain the second bit set, which is equivalent to the first bit set being cyclically shifted to the right bits to get the second bit set.

[0668] It should be noted that the offset constraint factor of the left cyclic shift is The offset constraint factor δ of the rightward cyclic shift is not fixed and can be time-varying. Usually, the period of the cyclic shift is p c , the cyclic shift is performed to the left for the first bit set of the i-th group containing K bits bits, or perform a right cyclic shift of δ ibits, where m is an integer p c Integer multiple of , 0≤i<p c Usually m = p c Typically, there are m offset constraint factors (Right now Any two of The values ​​of are not equal; m offset constraint factors δ i (i.e. δ0,δ1,…,δ m-1 ) the values ​​of any two δ are not equal.

[0669] like Fig. 27 As shown in (b), for the m third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and continuously performs m×N / 2 operations to obtain all the bits in the m third bit sets, and obtains a fourth bit set containing m×N bits.

[0670] The said second data stream contains multiple 4th bit sets, the said 1 4th bit set containing m×N bits is obtained by polling and reading out 2 bits of m 3rd bit sets, the said m 3rd bit sets containing N bits are obtained by cyclic shift of m inner code codewords, the said m inner code codewords are obtained by inner code encoding of m 1st bit sets, and the said m 1st bit sets are obtained by obtaining a0 1st bit sets from each 1st data stream in n1 1st data streams, where m=n1×a0.

[0671] It should be noted that the "polling read" polling obtains 2 bits from each of the third bit sets to obtain a fourth bit set containing m×N bits, which is equivalent to the following operations: first, for m second bit sets, polling obtains 2 bits from each of the second bit sets to obtain a total of m×K bits, and then for the check bit sets in the m inner code words, polling obtains 2 bits from each of the check bit sets to obtain a total of m×P bits, and combining the m×K bits obtained from the m second bit sets and the m×P bits obtained from the m check bit sets to obtain a fourth bit set containing m×N bits.

[0672] It should be noted that, in some specific applications, the cyclic shift and the polling read operation can be combined together to implement bit interleaving of the m inner code words containing m×N bits to obtain the fourth bit set in a one-step operation.

[0673] Fig.28 FIG. 2 is a schematic diagram of a second implementation method of interleaving coding processing. Fig.28As shown, the m first bit sets can be represented by a first bit matrix M1 with m rows and K columns, wherein each row in the first bit matrix M1 includes K bits of a first bit set. The bit in the i-th (0≤i<m) row and the e-th (0≤e<K) column in the first bit matrix M1 is denoted as M1[i][e]. The m inner codewords can be represented by an inner code codeword matrix M1 with m rows and N columns. c Represents, where the inner codeword matrix M c Each row in contains N bits of an inner code word. The inner code word matrix M c The bit in the i-th (0≤i<m) row and j-th (0≤j<N) column is denoted as M c [i][j]. The m second bit sets can be represented by a second bit matrix M2 with m rows and K columns, wherein each row in the second bit matrix M2 includes K bits of a second bit set. The bit in the i-th (0≤i<m) row and the e-th (0≤e<K) column of the second bit matrix M2 is denoted as M2[i][e]. The m check bit sets can be represented by a check bit matrix M2 with m rows and P columns. p Represents, where the check bit matrix M p Each row in M ​​contains P check bits of an inner code word. p The bit in the i-th (0≤i<m) row and the f-th (0≤f<P) column is denoted as M p [i][f]. The m third bit sets can be represented by a third bit matrix M3 with m rows and N columns, wherein each row in the third bit matrix M3 includes N bits of a third bit set. The bit in the i-th (0≤i<m)-th row and j-th (0≤j<N)-th column in the third bit matrix M3 is denoted as M3[i][j]. The fourth bit set containing m×N bits is represented by an array A. The k-th (0≤k<m×N)-th bit in the array A is denoted as A[k].

[0674] like Fig.28 As shown, the first bit matrix M1 is encoded by the inner code to obtain the inner code word matrix M c .

[0675] For the cyclic shift operation, take the left cyclic shift as an example, for the inner code word matrix M c The K information bits in the i-th (0≤i<m) row (i.e., the K bits in the i-th row of the first bit matrix M1) are cyclically shifted to the left. bits, and obtain the K bits in the i-th (0≤i<m)th row of the third bit matrix M3, where the non-zero integer is the offset constraint factor of the cyclic shift of the i-th row. At this time, the third bit matrix M3 and the inner codeword matrix M c Satisfy formula (X-1):

[0676]

[0677] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<m. Usually, the offset constraint factor of the left cyclic shift is is an integer multiple of 10, and

[0678] It should be noted that for the K information bits in the i-th row of the first matrix H1, a left cyclic shift is performed. bits, and obtain K bits from column 0 to column K-1 in row i of the second matrix H2. This is equivalent to performing a right cyclic shift on K information bits from column 0 to column K-1 in row i of the first matrix H1. bits, and obtain K bits from the 0th column to the K-1th column in the i-th row of the second matrix H2.

[0679] As another example, using right cyclic shift, the third bit matrix M3 and the inner codeword matrix M c Satisfy formula (X-2):

[0680]

[0681] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<m. Usually, the offset constraint factor δ of the right cyclic shift is i is an integer multiple of 10, and 0≤δ i <K.

[0682] It should be noted that for the inner codeword matrix M c The K information bits in the i-th row are cyclically shifted right by δ i bits, and obtain K bits from the 0th column to the K-1th column in the i-th row of the third bit matrix M3. This is equivalent to performing a left cyclic shift of δ on the K information bits from the 0th column to the K-1th column in the i-th row of the third bit matrix M3. i bits, and the inner code word matrix M is obtained c K bits from column 0 to column K-1 in row i. In other words, formula (X-2) can also be written as formula (X-3):

[0683]

[0684] The inner code word matrix M c The third bit matrix M3 is obtained by performing a cyclic shift on each row of information bits.

[0685] like Fig.28As shown, the "polling read" polling reads 2 bits from each row of the third bit matrix M3, obtains 2 columns in the third bit matrix M3 for m consecutive times, and reads all m×N bits for a total of m×N / 2 operations to obtain the array A containing m×N interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the i-th row and j-th column in the array A. bits, which satisfies formula (X-4):

[0686]

[0687] Among them, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0688] It should be noted that the operation of polling and reading 2 bits per row from the third bit matrix M3 is called m-way codeword interleaving.

[0689] The above codeword matrix M c Each row of information bits is cyclically shifted to obtain the third bit matrix M3, and then 2 bits are read out of each row by polling. This is implemented in two steps. It can also be implemented in one step. The following directly gives M c A direct correspondence.

[0690] If left circular shift is used, combining formula (X-1) and formula (X-4), the following formula (X-5) is obtained:

[0691]

[0692] Where 0≤i<m. Usually, the cyclic shift constraint factor is an integer multiple of 10 and Typically, there are m offset constraint factors (Right now Any two of The values ​​are not equal.

[0693] If right circular shift is used, combining formula (X-2) and formula (X-4), the following formula (X-6) is obtained:

[0694]

[0695] Where 0≤i<m. Usually, the cyclic shift constraint factor δ i is an integer multiple of 10 and Typically, there are m offset constraint factors δ i (i.e. δ0,δ1,…,δ m-1 ) the values ​​of any two δ are not equal.

[0696] It should be noted that the cyclic shift and polling readout are performed in one step, which has the advantages of simple implementation and low complexity.

[0697] It should be noted that the interleaving coding process performs cyclic shift and inner code coding in parallel, and then performs polling reading. This implementation mode is introduced below.

[0698] Fig.29 FIG. 4 is a schematic diagram of a third implementation method of interleaving coding processing. Fig.29 As shown, for the n1 first data streams, a0 first bit sets are obtained from each first data stream, to obtain a total of m=n1×a0 first bit sets, which contain a total of n1×a0×K bits.

[0699] like Fig.29 As shown in (b), the cyclic shift cyclically shifts the i-th first bit set among the m first bit sets to the left. bits or cyclic shift to the right δ i bits to obtain the i-th second bit set containing K bits, and a total of m second bit sets are obtained, 0≤i<m. Usually, the offset constraint factor of the left cyclic shift is is an integer multiple of 10, and The offset constraint factor δ for the right circular shift i is an integer multiple of 10, and 0≤δ i <K. Typically, m offset constraint factors (Right now Any two of The values ​​of are not equal; m offset constraint factors δ i (i.e. δ0,δ1,…,δ m-1 ) the values ​​of any two δ are not equal.

[0700] The inner code encoding performs inner code encoding on each of the m first bit sets containing K bits to obtain a check bit set containing P bits, and a total of m check bit sets are obtained. The "polling readout" first polls for m second bit sets, obtains 2 bits from each of the second bit sets, and obtains a total of m×K bits, and then polls for m check bit sets, obtains 2 bits from each of the check bit sets, and obtains a total of m×P bits. The m×K bits obtained from the m second bit sets and the m×P bits obtained from the m check bit sets obtain a fourth bit set containing m×N bits.

[0701] Fig.30 FIG. 4 is a schematic diagram of a fourth implementation method of interleaving coding processing. Fig.30As shown, m first bit sets can be represented by a first bit matrix M1 with m rows and k columns, and m second bit sets can be represented by a second bit matrix M2 with m rows and k columns. Specifically, the first bit matrix M1 is cyclically shifted to obtain the second bit matrix M2.

[0702] Taking the left cyclic shift as an example, the first bit matrix M1 and the second bit matrix M2 satisfy formula (X-7):

[0703]

[0704] Where Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor of the left cyclic shift is is an integer multiple of 10, and

[0705] It should be noted that for the K bits in the i-th row of the first bit matrix M1, a left cyclic shift is performed. bits, and obtain the K bits in the i-th row of the second bit matrix M2. This is equivalent to cyclically shifting the K bits in the i-th row of the first bit matrix M1 to the right. bits, and obtain the K bits in the i-th row in the second bit matrix M2.

[0706] As another example, the position change adopts right cyclic shift, and the i-th first bit set among the m first bit sets is cyclically shifted right by δ i bits, where the non-zero integer δ i is the cyclic shift offset constraint factor corresponding to the i-th bit set. The right cyclic shift satisfies formula (X-8):

[0707] M2[i][j]=M1[i][(j-δ i )% K]

[0708] Where Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor δ of the right cyclic shift is i is an integer multiple of 10, and 0≤δ i <K.

[0709] It should be noted that for the K bits in the i-th row of the first bit matrix M1, a rightward cyclic shift of δ is performed. i bits, and obtain the K bits of the i-th row of the second bit matrix M2. This is equivalent to performing a left cyclic shift of δ on the K bits of the i-th row of the second bit matrix M2. i bits to obtain the K bits of the ith row of the first bit matrix M1. In other words, formula (X-8) can also be written as formula (X-9):

[0710] M1[i][j]=M2[i][(j+δ i )% K]

[0711] Among them, 0≤i<m, 0≤j<K.

[0712] like Fig.30 As shown, the first bit matrix M1 is encoded by the inner code to obtain the check bit matrix M p . 2 bits are read out from each row of the second bit matrix M2 by polling, and all m×K bits of the second bit matrix M2 are read through m×K / 2 operations in total, to obtain the 0th to m×K-1th bits in the array A containing m×N interleaved bits. p Each row in the polling reads out 2 bits, a total of m×P / 2 operations to read the check bit matrix M p All m×P bits are obtained, and the m×Kth to m×N-1th bits in the array A are obtained.

[0713] It should be noted that the cyclic shift and inner code encoding are operated in parallel, which has the advantage of low delay.

[0714] It should be noted that the interleaving coding process first performs cyclic shift, then performs inner code coding, and then performs polling reading. This implementation method is introduced below.

[0715] Fig.31 FIG. 5 is a schematic diagram of a fifth implementation method of interleaving coding processing. Fig.31 As shown, for the n1 first data streams, a0 first bit sets are obtained from each first data stream, to obtain a total of m=n1×a0 first bit sets, which contain a total of n1×a0×K bits.

[0716] like Fig.31 As shown in (b), the cyclic shift cyclically shifts the i-th first bit set among the m first bit sets to the left. bits or cyclic shift to the right δ i bits to obtain the i-th second bit set containing K bits, and a total of m second bit sets are obtained, 0≤i<m. Usually, the offset constraint factor of the left cyclic shift is is an integer multiple of 10, and The offset constraint factor δ for the right circular shift i is an integer multiple of 10, and 0≤δ i <K. Typically, m offset constraint factors (Right now Any two of The values ​​of are not equal; m offset constraint factors δ i(i.e. δ0,δ1,…,δ m-1 ) the values ​​of any two δ are not equal.

[0717] like Fig.31 As shown in (b), the inner code encoding performs inner code encoding on each second bit set containing K bits in the m second bit sets, adds P check bits, and obtains an inner code codeword containing N bits, thereby obtaining a total of m inner code codewords.

[0718] like Fig.31 As shown in (b), for m inner code words, the polling read polling obtains 2 bits from each of the inner code words, and continuously performs m×N / 2 operations to obtain all the bits in the m inner code words, thereby obtaining a 4th bit set containing m×N bits.

[0719] Fig.32 FIG. 6 is a schematic diagram of a sixth implementation method of interleaving coding processing. Fig.32 As shown, m first bit sets can be represented by a bit matrix M1 with m rows and K columns, m second bit sets can be represented by a bit matrix M2 with m rows and K columns, and m inner code words can be represented by a bit matrix M with m rows and N columns. c The first bit matrix M1 is cyclically shifted to obtain the second bit matrix M2.

[0720] Taking the left cyclic shift as an example, the first bit matrix M1 and the second bit matrix M2 satisfy formula (X-10):

[0721]

[0722] Where Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor of the left cyclic shift is is an integer multiple of 10, and

[0723] It should be noted that for the K bits in the i-th row of the first bit matrix M1, a left cyclic shift is performed. bits, and obtain the K bits in the i-th row of the second bit matrix M2. This is equivalent to cyclically shifting the K bits in the i-th row of the first bit matrix M1 to the right. bits, and obtain the K bits in the i-th row in the second bit matrix M2.

[0724] As another example, the position change adopts right cyclic shift, and the i-th first bit set among the m first bit sets is cyclically shifted right by δ i bits, where the non-zero integer δ iis the offset constraint factor of the cyclic shift corresponding to the i-th bit set. The right cyclic shift satisfies formula (X-11):

[0725] M2[i][j]=M1[i][(j-δ i )% K]

[0726] Where Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor δ of the right cyclic shift is i is an integer multiple of 10, and 0≤δ i <K.

[0727] It should be noted that for the K bits in the i-th row of the first bit matrix M1, a rightward cyclic shift of δ is performed. i bits, and obtain the K bits of the i-th row of the second bit matrix M2. This is equivalent to performing a left cyclic shift of δ on the i-th row of the second bit matrix M2. i bits, and obtain the K bits of the ith row of the first bit matrix M1. In other words, formula (X-11) can also be written as formula (X-12):

[0728] M1[i][j]=M2[i][(j+δ i )% K]

[0729] Among them, 0≤i<m, 0≤j<K.

[0730] like Fig.32 As shown, the second bit matrix M2 is encoded by the inner code to obtain the inner code word matrix M c The "polling read" polls the inner codeword matrix M c Each row in the code is polled and read out 2 bits, and a total of m×N / 2 operations are performed to read all m×N bits, thereby obtaining the array A containing m×N interleaved bits. c The bit in the i-th row and j-th column of the array A is output to the bits, which satisfies formula (X-13):

[0731]

[0732] Among them, 0≤i<m, 0≤j<N, Indicates a floor operation.

[0733] 402. Map each 2 bits in the n2 second data streams to a PAM4 symbol to obtain n2 PAM4 symbol data streams.

[0734] For PAM4 modulation, every 2 bits are mapped to a PAM4 modulation symbol. For the 4th bit set or array A containing m×N bits, it is mapped to m×N / 2 PAM4 modulation symbols. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the m×2 bits mapped to m consecutive PAM4 modulation symbols come from m inner codewords.

[0735] Furthermore, for two outer code symbols from the same RS outer code word in a first data stream, after the above data processing, they are mapped into multiple PAM4 symbols in the same PAM4 symbol data stream, and the offset constraint factor of the left cyclic shift is selected. Or the offset constraint factor δ of the right cyclic shift i , so that any two PAM4 symbols among the multiple PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. It should be noted that two adjacent PAM4 symbols in a PAM4 symbol data stream are considered to be separated by one PAM4 symbol.

[0736] In some specific applications, before bit mapping is performed on the n2 second data streams, padding bits are periodically inserted into the n2 second data streams, where the padding bits include alignment markers used for alignment and synchronization of the receiving end.

[0737] In the embodiment of the present application, a cascade FEC transmission scheme is adopted, that is, the data stream is successively coded by the outer code and coded by the inner code. On this basis, the present application designs an interleaved coding processing method, so that the bits in the outer code word and the bits in the inner code word are discretely and evenly mapped to the modulation symbol, so that the cascade FEC transmission scheme has a strong burst resistance capability, especially for burst errors with a short length, which can be directly corrected by the inner code decoding, and can be applied to more transmission scenarios, especially for actual coherent transmission scenarios where the channel has colored noise.

[0738] It should be noted that the polling readout in the present application material obtains 2 bits from each of the 3rd bit sets to obtain a 4th bit set containing m×N bits. That is, 2 bits are obtained from the 0th 3rd bit set, 2 bits are obtained from the 1st 3rd bit set, ..., 2 bits are obtained from the m-1th 3rd bit set, and then 2 bits are obtained from the 0th 3rd bit set, until all m×N bits are obtained. In some specific implementations, the order of polling readout may be changed, and the offset constraint factor of the left loop in the cyclic shift operation is correspondingly changed. Or the right-loop offset constraint factors δ0,δ1,…,δ m-1 Just change the order accordingly.

[0739] The above figure is described below in conjunction with some specific embodiments. Fig.26 The data processing method described in the present invention is further described. The following examples X-1 to X-6 are examples of Fig. 27 and Fig.28 The data processing flow is introduced.

[0740] Embodiment X-1: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking the bit set representation as an example, using left cyclic shift.

[0741] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=4 first data streams. The above n0=4 first data streams are all data streams encoded with outer codes. The interleaving encoding process is performed on each n1=1 first data stream among the n0=4 first data streams to obtain a second data stream, so as to obtain a total of n2=4 second data streams.

[0742] Reference Fig. 27 , the interleaving coding process first performs inner code coding, then performs cyclic shift, and then performs polling reading. For the n1=1 first data stream, m=n1×a0=8 first bit sets containing K=120 bits are obtained, which contain a total of m×K=960 bits. The first data stream is also subjected to convolution interleaving before inner code coding so that the K=120 bits come from 12 KP4 symbols of 12 different outer code KP4RS code words.

[0743] The inner code encoding adds P=8 check bits to every K=120 bits to obtain an inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called information bit sequences.

[0744] In the present application, the cyclic shift operation performs a left cyclic shift on the K=120 information bits in the i-th (0≤i<8) inner codeword, i.e., the i-th first bit set. bits to get the ith second bit set, where the offset constraint factor of 8 left cyclic shifts The specific value of is one of the following value items 1:

[0745] {0,30,60,90,110,20,50,80},

[0746] {0,30,90,60,110,20,80,50},

[0747] {0,60,30,90,110,50,20,80},

[0748] {0,60,90,30,110,50,80,20},

[0749] {0,90,30,60,110,80,20,50},

[0750] {0,90,60,30,110,80,50,20}

[0751] It should be understood that for any term, the offset constraint factor of the 8 left cyclic shifts is Add a fixed offset to each factor value in is still considered a legal parameter term, where Δ is an integer.

[0752] The i-th second bit set is combined with P=8 check bits in the i-th inner code word to obtain the i-th third bit set containing N=128 bits.

[0753] Reference Fig. 27 For the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all the bits in the m=8 third bit sets, thereby obtaining a fourth bit set containing m×N=1024 bits.

[0754] Every 2 bits in the 4th bit set containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0755] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapping to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in the value item 1 is adopted Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two PAM4 symbols among the 10 PAM4 symbols come from different KP4 outer code words, they are spaced apart by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0756] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0757] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0758] Embodiment X-2: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking matrix representation as an example, using left cyclic shift.

[0759] Based on the scheme of embodiment X-1, the m=8 first bit sets can be represented by a first bit matrix M1 with 8 rows and 120 columns. The K=120 bits in each row of the first bit matrix M1 are respectively encoded by inner code to obtain an inner code of N=128 bits. The 8 inner code codewords can be represented by an inner code codeword matrix M1 with 8 rows and 128 columns. c Represents, where the inner codeword matrix M c Each row in M ​​contains N=128 bits of an inner code word. c The total m×K=960 bits from the 0th column to the K-1=119th column correspond to the m×K=960 information bits of m=8 inner code words; the inner code word matrix M c A total of m×P=64 bits from the K=120th column to the N-1=127th column correspond to m×P=64 check bits of m=8 inner code words.

[0760] The inner code matrix M c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row in the first bit matrix M1) are cyclically shifted to the left bits, and obtain 120 bits in the i-th row of the third bit matrix M3, satisfying the following formula:

[0761]

[0762] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 1.

[0763] Fig.33 FIG. 8 is a schematic diagram of the seventh implementation method of interleaving coding processing. Fig.33 As shown, considering The letters a, b, c, d, f, g, h, k, p, q, r, and s each represent a KP4 symbol, which contains 10 bits. Fig.33 KP4 symbols with the same letters come from the same KP4 external code, and KP4 symbols with different letters come from different KP4 external codes. Fig.33 The 8 KP4 symbols with the same letter a in the figure come from the same KP4 outer code.

[0764] 2 bits are read out from each row of the third bit matrix M3 in round robin, and all 1024 bits are read out in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the i-th row and j-th column in the array A. bits, satisfying the following formula:

[0765]

[0766] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0767] It should be noted that the above inner code matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A is:

[0768]

[0769] Among them, 0≤i<8.

[0770] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0771] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapping to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in the value item 1 is adopted Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two PAM4 symbols among the 10 PAM4 symbols come from different KP4 outer code words, they are spaced apart by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0772] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0773] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0774] Embodiment X-3: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking matrix representation as an example, using right circular shift.

[0775] Based on the scheme of embodiment X-2, the cyclic shift adopts right cyclic. c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row of the first bit matrix M1) are cyclically shifted right by δ i bits, and obtain 120 bits in the i-th row of the third bit matrix M3, satisfying the following formula:

[0776]

[0777] Wherein, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤i<m. The specific values ​​of the 8 right cyclic shift offset constraint factors {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} are one of the following value items 2:

[0778] {0,30,60,90,10,40,70,100},

[0779] {0,30,90,60,10,40,100,70},

[0780] {0,60,30,90,10,40,40,100},

[0781] {0,60,90,30,10,70,100,40},

[0782] {0,90,30,60,10,100,40,70},

[0783] {0,90,60,30,10,100,70,40}

[0784] It should be noted that the corresponding relationship between M3 and M2 can also be written as the following formula:

[0785]

[0786] Among them, 0≤i<8.

[0787] It should be noted that, for any item in the value item 2, a fixed offset is added to each factor value of the 8 right cyclic shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7], that is, {(δ0+Δ)%K, (δ1+Δ)%K, (δ2+Δ)%K, (δ3+Δ)%K, (δ4+Δ)%K, (δ5+Δ)%K, (δ6+Δ)%K, (δ7+Δ)%K} is still regarded as a legal parameter item, where Δ is an integer.

[0788] Fig.34 FIG. 8 is a schematic diagram of an eighth implementation method of interleaving coding processing. Fig.34As shown, consider {δ0=0,δ1=90,δ2=60,δ3=30,δ4=10,δ5=100,δ6=70,δ7=40}, where the letters a, b, c, d, f, g, h, k, p, q, r, s respectively represent 1 KP4 symbol, which contains 10 bits. Fig.34 KP4 symbols with the same letters come from the same KP4 external code, and KP4 symbols with different letters come from different KP4 external codes. Fig.34 The 8 KP4 symbols with the same letter a in the figure come from the same KP4 outer code.

[0789] 2 bits are read out from each row of the third bit matrix M3 in round robin, and all 1024 bits are read out in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the i-th row and j-th column in the array A. bits, satisfying the following formula:

[0790]

[0791] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0792] It should be noted that the above inner code matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A is:

[0793]

[0794] Among them, 0≤i<8.

[0795] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0796] For the two KP4 outer code symbols with a total of 20 bits from the same RS outer code word in the n1=1 first data stream, after the above interleaving coding processing and mapping to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift described in value item 2 is adopted i, any two PAM4 symbols among the 10 PAM4 symbols can be spaced at least 2 PAM4 symbols apart in the PAM4 symbol data stream. More specifically, when the two PAM4 symbols among the 10 PAM4 symbols come from different KP4 outer code words, they are spaced at least 12 PAM4 symbols apart in the PAM4 symbol data stream.

[0797] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0798] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0799] Embodiment X-4: n0=4, n1=1, a0=8, the data processing flow does not include convolution interleaving, and taking the bit set representation as an example, a left cyclic shift is adopted.

[0800] Based on Example X-1, the convolution interleaving operation is not performed (bypassed), which has the advantage of low latency and meets application scenarios with high latency requirements. The Physical Medium Attachment (PMA) sublayer of the transmitting processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=4 first data streams. The above n0=4 first data streams are all data streams encoded with external codes. The interleaving coding process is performed on each n1=1 first data stream among the n0=4 first data streams to obtain a second data stream, so as to obtain a total of n2=4 second data streams.

[0801] Reference Fig. 27, the interleaving coding process first performs inner code coding, then performs cyclic shift, and then performs polling reading. For the n1=1 first data stream, m=n1×a0=8 first bit sets containing K=120 bits are obtained, which contain a total of m×K=960 bits. The 120 information bits of each inner code word come from 12 KP4 symbols of 4 different outer code KP4RS code words.

[0802] The inner code encoding adds P=8 check bits to every K=120 bits to obtain an inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called information bit sequences.

[0803] In the present application, the cyclic shift operation performs a left cyclic shift on the K=120 information bits in the i-th (0≤i<8) inner codeword, i.e., the i-th first bit set. bits to get the ith second bit set, where the offset constraint factor of 8 left cyclic shifts The specific value of is one of the following 3 value items:

[0804] {0,30,60,90,110,20,50,80},

[0805] {0,60,30,90,110,50,20,80}

[0806] It should be understood that for any term, the offset constraint factor of the 8 left cyclic shifts is A fixed offset is added to each factor value in is still considered a legal parameter term, where Δ is an integer.

[0807] The i-th second bit set is combined with P=8 check bits in the i-th inner code word to obtain the i-th third bit set containing N=128 bits.

[0808] Reference Fig. 27 For the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all the bits in the m=8 third bit sets, thereby obtaining a fourth bit set containing m×N=1024 bits.

[0809] Every 2 bits in the 4th bit set containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0810] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapping to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in value item 3 is adopted Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0811] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be more discretely and evenly mapped to the modulation symbols while ensuring a lower delay, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0812] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0813] Example X-5: n0=4, n1=1, a0=8, the data processing flow does not perform convolution interleaving, and taking matrix representation as an example, a left circular shift is used.

[0814] Based on Example X-4, m=8 bit sets can be represented by a matrix. The K=120 bits in each row of the first bit matrix M1 are respectively encoded with inner codes to obtain an inner code word matrix M c . For the inner code word matrix M c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row in the first bit matrix M1) are cyclically shifted to the left bits, and obtain 120 bits in the i-th row of the third bit matrix M3, satisfying the following formula:

[0815]

[0816] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 3.

[0817] Fig.35 FIG. 9 is a schematic diagram of a ninth implementation method of interleaving coding processing. Fig.35 As shown, considering The letters a, b, c, and d each represent a KP4 symbol, which contains 10 bits. Fig.35 KP4 symbols with the same letters come from the same KP4 external code, and KP4 symbols with different letters come from different KP4 external codes. Fig.35 The 24 KP4 symbols with the same letter a in the equation come from the same KP4 outer code.

[0818] Two bits are read out from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read out through 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits.

[0819] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0820] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapping to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in value item 3 is adopted Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0821] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be more discretely and evenly mapped to the modulation symbols while ensuring a lower delay, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0822] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0823] Example X-6: n0=4, n1=1, a0=8, the data processing flow does not perform convolution interleaving, and taking matrix representation as an example, right circular shift is used.

[0824] Based on Example X-5, the cyclic shift adopts right cyclic. c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row of the first bit matrix M1) are cyclically shifted right by δ i bits, and obtain 120 bits in the i-th row of the third bit matrix M3, satisfying the following formula:

[0825]

[0826] Wherein, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤i<m. The specific values ​​of the 8 right cyclic shift offset constraint factors {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} are one of the following 4 value items:

[0827] {0,60,90,30,10,70,100,40},

[0828] {0,90,60,30,10,100,70,40}

[0829] It should be understood that, for any item, a fixed offset is added to each factor value of the 8 right cyclic shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, that is, {(δ0+Δ0%K, (δ1+Δ)%K, (δ2+Δ)%K, (δ3+Δ)%K, (δ4+Δ)%K, (δ5+Δ)%K, (δ6+Δ)%K, (δ7+Δ)%K} is still considered as a legal parameter item, where Δ is an integer.

[0830] It should be noted that M3 and M c The corresponding relationship can also be written as follows:

[0831]

[0832] Among them, 0≤i<8.

[0833] Fig.36 FIG. 10 is a schematic diagram of the tenth implementation method of interleaving coding processing. Fig.36 As shown, consider {δ0=0,δ1=60,δ2=90,δ3=30,δ4=10,δ5=70,δ6=100,δ7=40}, where letters a, b, c, and d respectively represent 1 KP4 symbol, which contains 10 bits. Fig.36 KP4 symbols with the same letters come from the same KP4 external code, and KP4 symbols with different letters come from different KP4 external codes. Fig.36 The 24 KP4 symbols with the same letter a in the equation come from the same KP4 outer code.

[0834] Two bits are read out from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read out through 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits.

[0835] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0836] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift described in the value item 4 is adopted i , so that any 2 PAM4 symbols among the 10 PAM4 symbols can be spaced apart by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0837] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be more discretely and evenly mapped to the modulation symbols while ensuring a lower delay, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0838] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0839] It should be noted that in Embodiments X-1 to X-6, inner code encoding is performed first, and then cyclic shift is performed. The inner code encoding and cyclic shift can also be performed in parallel, such as Fig.29 and Fig.30 The following is an introduction using Example X-7 as an example, and provides an equivalent execution method of Example X-3.

[0840] Example X-7: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking matrix representation as an example, using left cyclic shift, inner code encoding and cyclic shift in parallel.

[0841] Based on the scheme of Example X-3, in this embodiment, inner code encoding and cyclic shift are performed in parallel.

[0842] Fig.37 FIG. 11 is a schematic diagram of an eleventh implementation of interleaving coding processing. Fig.37 As shown, the 120 information bits in the i-th (0≤i<8) row in the first bit matrix M1 (i.e., the 120 bits in the i-th row in the first bit matrix M1) are cyclically shifted to the left. bits, and obtain 120 bits in the i-th row of the second bit matrix M2, satisfying the following formula:

[0843]

[0844] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8, 0≤j<120. The offset constraint factors of 8 left cyclic shifts The specific value of is one of the value items 1. Fig.37 As shown, considering

[0845] The K=120 bits in each row of the first bit matrix M1 are encoded with an inner code to obtain a P=8 check bit, and the check bit matrix M is obtained. p .

[0846] 2 bits are read out from each row of the third bit matrix M3 in round robin, and all 1024 bits are read out in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the i-th row and j-th column in the array A. bits, satisfying the following formula:

[0847]

[0848] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0849] It should be noted that the above inner code matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A is:

[0850]

[0851] Among them, 0≤i<8.

[0852] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0853] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is adopted. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0854] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0855] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n0=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0856] The following Examples X-8 to X-11 are based on Fig.31 and Fig.32 The data processing flow is introduced.

[0857] Embodiment X-8: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking the bit set representation as an example, using left cyclic shift.

[0858] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=4 first data streams. The above n0=4 first data streams are all data streams encoded with outer codes. The interleaving encoding process is performed on each n1=1 first data stream among the n0=4 first data streams to obtain a second data stream, so as to obtain a total of n2=4 second data streams.

[0859] Reference Fig.31, the interleaving coding process first performs cyclic shift, then performs inner code coding, and then performs polling reading. For the n1=1 first data stream, m=n1×a0=8 first bit sets containing K=120 bits are obtained, which contain a total of m×K=960 bits. The first data stream is also subjected to convolution interleaving before cyclic shift so that the K=120 bits come from 12 KP4 symbols of 12 different outer code KP4RS code words.

[0860] In the present application, the cyclic shift operation cyclically shifts the i-th (0≤i<8)-th bit set to the left. bits to get the ith second bit set, where the offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 1.

[0861] The inner code encodes K=120 bits in the ith second bit set and adds P=8 check bits to obtain the ith inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called information bit sequences.

[0862] Reference Fig.31 For the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all the bits in the m=8 third bit sets, thereby obtaining a fourth bit set containing m×N=1024 bits.

[0863] Every 2 bits in the 4th bit set containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0864] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is adopted. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0865] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0866] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0867] Example X-9: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking matrix representation as an example, using left circular shift.

[0868] Based on the scheme of embodiment X-8, the m=8 first bit sets can be represented by a first bit matrix M1 with 8 rows and 120 columns. The 120 information bits in the i-th (0≤i<8)th row of the first bit matrix M1 are cyclically shifted to the left. bits, and obtain 120 bits in the i-th row of the second bit matrix M2, satisfying the following formula:

[0869]

[0870] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8, 0≤j<120. The offset constraint factors of 8 left cyclic shifts The specific value of is one of the value items 1.

[0871] Fig.38 FIG. 12 is a schematic diagram of the twelfth implementation of interleaving coding processing. Fig.38 As shown, considering The K=120 bits in the i-th (0≤i<8)th row of the second bit matrix M2 are respectively encoded with inner code to obtain the i-th inner code word, and the inner code code word matrix M is obtained. c .

[0872] From the inner code word matrix M cIn each row, 2 bits are read out in round-robin fashion, and a total of 512 operations are performed to read all 1024 bits, thereby obtaining the array A containing m×N=1024 interleaved bits. c The bit in the i-th row and j-th column of the array A is output to the bits, satisfying the following formula:

[0873]

[0874] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0875] Every 2 bits in the array A containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0876] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is adopted. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0877] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0878] It should be noted that in this embodiment, n0=4, n1=1, a0=8, n2=n0 / n1=4, which can be applied to 800GE scenarios, wherein n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, wherein n0=8, n1=1, a0=8, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0879] Embodiment X-10: n0=8, n1=2, a0=4, the data processing flow includes convolution interleaving, taking the bit set representation as an example, and adopting right cyclic shift.

[0880] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=8 first data streams. The n0=8 first data streams are all data streams encoded with outer codes. The interleaving encoding process is performed on each n1=2 first data streams among the n0=8 first data streams to obtain a second data stream, so as to obtain a total of n2=4 second data streams.

[0881] Reference Fig.31, the interleaving coding process first performs cyclic shift, then performs inner code coding, and then performs polling readout. For the n1=2 first data streams, a0=4 first bit sets are obtained from each first data stream, and a total of m=n1×a0=8 first bit sets are obtained. Each of the first bit sets contains K=120 bits, and the 8 first bit sets contain a total of m×K=960 bits. The first data stream is also subjected to convolution interleaving processing before cyclic shift so that the K=120 bits come from 12 KP4 symbols of 12 different outer code KP4RS codewords. The four consecutive first bit sets in a first data stream are called the 0th first bit set, the 1st first bit set, the 2nd first bit set, and the 3rd first bit set; the four consecutive first bit sets in another first data stream are called the 4th first bit set, the 5th first bit set, the 6th first bit set, and the 7th first bit set.

[0882] In the present application, the cyclic shift operation performs a right cyclic shift of the i-th (0≤i<8)th bit set by δ i bits to obtain the i-th second bit set, where the specific value of the 8 right cyclic shift offset constraint factors {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} is one of the value items 2.

[0883] The inner code encodes K=120 bits in the ith second bit set and adds P=8 check bits to obtain the ith inner code word containing N=128 bits, and obtains a total of m=8 inner code words. The K=120 bits are also called information bit sequences.

[0884] Reference Fig.31 , for the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and obtains all bits in the m=8 third bit sets by 512 consecutive operations, and obtains a fourth bit set containing m×N=1024 bits. More specifically, 2 bits are obtained from the 0th third bit set, 2 bits are obtained from the 1st third bit set, ..., 2 bits are obtained from the 7th third bit set, and 2 bits are obtained from the 0th third bit set, until all 1024 bits are obtained.

[0885] It should be noted that, among the above 8 3-bit sets, the 0th 1st bit set, the 1st 1st bit set, the 2nd 1st bit set, and the 3rd 1st bit set come from the same data stream; the 4th 1st bit set, the 5th 1st bit set, the 6th 1st bit set, and the 7th 1st bit set come from another data stream. That is, the polling read operation first obtains 8 bits from one data stream, and then obtains 8 bits from another data stream.

[0886] Every 2 bits in the 4th bit set containing 1024 bits are mapped to a PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to a PAM4 modulation symbol come from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols come from 8 inner codewords.

[0887] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, after the above interleaving coding processing and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift is adopted. i , so that any 2 PAM4 symbols among the 10 PAM4 symbols can be spaced apart by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0888] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0889] It should be noted that in this embodiment, n0=8, n1=2, a0=4, n2=n0 / n1=4, which can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried on 4 optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=16, n1=2, a0=4, n2=n0 / n1=8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronous client lanes to obtain n0=16 first data streams. The above n0=16 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=2 first data streams in the n0=16 first data streams to obtain a second data stream, so as to obtain a total of n2=8 second data streams. The n2=8 second data flow rates (each approximately 200G) are correspondingly carried on 8 optical signals and sent out.

[0890] It should be noted that, in some other specific implementations, the four consecutive first bit sets in a first data stream are called the 0th first bit set, the 2nd first bit set, the 4th first bit set, and the 6th first bit set; the four consecutive first bit sets in another first data stream are called the 1st first bit set, the 3rd first bit set, the 5th first bit set, and the 7th first bit set. For the m=8 third bit sets output by the cyclic shift, the polling read obtains 2 bits from the 0th third bit set, 2 bits from the 1st third bit set, ..., 2 bits from the 7th third bit set, and then 2 bits from the 0th third bit set, until all 1024 bits are obtained. Correspondingly, the 0th bit set, the 2nd bit set, the 4th bit set, and the 8th bit set of the above 8 3-bit sets are from the same data stream; the 1st bit set, the 3rd bit set, the 5th bit set, and the 7th bit set are from another data stream. That is, the polling read operation first obtains 2 bits from one data stream, and then obtains 2 bits from another data stream.

[0891] It should be noted that, in some specific implementations, the four consecutive first bit sets in a first data stream are called the 0th first bit set, the 1st first bit set, the 4th first bit set, and the 5th first bit set; the four consecutive first bit sets in another first data stream are called the 2nd first bit set, the 3rd first bit set, the 6th first bit set, and the 7th first bit set. For the m=8 third bit sets output by the cyclic shift, the polling read obtains 2 bits from the 0th third bit set, 2 bits from the 1st third bit set, ..., 2 bits from the 7th third bit set, and then 2 bits from the 0th third bit set, until all 1024 bits are obtained. Correspondingly, the 0th bit set, the 1st bit set, the 4th bit set, and the 5th bit set of the above 8 3-bit sets are from the same data stream; the 1st bit set, the 3rd bit set, the 6th bit set, and the 7th bit set are from another data stream. That is, the polling read operation first obtains 4 bits from one data stream, and then obtains 4 bits from another data stream.

[0892] Fig.39 FIG. 2 is another structural diagram of a data processing device in an embodiment of the present application. Fig.39 As shown, the data processing device includes an interleaving coding module 501 and a bit mapping module 502. The interleaving coding module 501 is used to perform the above Fig.26The operation of step 401 in the data processing method shown in the figure. The bit mapping module 502 is used to perform the above Fig.26 The operation of step 402 in the data processing method shown in FIG. Fig.26 The relevant introduction in the data processing method shown will not be repeated here.

[0893] It should be understood that the device provided in the present application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system. In addition, each functional unit in each embodiment of the present application can be integrated in a processing unit, or it can be each independent physical unit, or two or more functional units can be integrated in a processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0894] Fig.40 FIG. 2 is another structural diagram of a data processing device in an embodiment of the present application. Fig.40 As shown, the data processing device includes a processor 201, a memory 202 and a transceiver 203. The processor 201, the memory 202 and the transceiver 203 are connected to each other through a line. Among them, the memory 202 is used to store program instructions and data. Specifically, the transceiver 203 is used to receive a first data stream. The processor 201 is used to execute the above Figure 3 or Fig.26 In one possible implementation, the processor 201 may include the above Fig. 22 The encoding module 101, the bit interleaving module 102 and the bit mapping module 103 are shown. In another possible implementation, the processor 201 may include the above Fig.39 An interleaving coding module 501 and a bit mapping module 502 are shown.

[0895] It should be noted that the above Fig.40 The processor shown in the figure may be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. Fig.40The memory shown in can store operating systems and other applications. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the program code for implementing the technical solutions provided by the embodiments of the present application is stored in the memory and executed by the processor. In one embodiment, the processor may include a memory. In another embodiment, the processor and the memory are two independent structures.

[0896] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0897] Those skilled in the art will appreciate that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware to accomplish the steps, and the program may be stored in a computer-readable storage medium, and the storage medium mentioned above may be a read-only memory, a random access memory, etc. Whether the above functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0898] When software is used for implementation, the method steps described in the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

Claims

1. A data processing method, characterized in that: include: Performing interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; Mapping each 2 bits in the n2 second data streams into one PAM4 symbol respectively, to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding process comprises: Obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by an outer code, each of the first bit sets includes K bits, and a0 and K are both integers greater than 1; Cyclic shift is performed on the m first bit sets respectively to obtain m second bit sets, each of the second bit sets includes K bits; Performing inner code encoding on the m second bit sets respectively to obtain m inner code codewords, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, each of the inner code codewords includes one second bit set participating in the inner code encoding and one check bit set, totaling N bits, N=K+P, each of the check bit sets includes P bits, and P is an integer greater than or equal to 1; Polling to obtain 2 bits from each of the inner code words to obtain a third bit set, wherein the third bit set includes m×N bits; Each of the second data streams includes multiple third bit sets, and each of the third bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping.

2. The method according to claim 1, characterized in that Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two PAM4 symbols of the at least 10 PAM4 symbols are spaced by at least 2 PAM4 symbols in the PAM4 symbol data stream.

3. The method according to claim 1 or 2, characterized in that: The number of bits cyclically shifted in any two of the m first bit sets is different.

4. The method according to claim 1 or 2, characterized in that: The m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

5. The method according to claim 4, characterized in that The second bit set is cyclically shifted right by δ from the first bit set i bits are obtained, the right cyclic shift satisfies the second condition, and the second condition includes: M2[i][j]=M1[i][(j-δ i )%K] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,0≤δ i <K.

6. The method according to claim 4, characterized in that The m inner code words are represented as a bit matrix including m rows and N columns, and the m inner code words and the third bit set satisfy a third condition, and the third condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words, Indicates the first bit in the third bit set (j%2) bits, 0≤i <m,0≤j<N, Indicates a floor operation.

7. The method according to claim 4, characterized in that K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include: {0，30，60，90，10，40，70，100}； {0，30，90，60，10，40，100，70}； {0，60，30，90，10，40，40，100}； {0，60，90，30，10，70，100，40}； {0, 90, 30, 60, 10, 100, 40, 70}; and {0，90，60，30，10，100，70，40}。 8. The method according to claim 1 or 2, characterized in that: The obtaining a0 first bit sets from each of the n1 first data streams includes: Convolution interleaving is performed on each of the first data streams.

9. The method according to claim 8, characterized in that The convolution interleaver for the convolution interleaving process comprises three delay lines, and the three delay lines respectively comprise 2Q, Q and 0 storage units, wherein Q is a positive integer.

10. The method according to claim 9, characterized in that The Q is ≥ 6, and each of the storage units is used to store 40 bits.

11. The method according to claim 1 or 2, characterized in that: n0=4, n1=1.

12. The method according to claim 1 or 2, characterized in that: n0=8, n1=1.

13. The method according to claim 1 or 2, characterized in that: a0＝8。 14. The method according to claim 1 or 2, characterized in that: The rate of each of the second data streams is 200G.

15. The method according to claim 1 or 2, characterized in that: Before mapping each 2 bits in the n2 second data streams into one PAM4 symbol, the method further includes: Stuffing bits are periodically inserted into the n2 second data streams.

16. The method according to claim 1 or 2, characterized in that: The inner code adopts Hamming code (128, 120).

17. A data processing device, characterized in that: Used to perform the method according to any one of claims 1 to 16.

18. A chip, characterized in that: Used to perform the method according to any one of claims 1 to 16.

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