Shift register, drive circuit, drive method, and display device

Abstract

The present disclosure provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: an input circuit configured to provide an input signal to a first node under the control of a first clock signal or a second clock signal, and control the potential of a second node by using a first power supply voltage of a first power supply or a third clock signal from a third clock terminal; a first control circuit configured to provide the potential of the first node to a third node under the control of the first power supply voltage, and provide at least one of the second power supply voltage of a second power supply and the potential of the second node to a fourth node under the control of the potential of the first node and the first clock signal or under the control of the potential of the first node and the second clock signal; and an output circuit configured to provide the first power supply voltage or the second power supply voltage to an output terminal as an output signal under the control of the potential of the third node and the potential of the fourth node.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0002] The circuit structure and internal connection relationship of the current shift register circuit are complex, and the space occupation is large. In addition, the shift register circuit has the problem of unstable pull-down capability, which may cause the voltage waveforms output by each shift register in the driving circuit to be different, thereby affecting the display quality of the display picture. SUMMARY

[0003] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit configured to provide an input signal from an input terminal to a first node under the control of a first clock signal from a first clock terminal or a second clock signal from a second clock terminal, and control a potential of a second node by a first power supply voltage of a first power supply or a third clock signal from a third clock terminal; a first control circuit configured to provide a potential of the first node to a third node under the control of the first power supply voltage, and provide at least one of a second power supply voltage of a second power supply and the potential of the second node to a fourth node under the control of the first node and the first clock signal or the potential of the first node and the second clock signal; and an output circuit configured to provide the first power supply voltage or the second power supply voltage to an output terminal as an output signal under the control of the potential of the third node and the potential of the fourth node.

[0005] According to a second aspect, the present disclosure provides a driving circuit, comprising M shift registers provided by the embodiments of the present disclosure connected in cascade, an input terminal of an mth shift register is electrically connected with an output terminal of an (m-1) th shift register, 1<m≤M, m is an integer, and M is an integer greater than 1.

[0006] According to a third aspect, the present disclosure provides a display device comprising a driving circuit provided by the embodiments of the present disclosure.

[0007] According to a fourth aspect, the present disclosure provides a driving method applied to any one of the shift registers provided by the embodiments of the present disclosure, including: a first stage, the input signal is a first level, the first clock signal is a second level, and the third clock signal is a first level; a second stage, the input signal is a first level, the first clock signal is a first level, and the third clock signal is a second level; a third stage, the input signal is a second level, the first clock signal is a first level, and the third clock signal is a second level; a fourth stage, the input signal is a second level, the first clock signal is a second level, and the third clock signal is a first level; and a fifth stage, the input signal is a second level, the first clock signal is a first level, and the third clock signal is a second level. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure;

[0009] Figure 2 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0010] Figure 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0011] Figure 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0012] Figure 5 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0013] Figure 6A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0014] Figure 6B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0015] Figure 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0016] Figure 8 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0017] Figure 9A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0018] Figure 9B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0019] Figure 10Ais a structural schematic diagram of a shift register according to another embodiment of the present disclosure;

[0020] Figure 10B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0021] Figure 11A is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0022] Figure 11B is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0023] Figure 11C is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0024] Figure 11D is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0025] Figure 12A is a signal timing diagram of a driving circuit according to an embodiment of the present disclosure;

[0026] Figure 12B is a signal timing diagram of a driving circuit according to another embodiment of the present disclosure;

[0027] Figure 13 is a structural schematic diagram of a display device according to an embodiment of the present disclosure; and

[0028] Figure 14 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort fall within the protection scope of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0030] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure shall have the ordinary meanings to those skilled in the art. The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components.

[0031] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0032] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain thereof can be interchangeable. In the embodiments of the present disclosure, the gate can be referred to as a control electrode, one of the source and drain can be referred to as a first electrode, and the other of the source and drain can be referred to as a second electrode according to their functions.

[0033] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the magnitudes of the two power supply voltages. For example, the following description takes "first power supply voltage" as a relatively high voltage, and "second power supply voltage" and "third power supply voltage" as relatively low voltages. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0034] It should be noted that in the description of the embodiments of the present disclosure, INPUT can represent both an input signal terminal and an input signal provided by the input signal terminal. Similarly, the symbol CK1 can represent both a clock terminal and a clock signal provided by the clock terminal, OUT can represent both an output signal terminal and an output signal output by the output signal terminal, and VGH and VGL can represent both a power supply terminal and a power supply voltage provided by the power supply terminal. For example, the power supply VGH can provide a high-level voltage, and the power supply VGL can provide a low-level voltage. The following embodiments are the same as this, and will not be described again.

[0035] Figure 1 is a structural schematic diagram of a shift register according to the embodiments of the present disclosure.

[0036] As Figure 1 shown, the shift register 100 includes an input circuit 110, a first control circuit 120, and an output circuit 130.

[0037] In the embodiments of the present disclosure, the input circuit 110 is electrically connected with the first clock terminal CK1 or the second clock terminal CK2, and under the control of the first clock signal CK1 from the first clock terminal CK1 or the second clock signal CK2 from the second clock terminal CK2, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1.

[0038] The input circuit 110 is also electrically connected with the first power supply VGL and the third clock terminal CK3. Under the control of the third clock signal CK3 from the third clock terminal CK3, the input circuit 110 can provide the first power supply voltage VGL of the first power supply VGL to the second node N2. In some embodiments, the input circuit 110 can also directly provide the third clock signal CK3 to the second node N2 to control the potential of the second node N2.

[0039] In the embodiments of the present disclosure, the first control circuit 120 is electrically connected with the first power supply VGL, the first clock terminal CK1, the second clock terminal CK2 and the second power supply VGH. Under the control of the first power supply voltage VGL, the potential of the first node N1 is provided to the third node N3. Under the control of the potential of the first node N1 and the first clock signal CK1 or under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4. For example, under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 can provide the second power supply voltage VGH to the fourth node N4, can provide the potential of the second node N2 to the fourth node N4, or can provide the second power supply voltage VGH and the potential of the second node N2 together to the fourth node N4 to control the potential of the fourth node N4.

[0040] For example, under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 can provide the second power supply voltage VGH to the fourth node N4, can provide the potential of the second node N2 to the fourth node N4, or can provide the second power supply voltage VGH and the potential of the second node N2 together to the fourth node N4 to control the potential of the fourth node N4.

[0041] In the embodiments of the present disclosure, the input circuit 110 is controlled by the second clock signal CK2, and the first control circuit 120 is controlled by the first clock signal CK1. Under the control of the second clock signal CK2, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0042] In the embodiment of the present disclosure, the input circuit 110 is controlled by the first clock signal CK1 and the second clock signal CK2, and the first control circuit 120 is controlled by the second clock signal CK2. Under the control of the first clock signal CK1, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0043] In the embodiment of the present disclosure, the input circuit 110 and the first control circuit 120 are controlled by the first clock signal CK1 and the second clock signal CK2. Under the control of the first clock signal CK1, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0044] In the embodiment of the present disclosure, the output circuit 130 is electrically connected to the first power supply VGL, the second power supply VGH and the output terminal OUT. Under the control of the potential of the third node N3 and the potential of the fourth node N4, the first power supply voltage VGL or the second power supply voltage VGH is provided to the output terminal OUT as the output signal OUT. The output signal OUT can be a scanning signal or a light-emitting control signal for driving a pixel circuit.

[0045] For example, when the third node N3 controls the first power supply VGL to be in communication with the output terminal OUT, the output circuit 130 outputs the first power supply voltage VGL to the output terminal OUT. When the fourth node N4 controls the second power supply VGH to be in communication with the output terminal OUT, the output circuit 130 outputs the second power supply voltage VGH to the output terminal OUT.

[0046] In the embodiment of the present disclosure, under the control of the potential of the first node N1, the first control circuit 120 can jointly control the potential of the fourth node N4 by the first clock signal CK and the second power supply VGH, and control the second power supply VGH and the output terminal OUT to be in a communication state or a cutoff state by the potential of the fourth node N4, so as to control whether the output terminal OUT outputs a high level. When the second power supply VGH and the output terminal OUT are in a communication state, the output terminal OUT can output a high level signal.

[0047] When the potential of the fourth node N4 controls the second power supply VGH and the output terminal OUT to maintain in the off state, the first control circuit 120 controls the potential of the third node N3, so that the potential of the third node N3 can control the first power supply VGL and the output terminal OUT to be in the on state. In this case, the output terminal OUT can output a low level signal.

[0048] In the embodiment of the present disclosure, the first control circuit 120 controls the potential of the fourth node N4 by using the first clock signal CK and the second power supply VGH, so that when the potential of the fourth node N4 is pulled up, the fourth node N4 and the second node N2 can be ensured to be in the off state, thereby ensuring that the potential of the fourth node N4 can be switched between high and low levels, which makes the second power supply VGH and the output terminal OUT switch between the on state and the off state.

[0049] According to the embodiment of the present disclosure, the first control circuit 120 controls the potential of the fourth node N4 by using the first clock signal CK and the second power supply VGH, and ensures the switching of the potential of the fourth node N4, thereby realizing the stable switching of the level of the output signal OUT between high and low levels, and outputting the scanning signal or the light emitting control signal required by the pixel circuit.

[0050] Figure 2 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0051] As shown in Figure 2 , the shift register 200 includes an input circuit 210, a first control circuit 220, and an output circuit 230. The first control circuit 220 includes a first control unit 221, a second control unit 222, and a third control unit 223.

[0052] In the embodiment of the present disclosure, the input circuit 210 and the output circuit 230 are similar to the input circuit 110 and the output circuit 130 described above, and are not described again for simplicity.

[0053] In the embodiment of the present disclosure, the first control unit 221 is electrically connected with the first node N1, the second node N2, the fourth node N4, and the first clock terminal CK1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control unit 221 controls the potential of the fourth node N4 by using the potential of the second node N2.

[0054] For example, based on the potential of the first node N1 and the first clock signal CK1, the first control unit 221 can control the second node N2 and the fourth node N4 to be in the on state or the off state. When the second node N2 and the fourth node N4 are in the on state, the first control unit 221 provides the potential of the second node N2 to the fourth node N4.

[0055] In the embodiment of the present disclosure, the second control unit 222 is electrically connected with the first node N1, the fourth node N4 and the second power supply VGH. Under the control of the potential of the first node N1, the second control unit 222 controls the potential of the fourth node N4 by using the second power supply voltage VGH.

[0056] For example, based on the potential of the first node N1, the second control unit 222 can control the second power supply VGH and the fourth node N4 to be in a conductive state or a non-conductive state. When the second power supply VGH and the fourth node N4 are in the conductive state, the first control unit 221 provides the second power supply voltage VGH to the fourth node N4.

[0057] In the embodiment of the present disclosure, the third control unit 223 is electrically connected with the first node N1, the third node N3 and the first power supply VGL. Under the control of the first power supply voltage VGL, the potential of the third node N3 is controlled by using the potential of the first node N1.

[0058] For example, based on the first power supply voltage VGL, the third control unit 223 can control the first node N1 and the third node N3 to be in a conductive state or a non-conductive state. When the first node N1 and the third node N3 are in the conductive state, the third control unit 223 provides the first node N1 to the third node N3.

[0059] In the embodiment of the present disclosure, the first control unit 221 can pull down the potential of the fourth node N4 by using the potential of the second node N2, so that under the control of the low potential of the fourth node N4, the output circuit 230 controls the second power supply VGH and the output terminal OUT to be in a conductive state, and the output terminal OUT outputs a high level signal. The second control unit 222 can pull up the potential of the fourth node N4 by using the second power supply voltage VGH, so that under the control of the high potential of the fourth node N4, the output circuit 230 controls the second power supply VGH and the output terminal OUT to be in a non-conductive state.

[0060] In the embodiment of the present disclosure, the third control unit 223 can pull down the potential of the third node N3 by using the potential of the first node N1, so that under the control of the low potential of the third node N3, the output circuit 230 controls the first power supply VGL and the output terminal OUT to be in a conductive state, and the output terminal OUT outputs a low level signal. The third control unit 223 can pull up the potential of the third node N3 by using the potential of the first node N1, so that under the control of the high potential of the third node N3, the output circuit 230 controls the first power supply VGL and the output terminal OUT to be in a non-conductive state.

[0061] In this embodiment of the disclosure, the first control circuit 120 uses the first clock signal CK and the second power supply VGH to jointly control the potential of the fourth node N4, which can maintain the potential of the fourth node N4 stably at a high level. This makes the second power supply VGH and the output terminal OUT stably maintain a cut-off state, thereby determining that the level of the output terminal OUT is pulled down by the first power supply VGL, and thus stably outputting a low level signal.

[0062] In this embodiment of the disclosure, the first control unit 221 and the second control unit 222 jointly control the potential of the fourth node N4 to switch between high and low potentials, thereby realizing the stable switching of the output signal OUT level between high and low levels, and outputting the scanning signal or light emission control signal required by the pixel circuit.

[0063] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0064] like Figure 3 As shown, the shift register 300 includes an input circuit 310, a first control circuit 320, and an output circuit 330. The first control circuit 320 includes a first control unit 321, a second control unit 322, a third control unit 323, and a fourth control unit 324.

[0065] In this embodiment, the input circuit 310 and the output circuit 330 are similar to the input circuit 110 and the output circuit 130 described above, respectively. The second control unit 322 and the third control unit 323 are similar to the second control unit 222 and the third control unit 223 described above, respectively. For the sake of brevity, they will not be described again.

[0066] In this embodiment, the first control unit 321 is electrically connected to the first node N1, the second node N2, the fourth node N4, and the second clock terminal CK2. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control unit 321 controls the potential of the fourth node N4 using the potential of the second node N2.

[0067] For example, based on the potential of the first node N1 and the second clock signal CK2, the first control unit 221 can control the second node N2 and the fourth node N4 to be in a connected or disconnected state. When the second node N2 and the fourth node N4 are in a connected state, the first control unit 221 provides the potential of the second node N2 to the fourth node N4.

[0068] In the embodiment of the present disclosure, the fourth control unit 324 is electrically connected with the third node N3, the fourth node N4, the second power supply VGH and the second clock terminal CK2. Under the control of the potential of the fourth node N4 and the potential of the third node N3, the fourth control unit 324 controls the potential of the third node N3 by using the second power supply voltage VGH and the second clock signal CK2.

[0069] When the input circuit 310 writes the low level of the input signal INPUT to the second node N2, the third control unit 323 can provide the low potential of the second node N2 to the third node N3. The fourth control unit 324 can accelerate the pull-down of the potential of the third node N3 based on the second power supply voltage VGH and the second clock signal CK2, so as to make the first power supply VGL and the output terminal OUT quickly switch to the connected state, and shorten the time for switching the output signal OUT from the high level to the low level.

[0070] Figure 4 FIG. 4 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure.

[0071] As shown in FIG. 4, the shift register 400 includes an input circuit 410, a first control circuit 420, an output circuit 430 and a second control circuit 440. Figure 4

[0072] In the embodiment of the present disclosure, the input circuit 410, the first control circuit 420 and the output circuit 430 are similar to the input circuit 110, the first control circuit 120 and the output circuit 130 described above respectively, and are not described herein again for simplicity.

[0073] In the embodiment of the present disclosure, the second control circuit 440 is electrically connected with the first node N1, the second node N2 and the third clock terminal. Under the control of the potential of the first node N1, the second control circuit 440 controls the potential of the second node N2 by using the third clock signal CK3.

[0074] For example, based on the potential of the first node N1, the second control circuit 440 controls the third clock terminal CK3 and the second node N2 to be in the connected state or the cut-off state, so as to control the potential of the second node N2 by using the third clock signal CK3.

[0075] For example, when the third clock signal CK3 is the high level, the second control circuit 440 can control the third clock terminal CK3 and the second node N2 to be in the connected state based on the potential of the first node N1, and pull up the potential of the second node N2 by using the third clock signal CK3, so as to maintain the potential of the fourth node N4 as the high level. When the potential of the fourth node N4 is the high level, the second power supply VGH and the output terminal OUT are in the cut-off state, so as to ensure that the output terminal OUT can stably output the low level signal. ​

[0076] Figure 5 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure.

[0077] As shown in Figure 5 , the shift register 500 includes an input circuit 510, a first control circuit 520, an output circuit 530, and a third control circuit 550.

[0078] In the embodiment of the present disclosure, the input circuit 510, the first control circuit 520, and the output circuit 530 are similar to the input circuit 110, the first control circuit 120, and the output circuit 130 described above respectively, and are not described again for simplicity.

[0079] In the embodiment of the present disclosure, the third control circuit 550 is electrically connected with the fourth node N4 and the third power supply VGX. Under the control of the control signal CX, the potential of the third node N3 is controlled by the third power supply voltage VGX of the third power supply VGX.

[0080] In the embodiment of the present disclosure, the shift register 800 is electrically connected with the pixel circuit in the display panel. When the display panel is powered on or in the initialization stage, the control signal CX is at a low level. When the display panel is in the normal display stage, the control signal CX remains at a high level. The third power supply VGX can be the first power supply VGL or the second power supply VGH. For example, when the display panel is powered on or in the initialization stage, the third power supply voltage VGX is written to the third node N3 based on the low level of the control signal CX.

[0081] For example, the output signal OUT can be a light-emitting control signal applied to the pixel circuit, and the transistor controlled by the light-emitting control signal is a PMOS transistor. At this time, the third power supply VGX can be the second power supply VGH. The third control circuit 550 pulls up the potential of the third node N3 by using the third power supply voltage VGX. The high potential of the third node N3 can quickly control the first power supply VGL and the output terminal OUT to be in a cut-off state, and the output terminal OUT can output a high-level signal. At this time, the output signal OUT controls the PMOS transistor to be closed, so that the power-on flash screen phenomenon of the display panel can be avoided.

[0082] For example, the output signal OUT can be a scanning signal applied to the pixel circuit, and the transistor controlled by the scanning signal is an NMOS transistor. At this time, the third power supply VGX can be the first power supply VGL. The third control circuit 550 pulls down the potential of the third node N3 by using the third power supply voltage VGX. The low potential of the third node N3 can quickly control the first power supply VGL and the output terminal OUT to be in a connected state, and the output terminal OUT can output a low-level signal. At this time, the output signal OUT controls the NMOS transistor to be closed, so that the power-on flash screen phenomenon of the display panel can be avoided.

[0083] Figure 6A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0084] In an embodiment of the present disclosure, the shift register 600 includes an input circuit 610, a first control circuit 620, and an output circuit 630.

[0085] In an embodiment of the present disclosure, the input circuit 610 includes a first transistor T1 and a second transistor T2.

[0086] The control electrode of the first transistor T1 is electrically connected to the second clock terminal CK2, the first electrode of the first transistor T1 is electrically connected to the input terminal INPUT, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0087] The control electrode of the second transistor T2 is electrically connected to the third clock terminal CK3, the first electrode of the second transistor T2 is electrically connected to the first power supply VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0088] In an embodiment of the present disclosure, the first control circuit 620 includes a first control unit 621, a second control unit 622, and a third control unit 623.

[0089] In an embodiment of the present disclosure, the first control unit 621 includes a third transistor T3, a fourth transistor T4, and a first capacitor C1.

[0090] The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the fifth node N5, and the second electrode of the third transistor T3 is electrically connected to the first clock terminal CK1.

[0091] The control electrode of the fourth transistor T4 is electrically connected to the fifth node N5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4.

[0092] The first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the fifth node N5.

[0093] In an embodiment of the present disclosure, the third control unit 623 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first power supply VGL, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3.

[0094] In this embodiment of the disclosure, the second control unit 622 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the second power supply VGH.

[0095] In this embodiment of the disclosure, the output circuit 630 includes a seventh transistor T7, an eighth transistor T8, a second capacitor C2, and a third capacitor C3.

[0096] The control electrode of the seventh transistor T7 is connected to the fourth node N4, the first electrode of the seventh transistor T7 is connected to the second power supply VGL, and the second electrode of the seventh transistor T7 is connected to the output terminal OUT.

[0097] The control electrode of the eighth transistor T8 is electrically connected to the third node, the first electrode of the eighth transistor T8 is electrically connected to the output terminal OUT, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply VGL.

[0098] The first terminal of the second capacitor C2 is electrically connected to the output terminal OUT, and the second terminal of the second capacitor C2 is electrically connected to the fourth node N4.

[0099] The first terminal of the third capacitor C3 is electrically connected to the second power supply VGH, and the second terminal of the third capacitor C3 is electrically connected to the output terminal OUT.

[0100] In the embodiments of this disclosure, the first transistor T1 to the second transistor T8 are P-type TFT transistors. It should be noted that the first transistor T1 to the second transistor T8 in this disclosure can also be N-type TFT transistors.

[0101] Figure 6B This is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0102] The following is based on Figure 6A Taking the structure of the shift register 600 shown as an example, combined with... Figure 6B The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure. The operation of the shift register 300 is divided into five stages.

[0103] In this embodiment of the disclosure, the first clock signal CK1 and the third clock signal CK3 are not at active levels. For example, in the shift register 600, the first clock signal CK1 and the third clock signal CK3 are used to control the PMOS transistor. When the first clock signal CK1 is low, the third clock signal CK3 is high. When the third clock signal CK3 is low, the first clock signal CK1 is high.

[0104] The first clock signal CK1 jumps from high level to low level earlier than the second clock signal CK2. The second clock signal CK2 jumps from low level to high level earlier than the first clock signal CK1. For example, when the first clock signal CK1 jumps from high level to low level, the second clock signal CK2 is still high. After the first clock signal CK1 is low, the second clock signal CK2 jumps from high level to low level. When the second clock signal CK2 jumps from low level to high level, the first clock signal CK1 is still low. After the second clock signal CK2 is high, the first clock signal CK1 jumps from low level to high level.

[0105] In the embodiment of the present disclosure, when the input signal INPUT jumps from low level to high level, the first clock signal CK1 and the second clock signal CK2 are high, and the third clock signal CK3 is low. When the input signal INPUT remains high, the first clock signal CK1 and the second clock signal CK2 jump from high level to low level, and then jump from low level to high level, and the third clock signal CK3 jumps from low level to high level, and then jumps from high level to low level. When the input signal INPUT remains high and the third clock signal CK3 jumps from high level to low level, the output terminal OUT outputs a high level signal, realizing scanning of the corresponding pixel circuit.

[0106] In the first stage S1, the input signal INPUT is high, the third clock signal CK3 is high, the first clock signal CK1 is low, and the second clock signal CK2 jumps from high level to low level, and then jumps from low level to high level.

[0107] When entering the first stage S1, the first clock signal CK1 jumps from high level to low level, and at this time the second clock signal CK2 is still high. In the first stage S1, when the second clock signal CK2 jumps from low level to high level, the first clock signal CK1 is still low. In the end of the first stage S1, the first clock signal CK1 jumps from low level to high level.

[0108] In the first stage S1, when the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is high, the first transistor T1 and the second transistor T2 are cut off. The first node N1 remains low level of the previous stage.

[0109] Under the control of the low level of the first node N1, the third transistor T3 and the sixth transistor T6 are turned on, the first clock signal CK1 is written into the fifth node N5 through the third transistor T3, the potential of the fifth node N5 is pulled low, and the fourth transistor T4 is turned on at this time. The second power voltage VGH is written into the fourth node N4 through the sixth transistor T6, and the seventh transistor T7 is cut off at this time. The second power voltage VGH charges the third capacitor C3, so that the third capacitor C3 stores a high level.

[0110] Under the control of the first power voltage VGL, the fifth transistor T5 is turned on. The low potential of the first node N1 is written into the third node N3 through the fifth transistor T5. Under the control of the low potential of the third node N3, the eighth transistor T8 is turned on, and the first power voltage VGL is written into the output terminal OUT through the eighth transistor T8. The output terminal OUT outputs a low level signal.

[0111] In the first stage S1, when the first clock signal CK1 is low, the second clock signal CK2 is low, and the third clock signal CK3 is high, the first transistor T1 is turned on, and the second transistor T2 is cut off. The input signal INPUT is written into the first node N1, and the node of the first node N1 is pulled high.

[0112] Under the control of the high level of the first node N1, the third transistor T3 and the sixth transistor T6 are cut off. The high potential of the first node N1 is written into the third node N3 through the fifth transistor T5, the potential of the third node N3 is pulled high, the eighth transistor T8 is cut off, the third node N3 charges the third capacitor C3, so that the second capacitor C2 stores a high level. The high level stored by the third capacitor C3 keeps the fourth node N4 high, and the seventh transistor T7 is cut off. At this time, the output terminal OUT keeps outputting a low level signal.

[0113] In the second stage S2, the input signal INPUT is high, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is low. The first transistor T1 is cut off, and the second transistor T2 is turned on. The first power voltage VGL is written into the second node N2 through the second transistor T2, and the potential of the second node N2 is pulled low. Under the action of the first capacitor C1, the potential of the fifth node N5 is pulled low again. Under the action of the low potential of the fifth node N5, the fourth transistor T4 is turned on. The low potential of the second node N2 is written into the fourth node N4, and the seventh transistor T7 is turned on at this time. Since the first transistor T1 is cut off, the high level stored by the second capacitor C2 keeps the third node N3 high, and the eighth transistor T8 is cut off. At this time, the output terminal OUT keeps outputting a high level signal.

[0114] In the third stage S3, the input signal INPUT is low, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK2 is low. The first transistor T1 is off, and the second transistor T2 is on. The first power voltage VGL is written into the second node N2 through the second transistor T2. The potential of the fifth node N5 is kept low under the action of the first capacitor Cl. The fourth transistor T4 is on under the action of the low potential of the fifth node N5. The low potential of the second node N2 is written into the fourth node N4, and the seventh transistor T7 is on. Since the first transistor T1 is off, the high level stored in the second capacitor C2 keeps the third node N3 high, and the eighth transistor T8 is off. At this time, the output terminal OUT keeps outputting a high level signal.

[0115] In the fourth stage S4, the input signal INPUT is low, the first clock signal CK1 is low, the second clock signal CK2 is low, and the third clock signal CK2 is high. The first transistor T1 is on, and the second transistor T2 is off. The input signal INPUT is written into the first node N1, and the node of the first node N1 is pulled low.

[0116] The third transistor T3 and the sixth transistor T6 are on under the control of the low level of the first node N1. The second power voltage VGH is written into the fourth node N4 through the sixth transistor T6, and the seventh transistor T7 is off at this time. The second power voltage VGH charges the third capacitor C3.

[0117] The fifth transistor T5 is on under the control of the first power voltage VGL. The low potential of the first node N1 is written into the third node N3 through the fifth transistor T5. The eighth transistor T8 is on under the control of the low potential of the third node N3, and the first power voltage VGL is written into the output terminal OUT through the eighth transistor T8. The potential of the output terminal OUT is pulled down, the output terminal OUT outputs a low level signal, and the output signal OUT is lowered. The low level of the third node N3 charges the second capacitor C2. The potential of the third node N3 is kept low under the action of the second capacitor C2, the eighth transistor T8 is kept on, and the output terminal OUT keeps outputting a low level signal.

[0118] In the fifth stage S5, the input signal INPUT is low, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK2 is low. The first transistor T1 is off, and the second transistor T2 is on. The first power voltage VGL is written into the second node N2 through the second transistor T2.

[0119] The potentials of the first node N1 and the third node N3 remain low in the previous stage, and the third transistor T3, the sixth transistor T6 and the eighth transistor T8 are turned on. The first clock signal CK1 is written into the fifth node N5 through the third transistor T3, the potential of the fifth node N5 is pulled high, and the fourth transistor T4 is turned off. The second power voltage VGH is written into the fourth node N4 through the sixth transistor T6, the potential of the fourth node N4 remains high, and the seventh transistor T7 is turned off. At this time, the output terminal OUT remains to output a low-level signal.

[0120] In the embodiment of the present disclosure, the first clock signal CK1 jumps from high level to low level earlier than the second clock signal CK2. Therefore, when the second clock signal CK2 is high in the stage S1, the low level of the first node N1 controls the third transistor T3 to be turned on, and the first clock signal CK1 can pull the potential of the fifth node N5 low in advance, so that the fourth transistor T4 is turned on. If the fourth transistor T4 remains to be turned on, when the input signal INPUT is high, the potential of the fourth node N4 can remain low, thereby controlling the output terminal OUT to stably output a high-level signal. In addition, the potential of the fifth node N5 can also be further pulled low by the first capacitor C1, thereby controlling the output terminal OUT to stably output a high-level signal.

[0121] In the embodiment of the present disclosure, the timing change of the first clock signal CK1 can also be the same as that of the second clock signal CK2. For example, the control electrode of the first transistor T1 and the second electrode of the third transistor T3 are electrically connected with the first clock terminal CK1.

[0122] In the embodiment of the present disclosure, the shift register 600 is a circuit structure of 8T3C, the circuit connection relationship is simple, the number of transistors and capacitors is less, the space occupation is smaller, and it is conducive to the narrowing of the display panel frame.

[0123] Figure 7 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0124] In the embodiment of the present disclosure, the shift register 700 includes the first transistor T1 to the ninth transistor T9 and the first capacitor C1 to the third capacitor C3. The shift register 700 including the first transistor T1 to the eighth transistor T8 and the first capacitor C1 to the third capacitor C3 can refer to the shift register 600 described in the foregoing, and will not be described here for the sake of simplicity.

[0125] In the embodiment of the present disclosure, the ninth transistor T9 can be the second control circuit described in the foregoing. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the third clock terminal CK3.

[0126] In the embodiments of the present disclosure, for example, in Figure 6B In the fourth stage S4 shown, the ninth transistor T9 is turned on based on the low potential of the first node N1. The third clock terminal CK3 is written to the second node N2, and the potential of the second node N2 is pulled high. When the fourth transistor T4 is turned on, the potential of the second node N2 is provided to the fourth node N4, ensuring that the potential of the fourth node N4 does not drop, thereby ensuring that the seventh transistor T7 is completely in the off state.

[0127] Figure 8 FIG. 8 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0128] In the embodiments of the present disclosure, the shift register 800 includes the first to eighth transistors T1-T8, the tenth transistor T10, and the first to third capacitors C1-C3. The shift register 900 includes the first to eighth transistors T1-T8 and the first to third capacitors C1-C3, which can refer to the shift register 600 described above, and will not be described again for simplicity.

[0129] In the embodiments of the present disclosure, the tenth transistor T10 can be the third control circuit described above. The control electrode of the tenth transistor T10 is electrically connected to the control terminal CX, the first electrode of the tenth transistor T10 is electrically connected to the third node N3, and the second electrode of the tenth transistor T10 is electrically connected to the third power supply VGX.

[0130] For example, the output signal OUT can be a light-emitting control signal applied to a pixel circuit, and the transistor controlled by the light-emitting control signal is a PMOS transistor. At this time, the third power supply VGX can be the second power supply VGH. After the display panel is powered on, the low level of the control signal CX controls the tenth transistor T10 to be turned on, and the third power supply voltage VGX pulls up the potential of the third node N3. The high potential of the third node N3 can quickly control the eighth transistor T8 to be turned off, and the output terminal OUT can maintain an output high level signal. At this time, the output signal OUT controls the PMOS transistor to be turned off, thereby avoiding the phenomenon of power-on flashing screen of the display panel.

[0131] For example, the output signal OUT can be a scanning signal applied to a pixel circuit, and the transistor controlled by the scanning signal is an NMOS transistor. At this time, the third power supply VGX can be the first power supply VGL. After the display panel is powered on, the low level of the control signal CX controls the tenth transistor T10 to be turned on, and the third power supply voltage VGX pulls down the potential of the third node N3. The low potential of the third node N3 can quickly control the eighth transistor T8 to be turned on, and the output terminal OUT can output a low level signal. At this time, the output signal OUT controls the NMOS transistor to be turned off, thereby avoiding the phenomenon of power-on flashing screen of the display panel.

[0132] Figure 9A is a structural schematic diagram of a shift register according to another embodiment of the disclosure.

[0133] In the embodiment of the disclosure, the shift register 900 includes the first transistor T1, the third transistor T3 to the eighth transistor T8, and the first capacitor C1 to the third capacitor C3. The third transistor T3, the fifth transistor T5 to the eighth transistor T8, the second capacitor C3, and the third capacitor C3 included in the shift register 900 can refer to the shift register 600 described in the foregoing, and are not described again for the sake of simplicity.

[0134] In the embodiment of the disclosure, the input circuit includes the first transistor T1, the control electrode of the first transistor T1 is electrically connected to the first clock end CK1, the first electrode of the first transistor T1 is electrically connected to the input end INPUT, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0135] In the embodiment of the disclosure, the third clock signal CK3 is directly written to the second node N2. The control electrode of the fourth transistor T4 is electrically connected to the fifth node N5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node. The first end of the first capacitor C1 is electrically connected to the second node, and the second end of the first capacitor C1 is electrically connected to the fifth node N5.

[0136] Figure 9B is a signal timing diagram of a shift register according to an embodiment of the disclosure. Figure 9B The potential changes of signals and nodes in the shift register 900 are shown.

[0137] As shown in Figure 9B , the potential changes of the input signal INPUT, the first clock signal CK1, the third clock signal CK3, the output signal OUT, the first node N1, and the third node N3 can refer to the timing waveform described in Figure 6B , and are not described again for the sake of simplicity.

[0138] In the embodiment of the disclosure, under the action of the first capacitor C1 and the third capacitor C3, the potentials of the fifth node N5 and the fourth node N4 are switched between high and low levels, so that the seventh transistor T7 is switched between conduction and cutoff. When the seventh transistor T7 is turned on, the output end OUT outputs a high-level signal. When the seventh transistor T7 is cut off, the output end OUT maintains the high-level signal output in the previous stage.

[0139] In the embodiment of the disclosure, the shift register 900 is a 7T3C circuit structure, further simplifying the circuit connection relationship, the number of transistors and capacitors is small, the space occupation is small, and it is conducive to the narrowing of the display panel frame.

[0140] Figure 10A is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0141] In the embodiment of the present disclosure, the shift register 1000 includes the first transistor T1, the third transistor T3 to the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, and the first capacitor C1 to the fourth capacitor C4. The first transistor T1, the fourth transistor T4 to the eighth transistor T8, and the first capacitor C1 to the third capacitor C3 included in the shift register 1000 can refer to the shift register 900 described in the foregoing, and are not described again for the sake of simplicity.

[0142] In the embodiment of the present disclosure, the control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the fifth node N5, and the second electrode of the third transistor T3 is electrically connected to the second clock end CK2.

[0143] The control electrode of the eleventh transistor T11 is electrically connected to the fourth node N4, the first electrode of the eleventh transistor T11 is electrically connected to the second power supply VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the sixth node N6.

[0144] The control electrode of the twelfth transistor T12 is electrically connected to the third node N3, the first electrode of the twelfth transistor T12 is electrically connected to the sixth node N6, and the second electrode of the twelfth transistor T12 is electrically connected to the second clock end CK2.

[0145] The first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and the second end of the fourth capacitor C4 is electrically connected to the third node N3.

[0146] Figure 10B is a signal timing diagram of a shift register according to an embodiment of the present disclosure. Figure 10B The potential changes of the signals and nodes in the shift register 1000 are shown.

[0147] As shown in Figure 10B , the potential changes of the input signal INPUT, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the output signal OUT, the first node N1, and the third node N3 can refer to the timing waveform described in Figure 6B , and are not described again for the sake of simplicity.

[0148] In this embodiment, when the input signal INPUT is high, and the first clock signal CK1 transitions from high to low, the second clock signal CK2 remains high. The first transistor T1 is turned on, and the high level of the input signal INPUT is written to the first node N1. When the second clock signal CK2 transitions from high to low, the third transistor T3 is already cut off by the high potential of the first node N1. At this time, the low level of the second clock signal CK2 is not partially written to the fifth node N5 through the third transistor T3, thus ensuring that the fifth node N5 remains high. The fourth transistor T4 is turned off, therefore, the potential of the fourth node N4 can remain at the low potential of the previous stage, and the second power supply tower VGH can be stably output through the turned-on seventh transistor T7, with the output terminal OUT stably outputting a high-level signal.

[0149] In this embodiment of the disclosure, when the potential of the fourth node N4 is kept at a low potential, the eleventh transistor T11 is turned on, and the second power supply voltage VGH is written to the sixth node N6 through the eleventh transistor T11, and the potential of the sixth node N6 is kept at a high level.

[0150] When the input signal INPUT is low and the first clock signal CK1 transitions from high to low, the low level of the input signal INPUT is written to the third node N3 through the first transistor T1 and the fifth transistor T5. At this time, the twelfth transistor T12 is turned on. When the second clock signal CK2 transitions from high to low, it pulls down the potential of the sixth node N6. Then, under the action of the fourth capacitor C4, the potential of the third node N3 is quickly pulled low, thus quickly turning on the eighth transistor T8. This achieves a rapid pull-down of the output terminal OUT, increasing the drop speed of the output signal OUT and reducing the drop time of the OUT signal.

[0151] Figure 11A This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure.

[0152] like Figure 11A As shown, the drive circuit 1100a includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include the first-stage shift register ST1, the third-stage shift register ST2, ..., the Mth-stage shift register STM.

[0153] In the embodiments of the present disclosure, the shift register ST1 can be any one of the shift register 100, the shift register 200, the shift register 300, the shift register 400, the shift register 500, the shift register 600, the shift register 700, the shift register 800, the shift register 900 and the shift register 1000 described above. For example, the M shift registers are all the shift register 300. For example, the M shift registers are all the shift register 500. Details are not described herein again.

[0154] In the embodiments of the present disclosure, in the M shift registers in cascade, the input signal INPUT of the input end INPUT of the first stage shift register ST1 is the start signal STV, the input end INPUT of the mth stage shift register is electrically connected with the output end OUT(m-1) of the (m-1)th stage shift register. The input end INPUT of the (m+1)th stage shift register is electrically connected with the output end OUT(m) of the mth stage shift register, 1 < m ≤ M-1, and m is an integer. For example, the input end INPUT of the second stage shift register ST2 is electrically connected with the output end OUT(1) of the first stage shift register ST1.

[0155] Figure 11B FIG. 6 is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0156] In the embodiments of the present disclosure, the driving circuit 1100b includes M shift registers in cascade, and the cascade mode of the M shift registers can refer to the driving circuit 1100a.

[0157] In the embodiments of the present disclosure, the shift register ST1 can be any one of the shift register 100, the shift register 200, the shift register 300, the shift register 400, the shift register 500, the shift register 600, the shift register 700 and the shift register 800 described above.

[0158] In the embodiments of the present disclosure, the driving circuit 1100b includes a first clock signal line ck1, a second clock signal line ck2 and a third clock signal line ck3. The first clock end CK1 of the mth stage shift register is electrically connected with the first clock signal line ck1, the second clock end CK2 of the mth stage shift register is electrically connected with the second clock signal line ck2, and the third clock end CK3 of the mth stage shift register is electrically connected with the third clock signal line ck3.

[0159] The signal timing provided by the first clock signal line ck1, the second clock signal line ck2 and the third clock signal line ck3 can refer to the timing of the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 provided by Figure 6B The timing of the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 provided by

[0160] In the embodiment of the present disclosure, the driving circuit 1100b further comprises a fourth clock signal line ck4. The first clock signal line ck1 provides a clock signal different from the clock signal provided by the third clock signal line ck3, and the second clock signal line ck2 and the fourth clock signal line ck4 provide clock signals different from each other.

[0161] For example, the control electrode of the first transistor T1 in the mth stage of the shift register is electrically connected to the second clock signal line ck2, the control electrode of the second transistor T2 in the mth stage of the shift register is electrically connected to the third clock signal line ck3, and the second electrode of the third transistor T3 in the mth stage of the shift register is electrically connected to the first clock signal line ck1.

[0162] For example, the control electrode of the first transistor T1 in the mth stage of the shift register is electrically connected to the second clock signal line ck2, the control electrode of the second transistor T2 in the mth stage of the shift register is electrically connected to the third clock signal line ck3, and the second electrode of the third transistor T3 in the mth stage of the shift register is electrically connected to the first clock signal line ck1.

[0163] When the clock signal provided by the first clock signal line ck1 jumps from high level to low level, the clock signal provided by the second clock signal line ck2 is still high level. When the clock signal provided by the second clock signal line ck2 jumps from low level to high level, the clock signal provided by the first clock signal line ck1 is still low level.

[0164] When the clock signal provided by the third clock signal line ck3 jumps from high level to low level, the clock signal provided by the fourth clock signal line ck4 is still high level. When the clock signal provided by the fourth clock signal line ck4 jumps from low level to high level, the clock signal provided by the third clock signal line ck3 is still low level.

[0165] For example, the first clock terminal CK1 of the first stage of the shift register is electrically connected to the first clock signal line ck1, the second clock terminal CK2 of the first stage of the shift register is electrically connected to the second clock signal line ck2, and the third clock terminal CK3 of the first stage of the shift register is electrically connected to the third clock signal line ck3. The first clock terminal CK1 of the second stage of the shift register is electrically connected to the third clock signal line ck3, the second clock terminal CK2 of the second stage of the shift register is electrically connected to the fourth clock signal line ck4, and the third clock terminal CK3 of the second stage of the shift register is electrically connected to the first clock signal line ck1.

[0166] Figure 11C FIG. 6 is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0167] In the embodiment of the present disclosure, the driving circuit 1100c includes M cascaded shift registers, and the cascaded manner of the M shift registers can refer to the driving circuit 1100a.

[0168] In the embodiment of the present disclosure, the shift register ST1 can be any one of the shift register 100, the shift register 200, the shift register 300, the shift register 400, the shift register 500, the shift register 600, the shift register 700, the shift register 800 and the shift register 900 described above. For the shift register 100, the shift register 200, the shift register 300, the shift register 400, the shift register 500, the shift register 600, the shift register 700 and the shift register 800, the first clock end CK1 and the second clock end CK2 are connected to the same clock signal line.

[0169] In the embodiment of the present disclosure, the driving circuit 1100c includes a first clock signal line ck1 and a third clock signal line ck3. The first clock end CK1 and the second clock end CK2 of the mth shift register are electrically connected to the first clock signal line ck1, and the third clock end CK3 of the mth shift register is electrically connected to the third clock signal line ck3.

[0170] For example, the first clock end CK1 and the second clock end CK2 of the first shift register are electrically connected to the first clock signal line ck1, and the third clock end CK3 of the first shift register is electrically connected to the third clock signal line ck3. The first clock end CK1 and the second clock end CK2 of the second shift register are electrically connected to the third clock signal line ck3, and the third clock end CK3 of the second shift register is electrically connected to the first clock signal line ck1.

[0171] Figure 11D FIG. 11 is a structural schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0172] In the embodiment of the present disclosure, the driving circuit 1100d includes M cascaded shift registers, and the cascaded manner of the M shift registers can refer to the driving circuit 1100a.

[0173] In the embodiment of the present disclosure, the shift register ST1 can be the shift register 900 described above.

[0174] In the embodiment of the present disclosure, the driving circuit 1100d includes a first clock signal line ck1, a second clock signal line ck2, a third clock signal line ck3 and a fourth clock signal line ck4.

[0175] For example, the first clock terminal CK1 of the first stage shift register is electrically connected with the second clock signal line ck2, the second clock terminal CK2 of the first stage shift register is electrically connected with the first clock signal line ck1, and the third clock terminal CK3 of the first stage shift register is electrically connected with the third clock signal line ck3. The first clock terminal CK1 of the second stage shift register is electrically connected with the fourth clock signal line ck4, the second clock terminal CK2 of the second stage shift register is electrically connected with the third clock signal line ck3, and the third clock terminal CK3 of the second stage shift register is electrically connected with the first clock signal line ck1.

[0176] Figure 12A is a signal timing diagram of the driving circuit according to an embodiment of the present disclosure. Figure 12A The timing changes of the clock signals output by the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3 and the fourth clock signal line ck4 in the driving circuit 1100b and the timing changes of the output signals of the first stage shift register, the second stage shift register, the third stage shift register and the fourth stage shift register are shown.

[0177] As shown in Figure 12A , the output signals of the first stage shift register, the second stage shift register, the third stage shift register and the fourth stage shift register are sequentially shifted and output.

[0178] For example, the timing change of the output signal OUT(1) of the first stage shift register can refer to the change process described in Figure 6B , which will not be described again for the sake of simplicity.

[0179] Figure 12B is a signal timing diagram of the driving circuit according to an embodiment of the present disclosure. Figure 12B The timing changes of the clock signals output by the first clock signal line ck1, the second clock signal line ck2 and the third clock signal line ck3 in the driving circuit 1100d and the timing changes of the output signals of the first stage shift register, the second stage shift register, the third stage shift register and the fourth stage shift register are shown.

[0180] As shown in Figure 12B , the output signals of the first stage shift register, the second stage shift register, the third stage shift register and the fourth stage shift register are sequentially shifted and output.

[0181] For example, the timing change of the output signal OUT(1) of the first stage shift register can refer to the change process described in Figure 10B , which will not be described again for the sake of simplicity.

[0182] Figure 13 is a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0183] like Figure 13 As shown, the display device 1300 may include a driving circuit 1310.

[0184] In this embodiment, the driving circuit 1310 can be any one of the driving circuits 1100a, 1100b, 1100c and 1100d described above, and will not be repeated here.

[0185] Figure 14 This is a flowchart of a driving method according to an embodiment of the present disclosure.

[0186] like Figure 14 As shown, the driving method may include operations S1410 to S1450.

[0187] In operation of S1410, in the first stage, the input signal is at the first level, the first clock signal is at the second level, and the third clock signal is at the first level.

[0188] In operation S1420, in the second stage, the input signal is at the first level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0189] During operation of S1430, in the third stage, the input signal is at the second level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0190] During operation of S1440, in the fourth stage, the input signal is at the second level, the first clock signal is at the second level, and the third clock signal is at the first level.

[0191] When operating S1450, the input signal is at the second level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0192] In this embodiment of the disclosure, operations S1410 to S1450 are similar to the operations performed by the shift register 600 described above, and will not be repeated here.

[0193] In this embodiment of the disclosure, the first stage and Figure 6B The operation of the first stage S1 shown is similar, and the second stage includes... Figure 6B The second stage S2 operation shown, the third stage and Figure 6B The operation of the third stage S3 shown is similar, and the fourth stage is similar. Figure 6B The operation of the fourth stage S4 shown is similar, and the fifth stage is the same. Figure 6B The operation of the fifth stage S5 shown is similar. For the sake of simplicity, the same parts will not be described again in this disclosure.

[0194] In the embodiments of the present disclosure, the first level is high level and the second level is low level. The first level can also be low level and the second level can be high level according to the type of the transistor in the shift register.

[0195] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0196] Those skilled in the art can understand that the features described in various embodiments of the present disclosure and / or claims can be combined and / or integrated, even if such combinations or integrations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure and / or claims can be combined and / or integrated in various combinations, without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0197] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: The input circuit is configured to provide an input signal from the input terminal to the first node under the control of a first clock signal from a first clock terminal or a second clock signal from a second clock terminal, and to control the potential of the second node using a first power supply voltage from a first power supply or a third clock signal from a third clock terminal. The first control circuit is configured to provide the potential of the first node to the third node under the control of the first power supply voltage, and to provide the potential of the second node to the fourth node under the control of the potential of the first node and the first clock signal or under the control of the potential of the first node and the second clock signal, or to provide the second power supply voltage of the second power supply and the potential of the second node to the fourth node. as well as The output circuit is configured to provide either the first power supply voltage or the second power supply voltage to the output terminal as an output signal, under the control of the potential of the third node and the potential of the fourth node.

2. The shift register according to claim 1, wherein, The first control circuit includes: The first control unit is configured to control the potential of the fourth node using the potential of the second node under the control of the potential of the first node and the first clock signal; The second control unit is configured to control the potential of the fourth node using the second power supply voltage, under the control of the potential of the first node; and The third control unit is configured to provide the potential of the first node to the third node under the control of the first power supply voltage.

3. The shift register according to claim 1, wherein, The first control circuit includes: The first control unit is configured to control the potential of the fourth node using the potential of the second node under the control of the potential of the first node and the second clock signal; The second control unit is configured to control the potential of the fourth node using the second power supply voltage under the control of the potential of the first node; A third control unit is configured to provide the potential of the first node to the third node under the control of the first power supply voltage; and The fourth control unit is configured to control the potential of the third node using the second power supply voltage and the second clock signal, under the control of the potential of the fourth node.

4. The shift register according to claim 1, further comprising: The second control circuit is configured to control the potential of the second node using the third clock signal, under the control of the potential of the first node.

5. The shift register according to claim 1, further comprising: The third control circuit is configured to control the potential of the third node using the third power supply voltage of the third power supply under the control of the control signal.

6. The shift register according to claim 1, wherein, The input circuit includes a first transistor and a second transistor; Wherein, the control electrode of the first transistor is electrically connected to the second clock terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the third clock terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the second node.

7. The shift register according to claim 1, wherein, The first control circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the fifth node, and the second electrode of the third transistor is electrically connected to the first clock terminal. The control electrode of the fourth transistor is electrically connected to the fifth node, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first power supply, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the second power supply. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the fifth node.

8. The shift register according to claim 1, wherein, The output circuit includes a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second power supply, and the second electrode of the seventh transistor is electrically connected to the output terminal. The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the output terminal, and the second electrode of the eighth transistor is electrically connected to the first power supply. The first terminal of the second capacitor is electrically connected to the output terminal, and the second terminal of the second capacitor is electrically connected to the third node; The first terminal of the third capacitor is electrically connected to the second power source, and the second terminal of the third capacitor is electrically connected to the fourth node.

9. The shift register according to claim 4, wherein, The second control circuit includes a ninth transistor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the third clock terminal.

10. The shift register according to claim 5, wherein, The third control circuit includes a tenth transistor; The control electrode of the tenth transistor is electrically connected to the control terminal, the first electrode of the tenth transistor is electrically connected to the third node, and the second electrode of the tenth transistor is electrically connected to the third power supply.

11. The shift register of claim 1, wherein the first control circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, an eleventh transistor, a twelfth transistor, a first capacitor, and a fourth capacitor; in, The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the fifth node, and the second electrode of the third transistor is electrically connected to the second clock terminal. The control electrode of the fourth transistor is electrically connected to the fifth node, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first power supply, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the second power supply. The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode of the eleventh transistor is electrically connected to the second power supply, and the second electrode of the eleventh transistor is electrically connected to the sixth node. The control electrode of the twelfth transistor is electrically connected to the third node, the first electrode of the twelfth transistor is electrically connected to the sixth node, and the second electrode of the twelfth transistor is electrically connected to the second clock terminal; The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the fifth node. The first terminal of the fourth capacitor is electrically connected to the sixth node, and the second terminal of the fourth capacitor is electrically connected to the third node.

12. A driving circuit comprising M cascaded shift registers as described in any one of claims 1 to 11, wherein the input terminal of the m-th shift register is electrically connected to the output terminal of the (m-1)-th shift register, 1 < m ≤ M, where m is an integer and M is an integer greater than 1.

13. The driving circuit according to claim 12, further comprising: First clock signal line, second clock signal line, and third clock signal line; Specifically, the first clock terminal of the m-th stage shift register is electrically connected to the first clock signal line, the second clock terminal of the m-th stage shift register is electrically connected to the second clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line.

14. The driving circuit according to claim 12, further comprising: First clock signal line and third clock signal line; The first and second clock terminals of the m-th stage shift register are both electrically connected to the first clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line.

15. A display device comprising the driving circuit as described in claims 12 to 14.

16. A driving method applied to a shift register as described in any one of claims 1-11, comprising: In the first stage, the input signal is at a first level, the first clock signal is at a second level, and the third clock signal is at a first level; In the second stage, the input signal is at a first level, the first clock signal is at a first level, and the third clock signal is at a second level; In the third stage, the input signal is at a second level, the first clock signal is at a first level, and the third clock signal is at a second level; In the fourth stage, the input signal is at the second level, the first clock signal is at the second level, and the third clock signal is at the first level; as well as In the fifth stage, the input signal is at the second level, the first clock signal is at the first level, and the third clock signal is at the second level.

17. The driving method according to claim 16, wherein, When the first clock signal switches from the first level to the second level, the second clock signal is at the first level; as well as When the second clock signal switches from the second level to the first level, the first clock signal is at the second level.

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