Memory devices and memory systems

Abstract

This disclosure provides a memory device and a memory system; wherein the memory device includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes selected memory cells; the peripheral circuitry is configured to: when it is determined that a first write operation has been performed on the selected memory cell, perform a read operation on the selected memory cell; and determine whether to perform a second write operation on the selected memory cell based on the direction of a first pulse, the direction of a second pulse, and the read result of the read operation; the first pulse is a pulse applied to the selected memory cell when the first write operation is performed; and the second pulse is a pulse applied to the selected memory cell when the read operation is performed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory device and memory system. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices (such as computers, wireless communication devices, cameras, digital displays, and the like). This information is typically stored by editing different states of the memory device. With the rapid development of artificial intelligence, higher demands are being placed on electronic devices such as Dynamic Random Access Memory (DRAM) in terms of computing performance, read performance, write performance, reliability, and data retention capabilities.

[0003] Compared to 3D XPoint, Selector Only Memory (SOM) has advantages such as simple structure, high miniaturization, fast data read and write speed, good cycle life, vertical stackability, and low write crosstalk caused by thermal effects. It is a promising non-volatile memory with obvious advantages and good application prospects in fields such as Compute Express Link (CXL) and High Bandwidth Memory (HBM). Summary of the Invention

[0004] In view of the above, this disclosure provides a memory device and a memory system. To achieve the above objectives, the technical solution of this disclosure is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory device including: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes selected memory cells; the peripheral circuitry is configured to: when it is determined that a first write operation has been performed on the selected memory cell, perform a read operation on the selected memory cell; and determine whether to perform a second write operation on the selected memory cell based on the direction of a first pulse, the direction of a second pulse, and the read result of the read operation; the first pulse is a pulse applied to the selected memory cell when the first write operation is performed; and the second pulse is a pulse applied to the selected memory cell when the read operation is performed.

[0006] In some embodiments, before performing the read operation, the selected storage unit is in a first state or a second state.

[0007] In some embodiments, the peripheral circuit is configured to: determine whether to perform a second write operation on the selected memory cell based on whether the direction of the first pulse is the same as the direction of the second pulse; and based on the storage state of the selected memory cell displayed in the read result; the storage state of the selected memory cell displayed in the read result includes the first state and the second state.

[0008] In some embodiments, before performing the read operation, the selected memory cell is in a first state, and the peripheral circuit is configured to: determine that the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the selected memory cell is in a second state, and then perform the second write operation on the selected memory cell; or, determine that the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the selected memory cell is in the first state, and then perform the second write operation on the selected memory cell.

[0009] In some embodiments, before performing the read operation, the selected memory cell is in a second state, and the peripheral circuit is configured to: determine that the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the selected memory cell is in a first state, and then perform the second write operation on the selected memory cell; or, determine that the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the selected memory cell is in a second state, and then perform the second write operation on the selected memory cell.

[0010] In some embodiments, the peripheral circuit is further configured to: apply a third pulse to the selected memory cell to perform the second write operation; wherein, when the direction of the first pulse is the same as the direction of the second pulse, the direction of the third pulse is opposite to the direction of the first pulse; and when the direction of the first pulse is opposite to the direction of the second pulse, the direction of the third pulse is the same as the direction of the first pulse.

[0011] In some embodiments, when the read result shows that the storage state of the selected storage cell is a first state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the first state; when the read result shows that the storage state of the selected storage cell is a second state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the second state.

[0012] In some embodiments, the peripheral circuitry is configured to: after performing the read operation on the selected memory cell once, or after performing the read operation on the selected memory cell multiple times consecutively, determine whether to perform a second write operation on the selected memory cell.

[0013] In some embodiments, the memory device includes selector-only memory.

[0014] Secondly, embodiments of this disclosure provide a memory system, including: one or more memory devices as described in the above embodiments of this disclosure; and a memory controller coupled to the memory devices for controlling the memory devices.

[0015] This disclosure provides a memory device and a memory system. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes selected memory cells. The peripheral circuitry is configured to: when a first write operation has been performed on the selected memory cell, perform a read operation on the selected memory cell; and determine whether to perform a second write operation on the selected memory cell based on the direction of a first pulse, the direction of a second pulse, and the read result of the read operation. The first pulse is a pulse applied to the selected memory cell during the first write operation; the second pulse is a pulse applied to the selected memory cell during the read operation. In this embodiment of the present disclosure, after performing a first write operation and a read operation on a selected memory cell, in order to prevent a large voltage difference from being generated due to the different polarities of the second pulse applied to the selected memory cell during the read operation and the first pulse applied to the selected memory cell during the first write operation, which could lead to a change in the storage state of the selected memory cell, after performing the read operation, the direction of the first pulse, the direction of the second pulse, and the read result are judged, and a decision is made on whether to perform a second write operation on the selected memory cell based on the judgment result. By performing the second write operation, the storage state of the selected memory cell after the second write operation can be made the same as the storage state of the selected memory cell after the first write operation and before the read operation. This reduces read interference caused by the read operation to the selected memory cell and improves the read performance and reliability of the memory device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0017] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0018] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0019] Figure 3 This is a cross-sectional schematic diagram of a memory cell array in an SOM device according to an embodiment of the present disclosure;

[0020] Figure 4 This is a schematic diagram of the threshold voltage distribution in the SET and RESET states according to an embodiment of this disclosure;

[0021] Figure 5 This is a schematic diagram of two pulse directions provided in one embodiment of the present disclosure;

[0022] Figure 6a A schematic diagram illustrating the generation of overshoot instantaneous current when the storage state changes from SET state to RESET state according to an embodiment of this disclosure;

[0023] Figure 6b for Figure 6a The diagram shows the change of overshoot instantaneous current over time.

[0024] Figure 7 This is a schematic diagram illustrating an operation method of a memory device provided in an embodiment of the present disclosure;

[0025] Figure 8 This is a schematic flowchart illustrating the operation method of a memory device according to an embodiment of the present disclosure;

[0026] Figure 9 Schematic diagram of the directions of the first pulse and the second pulse provided in an embodiment of this disclosure. Figure 1 ;

[0027] Figure 10 This is a schematic diagram of the directions of the first pulse and the second pulse provided in an embodiment of the present disclosure;

[0028] Figure 11 Schematic diagram of the directions of the first pulse and the second pulse provided in an embodiment of this disclosure. Figure 3 ;

[0029] Figure 12 Schematic diagram of the directions of the first pulse and the second pulse provided in an embodiment of this disclosure. Figure 4 . Detailed Implementation

[0030] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0032] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0037] Memory devices can include magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), ferroelectric RAM (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), flash memory, phase-change memory (PCM), selector-only memory (SOM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for extended periods without external power. Volatile memory cells lose their stored state over time after power loss and typically require periodic refresh via external power.

[0038] For ease of understanding, the memory device in the embodiments of this disclosure is described using a selector-only memory (SOM) as an example.

[0039] Figure 1A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or retrieve data from the memory device 104.

[0040] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as solid state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0041] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0042] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0043] Return to reference Figure 1Each memory device 104 may include a memory cell array 1041 and peripheral circuitry 1042, which may be integrated on the same or different dies, allowing for wider buses and higher operating speeds.

[0044] The peripheral circuitry 1042 may include any suitable digital, analog, and / or mixed-signal circuitry to facilitate operation of the memory device. For example, the peripheral circuitry may include control logic, a data buffer, a decoder (also called a decoder), a driver, and read / write circuitry. When the control logic receives a read / write operation command and address data, under the control logic's control, the decoder can apply the corresponding voltage generated from the driver to the corresponding word line (WL) and bit line (BL) based on the decoded address to perform a data read or write operation and interact with the outside world through the data buffer. For example, after receiving a read or write operation command and address data, the control logic can, under the control of the decoder, determine the selection word line and selection bit line corresponding to the selected memory cell from among multiple memory cells. For example, the memory cell can be controlled by a row decoder and a column decoder. Specifically: the row decoder can receive a row address from the memory controller and activate the appropriate word line based on the received row address. The column decoder can receive a column address from the memory controller and activate the appropriate bit line, activating the memory cell at the intersection of the word line and the bit line.

[0045] The memory cell array 1041 may include at least one memory array block, each memory array block may include multiple memory cell layers stacked along the Z-axis, and each memory cell layer may include multiple memory cells. Each memory cell may include a first electrode, a selection memory, and a second electrode stacked along the Z-axis, wherein each row of memory cells is connected to an address line (e.g., a word line), and each column of memory cells is connected to an address line (e.g., a bit line). It should be understood that a memory cell may be located at the intersection of two address lines, and this intersection may be referred to as the address of the memory cell; other memory cells connected to the common wire may be referred to as unselected memory cells.

[0046] For example, refer to Figure 3 and Figure 5The memory cell array 1041 includes a first memory cell layer located between a first type of address line 301 and a second type of address line 303, and a second memory cell layer located between the second type of address line 303 and a third type of address line 305. The first memory cell layer includes a plurality of first memory cells 302, and the second memory cell layer includes a plurality of second memory cells 304. Each first memory cell 302 includes a first electrode 3021, a selection memory 3023, and a second electrode 3025. Each second memory cell 304 includes a first electrode 3041, a selection memory 3043, and a second electrode 3045. In some embodiments, the first type of address lines are perpendicular to the second type of address lines, and the first type of address lines are parallel to the third type of address lines. Exemplarily, the first type of address lines and the third type of address lines are word lines (WL), and the second type of address lines are bit lines (BL). It should be understood that word lines (WL) and bit lines (BL) are interchangeable.

[0047] In some embodiments, the selection memory has both storage and switching functions, that is, the material of the selection memory is a dual-function material (DFM). For example, the material of the selection memory can include any suitable bidirectional threshold switch (OTS) material, which can include chalcogenide alloys such as germanium (Ge), arsenic (As), and selenium (Se) and their compounds. The first electrode and the second electrode can be the same material or different materials. The materials of the first electrode and the second electrode include, but are not limited to, copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and their compounds, conductive doped semiconductors, etc.

[0048] In some embodiments, during a write operation, each memory cell of a memory device, such as an SOM device, can be programmed to store two states: a logic "1" (low resistance, SET state) and a logic "0" (high resistance, RESET state). Applying a positive pulse to a selected memory cell causes the elements in the OTS material to migrate forward or become positively polarized; this process is called the SET process, or SET operation. Applying a negative pulse (or negative pulse) to a selected memory cell causes the elements in the OTS material to migrate backward or become reversely polarized; this process is called the RESET process, or RESET operation. In other devices, more than two states can be stored, which will not be elaborated here.

[0049] In some embodiments, during a read operation, the SOM device can apply a pulse voltage, i.e., a read voltage V, between the SET and RESET state threshold transition voltages to the memory cell. Read Data is obtained by measuring the resistance values ​​of the OTS material in two states within the memory cell. It should be understood that a limited number of read voltage readings generally will not change the memory state of the SOM device.

[0050] It should be noted that, as the storage medium in the memory cell, the OTS material results in a significant threshold voltage difference between the two storage states; this difference is approximately 1V. For example, refer to... Figure 4 Threshold voltage V in SET state th1 Threshold voltage V of the RESET state th2 The voltage difference between them (i.e., the memory window, MW) is approximately 1.2V, such as MW ~ 1.2V. Thus, the read voltage V Read It can be located in V th1 and V th2 The spaces between them are used to distinguish the two storage states of a storage unit.

[0051] It should be noted that during a write operation, the direction of the current (pulse) can be either positive or negative during the SET process, and the direction of the current (pulse) can also be either positive or negative during the RESET process, but the directions of the current (pulse) are opposite during the SET and RESET processes. For example, refer to... Figure 5 During the SET process, the current (pulse) flows from the word line WL to the bit line BL, which is a positive pulse (①). During the RESET process, the current (pulse) flows from the bit line BL to the word line WL, which is a negative pulse (②). This can also be understood as the current direction being different for the same memory cell during different write operations. Furthermore, during a read operation, the direction of the current applied to the selected memory cell can be either positive or negative; however, it should be understood that the direction of the read current remains unchanged across multiple read operations. In other words, the direction of the current (pulse) during a read operation may be the same as or different from the direction of the current (pulse) during a write operation. However, when the two directions are different and the applied voltage reaches the threshold transition voltage of the OTS material, the resistance of the OTS material in the SET state decreases, and there is a large inrush current in the circuit, causing the state of the memory cell to flip from the SET state to the RESET state. Alternatively, the inrush current in the RESET state may be too large, causing the state of the memory cell to flip, and the memory cell to change from the RESET state to the SET state. This can lead to bit errors in the memory cell, reducing the read performance and reliability of the memory device.

[0052] For example, refer to Figure 6a , Figure 6b , Figure 6a This is a schematic diagram illustrating the generation of overshoot instantaneous current when the storage state changes from SET state to RESET state in one embodiment of this disclosure; Figure 6b for Figure 6a A schematic diagram illustrating the change of overshoot instantaneous current over time; as shown in the figure. Figure 6aAs shown, the horizontal axis represents the voltage (V) of the memory cell. CELL The vertical axis represents the current (I) of the storage cell. CELL Solid lines represent the SET state, and dashed lines represent the RESET state; when the storage state of a memory cell is SET, a read voltage (V) is applied to the memory cell. Read The pulse direction for reading the voltage is opposite to that in the SET process (i.e., the pulse direction for reading the voltage is the same as that in the RESET process). At this time, the resulting overshoot instantaneous current (I) inrush (Too large, refer to) Figure 6b Overshoot instantaneous current I inrush The threshold current I during the RESET process was exceeded. RESET , that is I inrush >I RESET This causes the storage state of the memory cell to become RESET. In particular, after multiple repeated reads, the effect of the overshoot instantaneous current will accumulate, thus affecting the storage state of the SOM device.

[0053] In other words, applying a read voltage (V) to the memory cell Read The process of performing a read operation is equivalent to performing a RESET operation on the memory cell, causing the memory cell's state to change to RESET after the read operation. This transition from SET to RESET state can lead to bit errors in the memory cell and reduce the read performance of the memory device. Furthermore, during a RESET read, if the read direction is opposite to the operation direction, there is an unavoidable overshoot current in the circuit, which can also cause the SOM device to transition from RESET to SET state.

[0054] Based on this, embodiments of the present disclosure provide a memory device and its operation method, which can reduce read interference caused by read operations to memory cells and improve the read performance and reliability of the memory device. The memory device includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of memory cells connected between first type address lines and second type address lines; the plurality of memory cells includes a selected memory cell; here, the selected memory cell is a memory cell connected between the first address lines and the second address lines, the first address lines are selected address lines in the first type address lines, and the second address lines are selected address lines in the second type address lines. Exemplarily, the first type address lines are word lines, the second type address lines are bit lines, and the selected memory cell is a target memory cell connected between the selected word lines and the selected bit lines.

[0055] refer to Figure 7 , Figure 7 This is a schematic diagram illustrating an operation method of a memory device provided in an embodiment of this disclosure; as shown below. Figure 7 As shown, the operation method includes the following steps:

[0056] Step S701: When it is determined that the selected memory cell has performed the first write operation, a read operation is performed on the selected memory cell.

[0057] Step S702: Based on the direction of the first pulse, the direction of the second pulse, and the read result of the read operation, determine whether to perform a second write operation on the selected memory cell; the first pulse is the pulse applied to the selected memory cell when performing the first write operation; the second pulse is the pulse applied to the selected memory cell when performing the read operation.

[0058] In step S701, the method includes: applying a first pulse to a selected memory cell to perform a first write operation on the selected memory cell. The first write operation can be a SET procedure, i.e., storing a state representing logic "1" in the selected memory cell; or it can be a RESET procedure, i.e., storing a state representing logic "0" in the selected memory cell. When the direction of the first pulse in the SET procedure is a first direction, the direction of the first pulse in the RESET procedure is a second direction; when the direction of the first pulse in the SET procedure is a second direction, the direction of the first pulse in the RESET procedure is the first direction; the first direction and the second direction are opposite. Here, the first direction is the direction in which the first pulse flows from the first address line to the second address line; the second direction is the direction in which the first pulse flows from the second address line to the first address line. For example, refer to... Figure 5 During the SET process, the direction of the first pulse flows from the word line WL to the bit line BL (positive ①), and during the RESET process, the direction of the first pulse flows from the bit line BL to the word line WL (negative ②). In some other specific embodiments, the direction of the current during the SET and RESET processes can also be selected and set according to requirements, which is not limited here.

[0059] After performing the first write operation, the selected memory cell can be in either a first state or a second state. Specifically, when the first write operation is a SET operation, the selected memory cell is in the first state (SET state), representing a logic "1". When the first write operation is a RESET operation, the selected memory cell is in the second state (RESET state), representing a logic "0".

[0060] Continuing with step S701, a read operation is performed on the selected memory cell. During the read operation, a second pulse is applied to the selected memory cell. The direction of the second pulse can be either a first direction (positive ①) or a second direction (negative ②). In other words, the direction of the second pulse may be the same as or different from the direction of the first pulse. Therefore, the bit error situation described in the previous embodiments may occur.

[0061] It should be noted that the process of performing a read operation may include: the host 108 sending a read command to the memory system 102; after receiving the read command from the host 108, the memory controller 106 in the memory system 102 parses the read command and, based on the parsing result, selects the memory cell to be read in the memory device 104, i.e., determines the selected memory cell. This process may also include a selected address decoding operation. After determining the selected memory cell, the read operation is performed on the selected memory cell based on the read command.

[0062] Based on this, step S702 is executed, which determines whether the direction of the first pulse and the direction of the second pulse are the same based on the storage status of the selected storage unit before and after the read operation, and determines whether to perform a second write operation on the selected storage unit based on the storage status of the selected storage unit displayed in the read result.

[0063] On the one hand, after performing the first write operation, the storage state of the selected memory cell can be determined (either the first state or the second state). On the other hand, after performing the first write operation, the direction of the first pulse is already determined, and after performing the read operation, the direction of the second pulse is already determined; in some specific embodiments, the directions of the first and second pulses can be system-defined. In other words, after performing the first write and read operations, it can be determined whether the directions of the first and second pulses are the same. Furthermore, after performing the read operation, the storage state of the selected memory cell after performing the read operation can be judged based on the result of the read operation; in other words, when the read result of the read operation shows "1", the storage state of the selected memory cell after performing the read operation is determined to be the first state, i.e., the SET state. When the read result of the read operation shows "0", the storage state of the selected memory cell after performing the read operation is determined to be the second state, i.e., the RESET state.

[0064] Thus, after determining the storage state of the selected storage unit after performing a read operation, and after determining whether the direction of the first pulse is the same as the direction of the second pulse, it can be determined whether to perform a second write operation on the selected storage unit.

[0065] In some embodiments, when the storage state of the selected storage unit is a first state before performing a read operation, the method includes: determining that the direction of the first pulse is the same as the direction of the second pulse, and when the read result shows that the storage state of the selected storage unit is a second state, performing a second write operation on the selected storage unit; or, determining that the direction of the first pulse is opposite to the direction of the second pulse, and when the read result shows that the storage state of the selected storage unit is a first state, performing a second write operation on the selected storage unit.

[0066] It should be understood that when the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is the first state, the second write operation is not performed on the selected storage unit. In this case, read operations can continue to be performed on the selected storage unit. Similarly, when the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is the second state, the second write operation is not performed on the selected storage unit. In this case, read operations can continue to be performed on the selected storage unit.

[0067] For example, before performing a read operation, the storage state of the selected storage unit is set to SET. The directions of the first pulse and the second pulse are both the first direction (e.g., positive ①) or both the second direction (e.g., negative ②). When the read result shows that the storage state of the selected storage unit is "0", a second write operation is performed on the selected storage unit.

[0068] For example, before performing a read operation, the storage state of the selected storage unit is set to SET, the direction of the first pulse is the first direction (e.g., positive ①), the direction of the second pulse is the second direction (e.g., negative ②), or, when the direction of the first pulse is the second direction (e.g., negative ②), the direction of the second pulse is the first direction (e.g., positive ①), and the read result shows that the storage state of the selected storage unit is "1", a second write operation is performed on the selected storage unit.

[0069] In other words, after the first write operation is performed, the storage state of the selected storage cell is the first state, i.e., the SET state, which means the storage state of the selected storage cell is "1". Based on this, after the read operation is performed, when the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage cell is "0", it indicates that the storage state of the selected storage cell has been flipped after the read operation. At this time, a second write operation needs to be performed on the selected storage cell, and the storage state of the selected storage cell after the second write operation should be the same as the storage state of the selected storage cell before the read operation, so as to ensure the correctness of the data in the selected storage cell.

[0070] Similarly, after the first write operation is performed, the storage status of the selected storage cell is "1"; based on this, a read operation is performed; where, when the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage status of the selected storage cell is "1", then a second write operation needs to be performed on the selected storage cell to ensure the correctness of the data in the selected storage cell.

[0071] In some embodiments, when the storage state of the selected storage unit is in the second state before performing a read operation, the method includes: determining that the direction of the first pulse is the same as the direction of the second pulse, and when the read result shows that the storage state of the selected storage unit is in the first state, performing a second write operation on the selected storage unit; or, determining that the direction of the first pulse is opposite to the direction of the second pulse, and when the read result shows that the storage state of the selected storage unit is in the second state, performing a second write operation on the selected storage unit.

[0072] For example, before performing a read operation, the storage state of the selected storage unit is set to RESET. The directions of the first pulse and the second pulse are both in the first direction (e.g., positive ①) or both in the second direction (e.g., negative ②). When the read result shows that the storage state of the selected storage unit is "1", a second write operation is performed on the selected storage unit.

[0073] For example, before performing a read operation, the storage state of the selected storage cell is set to RESET, the direction of the first pulse is a first direction (e.g., positive ①), the direction of the second pulse is a second direction (e.g., negative ②), or, when the direction of the first pulse is a second direction (e.g., negative ②), the direction of the second pulse is a first direction (e.g., positive ①), and the read result shows that the storage state of the selected storage cell is "0", a second write operation is performed on the selected storage cell.

[0074] In other words, after the first write operation is performed, the storage state of the selected storage cell is the second state, i.e., the RESET state, which means the storage state of the selected storage cell is "0". Based on this, after the read operation is performed, when the direction of the first pulse and the direction of the second pulse are the same, and the read result shows that the storage state of the selected storage cell is "1", it indicates that the storage state of the selected storage cell has been flipped after the read operation. At this time, a second write operation needs to be performed on the selected storage cell, and the storage state of the selected storage cell after the second write operation should be the same as the storage state of the selected storage cell before the read operation, so as to ensure the correctness of the data in the selected storage cell.

[0075] Similarly, after the first write operation is performed, the storage state of the selected storage cell is "0"; based on this, a read operation is performed; where, when the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage cell is "0", then a second write operation needs to be performed on the selected storage cell to ensure the correctness of the data in the selected storage cell.

[0076] In some embodiments, the method further includes: applying a third pulse to a selected memory cell to perform a second write operation; wherein, when the direction of the first pulse is the same as the direction of the second pulse, the direction of the third pulse is opposite to the direction of the first pulse. When the direction of the first pulse is opposite to the direction of the second pulse, the direction of the third pulse is the same as the direction of the first pulse.

[0077] In some embodiments, when the read result shows that the storage state of the selected storage cell is a first state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the first state; when the read result shows that the storage state of the selected storage cell is a second state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the second state.

[0078] The direction and amplitude of the third pulse will be described in detail below with reference to specific embodiments.

[0079] In some embodiments, when the storage state of the selected storage unit is in the first state before performing the read operation, and when the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is in the second state, the direction of the third pulse is opposite to the direction of the first pulse; when the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is in the first state, the direction of the third pulse is the same as the direction of the first pulse.

[0080] Furthermore, when the storage state of the selected storage unit is in the first state before performing the read operation, and when the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is in the second state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the second state; when the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is in the first state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the first state.

[0081] For example, before performing a read operation, the storage state of the selected storage cell is set to SET. When the directions of the first pulse and the second pulse are both in the first direction (e.g., positive ①), and the read result shows that the storage state of the selected storage cell is "0", the direction of the third pulse is in the second direction (e.g., negative ②). At this time, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the RESET state ("0" state).

[0082] For example, before performing a read operation, the storage state of the selected storage cell is set to SET. When the direction of the first pulse is the first direction (e.g., positive ①), the direction of the second pulse is the second direction (e.g., negative ②), and the read result shows that the storage state of the selected storage cell is "1", the direction of the third pulse is the first direction (e.g., positive ①). At this time, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the SET state ("1" state).

[0083] In some embodiments, before performing a read operation, the storage state of the selected storage unit is set to the second state. When the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is set to the first state, the direction of the third pulse is opposite to the direction of the first pulse. When the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is set to the second state, the direction of the third pulse is the same as the direction of the first pulse.

[0084] Furthermore, before performing the read operation, the storage state of the selected storage unit is set to the second state. When the direction of the first pulse is the same as the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is set to the first state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the first state. When the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows that the storage state of the selected storage unit is set to the second state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the second state.

[0085] For example, before performing a read operation, the selected memory cell is set to RESET state. When the directions of the first and second pulses are both in the first direction (e.g., positive ①), and the read result shows that the selected memory cell's storage state is "1", the direction of the third pulse is in the second direction (e.g., negative ②). At this time, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the SET state ("1" state).

[0086] For example, before performing a read operation, the selected memory cell is set to RESET. The first pulse is in the first direction (e.g., positive ①), the second pulse is in the second direction (e.g., negative ②), and the read result shows the selected memory cell's memory state as "0". Then, the third pulse is in the first direction (e.g., positive ①). At this time, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the RESET state ("0" state).

[0087] For example, the amplitude range of the first and third pulses is 3-6V. The width range of the first and third pulses is 20-500ns.

[0088] Thus, by applying a third pulse with the same or opposite direction to the first pulse to the selected memory cell, the storage state of the selected memory cell after the second write operation can be the same as the storage state of the selected memory cell after the first write operation and before the read operation. This reduces the bit error rate, minimizes read interference caused by read operations to the selected memory cell, and improves the read performance and reliability of the memory device. It is important to emphasize that the pulse amplitude and width used in the SET and RESET operations are not necessarily the same. In the second write operation, the amplitude and width of the third pulse should be consistent with the amplitude of the last write operation (SET / RESET operation) before the read operation.

[0089] To better understand this solution, the following will be combined with... Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 The above embodiments will be described in detail. Figure 9 , Figure 10 , Figure 11 , Figure 12 The horizontal axis represents time, and the vertical axis represents voltage (i.e., the amplitude of the pulse).

[0090] refer to Figure 8Step 801: Perform a first write operation on the selected memory cell, i.e., apply a first pulse to the selected memory cell; after performing the first write operation, the storage state of the selected memory cell is either SET or RESET. Step 802: Perform a selected address decoding operation to determine the target memory cell to be read, i.e., determine the selected memory cell. Step 803: Perform a read operation on the selected memory cell, i.e., apply a second pulse to the selected memory cell and obtain the read result. Step 804: Determine whether the direction of the first pulse and the direction of the second pulse are the same, and determine whether the read result of the read operation is displayed as SET or RESET. Specifically, if the storage state of the selected memory cell is SET before the read operation, and the direction of the first pulse and the direction of the second pulse are the same, and the read result is displayed as RESET, then execute step 805, i.e., perform a second write operation on the selected memory cell. If the direction of the first pulse and the direction of the second pulse are opposite, and the read result is displayed as SET, then execute step 805, i.e., perform a second write operation on the selected memory cell.

[0091] Conversely, if the selected memory cell is in the SET state before the read operation, and the direction of the first pulse is opposite to the direction of the second pulse, and the read result shows a RESET state, the read operation can continue to be performed on the selected memory cell. Similarly, if the direction of the first pulse is the same as the direction of the second pulse, and the read result shows a SET state, the read operation can continue to be performed on the selected memory cell.

[0092] For example, refer to Figure 9 The first write operation is the SET process. In the SET operation, the first pulse is in a positive direction, and in the read operation (Read), the second pulse is in a positive direction. At this point, the directions of the first and second pulses are the same. Further, the read result is evaluated. When the read result indicates that the selected memory cell is in a RESET state, a second write operation (Write) is performed on the selected memory cell. During the second write operation (Write), a third pulse is applied to the selected memory cell. The direction of the third pulse is the same as the pulse direction corresponding to the RESET state, i.e., it is a negative pulse; in other words, the direction of the third pulse is opposite to the direction of the first pulse. Here, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the RESET operation, and the width of the third pulse is the same as the width of the write pulse corresponding to the RESET operation.

[0093] For example, refer to Figure 10The first write operation is the SET process. In the SET operation, the direction of the first pulse is negative, and the direction of the second pulse in the read operation is also negative. At this time, the directions of the first pulse and the second pulse are the same. Further, the read result is judged. When the read result shows that the selected memory cell is in the RESET state, the second write operation is performed on the selected memory cell. In the second write operation, a third pulse is applied to the selected memory cell. The direction of the third pulse is the same as the pulse direction corresponding to the RESET state, that is, positive. In other words, the direction of the third pulse is opposite to the direction of the first pulse. Here, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the RESET operation, and the width of the third pulse is the same as the width of the write pulse corresponding to the RESET operation.

[0094] For example, refer to Figure 11 The first write operation is the SET process. In the SET operation, the direction of the first pulse is positive, while the direction of the second pulse in the Read operation is negative. At this time, the directions of the first pulse and the second pulse are different. Further, the read result is judged. When the read result shows that the selected memory cell is in the SET state, the second write operation is performed on the selected memory cell. In the second write operation, a third pulse is applied to the selected memory cell. The direction of the third pulse is the same as the direction of the first pulse in the SET operation, both being positive. In other words, the direction of the third pulse is the same as the direction of the first pulse; and the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the SET operation, and the width of the third pulse is the same as the width of the write pulse corresponding to the SET operation.

[0095] For example, refer to Figure 12 The first write operation is the SET process. In the SET operation, the direction of the first pulse is negative, while the direction of the second pulse in the Read operation is positive. At this time, the directions of the first pulse and the second pulse are different. Further, the read result is judged. When the read result shows that the selected memory cell is in the SET state, the second write operation is performed on the selected memory cell. In the second write operation, a third pulse is applied to the selected memory cell. The direction of the third pulse is the same as the direction of the first pulse in the SET operation, which is negative. In other words, the direction of the third pulse is the same as the direction of the first pulse; and the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the SET operation, and the width of the third pulse is the same as the width of the write pulse corresponding to the SET operation.

[0096] Thus, when the pulse direction in the first write operation is the same as the pulse direction in the read operation, and the read result shows that the storage state of the selected memory cell is different from the storage state of the selected memory cell after the first write operation, by performing a second write operation on the selected memory cell, the storage state of the selected memory cell after performing the second write operation is the same as the storage state after performing the first write operation and before performing the read operation. In this way, the bit error rate caused by the read operation to the selected memory cell can be reduced, and the read performance and reliability of the memory device can be improved.

[0097] In some embodiments, the method further includes: after performing a read operation on the selected storage unit, or after performing multiple read operations on the selected storage unit consecutively, determining whether to perform a second write operation on the selected storage unit.

[0098] Specifically, after each read operation, it can be determined whether the direction of the first pulse is the same as the direction of the second pulse, and the storage state of the selected memory cell after the read operation can be determined based on the read result; alternatively, after multiple consecutive read operations, it can be determined whether the direction of the first pulse is the same as the direction of the second pulse, and the storage state of the selected memory cell after the read operation can be determined based on the read result. Then, based on the determination result, it is decided whether to perform a second write operation on the selected memory cell.

[0099] In other words, after each read operation, the pulse direction and read result can be determined, and a second write operation can be performed based on the determination result. This can avoid bit errors in selected memory cells after read operations, improving the read performance and reliability of the memory device. Alternatively, after multiple consecutive read operations, the pulse direction and read result can be determined, and a second write operation can be performed based on the determination result. This can improve the read efficiency of the memory device while reducing the probability of bit errors in selected memory cells, thus improving the read performance and reliability of the memory device.

[0100] It should be noted that when judging the pulse direction and reading results after multiple consecutive read operations, the magnitude and direction of the multiple read currents (i.e., the second pulses) are the same or remain unchanged. When judging the reading results after multiple consecutive read operations, the result of the last read operation is used as the basis for judgment.

[0101] Based on the above-described operation method of the memory device, this disclosure also provides a memory device, wherein the memory device includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes selected memory cells; the peripheral circuitry is configured to: when it is determined that a first write operation has been performed on the selected memory cell, perform a read operation on the selected memory cell; and determine whether to perform a second write operation on the selected memory cell based on the direction of a first pulse, the direction of a second pulse, and the read result of the read operation; the first pulse is a pulse applied to the selected memory cell when performing the first write operation; and the second pulse is a pulse applied to the selected memory cell when performing the read operation.

[0102] In some embodiments, before performing a read operation, the storage state of the selected storage unit is either a first state or a second state.

[0103] In some embodiments, the peripheral circuit is configured to: determine whether to perform a second write operation on the selected memory cell based on whether the direction of the first pulse is the same as the direction of the second pulse; and based on the storage state of the selected memory cell displayed in the read result; the storage state of the selected memory cell displayed in the read result includes a first state and a second state.

[0104] In some embodiments, before performing a read operation, the storage state of the selected storage cell is set to a first state, and the peripheral circuitry is configured as follows:

[0105] If the direction of the first pulse is the same as the direction of the second pulse, and the reading result shows that the storage state of the selected storage unit is the second state, then a second write operation is performed on the selected storage unit; or, if the direction of the first pulse is opposite to the direction of the second pulse, and the reading result shows that the storage state of the selected storage unit is the first state, then a second write operation is performed on the selected storage unit.

[0106] In some embodiments, before performing a read operation, the storage state of the selected storage cell is in a second state, and the peripheral circuit is configured to: determine that the direction of the first pulse is the same as the direction of the second pulse, and when the read result shows that the storage state of the selected storage cell is in the first state, perform a second write operation on the selected storage cell; or, determine that the direction of the first pulse is opposite to the direction of the second pulse, and when the read result shows that the storage state of the selected storage cell is in the second state, perform a second write operation on the selected storage cell.

[0107] In some embodiments, the peripheral circuitry is further configured to: apply a third pulse to the selected memory cell to perform a second write operation; wherein, when the direction of the first pulse is the same as the direction of the second pulse, the direction of the third pulse is opposite to the direction of the first pulse; and when the direction of the first pulse is opposite to the direction of the second pulse, the direction of the third pulse is the same as the direction of the first pulse.

[0108] In some embodiments, when the read result shows that the storage state of the selected storage cell is a first state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the first state; when the read result shows that the storage state of the selected storage cell is a second state, the amplitude of the third pulse is the same as the amplitude of the write pulse corresponding to the second state.

[0109] In some embodiments, the peripheral circuitry is configured to determine whether to perform a second write operation on the selected memory cell after performing a read operation on the selected memory cell once, or after performing multiple read operations on the selected memory cell consecutively.

[0110] In some embodiments, the memory device includes selector-only memory.

[0111] Based on the above-described memory devices, this disclosure also provides a memory system comprising: one or more memory devices as described in the above-described embodiments of this disclosure; and a memory controller coupled to the memory devices for controlling the memory devices.

[0112] Based on this, embodiments of the present disclosure provide a memory device and a memory system. The operation method of the memory device includes: when it is determined that a first write operation has been performed on a selected memory cell, performing a read operation on the selected memory cell; determining whether to perform a second write operation on the selected memory cell based on the direction of a first pulse, the direction of a second pulse, and the read result of the read operation; the first pulse is a pulse applied to the selected memory cell when performing the first write operation; the second pulse is a pulse applied to the selected memory cell when performing the read operation. In this embodiment of the present disclosure, after performing the first write operation and the read operation sequentially, in order to prevent a large voltage difference from being generated due to the different polarities of the second pulse applied to the selected memory cell during the read operation and the first pulse applied to the selected memory cell during the first write operation, which could lead to a change in the storage state of the selected memory cell, after the read operation, it is determined whether to perform a second write operation on the selected memory cell by judging whether the directions of the first pulse and the second pulse are the same, and based on the storage state of the selected memory cell displayed in the read result. After performing the second write operation, the storage state of the selected memory cell can be the same as the storage state of the selected memory cell after performing the first write operation and before the read operation. This reduces read interference caused by the read operation on the selected memory cell, improving the read performance and reliability of the memory device.

[0113] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0114] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, comprising: The memory device comprises: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a selected memory cell; the peripheral circuit is configured to: determine whether the selected memory cell has executed a first write operation, and perform a read operation on the selected memory cell when it is determined that the selected memory cell has executed the first write operation; determine whether to perform a second write operation on the selected memory cell based on a directional relationship between a first pulse and a second pulse and a relationship between a read result of the read operation and a storage state corresponding to the first write operation; the first pulse is a pulse applied to the selected memory cell when the first write operation is performed; the second pulse is a pulse applied to the selected memory cell when the read operation is performed; wherein, when the direction of the first pulse is opposite to the direction of the second pulse, and the storage state of the selected memory cell shown by the read result is the same as the storage state of the selected memory cell after the first write operation is performed, or when the direction of the first pulse is the same as the direction of the second pulse, and the storage state of the selected memory cell shown by the read result is different from the storage state of the selected memory cell after the first write operation is performed, the second write operation is performed; apply a third pulse to the selected memory cell to perform the second write operation; wherein, when the direction of the first pulse is the same as the direction of the second pulse, the direction of the third pulse is opposite to the direction of the first pulse; when the direction of the first pulse is opposite to the direction of the second pulse, the direction of the third pulse is the same as the direction of the first pulse.

2. The memory device of claim 1, wherein, Before the read operation is performed, the storage state of the selected memory cell is a first state or a second state.

3. The memory device of claim 2, wherein, The peripheral circuit is configured to: determine whether the first pulse and the second pulse are in the same direction based on whether the direction of the first pulse is the same as the direction of the second pulse; and determine whether to perform a second write operation on the selected memory cell based on the storage state of the selected memory cell shown by the read result; the storage state of the selected memory cell shown by the read result comprises the first state and the second state.

4. The memory device of claim 3, wherein, Before the read operation is performed, the storage state of the selected memory cell is a first state, and the peripheral circuit is configured to: determine whether the first pulse and the second pulse are in the same direction, and whether the read result shows that the storage state of the selected memory cell is a second state, and perform the second write operation on the selected memory cell when it is determined that the first pulse and the second pulse are in the same direction and the read result shows that the storage state of the selected memory cell is the second state; or determine whether the first pulse and the second pulse are in opposite directions, and whether the read result shows that the storage state of the selected memory cell is the first state, and perform the second write operation on the selected memory cell when it is determined that the first pulse and the second pulse are in opposite directions and the read result shows that the storage state of the selected memory cell is the first state.

5. The memory device of claim 3, wherein, Before the read operation is performed, the storage state of the selected memory cell is a second state, and the peripheral circuit is configured to: determine whether the first pulse and the second pulse are in the same direction, and whether the read result shows that the storage state of the selected memory cell is a first state, and perform the second write operation on the selected memory cell when it is determined that the first pulse and the second pulse are in the same direction and the read result shows that the storage state of the selected memory cell is the first state; or determine whether the first pulse and the second pulse are in opposite directions, and whether the read result shows that the storage state of the selected memory cell is the second state, and perform the second write operation on the selected memory cell when it is determined that the first pulse and the second pulse are in opposite directions and the read result shows that the storage state of the selected memory cell is the second state. determining that the first pulse has an opposite direction to the second pulse, and performing the second write operation on the selected memory cell when the read result indicates that the selected memory cell has the second state.

6. The memory device of claim 1, wherein, when the read result indicates that the selected memory cell has the first state, the third pulse has an amplitude same as that of a write pulse corresponding to the first state; when the read result indicates that the selected memory cell has the second state, the third pulse has an amplitude same as that of a write pulse corresponding to the second state.

7. The memory device of claim 1, wherein, the peripheral circuit is configured to: determining whether to perform a second write operation on the selected memory cell after performing the read operation on the selected memory cell once, or after performing the read operation on the selected memory cell consecutively for a plurality of times.

8. The memory device of claim 1, wherein, the memory device comprises a selector memory only.

9. A memory system, comprising: comprising: one or more memory devices as claimed in any of claims 1 to 8; and a memory controller coupled to the memory device for controlling the memory device.

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