Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device, which has a first dielectric layer on a substrate, a plurality of first conductive patterns and a barrier layer being separated from each other in the first dielectric layer, the barrier layer being on the first conductive patterns, and at least part of the top surface of the barrier layer being exposed to the first dielectric layer; a metal oxide layer being on the first dielectric layer and the barrier layer, a second dielectric layer being on the metal oxide layer, a plurality of conductive columns being separated from each other in the second dielectric layer and being in contact with the barrier layer through the metal oxide layer to be electrically connected with the first conductive patterns through the barrier layer. The barrier layer can block the metal oxide layer from the first conductive patterns, and after the metal oxide layer is formed, the metal oxide layer will not be in contact with the first conductive patterns, thereby avoiding the generation of a neoplasm, and the conductive columns can be in good electrical connection with the first conductive patterns, thereby improving the performance and stability of the memory. Accordingly, the application also provides a preparation method of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Memory plays an indispensable and important role in modern electronic products. In addition to storing user data, memory is also responsible for storing program code executed by the central processing unit and information that needs to be temporarily saved during calculations. Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory). Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). The data in these volatile memories disappears after power is removed and must be re-entered when power is next supplied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in these memories persists even after power is removed, so the previously stored valid data can be directly read after power is restored.

[0003] Advances in semiconductor manufacturing processes have shifted from planar structures to three-dimensional (3D) stacking to achieve higher cell density per unit wafer area and meet the demand for higher storage capacity. The conductive pillars of memory devices need to contact and electrically connect to the conductive pattern below them. However, some growth (Q) often exists between the conductive pillars and the underlying conductive pattern, resulting in poor adhesion between the conductive pillars and the conductive pattern, easy delamination, and a poor electrical connection, which in turn affects the performance and stability of the memory. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem that growths are easily generated between a conductive pillar and a conductive pattern, resulting in poor adhesion between the conductive pillar and the conductive pattern.

[0005] In order to achieve the above object, the present invention provides a semiconductor device comprising:

[0006] substrate;

[0007] a first dielectric layer, located on the substrate;

[0008] A plurality of first conductive patterns are disposed in the first dielectric layer in a manner spaced apart from each other;

[0009] a barrier layer located in the first dielectric layer and on the first conductive pattern, wherein at least a portion of a top surface of the barrier layer is exposed to the first dielectric layer;

[0010] a metal oxide layer, located on the first dielectric layer and the barrier layer;

[0011] a second dielectric layer, located on the metal oxide layer; and

[0012] A plurality of conductive pillars are disposed in the second dielectric layer in a spaced-apart manner and pass through the metal oxide layer to contact the barrier layer so as to be electrically connected to the first conductive pattern through the barrier layer.

[0013] Optionally, the top surface of the barrier layer is flush with the top surface of the first dielectric layer.

[0014] Optionally, a top surface of the barrier layer is lower than a top surface of the first dielectric layer.

[0015] Optionally, the first conductive pattern and the metal oxide layer are separated by the barrier layer and have no contact with each other.

[0016] Optionally, the bottom surface of the metal oxide layer is higher than the top surface of the barrier layer.

[0017] Optionally, the bottom surface of the conductive pillar is in direct contact with the top surface of the barrier layer.

[0018] Optionally, the material of the barrier layer includes at least one of tungsten nitride, titanium nitride, molybdenum, nickel, ruthenium, rhodium, palladium, silver, rhenium, osmium, iridium, platinum, and zirconium.

[0019] The present invention provides a method for preparing a semiconductor device, comprising:

[0020] providing a substrate;

[0021] forming a first dielectric layer on the substrate;

[0022] forming a plurality of first conductive patterns separated from each other in the first dielectric layer;

[0023] forming a barrier layer in the first dielectric layer, the barrier layer being located on the first conductive pattern, with at least a portion of the top surface of the barrier layer being exposed from the first dielectric layer;

[0024] forming a metal oxide layer on the first dielectric layer and the barrier layer;

[0025] forming a second dielectric layer on the metal oxide layer; and,

[0026] A plurality of conductive pillars separated from each other are formed in the second dielectric layer. The conductive pillars pass through the metal oxide layer and contact the barrier layer, and are electrically connected to the first conductive pattern through the barrier layer.

[0027] Optionally, the step of forming the first dielectric layer, the first conductive pattern, and the barrier layer includes:

[0028] forming a first sub-dielectric layer, a conductive material layer, the barrier layer and a mask layer in sequence on the substrate;

[0029] etching the mask layer, the barrier layer, and the conductive material layer in sequence until the first sub-dielectric layer is exposed, and the remaining conductive material layer constitutes the first conductive pattern;

[0030] forming a second sub-dielectric layer on the first sub-dielectric layer, wherein the second sub-dielectric layer covers the first sub-dielectric layer and the mask layer;

[0031] The second sub-dielectric layer and the mask layer are ground until the mask layer is removed and the barrier layer is exposed, and the remaining first sub-dielectric layer and the second sub-dielectric layer constitute the first dielectric layer.

[0032] Optionally, after grinding the second sub-dielectric layer and the mask layer, the top surface of the barrier layer is flush with the top surface of the first dielectric layer.

[0033] Optionally, after grinding the second sub-dielectric layer and the mask layer, the top surface of the barrier layer is lower than the top surface of the first dielectric layer.

[0034] Optionally, after the metal oxide layer is formed on the first dielectric layer and the barrier layer, the bottom surface of the metal oxide layer is higher than the top surface of the barrier layer.

[0035] Optionally, the step of forming the conductive pillar in the second dielectric layer includes:

[0036] etching the second dielectric layer and the metal oxide layer to form a groove exposing the barrier layer;

[0037] The conductive pillar is formed in the groove, and the bottom surface of the conductive pillar is in direct contact with the top surface of the barrier layer.

[0038] The semiconductor device provided by the present invention includes a substrate;

[0039] a first dielectric layer, located on the substrate;

[0040] A plurality of first conductive patterns are disposed in the first dielectric layer in a manner spaced apart from each other;

[0041] a barrier layer located in the first dielectric layer and on the first conductive pattern, wherein at least a portion of a top surface of the barrier layer is exposed to the first dielectric layer;

[0042] a metal oxide layer, located on the first dielectric layer and the barrier layer;

[0043] a second dielectric layer, located on the metal oxide layer; and

[0044] A plurality of conductive pillars are disposed in the second dielectric layer in a spaced manner and pass through the metal oxide layer to contact the barrier layer so as to be electrically connected to the first conductive pattern through the barrier layer.

[0045] In the semiconductor device provided by the present invention, a first dielectric layer is provided on a substrate. The first dielectric layer includes a plurality of first conductive patterns and a barrier layer, each separated from each other. The barrier layer is located on the first conductive pattern, and at least a portion of the top surface of the barrier layer is exposed from the first dielectric layer. A metal oxide layer is located on the first dielectric layer and the barrier layer, and a second dielectric layer is located on the metal oxide layer. A plurality of conductive pillars are disposed in the second dielectric layer, each separated from each other, and pass through the metal oxide layer to contact the barrier layer, thereby electrically connecting to the first conductive pattern through the barrier layer. In the present invention, the barrier layer can block the metal oxide layer from the first conductive pattern. After the metal oxide layer is formed, the metal oxide layer does not contact the first conductive pattern, thereby preventing the formation of growth. The conductive pillars have better adhesion to the first conductive pattern, and can achieve a better electrical connection with the first conductive pattern, thereby improving the performance and stability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0047] Figures 2 to 11 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 11 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0048] Wherein, the accompanying drawings are marked as follows:

[0049] 100 - substrate; 201 - third dielectric layer; 211 - plug; 202 - spacer dielectric layer; 203a - first sub-dielectric layer; 203b - second sub-dielectric layer; 203 - first dielectric layer; 301 - second conductive pattern; 311 - first work function layer; 312 - first metal barrier layer; 302 - first conductive pattern; 321 - fourth work function layer; 322 - second metal barrier layer; 401 - second work function layer; 402 - third work function layer; 501 - gate conductive layer; 502 - gate dielectric layer; 503 - channel hole; 504 - channel layer; 505 - insulating layer; 600 - metal oxide layer; 700 - second dielectric layer; 701 - conductive layer; 702 - first dielectric layer; 703 - groove; 800 - conductive pillar; 801 - second dielectric layer; 802 - barrier layer; 900 - barrier layer;

[0050] x-first direction; y-second direction; z-third direction. DETAILED DESCRIPTION

[0051] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0052] Figure 11 This is a schematic diagram of the structure of the semiconductor device provided in this embodiment. Figure 11 As shown, the semiconductor device includes a substrate 100, which can be, for example, a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI). A third dielectric layer 201 is formed on the substrate 100, and a plug 211 is formed in the third dielectric layer 201. The plug 211 penetrates the third dielectric layer 201 and is electrically connected to the substrate 100.

[0053] A plurality of second conductive patterns 301 are disposed on the third dielectric layer 201. The second conductive patterns 301 extend along a first direction x and are spaced apart along a second direction y. In this embodiment, the second conductive patterns 301 include a first work function layer 311 and a first metal barrier layer 312 stacked sequentially from bottom to top. The material of the first work function layer 311 includes tungsten, and the material of the first metal barrier layer 312 includes, for example, titanium nitride.

[0054] A corresponding second work function layer 401 is disposed on each second conductive pattern 301. The work function value of the second work function layer 401 is lower than the work function value of the first work function layer 311. The second work function layer 401 is electrically connected to the corresponding second conductive pattern 301 and has the same shape as the corresponding second work function layer 401. The material of the second work function layer 401 may include polycrystalline silicon.

[0055] A spacer dielectric layer 202 and a first dielectric layer 203 are sequentially disposed above the second work function layer 401. The first dielectric layer 203 includes a first sub-dielectric layer 203a and a second sub-dielectric layer 203b, sequentially disposed from bottom to top. The materials of the first sub-dielectric layer 203a, the second sub-dielectric layer 203b, and the spacer dielectric layer 202 include, for example, silicon oxide and / or silicon nitride.

[0056] The first sub-dielectric layer 203a includes multiple, mutually separated transistor structures. Each transistor structure is located on the spacer dielectric layer 202 and penetrates the spacer dielectric layer 202 to be electrically connected to the corresponding second work function layer 401. The transistor structure includes a gate conductive layer 501, a gate dielectric layer 502, and a channel layer 504. The gate conductive layer 501 is located on the spacer dielectric layer 202 and has a channel hole 503 therein. The channel hole 503 penetrates the gate conductive layer 501 and the spacer dielectric layer 202, exposing the corresponding second work function layer 401. In this embodiment, the channel hole 503 extends upward after penetrating the gate conductive layer 501. The gate dielectric layer 502 is located within the channel hole 503 and covers the sidewalls of the channel hole 503. The channel layer 504 is also located within the channel hole 503 and covers at least the gate dielectric layer 502 and the second work function layer 401 at the bottom of the channel hole 503.

[0057] The material of the gate dielectric layer 502 may include silicon oxide. In this embodiment, the gate dielectric layer 502 specifically includes a silicon oxide layer covering the sidewalls of the channel hole 503 and a silicon nitride layer covering the sidewalls of the silicon oxide layer. The silicon nitride layer can be formed by nitriding the sidewalls of the silicon oxide layer. The silicon nitride layer is provided on the sidewalls of the silicon oxide layer to prevent oxidation of the gate conductive layer 501. In some embodiments, an aluminum oxide layer may also be formed on the sidewalls of the gate dielectric layer 502 to alleviate the problem of oxidation of the gate conductive layer 501.

[0058] Furthermore, an insulating layer 505 and a third work function layer 402 are formed in the channel hole 503. The insulating layer 505 fills a portion of the depth of the channel hole 503, and the third work function layer 402 fills the remaining depth of the channel hole 503 and is electrically connected to the channel layer 504. In some embodiments, the third work function layer 402 can be extended upward from the channel hole 503 to a position higher than the top of the channel hole 503, and can also be extended laterally to the periphery of the channel hole 503 to completely cover the top of the channel layer 504, thereby increasing the contact area between the channel layer 504 and the third work function layer 402, thereby reducing the on-resistance.

[0059] Please continue reading Figure 11 A plurality of first conductive patterns 302 are disposed within the second sub-dielectric layer 203b. The first conductive patterns 302 extend along the second direction y and are spaced apart along the first direction x. Furthermore, the top surfaces of the first conductive patterns 302 expose the first dielectric layer 203. In this embodiment, the first conductive patterns 302 include a second metal barrier layer 322 and a fourth work function layer 321 stacked sequentially from bottom to top (the top surface of the fourth work function layer 321 exposes the first dielectric layer 203). The work function value of the fourth work function layer 321 is greater than the work function value of the third work function layer 402. The material of the fourth work function layer 321 includes tungsten, and the material of the second metal barrier layer 322 includes, for example, titanium nitride.

[0060] As can be seen, the second work function layer 401 and the third work function layer 402 are located at the bottom and top of the transistor structure, respectively, and are both electrically connected to the channel layer 504. The second work function layer 401 and the third work function layer 402 can be formed of the same material, such as polysilicon. Furthermore, the second work function layer 401 is electrically connected to the second conductive pattern 301, and the third work function layer 402 is electrically connected to the first conductive pattern 302.

[0061] Furthermore, the second sub-dielectric layer 203b further includes a barrier layer 900, which is located on the first conductive pattern 302 and completely covers the top surface of the first conductive pattern 302. Moreover, at least a portion of the top surface of the barrier layer 900 is exposed from the second sub-dielectric layer 203b.

[0062] In this embodiment, the top surface of the barrier layer 900 is flush with the top surface of the second sub-dielectric layer 203 b , that is, the top surface of the barrier layer 900 is flush with the top surface of the first dielectric layer 203 .

[0063] In some embodiments, the top surface of the barrier layer 900 may also be lower than the top surface of the second sub-dielectric layer 203 b , that is, the top surface of the barrier layer 900 may also be lower than the top surface of the first dielectric layer 203 .

[0064] In this embodiment, the material of the barrier layer 900 includes at least one of tungsten nitride (WN), titanium nitride (TiN), molybdenum (Mo), nickel (Ni), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), and zirconium (Zr).

[0065] Furthermore, a metal oxide layer 600 and a second dielectric layer 700 are stacked sequentially from bottom to top above the first dielectric layer 203. The metal oxide layer 600 covers the top surfaces of the first dielectric layer 203 and the barrier layer 900, while the second dielectric layer 700 covers the metal oxide layer 600. The barrier layer 900 can block the metal oxide layer 600 from the first conductive pattern 302. After the metal oxide layer 600 is formed, the metal oxide layer 600 and the first conductive pattern 302 are completely separated, thereby preventing the formation of growth (e.g., tungsten oxide).

[0066] exist Figure 11 As can be seen in FIG. 6 , the metal oxide layer 600 is entirely located above the barrier layer 900 , and the bottom surface of the metal oxide layer 600 is higher than the top surface of the barrier layer 900 .

[0067] It should be noted that the metal oxide layer 600 has a significant etching selectivity ratio with the first dielectric layer 203. The material of the metal oxide layer 600 can be, for example, aluminum oxide, titanium oxide, tantalum oxide, tungsten oxide or copper oxide, preferably including aluminum oxide, but not limited thereto.

[0068] The second dielectric layer 700 is a stacked structure. In this embodiment, the second dielectric layer 700 includes a plurality of first dielectric layers 702 and a plurality of conductive layers 701 stacked alternately, and each conductive layer 701 and the first dielectric layer 702 thereon together form a pair of conductive-first dielectric layers 702. The specific number of conductive-first dielectric layer 702 pairs can be adjusted according to actual needs and is not limited to the number of conductive-first dielectric layers 702 pairs. Figure 11 The conductive layer 701 may be made of, for example, aluminum, titanium, tantalum, tungsten, copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten, titanium nitride, polysilicon, doped silicon, metal silicide, or any combination thereof, preferably including tungsten. The first dielectric layer 702 may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, preferably including the same material as the first dielectric layer 203, but not limited thereto.

[0069] The second dielectric layer 700 includes a plurality of conductive pillars 800, which are spaced apart from each other. Each conductive pillar 800 penetrates the second dielectric layer 700 and the metal oxide layer 600 and directly contacts the corresponding barrier layer 900, thereby electrically connecting to the first conductive pattern 302 through the barrier layer 900. Specifically, the second dielectric layer 700 includes a plurality of grooves 703, each of which penetrates the second dielectric layer 700 and the metal oxide layer 600 and exposes the barrier layer 900. The conductive pillars 800 are filled in the grooves 703, and the bottom surface of each conductive pillar 800 is in direct contact with the top surface of the barrier layer 900.

[0070] Since the metal oxide layer 600 does not contact the first conductive pattern 302, the generation of growth between the metal oxide layer 600 and the first conductive pattern 302 can be avoided. The conductive pillar 800 has better adhesion to the first conductive pattern 302, and the conductive pillar 800 can achieve a better electrical connection with the first conductive pattern 302, thereby improving the performance and stability of the memory.

[0071] Furthermore, a second dielectric layer 801 and a barrier layer 802 are stacked in sequence on the sidewalls of the groove 703. The second dielectric layer 801 covers the sidewalls of the groove 703, and the barrier layer 802 covers the second dielectric layer 801. In this embodiment, both the second dielectric layer 801 and the barrier layer 802 have an L-shaped cross-sectional structure.

[0072] The material of the second dielectric layer 801 can be a high dielectric constant dielectric material, such as at least one of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride silicon (HfSiON), zinc oxide (ZrO2), and titanium oxide (TiO2). The material of the barrier layer 802 can include materials such as titanium, tantalum, titanium nitride or tantalum nitride, but is not limited to these.

[0073] Based on this, this embodiment also provides a method for preparing a semiconductor device. Figure 1 The flowchart of the method for preparing the semiconductor device provided in this embodiment is as follows: Figure 1 As shown, the method for preparing the semiconductor device includes:

[0074] Step S100: providing a substrate;

[0075] Step S200: forming a first dielectric layer on the substrate;

[0076] Step S300: forming a plurality of first conductive patterns separated from each other in the first dielectric layer;

[0077] Step S400: forming a barrier layer in the first dielectric layer, the barrier layer being located on the first conductive pattern, with at least a portion of the top surface of the barrier layer exposed from the first dielectric layer;

[0078] Step S500: forming a metal oxide layer on the first dielectric layer and the barrier layer;

[0079] Step S600: forming a second dielectric layer on the metal oxide layer; and

[0080] Step S700: forming a plurality of mutually separated conductive pillars in the second dielectric layer, wherein the conductive pillars pass through the metal oxide layer and contact the barrier layer, and are electrically connected to the first conductive pattern through the barrier layer.

[0081] Figures 2 to 11 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Figures 2 to 11 The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0082] like Figure 2 As shown, step S100 is performed to provide a substrate 100. A third dielectric layer 201 is formed on the substrate 100, and then the third dielectric layer 201 is etched to form a through-hole penetrating the third dielectric layer 201. The through-hole is then filled with a conductive material to form a plug 211 in the third dielectric layer 201. The plug 211 is electrically connected to the substrate 100.

[0083] Next, a first work function layer 311 and a first metal barrier layer 312 are sequentially formed on the third dielectric layer 201. The first work function layer 311 and the first metal barrier layer 312 are sequentially stacked and cover the third dielectric layer 201 and the plug 211. The first work function layer 311 and the first metal barrier layer 312 are patterned to form a second conductive pattern 301. A second work function layer 401 is then formed on each second conductive pattern 301. The second work function layer 401 is electrically connected to the corresponding second conductive pattern 301.

[0084] Please continue reading Figure 2, executing steps S200, S300, and S400. First, a spacer dielectric layer 202 and a first sub-dielectric layer 203a are sequentially formed on the second work function layer 401. The first sub-dielectric layer 203a comprises multiple layers, with a single layer being schematically illustrated in this embodiment. During the formation of the first sub-dielectric layer 203a, transistor structures are also formed within the first sub-dielectric layer 203a, and a third work function layer 402 is formed on each of the transistor structures.

[0085] Then, a second metal barrier layer 322, a fourth work function layer 321, a barrier layer 900, and a mask layer 204 are sequentially formed on the first sub-dielectric layer 203a. The second metal barrier layer 322, the fourth work function layer 321, the barrier layer 900, and the mask layer 204 are sequentially stacked on the first sub-dielectric layer 203a, and the second metal barrier layer 322 and the fourth work function layer 321 constitute a conductive material layer.

[0086] See also Figure 3 , the mask layer 204, the barrier layer 900, the fourth work function layer 321, and the second metal barrier layer 322 are sequentially etched. After etching, the mask layer 204, the barrier layer 900, the fourth work function layer 321, and the second metal barrier layer 322 are strip-shaped, and each strip of the fourth work function layer 321 and the second metal barrier layer 322 constitutes a first conductive pattern 302. The first conductive pattern 302 is located on each of the third work function layers 402, and the barrier layer 900 is located on the first conductive pattern 302.

[0087] Furthermore, the top surface and bottom surface of the transistor structure contact the corresponding third work function layer 402 and the second work function layer 401 respectively, so as to be electrically connected to the corresponding first conductive pattern 302 and the second conductive pattern 301 through the corresponding third work function layer 402 and the second work function layer 401, and the top surface of the first conductive pattern 302 (that is, the top surface of the fourth work function layer 321) needs to expose the first sub-dielectric layer 203a.

[0088] It should be noted that the preparation method of the transistor structure can adopt any existing method. Since the preparation of the transistor structure is not the focus of the present invention, it will not be described in detail here.

[0089] like Figure 4 As shown, a second sub-dielectric layer 203 b is formed on the first sub-dielectric layer 203 a , and the second sub-dielectric layer 203 b covers the first sub-dielectric layer 203 a and the mask layer 204 .

[0090] like Figure 5As shown, the second sub-dielectric layer 203 b and the mask layer 204 are ground until the mask layer 204 is removed and the barrier layer 900 is exposed. The remaining first sub-dielectric layer 203 a and the second sub-dielectric layer 203 b constitute the first dielectric layer 203 .

[0091] In this embodiment, after grinding the second sub-dielectric layer 203 b and the mask layer 204 , the top surface of the barrier layer 900 is flush with the top surface of the second sub-dielectric layer 203 b , that is, flush with the top surface of the first dielectric layer 203 .

[0092] In some embodiments, after grinding the second sub-dielectric layer 203 b and the mask layer 204 , the top surface of the barrier layer 900 may be lower than the top surface of the second sub-dielectric layer 203 b , that is, lower than the top surface of the first dielectric layer 203 .

[0093] like Figure 6 As shown, steps S500 and S600 are performed to sequentially form a metal oxide layer 600 and a second dielectric layer 700 on the first dielectric layer 203. The metal oxide layer 600 covers the first dielectric layer 203 and the barrier layer 900, and the second dielectric layer 700 covers the metal oxide layer 600. In this embodiment, the metal oxide layer 600 constitutes an etch stop layer, and the second dielectric layer 700 comprises a plurality of first dielectric layers 702 and a plurality of conductive layers 701 alternately stacked.

[0094] like Figure 7 As shown, step S700 is performed to etch the second dielectric layer 700 using a dry etching process to form a plurality of grooves 703 that expose the metal oxide layer 600. Each groove 703 is located above a corresponding first conductive pattern 302. Specifically, the dry etching process vertically etches downward through each first dielectric layer 702 and each conductive layer 701, so that the grooves 703 can penetrate the second dielectric layer 700 and expose the top surface of the metal oxide layer 600.

[0095] like Figure 8 As shown, the metal oxide layer 600 is etched downward along the bottom of the groove 703 using a wet etching process, so that the groove 703 extends downward until the top surface of the barrier layer 900 is exposed. Specifically, the wet etching process etches the metal oxide layer 600 vertically through the groove 703.

[0096] like Figure 9As shown, a second dielectric layer 801 and a barrier layer 802 are sequentially formed on the second dielectric layer 700 and the inner wall of the groove 703. The second dielectric layer 801 conformally covers the second dielectric layer 700 and the inner wall of the groove 703, and the barrier layer 802 conformally covers the second dielectric layer 801.

[0097] like Figure 10 As shown, the barrier layer 802 and the second dielectric layer 801 covering the second dielectric layer 700 and the bottom wall of the groove 703 are removed by an etch-back process, exposing the barrier layer 900. The barrier layer 802 and the second dielectric layer 801 may have an L-shaped cross-sectional structure and are sequentially stacked on the sidewalls of the groove 703.

[0098] like Figure 11 As shown, a conductive material is filled in each of the grooves 703 to form the conductive pillar 800 . The bottom of the conductive pillar 800 is in direct contact with the barrier layer 900 , thereby being electrically connected to the corresponding first conductive pattern 302 through the barrier layer 900 .

[0099] In summary, in a semiconductor device provided by an embodiment of the present invention, a first dielectric layer is provided on a substrate, and a plurality of mutually separated first conductive patterns and a barrier layer are provided within the first dielectric layer. The barrier layer is located on the first conductive pattern, and at least a portion of the top surface of the barrier layer is exposed from the first dielectric layer. The metal oxide layer is located on the first dielectric layer and the barrier layer, and a second dielectric layer is located on the metal oxide layer. A plurality of conductive pillars are disposed in the second dielectric layer, separated from each other, and pass through the metal oxide layer to contact the barrier layer, thereby electrically connecting to the first conductive pattern through the barrier layer. In the present invention, the barrier layer can block the metal oxide layer from the first conductive pattern. After the metal oxide layer is formed, the metal oxide layer does not contact the first conductive pattern, thereby preventing the formation of growth. The conductive pillars can achieve a good electrical connection with the first conductive pattern, thereby improving the performance and stability of the memory.

[0100] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0101] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0102] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0103] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: substrate; a first dielectric layer, located on the substrate; A plurality of first conductive patterns are disposed in the first dielectric layer in a manner spaced apart from each other; a barrier layer located in the first dielectric layer and on the first conductive pattern, wherein at least a portion of a top surface of the barrier layer is exposed to the first dielectric layer; a metal oxide layer, located on the first dielectric layer and the barrier layer, wherein the first conductive pattern and the metal oxide layer are separated by the barrier layer; a second dielectric layer, located on the metal oxide; as well as, A plurality of conductive pillars are disposed in the second dielectric layer in a spaced-apart manner and pass through the metal oxide layer to contact the barrier layer so as to be electrically connected to the first conductive pattern through the barrier layer.

2. The semiconductor device according to claim 1, wherein The top surface of the barrier layer is flush with the top surface of the first dielectric layer.

3. The semiconductor device according to claim 1, wherein A top surface of the barrier layer is lower than a top surface of the first dielectric layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein The bottom surface of the metal oxide layer is higher than the top surface of the barrier layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein The bottom surface of the conductive column is in direct contact with the top surface of the barrier layer.

6. The semiconductor device according to any one of claims 1 to 3, wherein The material of the barrier layer includes at least one of tungsten nitride, titanium nitride, molybdenum, nickel, ruthenium, rhodium, palladium, silver, rhenium, osmium, iridium, platinum, and zirconium.

7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate; forming a plurality of first conductive patterns separated from each other in the first dielectric layer; forming a barrier layer in the first dielectric layer, the barrier layer being located on each of the first conductive patterns, with at least a portion of a top surface of the barrier layer being exposed from the first dielectric layer; forming a metal oxide layer on the first dielectric layer and the barrier layer; forming a second dielectric layer on the metal oxide layer; as well as, A plurality of conductive pillars separated from each other are formed in the second dielectric layer. The conductive pillars pass through the metal oxide layer and contact the barrier layer, and are electrically connected to the first conductive pattern through the barrier layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The steps of forming the first dielectric layer, the first conductive pattern and the barrier layer include: forming a first sub-dielectric layer, a conductive material layer, the barrier layer and a mask layer in sequence on the substrate; etching the mask layer, the barrier layer, and the conductive material layer in sequence until the first sub-dielectric layer is exposed, and the remaining conductive material layer constitutes the first conductive pattern; forming a second sub-dielectric layer on the first sub-dielectric layer, wherein the second sub-dielectric layer covers the first sub-dielectric layer and the mask layer; The second sub-dielectric layer and the mask layer are ground until the mask layer is removed and the barrier layer is exposed, and the remaining first sub-dielectric layer and the second sub-dielectric layer constitute the first dielectric layer.

9. The method for preparing a semiconductor device according to claim 8, wherein: After grinding the second sub-dielectric layer and the mask layer, the top surface of the barrier layer is flush with the top surface of the first dielectric layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: After grinding the second sub-dielectric layer and the mask layer, the top surface of the barrier layer is lower than the top surface of the first dielectric layer.

11. The method for preparing a semiconductor device according to any one of claims 7 to 10, wherein: After the metal oxide layer is formed on the first dielectric layer and the barrier layer, the bottom surface of the metal oxide layer is higher than the top surface of the barrier layer.

12. The method for preparing a semiconductor device according to any one of claims 7 to 10, wherein: The step of forming the conductive pillar in the second dielectric layer includes: etching the second dielectric layer and the metal oxide layer to form a groove exposing the barrier layer; The conductive pillar is formed in the groove, and the bottom surface of the conductive pillar is in direct contact with the top surface of the barrier layer.

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