Integrated circuit interconnect shape optimizer

Abstract

Systems, apparatus, and methods for optimizing conductive interconnects are described. One method includes receiving an integrated circuit layout comprising a plurality of terminals and interconnects, wherein the interconnects represent conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material properties of the plurality of terminals and interconnects. The method includes generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and layer information. The method includes using the three-dimensional representation and terminal information to determine the individual contribution of each individual component included in the three-dimensional representation to the resistance-capacitance (RC) value of the interconnects. The method also includes generating an updated integrated circuit layout based at least in part on the individual contributions.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 310,750, filed February 16, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to integrated circuits, and specifically, but not exclusively, to first-principles electronic design automation for integrated circuit shape optimization and layout generation. Background Technology

[0004] Routing is a fundamental problem in electronic design and automation, generating connections to interconnect pins of common signals while adhering to manufacturing design rules. For very large-scale integrated circuit designs, where billions of transistors may exist on a single chip, routing optimization is particularly challenging due to the complexity of integrated circuits. Typically, routing is divided into at least a global routing phase and a detailed routing phase. Global routing planning generates routing paths without considering the manufacturing design rules of a given vendor's process nodes, while detailed routing determines the exact route.

[0005] Multidimensional grid-based graph search techniques (e.g., a two-dimensional grid with a third dimension corresponding to the wiring layers) can be used to generate conventional routing algorithms, where routing resources are modeled as a graph, and the graph topology can represent the integrated circuit structure. Global routing then divides the graph into tiles and finds tile-to-tile paths to guide the detailed router. The detailed router then overlays a grid on the graph, where each cell of the grid is greater than or equal to the sum of the minimum width of a given vendor process node and the wire spacing, to find the exact wiring routes. Typical routers sequentially generate detailed routes and have preferred routing orientations (i.e., metal lines arranged horizontally or vertically for different metallization layers of the integrated circuit), and may therefore be limited in both efficiency and geometry (e.g., limited to the Manhattan routing convention of vertical and horizontal straight lines). Attached Figure Description

[0006] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following accompanying drawings, wherein, unless otherwise stated, the same reference numerals refer to the same parts throughout the various views. Not all instances of elements need to be labeled to avoid confusing the drawings where appropriate. The drawings are not necessarily drawn to scale, but instead focus on illustrating the principles described.

[0007] Figure 1 This is a schematic diagram of an example system for modifying conductive interconnects in an integrated circuit layout according to embodiments of the present disclosure.

[0008] Figure 2 This is a schematic diagram illustrating an example process for generating an updated layout of integrated circuit interconnects according to embodiments of the present disclosure.

[0009] Figure 3A This is a schematic diagram illustrating a toy model with two interconnected ports according to an embodiment of the present disclosure.

[0010] Figure 3B This is a schematic diagram illustrating an example variable-width interconnect of two coupled terminals according to an embodiment of the present disclosure.

[0011] Figure 4A This is a schematic diagram of an example layout showing a simplified three-dimensional representation of at least a portion of a layout file describing an interconnection (e.g., a two-port interconnection) of two terminals coupled according to embodiments of the present disclosure.

[0012] Figure 4B According to embodiments of this disclosure, a first set 220 of terminal information is obtained from... Figure 4A Example plan 500 generates an example layout of the updated layout.

[0013] Figure 4C The second set of terminal information used according to embodiments of this disclosure is from Figure 4A Another example plan for the updated layout generated by the example plan.

[0014] Figure 4D The third set of terminal information used according to embodiments of this disclosure is from Figure 4A Another example plan for the updated layout generated by the example plan.

[0015] Figure 5A This is a schematic diagram illustrating an example three-dimensional representation of a layout file according to an embodiment of the present disclosure.

[0016] Figure 5B This is a schematic diagram illustrating an example three-dimensional representation of an updated layout according to an embodiment of the present disclosure.

[0017] Figure 6A This is a schematic diagram illustrating an example layout of a layout file according to an embodiment of the present disclosure.

[0018] Figure 6B This is a schematic diagram illustrating an example layout of an updated layout in an intermediate state according to an embodiment of the present disclosure.

[0019] Figure 6C This is a schematic diagram illustrating an example layout of an updated layout in an advanced state according to an embodiment of the present disclosure.

[0020] Figure 7This illustrates an embodiment according to the present disclosure. Figure 2 The example process 200 is a block diagram of an example operation flow applied to a three-dimensional representation.

[0021] Figure 8 This is a schematic diagram illustrating an example three-dimensional representation of an updated layout file including a fan-out configuration according to an embodiment of the present disclosure.

[0022] Figure 9 This is a schematic diagram illustrating an example three-dimensional representation of an updated layout file including a fan-in-out configuration according to an embodiment of the present disclosure.

[0023] Figure 10 This is a block diagram illustrating an example flow for shape modification of a fan-in or fan-out layout file according to embodiments of the present disclosure.

[0024] Figure 11 This is a schematic diagram illustrating an example three-dimensional representation of a multi-layer layout file including multiple interconnects with coupled multiple terminals according to an embodiment of the present disclosure. Detailed Implementation

[0025] This document describes embodiments of systems and methods for detailed, monomer-based interconnect routing based on RC simulation. Numerous specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0026] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0027] Most fundamental properties of integrated circuits (ICs) relate to resistance and capacitance. The delay in charging and discharging IC components per clock cycle is directly given by the RC time constant. Capacitance is related to the amount of charge flowing into and out of the circuit, thus deriving current, which in turn drives the power required to power the IC. Furthermore, Joule heating generated during operation also follows resistance and current. As a result of miniaturization, phenomena such as electromigration and dielectric breakdown have affected the reliability of ICs, which is also related to conductors (e.g., metals such as Au, Ag, Al, Cu, Ti, and combinations thereof forming metal alloys) and conductors (e.g., SiO2, SiO2). x The electric field strength is related to the electric field strength between oxides or other insulators.

[0028] This document describes embodiments of a monolithic integrated circuit (IC) optimizer that implements first-principles techniques to iteratively modify the detailed interconnect shapes in an integrated circuit layout. In this context, an integrated circuit layout describes a graphical and / or digital representation of at least a portion of an integrated circuit—such as a layer of the integrated circuit—including one or more interconnects between one or more terminals. In this context, a terminal is a contact coupled to an IC element, also referred to as a port, and an interconnect is a conductive material electrically coupling two or more terminals. Interconnects are also referred to as “nets” or “wires” consistent with the technical terminology used in the field of IC layout routing.

[0029] Integrated circuit layout can describe the location and size of multiple interconnects and various types of terminals. For example, an interconnect can electrically couple multiple input terminals to a single output terminal (referred to as a "fan-in" configuration). In another example, an interconnect can electrically couple a single input terminal to multiple output terminals (referred to as a "fan-out" configuration). In yet another example, an interconnect can electrically couple multiple input terminals to multiple output terminals (referred to as a "fan-in-out" configuration). In some embodiments, an interconnect electrically couples one or more drivers to one or more loads, for example, as part of powering one or more transistors.

[0030] Analytical solutions for the RC values ​​of interconnects, incorporating physically meaningful terminology, are practically unavailable given the dimensions and geometries employed in IC layouts. For this reason, finite volume, finite element, or other types of 3D full-field numerical simulation methods can be used to determine the RC values. Specifically, a three-dimensional representation of the IC layout can be generated to discretize the layout into an array of volumetric elements, referred to as a monomer or voxel. A monomer is characterized by uniform material properties corresponding to its location within the IC layout. As an example, a monomer at the location of an interconnect in the IC layout can be defined as a conductor (e.g., a metal). In another example, a monomer at a location outside the interconnect can be defined as a dielectric or insulator (e.g., an oxide). The material can include materials used in multilayer CMOS processes applied in IC manufacturing.

[0031] A three-dimensional representation describes at least a portion of an integrated circuit, including interconnects and terminals, where terminals can be used to simulate the contribution of individual monomers to the RC time constant of the interconnect. The RC time constant of the interconnect can be simulated from the material properties of the individual monomers and the operating parameters of the terminals. Simulation of the capacitive and conductive contributions of each monomer to the overall electrical properties (e.g., conductance and capacitance) of the interconnect and / or dielectric can be used to reshape the interconnect, including reassigning the materials of individual monomers, as a method to optimize the RC time constant of the interconnect.

[0032] Advantageously, the techniques described herein facilitate a departure from conventional straight-line interconnect layouts. Currently, supplier process nodes are approaching the optical resolution threshold of semiconductor manufacturing systems. Straight-line routing and edge placement errors, as quality factors for manufacturability and process optimization, significantly constrain conventional layout designs and introduce inefficiencies into integrated circuit operation. Therefore, the curved layouts shown in the following figures represent a significant advancement towards improved integrated circuit design in the context of nanometer process nodes. For example, the techniques described herein allow for the preservation of functionality to guide manufacturability determinations, rather than edge placement errors, and allow physically meaningful RC values ​​of the IC layout to be used as optimization metrics. Interconnects can be modified in ways unavailable to optimize RC values ​​and improve the overall performance and robustness of IC interconnects.

[0033] Figure 1 This is a schematic diagram of an example system 100 for modifying conductive interconnects in an integrated circuit layout according to embodiments of the present disclosure. Example system 100 includes: one or more servers 105, one or more client computing devices 110, one or more semiconductor manufacturing systems 115, and a network 120. Server 105 includes: a first database 125 of training data 130, a second database 135 of process data 137, a shape optimizer 140, and one or more machine learning models 150 encoded in software 155. As part of the software 155, server 105 includes instructions for training and / or deploying the shape optimizer 140 and / or models 150 using computer circuitry 160. In some embodiments, server 105 also includes a third database 165 storing design files 170—also referred to as integrated circuit layout files—which may be stored in one or more database file formats, including but not limited to GDSII or OASIS.

[0034] The following description focuses on embodiments of this disclosure that implement a networked system for deploying shape optimizer 140 as part of a detailed routing platform for optimizing integrated circuit layout 170. However, it is contemplated that some embodiments of this disclosure include some or all of the processes implemented on a client computing device 110, such as a laptop computer or personal computer. For example, training of an untrained model 150 can be implemented using server 105, while a trained model 150 can be transmitted to the client computing device 110 via network 120 and can be deployed directly on the client computing device 110. Similarly, components of the example system 100 can be hosted and / or stored on a distributed computing system (e.g., a cloud system) rather than in a single system. For example, a first database 125, a second database 135, a third database 165, and / or computer circuitry 160 can be implemented across a distributed system, such that portions of training data 130, process data 137, software 155, and / or design documents 170 can be stored or executed by the distributed computing system in one or more physical locations.

[0035] In an illustrative example of the operation of example system 100, the user of client computing device 110 prepares to describe the layout 170 of an integrated circuit to be manufactured using manufacturing system 115 (see reference). Figure 2 In the conventional system, layout 170 is routed based on design rules that can be coded in software, which can be stored and / or hosted on server 105 and / or client computing device 110. The design rule checking software generates a Boolean result describing whether the design is manufacturable and can also provide Boolean values ​​for "required" or "recommended" rules. Using the design rule checking software, layout 170 can be easily identified as compliant or non-compliant, but not manually modified.

[0036] For this purpose, shape optimizer 140 software 155 stored on server 105 and / or client computing device 110 can be used to process layout 170 to generate an updated layout 270 optimized for physically meaningful parameters—including but not limited to the RC time constant. In some embodiments, layout 170 is transmitted to server 105 via network 120, where shape optimizer 140 processes layout 170. In some embodiments, shape optimizer 140 is implemented as part of an interactive design environment hosted on client computing device 110 and / or server 105, such as a browser environment or graphical user interface that presents layout information and one or more tools for designing layout file 170.

[0037] Optimization criteria can also include metrics such as power consumption, integrated circuit area, processing power, and design and / or wafer-level yield, which can be application-specific. In this way, the combined effect of multiple detailed routing optimizations can be identified and evaluated against global optimization metrics. Additionally, composite optimization factors can be used to guide detailed routing. In an illustrative example, for designs intended for use in highly specialized, space- or power-constrained, or fault-tolerant applications, lower yields may be tolerated to benefit other metrics. For fault-tolerant or size-independent high-capacity applications, yields can be prioritized at the expense of area or processing power. Similarly, indirect quantities can be suitable as optimization metrics. For example, the total cost of ownership of an application-specific integrated circuit (ASIC) intended for use in data center operations can be applied as an optimization function.

[0038] Manufacturing system 115 is an example of a complex system in a pipeline between a semiconductor foundry and a layout design facility, where integrated circuit layout is processed and design data is converted into mask data. The mask data is then used to generate photomasks for use in the lithography process of physical semiconductor equipment manufacturing. In the context of example system 100, manufacturing system 115 is represented by a network interface computer (e.g., a server) to simplify visual interpretation. Typically, multiple processes (e.g., reverse lithography, optical proximity correction, process correction codes) are completed between “tapeout” and the fabrication of compatible integrated circuits on the wafer, where “tapeout” refers to the point where the design rules-compatible design of the integrated circuit is sent to the foundry.

[0039] In some embodiments, software 155 implements shape optimizer 140 in a manner that generates one or more updated layouts 270 from layout 170. In some cases, the updated layouts 270 are merged to generate an updated layout 270 comprising multiple layers, which is then output to a user, for example, as part of an interactive design environment. The output may include, but is not limited to, transmission via network 120 to client computing device 110 and / or storage of the updated layouts 270 and / or optimized data in a third database 165. In the case where example system 100 operates as part of an interactive design environment, the output manufacturability data may include user interface data that generates and transmits data that causes client computing device 110 to render manufacturability parameters on display 111.

[0040] In some embodiments, updated process data 137 and / or new process data 137 are received from manufacturing system 115. As semiconductor processing technology is regularly improved with the development of new equipment and technologies, it is envisioned that example system 100 will support the retraining of shape optimizer 140 and prepare new models 145-150 with changes to process data 137 or when new process data 137 is received.

[0041] In the illustrated embodiment, the shape optimizer 140 includes functional sub-units described as modules 141-149 for generating updated integrated circuit layout 270. In some embodiments, the shape optimizer 140 includes a discretization module 141 configured to receive layout data 215 (see reference). Figure 2 The layout data 215 is used to generate a three-dimensional representation of a layout file 170 comprising multiple monomers. The shape optimizer 140 may include a physical simulation module 143 configured to solve electromagnetic equations as part of an electromagnetic simulation of the integrated circuit layout 170. The physical simulation module 143 may allow the example system 100 to determine the local contribution of a monomer to a characteristic metric of at least a portion of the layout 170, which may include, but is not limited to, the RC values ​​of interconnects. A shape optimization module 145 may be included, configured to implement physically meaningful heuristics based on one or more outputs of the physical simulation module 143. For example, the shape optimization module 145 may include routines in software 155 for modifying the definition of one or more monomers in the three-dimensional representation of the layout 170 based on the relationship between the contributions of individual monomers near the boundaries of interconnects.

[0042] In some embodiments, the operation of the physical simulation module 143 may be supplemented and / or implemented by one or more machine learning models 144 trained to generate at least a portion of an updated layout 270 using layout files 170 as input. In an illustrative example, the machine learning model 144 may be or include a deep convolutional neural network model trained using the updated layout 270 generated by the physical simulation module 143. For example, a database 146 of training data may be generated by optimizing multiple layout files 170 using physical-based simulations. The training data may include paired layout files 170 with corresponding updated layouts 270, which allows the machine learning model 144 to be trained via supervised learning. In some embodiments, the shape optimizer 140 generates the updated layout 270 by first generating and then optimizing the output layout of the machine learning model 144 by the physical simulation module 143. Advantageously, supplementing the physical simulation module 143 with machine learning models 144 in this manner can reduce the number of iterations of the physical simulation module 143 used to generate the updated layout 270.

[0043] In some embodiments, the shape optimizer 140 includes a process simulator 147 configured to perform a manufacturability simulation of the updated layout 270. In some embodiments, the process simulator 147 may perform manufacturability analysis based on process node design rules and / or function retention criteria. A correction module 149 may be provided, configured to correct the updated layout 270 based on the output returned by the process simulator 147. For example, if the process simulator 147 indicates that the updated layout 270 is not manufacturable by the semiconductor manufacturing system 115, the correction module 149 may modify the updated layout to meet the manufacturability constraints of the semiconductor manufacturing system 115. The techniques described herein can be applied to multiple characteristic scales. For example, interconnect wiring may be implemented at a first scale, while shape optimization of individual interconnects may be implemented at a smaller scale, wherein each corresponding scale may correspond to the characteristic size of a single entity constituting a three-dimensional representation.

[0044] It should be understood that the techniques described herein can be iterative, where the output of a given iteration is used as the input for subsequent iterations. In this way, the initial layout file 170 can be repeatedly modified toward optimization metrics, such as minimizing the RC values ​​of interconnects. For this purpose, the example process described with reference to the upcoming figures is understood to represent individual iterations of an optimization technique that may include multiple iterations. Individual iterations may include additional operations, omission of one or more operations, or reordering of constitutive operations.

[0045] Figure 2 This is a schematic diagram illustrating an example process 200 for generating an updated layout 270 of integrated circuit interconnects according to an embodiment of the present disclosure. It should be understood that the example process 200 can be performed by a system (e.g., Figure 1 The system 100 is implemented to perform iterative optimization of characteristic metrics to generate a manufacturable integrated circuit layout, which can be stored as a layout file 170 (e.g., in...). Figure 1 (In database 165). Example process 200 may be a computer-implemented method coded in software 155 provided by at least one machine-accessible storage medium (e.g., non-transitory memory), which, when executed by a machine (e.g., server 150 and / or client computing device 110), causes the machine to perform operations for generating an updated layout 270. The updated layout 270 refers to the updated integrated circuit layout in the upcoming description, in the form of layout file 170, which includes or otherwise incorporates at least a subset of multiple shape modifications to interconnects and / or terminals.

[0046] It should also be understood that the order in which some or all of the process blocks appear in example process 200 should not be considered limiting. Rather, those skilled in the art who benefit from this disclosure will understand that some process blocks may be executed in various orders or in parallel, not shown. Furthermore, while example process 200 is described as a sequence of operations implemented by modules 141-149 of shape optimizer 140, it is conceivable that non-modular software 155 may be provided. Alternatively, as part of load optimization, for example, as part of parallelizing or executing software 155 on a distributed system, one or more modules may be divided into submodules.

[0047] At operation 201, example procedure 200 includes receiving layout data 215. (See reference...) Figure 1 In a more detailed description, layout document 170 may be or include a digital description of one or more interconnections between terminals associated with an integrated circuit. This description may correspond to a netlist, layout, schematic diagram, figure, or any other representation of an integrated circuit that describes the orientation, number, and connectivity of the terminals. In some embodiments, layout document 170 includes wiring information (e.g., unoptimized or unmanufacturable wiring), information regarding the number of metallization layers, the physical dimensions of the integrated circuit, wiring, etc. It should be understood that an integrated circuit may contain many components (e.g., resistors, transistors, capacitors, diodes, transistors, or other electronic sub-components), wherein a specific or relative spatial arrangement of the components is provided by the description. Accordingly, layout document 170 indicates how individual terminals among a plurality of terminals are electrically coupled. In some embodiments, layout document 170 also describes information related to terminals not directly located on the integrated circuit (e.g., ground connections).

[0048] In operations 203 and 205, example procedure 200 includes receiving terminal information 220 and layer information 225. Terminal information 220 refers to data describing one or more operating parameters of at least a subset of terminals included in layout file 170. In an illustrative example, layout file 170 may include a description of interconnections coupling driver terminals to load terminals, as referenced... Figure 4A A more detailed description follows. In this example, terminal information 220 may describe the operating parameters of this portion of layout file 170, including but not limited to driver impedance, operating frequency, and / or load capacitance. In some embodiments, terminal information 220 includes metadata identifying each terminal with reference to layout file 170, such that the terminals included in the layout file are correctly associated with the terminal operating parameters.

[0049] Layer information 225 may include, but is not limited to, material property information of the layer corresponding to layout document 170. For example, layout document 170 may describe via layers, metal layers, or other layers that may be included in a multilayer integrated circuit fabricated using a CMOS process. In this way, layer information 225 may include material property information, including electronic properties, thermal properties, elemental composition, phase / structure information, etc. Examples of electronic properties include, but are not limited to, conductivity, permittivity, and dielectric breakdown voltage. Examples of thermal properties include, but are not limited to, conductivity. In an illustrative example, layer information 225 may define a layer as a metal layer and may define the layer as two or more materials including dielectric oxides and conductive metals. Layer information 225 may be associated with layout document 170 through spatial encoding, for example, where interconnects are encoded to metals and regions outside the interconnects are encoded to dielectrics. In some embodiments, layout document 170 may include multiple interconnects and / or terminals within a given region, such that multiple regions of the layout are represented as conductive materials, as referenced. Figure 4A-1 2. A more detailed description.

[0050] In operation 207, example procedure 200 includes discretizing layout file 170 as part of a three-dimensional representation 235 that generates at least a portion of layout file 170. The three-dimensional representation 235 may include a plurality of monomers, each corresponding to a discrete volumetric element describing a portion of layout file 170. As previously described, a monomer is a volumetric element having a specific size, shape, and volume. In some embodiments, monomers share a common size, a common shape, and / or a common volume. In some embodiments, monomers may have diverse sizes, shapes, and / or volumes, such that layout file 170 can be discretized into a more general collection of monomers of varying sizes and shapes.

[0051] For example, in one embodiment, multiple monomers may include a first monomer having a first volume and a second monomer having a second volume different from the first volume. Certain computational advantages may exist for monomers of different sizes. For example, a region of the simulation environment further away from the interconnect boundary can be generated that has a larger size relative to monomers on or near the interconnect boundary. Advantageously, dynamic monomer size settings can reduce the computational resource requirements of the electromagnetic simulation techniques described herein, thereby improving the operation of the example process 200 on example system 100. It should be understood that individual monomers are not necessarily limited to a specific shape and may include any one or combination of cubes, cuboids, triangular prisms, spheres, cylinders, tetrahedrons, hexagonal prisms, pyramids, or other shapes not explicitly listed. Rather, it should be understood that the size, shape, and / or position of monomers can be set to favor any resolution of the three-dimensional representation 235. For example, a monomer may be defined as an arbitrary volume mapped between node arrays on layout file 170. The positioning of nodes in the node array may be guided by the geometry of layout file 170. For example, corners or other feature-dense regions of layout file 170 may correspond to higher node densities, while feature-sparse regions may correspond to lower node densities. In some embodiments, each individual monomer is small enough that a given terminal included in a plurality of terminals of an integrated circuit is represented by more than one monomer included in the plurality of monomers.

[0052] In some embodiments, generating the three-dimensional representation 235 may include configuring a coordinate system (e.g., a Cartesian, cylindrical, spherical, etc. coordinate system), size, shape, and / or the number of units. Configuration may include assigning material properties of the units to correspond to or otherwise represent the description of the integrated circuit (e.g., based on the arrangement and location of multiple terminals associated with the integrated circuit). For example, a unit representing a terminal of a given network may be assigned material properties corresponding to a conductor (e.g., metals such as Au, Ag, Al, Cu, Ti, combinations thereof to form metal alloys, or other suitable materials). Conversely, insulators or dielectrics (e.g., such as SiO2, SiO2, etc.) may be assigned to units outside interconnects, terminals, or other conductors. x Material properties such as oxides like SiN, high-k dielectrics, and low-k dielectrics.

[0053] As part of shape optimization, an initial 3D representation 235 can be generated from the already wired layout file 170, including interconnections arranged according to a straight-line wiring convention (e.g., "Manhattan wiring"). In subsequent iterations of the example process 200, operations 201-207 can be omitted, where the updated layout 270 can be stored as the 3D representation 235.

[0054] At operation 209, example process 200 includes generating individual contributions of one or more electronic properties of the interconnects to the monomers constituting the three-dimensional representation 235. Individual contributions may include capacitance contribution 250 and conductance contribution 255 to characteristic metric 260. Characteristic metric 260 may be based on an objective function that defines one or more parameters of the interconnect. Characteristic metric 260 may include any electrical characteristic or parameter that can be derived from first-principles simulation or otherwise inferred from a simulation environment of a given network and / or integrated circuit, such as, but not limited to, resistance, capacitance, admittance, admittance density, impedance, or RC time constant. In the illustrative example, characteristic metric 260 may correspond to the RC time constant of the interconnect, which may be used as a convergence metric for multiple iterations of example process 200. Individual contributions 250 and 255 may be used as part of a physically meaningful heuristic or other modeling approach in shape optimization, which may refine characteristic metric 260 as part of the optimization of layout file 170. For example, convergence of the physical simulation to the optimal RC value can correspond to approximately 20 iterations or less, approximately 19 iterations or less, approximately 18 iterations or less, approximately 17 iterations or less, approximately 16 iterations or less, approximately 15 iterations or less, approximately 14 iterations or less, approximately 13 iterations or less, approximately 12 iterations or less, approximately 11 iterations or less, approximately 10 iterations or less, approximately 9 iterations or less, approximately 8 iterations or less, approximately 7 iterations or less, approximately 6 iterations or less, approximately 5 iterations or less, approximately 4 iterations or less, approximately 3 iterations or less, approximately 2 iterations or less, or 1 iteration. However, as the complexity of layout 170 increases, the number of iterations can exceed 20.

[0055] In one or more embodiments, the electromagnetic simulations used to determine individual contributions 250 and 255 correspond to simulations of a given interconnect. The electromagnetic simulations may be based at least in part on layer information 225 and terminal information 220 to generate electrostatic and / or electromagnetic field values ​​for at least a subset of the cells included in the three-dimensional representation 235. In some embodiments, local contributions to characteristic metrics are calculated based on field values ​​obtained via electromagnetic simulation (e.g., physical simulation module 143). For example, fluxes of current density, admittance density, or more generally, parameters related to the resistance or capacitance of the interconnect can be calculated for individual cells. In this way, spatially localized cell-level simulation results can be used to determine how current flows through the simulated environment in response to a bias signal, which in turn can be used to calculate the local contribution of individual cells to characteristic metric 260.

[0056] It should also be understood that, since the field values ​​from the electromagnetic simulation are based on the material properties of individual cells, the local contribution is calculated at least in part based on the material properties. In some embodiments, the admittance density of at least a subset of cells is calculated at least in part based on the field values ​​to determine how the cells affect the admittance matrix of the interconnect. In some embodiments, the admittance density corresponds to the scalar field of the simulation environment at the location discretized using the cells. The admittance density can be understood as describing the local contribution to the overall conductance and capacitance of the interconnect. It should be understood that the admittance density can be derived in part from the field values ​​of the electromagnetic simulation in a three-dimensional representation of 235, as referenced in [reference missing]. Figure 3A -3F and Figures 3A-4B More detailed description.

[0057] At operation 211, the example procedure includes modifying the 3D representation 235 using the output of the physical simulation module 143 and / or the machine learning model 144. (See reference...) Figures 3A-4B and Figure 7 In more detail, the local contribution of a monomer to a characteristic metric (e.g., a convergence metric or optimization criterion) can be used to reshape the interconnect by reassigning material property information of one or more monomers in the 3D representation 235 or by deforming one or more monomers in the 3D representation 235. In an illustrative example, layer information 225 and terminal information 220 can be used to determine the capacitive and conductive contributions to the overall RC value of the interconnects of at least a subset of the monomers in the 3D representation 235. In this example, the material identifier of one or more monomers in the subset of monomers can be modified, at least in part, based on a comparison of the relative magnitudes of the respective contributions of each monomer. Reference Figure 4A-7 C Figure 8-10 and Figure 11 An exemplary embodiment of the three-dimensional representation 235 generated at operation 211 is described in more detail.

[0058] In some embodiments, example process 200 includes one or more sub-operations to modify operation 211. For example, modules 147 and / or 149 can verify the manufacturability of the 3D representation through process simulation to generate a predicted manufacturing state of a modified 3D representation 235 of the semiconductor manufacturing system 115, as referenced. Figure 1 In a more detailed description, if the manufacturing state fails to reproduce one or more functional aspects of the modifications to the 3D representation 235, the manufacturability check implemented as module 147 can return a simple Boolean false value or indicate which modifications might introduce defects into the manufacturing layout. Advantageously, performing the manufacturability check using a physically meaningful process can facilitate curved routing, at least in part because heuristics and / or rule-based manufacturability verification tools (e.g., design rule checker algorithms) are typically formulated for conventional straight routing.

[0059] Using the output of manufacturability analysis, example process 200 may include correcting modifications to the 3D representation 235 to maintain interconnect functionality within the context of layout file 170. In some embodiments, a machine learning model 144 may be trained to correct modifications to the 3D representation 235 to preserve manufacturability, for example, through supervised training using a set of paired manufacturable and non-manufacturable layouts 170. In this context, training data may be generated from multiple layout files 170 validated using a physics-based process model. Such a physical simulation may include elements configured to identify units and / or regions of the 3D representation 235 that may be mismanufactured, for example, using a process model developed for compositional operations included as part of manufacturing an integrated circuit using semiconductor manufacturing system 115. By preserving functionality as a criterion for determining manufacturability, rather than other quality factors (e.g., edge placement error), operation 211 may advantageously generate physically meaningful manufacturability scores that facilitate the transition to curved interconnect shapes. As shown, iterations of example process 200 may occur on a subset of compositional operations. For example, iterations may include operations 209 and 211, where layer information 225 and terminal information 220 are maintained for each iteration based on layout data 215 received at operations 201-205. Similarly, the 3D representation 235 may be modified on a per-mono basis, rather than modifying the layout file (e.g., as a transformation of one or more polygons or vertices of layout file 170). Thus, encoding layout file 170 with 3D representation 235 and modifications from operation 211 may include one or more image processing techniques applied to 3D representation 235 to convert quantized regions described by monomers into smooth regions with lines. In doing so, a portion of conductive material in a subset of monomers may be reassigned to dielectric material, and a portion of dielectric material in a subset of monomers may be reassigned to conductive material. However, in some embodiments, where the monomers have feature sizes below the resolution lower limit of one or more processes of semiconductor manufacturing system 115, the updated layout may retain smooth quantization boundaries during manufacturing.

[0060] At operation 213, example process 200 includes outputting an updated layout 270. The updated layout 270 may include, but is not limited to, generating a layout file 170 using a 3D representation 235, which incorporates modifications made in one or more iterations of operations 209 and 211. In some embodiments, the updated layout 270 may be encoded as layout file 170, such as GDSII or OASIS, a mask set, or any other data format used in integrated circuit design. In some embodiments, the updated layout 270 may be encoded as visualization data, which may be distributed by client computing device 110 or otherwise accessed as part of an interactive design environment. In this manner, one or more users of the interactive design environment may simultaneously or in parallel access and / or modify layout file 170 and / or the updated layout 270.

[0061] Detailed discussion of interconnect shape modification

[0062] With a successful path established between terminals, the capacitance between the grids can be determined and used to optimize the interconnect shape to improve RC. However, other optimization metrics can also be envisioned, including but not limited to reduced electromigration and avoidance of dielectric breakdown. For this purpose, the admittance density can be calculated using the repeated equation (1) below. y To understand which regions contribute to RC, we can then develop heuristics to reshape interconnects to improve RC.

[0063]

[0064] Among them, the basic element f k It is a solution to the complex Laplace equation.

[0065]

[0066] The Dirichlet boundary condition is 1 at terminal k and 0 at all other terminals. The Neumann boundary condition applies everywhere else. Here, the complex material parameters are given by the following equation:

[0067]

[0068] The dielectric constant is ε, the conductivity is σ, and the angular frequency is ω. Then, the admittance matrix of the system with N ports can be determined as a volume integral over the admittance density:

[0069]

[0070] Without being defined by a specific physical mechanism, it should be understood that RC depends on the load attached to the output terminal of the interconnect, which represents the transistor gate contact in CMOS logic. When the gate capacitance of the transistor gate is large, interconnect shape optimization can include reducing the interconnect resistance while the interconnect capacitance can be negligible or substantially negligible. While such a scenario is typical for older vendor process nodes, in modern technology nodes such as FinFET technology, the interconnect capacitance is comparable to the transistor gate capacitance. Thus, modifying the interconnect shape can depend on the ratio between the wire capacitance and the attached load.

[0071] Input Admittance and RC: RC can be calculated from admittance, at least in part, based on the effect of the admittance density of a single interconnect on the overall RC of the routing IC layout. As part of the time constant for generating the overall RC, the admittance matrix for a complete routing system with N ports can be determined using the following expression. Y kl :

[0072]

[0073] Furthermore, the regions represented in the three-dimensional layout file 170 can be assigned to terminals belonging to transistors or external pins. Input admittance of input i. Y i in It can be limited by the following formula:

[0074]

[0075] And it is determined by the underlying system of interconnects and transistors.

[0076] Since the attached load (e.g., the transistor) is a non-linear component, the transistor resistance and capacitance are evaluated based on the instantaneously applied voltage signal. As a simplifying assumption, the gate capacitance can be defined by assuming the maximum capacitance across all operating points of each transistor t:

[0077]

[0078] However, in practice, the effective capacitor for the characteristic voltage ramp or slew can be selected according to embodiments of this disclosure.

[0079] For RC calculation purposes, the low-frequency component of the capacitor is significant. Since the capacitor is frequency-independent until somewhere around the cut-off frequency, in some embodiments, the frequency dependence will be assumed to be negligible. To calculate the input admittance at terminal i... Y i in We will also need to assume the load admittance at all other input terminals j≠i. For simplicity, we can assume ideal ohmic contact, i.e. Finally, we can calculate the input admittance of terminal i as follows:

[0080]

[0081] Here, considering the load Y in addition to the input terminal i, we set the current to its appropriate value. Therefore, we can directly solve the following linear equation:

[0082]

[0083] Where δ kl It is Kronecker-delta.

[0084] The input admittance defined in equation (6) can be determined according to equation (9). Y i in Having l≠i V l appl The value can be calculated and used in the top equation of equation (9), but the bottom equation is calculated by taking all values ​​with l ≠ i. V l appl Represented as V l appl A function to precisely contain that information.

[0085] Using input admittance Y i in The RC at terminal i can be calculated using the following expression. i :

[0086]

[0087] RC i Capacitive and resistive effects, as well as other phenomena, including but not limited to crosstalk and / or coupling efficiency based on loads attached to other wires, are considered. However, equation (10) describes the instantaneous RC time constant. For nonlinear elements such as transistors, the instantaneous RC time constant differs from the RC measured in large-signal operation. For this reason, the following discussion assumes the worst-case gate capacitance for all operating states. In this way, the objective function for optimizing the interconnect shape for RC values ​​is understood to be defined by the worst-case RC.

[0088] RC Improvement Heuristic: Equation (10) shows that the wires used in optimizing RC are not unimportant. First, the input admittance... Y i in It is the admittance matrix Y k lThe complex function of the elements is understood to lack an analytical solution. Secondly, RC is determined by the quotient in equation (10), which means its value is non-locally determined. In this way, algorithms for optimizing RC cannot easily determine whether local changes in the interconnect structure (e.g., widening and / or narrowing of the interconnect at one or more locations) improve or worsen the output of the objective function. Thirdly, due to the nature of how RC is calculated, the transistor load in the implicit input admittance system of equation (9) is an important factor in determining how to optimize the interconnect structure. In some embodiments, the magnitude of the load at the terminals can make the interconnect capacitance essentially negligible, resulting in a wide optimal interconnect to increase conductivity. This was the case in older supplier process nodes, but in contemporary and foreseeable process nodes, interconnect capacitance and gate capacitance can be comparable. In such cases, the width of the interconnect can depend on the length of the interconnect. For example, a relatively short interconnect can be relatively wide, while a longer interconnect can be characterized by capacitance indicating that RC is improved by reducing its width.

[0089] In short, interconnect optimization presents a significant computational challenge. Advantageously, the numerical techniques described in this paper can be supplemented with simple heuristics to improve circuit timing, such as widening interconnects, inserting vias to reduce resistance and / or increasing the spacing between near-side conductors or reducing the parallel travel length of near-side conductors to reduce cross-coupling capacitance. Thus, the RC optimization scenario can be understood as allowing the algorithm to follow gradients toward local optima. Such a hybrid approach, including finite volume methods and simple heuristics, can improve IC performance by modifying the layout file 170 while simultaneously reducing the computational resource requirements of the optimization process.

[0090] The structure of the capacitor is illustrated by an algorithm such as FasterCap, which represents the interconnect capacitance according to the Green's function of the Laplace equation, since the electric field strength between the interconnects is an equivalent measurement of the capacitance. Similarly, the current density within the interconnects is an equivalent measurement of the conductance via Ohm's law. Thus, the admittance density of equation (1) can be used to determine the local conductance and capacitance contributions to the overall admittance of equation (5). In this way, the admittance density... y The contribution in the space can be used as the basis for determining the RC of equation (10).

[0091] As a preliminary point, a heuristic for improving interconnect design without numerical or analytical methods is described. Starting with a layout 170 including interconnects and one or more terminals, each described by a material parameter κ(r) defined using the following expression:

[0092]

[0093] In this way, the layout file 170 can be updated at least in part based on the determination of the material parameters of whether the spatial coordinate r should have interconnecting metals or insulators and / or dielectrics.

[0094] Single load: Attached load The optimization of the wire shape at input terminal a significantly affects whether the interconnect can be widened to carry more current or narrowed to avoid capacitive cross-coupling, as well as the optimization of RC. a Part of it. In some cases, it can be assumed that the network connects two terminals a and b to a single load. Connected, while all other terminals are short-circuited, where Inserting these loads into equation (9) yields the following expression:

[0095]

[0096] In the second component expression of equation (12), terms with relatively small amplitudes, such as those other than the load at the short-circuit terminal, can be ignored. Because Since it is non-zero, the bias applied at the short-circuit port k can be understood as the applied voltage being close to zero. V l appl →0. Inserting this into the first two component expressions produces the following equation:

[0097]

[0098] Solve The second component expression, and the result inserted into the first component expression, allows the following equation for the input admittance to be derived:

[0099]

[0100] It is understood as an expression for an interconnection that couples two terminals to a single load.

[0101] RC of equation (10) a The expression is expanded to include real and imaginary components, and equation (14) can be used to derive RC. a The following expressions:

[0102]

[0103] For a single interconnect coupling terminal a to terminal b, the admittance matrix can be expressed as:

[0104]

[0105] For CMOS technology, it can be assumed that terminal b corresponds to the gate, which acts as a capacitive load. Therefore, It can be represented as a complex number. Using this complex value, the RC of equation (13) a It can be rewritten as:

[0106]

[0107] In equation (17), the structure of the RC time constant is shown as the ratio of the capacitance contribution to the conductance contribution. This allows for a comparison of the interconnect conductivity with the capacitance of the load and the interconnect. The output capacitance C is compared with the load capacitance C0. L At least partially combined, because from the perspective of input a, it can be understood that it is physically indistinguishable whether the capacitance at the output is part of the interconnect structure or part of the load.

[0108] Constant width toy model optimization: Figure 3A This is a schematic diagram illustrating a toy model 300 of a two-port interconnect 310 according to an embodiment of the present disclosure. Figure 3A An interconnect 310 is shown electrically coupled to two terminals 305 (e.g., "ports") having an equivalent circuit with physical size, conductance G, and capacitance C. In subsequent processing, the interconnect 310 is optimized to drive the load C. L . Figure 3A Toy model 300 is shown, where transmission line effects are neglected, such as the effect of capacitance distribution along the length "L" of interconnect 310. Thus, the following simple analytical model for conductance and capacitance is applied:

[0109]

[0110] Where x W L and W are like Figure 3A The indicated dimensions, and H is the height in the remaining direction. σ and ε are the conductance and dielectric constant, respectively.

[0111] Inserting the terms from equation (18) into equation (17) gives the following equation:

[0112]

[0113] Equation (16) reveals that if the interconnect capacitance 310 is equal to or greater than the load capacitance, then RC can be compared with L. 2 Proportional. Thus, the short conductor driving a large load can be understood as being proportional to L, as in reference... Figure 2 In more detail, in some embodiments, the local width of interconnect 310 is a manipulated variable in the optimization scheme to improve the performance of interconnect 310 (e.g., by minimizing RC). a In this method, the width x of the interconnect 310 WThis is understood to depend at least in part on the operating parameters of the load as represented by terminal information 220. Figure 3A The figure shown has a uniform width x W In a two-port scenario, given the load capacitance C L The optimal width is described by the following expression:

[0114]

[0115] In equation (20), C0 is defined as the capacitance of interconnect 310 over the full width L or It should be noted that the minimum RC a value x opt The location of the interconnect is independent of conductivity and can be determined based on the ratio of the inherent capacitance of the interconnect 310 to the external load capacitance. For small loads, the interconnect 310 primarily drives its own capacitance, resulting in an optimal width x. opt ≈W / 2. However, as the load increases, the delay caused by the charging of the load capacitance becomes significant. As a result, x opt Increase. Note that due to the inverse dependence of interconnect capacitance on dielectric width, the inherent wire capacitance can be balanced with capacitive loads. Thus, as the capacitive load approaches infinity (C... L →∞), asymptotically approaching x opt →The limit of W.

[0116] For RC-based shape optimization, the position of one or more interfaces between the conductive and dielectric materials can be modified, at least in part, based on the relative amplitudes of the electric fields stored in the conductor and dielectric. For this purpose, the admittance density of equation (1) can be expressed in the interconnect metal M and the dielectric OX (in the oxide example):

[0117]

[0118] The expression for RC is:

[0119]

[0120] Equation (22) qualitatively reveals a technique for locally optimizing interconnect 310: at the interface between the metal and oxide, if the imaginary part of the admittance density contributes more to the overall capacitance than the real part of the admittance density contributes to the overall conductance in the conductor, then the interconnect boundary 311 is moved to increase the capacitor plate distance (e.g., reduce the interconnect 310). On the other hand, if the real part in the conductor has a larger contribution, then the interconnect boundary 311 is moved to increase the conductor cross-section.

[0121] For gradient-based optimization, a differentiable function of RC is derived, at which the optimal value can be approximated by the difference δRC. a [y The stationary point corresponds to 0. Solving the equation (22) for the stationary point yields an expression that holds for all values ​​of r0:

[0122]

[0123] As shown in equation (23), in the optimal configuration, the contributions of local capacitance and conductance are balanced, and the corresponding contributions are limited to:

[0124]

[0125] Equation (24) describes the local capacitance contribution at position r, and equation (25) describes the local conductance contribution at position r. From these expressions, which are informed by the qualitative method described in equation (22), the heuristic for improving the RC of the interconnect can be derived as follows, based on r. inter To formulate, r inter It is located on the interface 311 between interconnect 310 and dielectric:

[0126] If C C (r inter >C G (r inter If ), then the interconnect width is reduced.

[0127] If C C (r inter ) < C G (r inter If ), then the interconnect width is increased.

[0128] If C C (r inter ) = C G (r inter If ), then the interconnect width is maintained.

[0129] To summarize the previous processing of the RC circuit, the voltage generator Can be associated with generator admittance Y G Including together. In digital circuits, the generator is typically the power grid, and the generator admittance Y G The real part of the generator admittance is related to the channel resistance and capacitance of the interconnect 310 and the MOSFET. It can be associated with the channel conductance of the MOSFET in the on-state and therefore interpreted as the drive strength of the interconnect 310. Different drive strengths can lead to different optimal interconnect 310 designs, similar to what was previously demonstrated for load admittance.

[0130] To determine RC, the following relationship can be used from an ideal voltage source. Find the input admittance

[0131]

[0132] Where the generator current I G The admittance value of the two-port interconnect 310 can be obtained using the following expression. Y in and Y G Related:

[0133]

[0134] Equation (27) can be combined with and rearranged with equation (26) to find The expression is as follows:

[0135]

[0136] Equation (28) can be combined with equation (25) to produce the expression for RC:

[0137]

[0138] Figure 3B This is a schematic diagram illustrating an example variable-width interconnect 310 with two coupled terminals 305 according to an embodiment of the present disclosure. To derive the corresponding two-port admittance matrix, an approximation based on the solution of the Laplace equation for the fundamental elements can be used to reduce the complexity of the description using equivalent circuits. For this purpose, it can be assumed that the potential in the highly conductive interconnect is constant in the x-direction. Figure 3B In this context, the x-direction is defined as shown.

[0139] Using the assumed constant conductivity, the basic element f a and f b The Laplace equation can be understood as a statement of current conservation as a function of the position in the y region between terminals 305. More specifically, the basic metallic elements can be defined for the metallic region. In this context, using Gauss's integral theorem, the integral over the control volume containing two interconnected slices at y=0 and some arbitrary interior point y0 presents the following expression:

[0140]

[0141] Since equation (30) is a general expression for any y0, the conservation of current provides that I0 is constant, and the fundamental elements of the metal... The following expressions can be used to qualify:

[0142]

[0143] As previously stated, the subscript "a" is assigned to one of the terminals 305 coupled by interconnect 310. In this manner, for terminal "b", the basic metallic element can be defined by the following formula:

[0144]

[0145] For equations (31) and (32), the boundary conditions are respectively limited as follows: and

[0146] The basic elements of a dielectric can be expressed as simple linear functions, derived from their properties in metals. The corresponding value decays to zero at the electrode position x = W, such as Figure 3B As shown. The resulting dielectric basis functions can be constrained for the dielectric as follows:

[0147]

[0148] In simplifying assumptions In this case, equation (28) can be used in conjunction with equation (29) to derive constraints on the admittance density generated by the fixed point of the RC. Once found, the fixed point can be defined as a fixed point used to modify the shape of the interconnect 310 (e.g., by shifting at least a portion of the interface 311). The general form of the RC expression, including the generator and load admittance, is used as described in equation (29):

[0149]

[0150] The fixed point is given by the following formula:

[0151]

[0152] The functional derivative of the generator input admittance is given by the following equation:

[0153]

[0154] For the two-terminal interconnect 310 of 305, the complete expression for the functional derivative of equation (35) can be derived from it as:

[0155]

[0156] in:

[0157]

[0158] as well as

[0159]

[0160] According to equations (37) to (39), the fixed-point expression can be limited to any point r0 on interface 311 as follows:

[0161]

[0162] Detailed discussion of arbitrary fan-out

[0163] The derivation of RC variations can be extended to the interconnection of the driver (input terminal 305) to multiple output terminals 305, as shown in the reference. Figure 8 A more detailed description follows. In the RC expression given in equation (34), output terminal 305 affects the input admittance that forms part of the generator input admittance. Y in The value of . In this way, the RC of any fanout and its variation can be determined at least in part by calculating the input admittance and its derivative with respect to different admittances.

[0164] Therefore, consider an interconnect 310 with input terminals 305a∈{1,2,…,N}, which can be represented by an N×N admittance matrix. And the loads of all terminals 305 with i = 1, 2, ..., N. Y i L To characterize this, we use Ohm's law to determine the input admittance in this case. Initially, simplified notation is used, but it should be understood that both I and V refer to vectors of complex phasors. To calculate the input admittance relative to terminal 305a, the effect of the load on all ports except a can be determined. For this, remove all values ​​equal to the values ​​in the row and column corresponding to terminal 305a. The reduced (N-1)×(N-1) matrix Similarly, vectors and They are respectively decomposed into equalities I and V, but without element a. Then... In this regard, Ohm's law can be expressed as:

[0165]

[0166] in It is an (N-1)×(N-1) diagonal matrix, where all loads except terminal 305a lie on its diagonal. Furthermore, H contains elements H = (..., Y k a ,...) T , k∈{1,...,N}\{a}.

[0167] Equation (41) can be simplified to voltage ratio (V rThe expression relating H and H is shown below:

[0168]

[0169] Where Vr = V ～ / Va is the ratio relative to the input voltage.

[0170] Equation (42) can be used to determine the input admittance as a function of the elements of the voltage ratio and admittance matrix:

[0171]

[0172] Using these expressions, we can constrain and solve systems of linear equations to constrain the derivative of the input admittance:

[0173]

[0174] Detailed discussion of monomeric RC contribution

[0175] For reference Figure 2 In more detail, the following discussion illustrates an illustrative example of a calculation technique for optimizing the RC of interconnects 310 in a layout file 170 comprising one or more nets. Starting with a complete wiring layout 170 comprising N interconnects 310, each interconnect 310 having a T... n A set of terminals 305, where n ∈ {1, 2, ..., N}. Furthermore, each interconnect 310n has one or more inputs originating from pull-up and / or pull-down networks, and one or more outputs terminating at a load (e.g., a gate in CMOS technology). The set of inputs for interconnect 310n is represented as... And the output set is in Describe terminal set 305 (e.g., terminal 310 can couple an input to an output without a dead or null terminal).

[0176] The shape optimization of interconnect 310 includes defining the local contribution δRC(r) of each interconnect 310. When RC is minimized, it is stationary and the variation δRC disappears, which occurs by eliminating its conductive component inside the interconnect and its capacitive component outside the interconnect, see two terms in equation (40).

[0177] Detailed discussion of shape modification:

[0178] Therefore, if the interconnect is not RC optimal, we can find the interconnect interface "r inter The imbalance of components at point "" indicates the contribution of conductivity. δRC is the value within the interconnect, and represents the capacitance contribution. Let δRC be the value of the external interconnect. Then, the heuristic for improving RC is given by the following equation:

[0179] if This reduces the interconnect width.

[0180] if This increases the interconnect width.

[0181] if Then maintain the interconnect width.

[0182] In the context of the heuristic described above, an equation can be understood as being approximate within the range of values. For example, if Within a given tolerance, it is essentially equal to This allows maintaining the interconnect boundary 311. Similarly, if Greater than If the given tolerance is exceeded, the width of interconnect 310 can be reduced. In some embodiments, the tolerance can be used as... and The values ​​are given as ratios. For example, approximately 1.5 or less, approximately 1.4 or less, approximately 1.3 or less, approximately 1.2 or less, approximately 1.1 or less, approximately 1.05 or less, approximately 1.01 or less. and The ratio of interpolation to its fraction can be considered equal within the tolerance.

[0183] The algorithm implements local modifications to interconnect boundary 311, affecting the boundary region 313 near interconnect boundary 311. and The value becomes complex due to its geometric dependence. (See reference...) Figure 7 In more detail, assigning material to a single entity in the three-dimensional representation 235 may include determining the differential contribution of the single entity in the discretized space and comparing the corresponding contributions of adjacent discretized volumes (e.g., single entities) in the boundary region 313.

[0184] In some embodiments, the relative influence of the conductive and dielectric materials in the boundary region 313 on the differential RC contribution at a given location r of the interconnect 310 can be determined by... and The value is extrapolated to neighboring cells in the three-dimensional representation 235 to resolve the issue. In some embodiments, extrapolation may include applying a three-dimensional smoothing operation to the cells. Examples of three-dimensional smoothing include a Gaussian smoothing function, defined as follows:

[0185]

[0186] Where σ is the three-dimensional standard deviation vector of the value, and in Cartesian space, σ = (σ x , σ y , σz It should be understood that σ can be defined in other coordinate spaces to correspond to the coordinate space used to define the three-dimensional representation 235. The value of σ affects the range of smoothing, with smaller values ​​resulting in more restricted smoothing and larger values ​​resulting in wider smoothing. In some embodiments, in order to limit the possibility of the relative boundary 311 influencing the field contribution—which is a vector quantity—the value of σ can be smaller than the width X of the interconnect 310. W (Y). In this way, σ can be a function of the position in the three-dimensional representation 235, or it can be a consistent value of the layout 170. In some embodiments, the initial value of σ is selected to be greater than the initial width of the interconnect 310 (e.g., in straight wiring, the width can be a single value).

[0187] In the case of the Gaussian smoothing function in equation (45), the smoothing contribution of conductance and capacitance at a given position r can be expressed as a three-dimensional convolution:

[0188]

[0189] in and Let r represent the smooth capacitance contribution and smooth conductance contribution at position r in the three-dimensional representation 235, respectively. Advantageously, smooth extrapolation, such as that described in equations (45) and (46), allows the relative contributions of the monomer to the conductance and capacitance of the interconnect 310 (e.g., the real and imaginary parts of RC) to be determined with minimal influence of the relative position of the monomer to the interconnect boundary 311. In this way, for position r in the interconnect 310, where Within a given tolerance ε, material can be reassigned from conductor to dielectric (e.g., from metal to oxide). Otherwise, the material in the corresponding monomer from interconnect 310 to location r can be maintained as conductor. Similarly, for location r outside interconnect 310, where Within a given tolerance ε, material can be reassigned from dielectric to conductor (e.g., from oxide to metal). Otherwise, the material of the interconnect 310 to position r in the corresponding monomer can be maintained as dielectric.

[0190] In some embodiments, the simulated mesh is unstructured, and instead of reassigning material to monomers, we can move interconnecting walls via mesh movement operations.

[0191] For reference Figure 7In more detail, in some embodiments, manufacturability checks may be included as part of the operation of example process 200, including but not limited to generating an updated layout 270. Given that a process function P(M,θ) depending on the mask set M and the fab parameter θ is available, the material parameter domain describing the interconnect 310 can be determined. Using the interconnect 310 structure with a given M0 and θ, the material parameters and other quantities of interest of the interconnect 310 structure can be determined using the process function P(M0,θ) = {σ(r), ε(r), ...} = S0, where the wafer state S0 of the initial iteration 0 is defined as the set of physical quantities describing layout 170. Using the methods described above, the admittance of the interconnect 310 can be determined, and the smoothing contribution of the interconnect 310 can be determined based on the generator and load admittance.

[0192] Using the updated layout 270, the index design D1 can be defined for the next iteration (e.g., iteration 1 after initial state 0), which includes updated material parameters for the monomers constituting the three-dimensional representation 235. Using process data describing the wafer fab parameters θ, process simulations can be performed to simulate the manufacturing outcome of D1, which can be used to modify D1 to a new wafer state S1. In some embodiments, D1 can be manufactured based on physical simulations while also violating the Boolean design rules of the process. In this way, the manufacturability checks described herein can target reserved features rather than satisfying manufacturer-provided design rules, which can be developed to minimize other quality factors, such as edge placement errors, based on straight-line routing but less applicable to curved routing.

[0193] In one or more iterations (“i”) of the above operation, the wafer state S i The RC value can converge to an optimal value, which can also be manufactured based on physically meaningful process simulations. Advantageously, manufacturability verification based at least in part on process data can provide differentiable manufacturability corrections, where small changes to design D will result in small changes to the wafer state. In contrast, Boolean design rules are not smooth or differentiable and do not allow the gradient-based optimization techniques described above to include manufacturability-based corrections to update layout 270.

[0194] To achieve the above optimization in order to receive the mask set M IN Combine process data θ and output the corrected mask set M OUT An exemplary algorithm, see reference Figure 7 A more detailed description of layout file 170 includes the following operations, which can be parallelized or otherwise reordered:

[0195] 1. Calculate wafer state S0 using the process model (“P”).

[0196] 2. Calculate the wafer state S of interconnect 310 using equation (37). i Net contribution and

[0197] 3. Calculate the Gaussian smoothing of equation (46) for interconnect 310. and

[0198] 4. Use the above heuristics to generate a new indicator design D i+1 .

[0199] 5. At least partially use process simulation P(D) i+1 To calculate the closest value to D, θ) i+1 Time-manufacturing mask set M i+1 .

[0200] 6. Using P(M) i+1 ,θ)=S i+1 Calculate the new wafer state S i+1 .

[0201] 7. Using the new chip, status S i+1 Calculate the optimization objective (e.g., RC value). If the optimization objective value does not meet the metric or standard (e.g., increment or convergence metric), increment i and return to step 2.

[0202] 8. As convergence occurs, return the final mask set M. F .

[0203] Figures 4A-4D This is a schematic diagram illustrating a two-dimensional planning projection on the "xy" plane of a portion of a three-dimensional representation 235 of a layout file 170 and an updated layout 270 according to an embodiment of the present disclosure. The projection representation is as shown in the reference. Figures 3A-3B A more detailed description of the two-port interconnect, including one or more iterations of shape optimization, can be completed and / or has been completed, as shown in the reference. Figure 2 and Figures 3A-3B As described above. In this manner, it provides... Figures 4A-4D This illustrates the impact of layer information 225 and terminal information 220 on shape optimization and the updated layout 225. While representing exemplary simulation and optimization results, Figures 4A-4D This is not intended to be restrictive, but rather illustrative. For example, the shape optimization result may differ from the result based at least in part on the layer information 225, terminal information 220, and layout file 170 used to generate the 3D representation 235. Figure 4B-4DExamples are provided herein. Additionally or alternatively, the characteristic metrics used to guide shape optimization can also influence the results of shape optimization, as they may include physical effects such as dielectric breakdown or other field effects that can become significant at small length scales of nanometers or smaller. In this way, optimization using the same layout file 170, the same layer information 225, and the same terminal information 220 can lead to a modified layout 225 that differs from those shown. Advantageously, the actual interconnect structure may include layer-specific material parameters for each of the multiple layers. Furthermore, physical parameters such as electrical conductivity may vary within a single interconnect 310, for example, as a function of wall distance. Such variations are directly captured by the techniques described herein, but introduce significant complexity to rule-based systems, which may include adding new rule-based models for each layer and each interconnect 310.

[0204] Figure 4A This is a schematic diagram of an example layout 400, showing a simplified three-dimensional representation 235 of a layout file 170 illustrating at least a portion of an interconnect 310 (e.g., a two-port interconnect) that couples two terminals 305 according to embodiments of the present disclosure. The example layout 400 also includes additional conductive features 415, including but not limited to conductive backplanes, vias, or other terminals not coupled to the interconnect 310. (See reference...) Figure 2 In a more detailed description, three-dimensional representation 235 defines the monomer 401 of the dielectric material surrounding the interconnect 310, the terminal 305, the conductive element 415, and the interconnect 310. (See reference...) Figures 3A-3B In more detail, as part of shape optimization, the boundary region 313 near the surface of the interconnect 310 can be modified. Although the monomer 401 for the dielectric material is omitted in the example layout 400 for visual clarity, the boundary region 313, the conductive monomer 411 of the interconnect 310, and the dielectric monomer 413 outside the interconnect 310 (e.g., corresponding to oxide or nitride materials) are shown together in the illustration. The accompanying layout file 170 for generating the three-dimensional representation, and layer information 225, are used to identify the conductive monomer 411 and dielectric monomer 413 based on spatial information from the layout file 170.

[0205] While example layout 400 conforms to straight-line routing conventions, characteristic measures, including but not limited to, those of the RC time constant of interconnect 310, can indicate that interconnect 310 may be suboptimal in terms of its shape. For example, electromagnetic interactions between interconnect 310 and one or more conductive elements 415 can increase the RC time constant of a given set of terminal information 220. As part of reshaping interconnect 310, terminal information 220 can be used with the three-dimensional representation 235 of example layout 400 to determine the individual contribution of individual units 401—such as units 401 near boundary region 313—to the RC value of the interconnect under specific operating conditions defined in terminal information 220. In this way, different terminal information 220 can lead to different updated layouts 270, as referenced. Figure 4B-4D More detailed description.

[0206] Figure 4B According to an embodiment of this disclosure, a first set of terminal information 220 is obtained from... Figure 4A Example plan 425 is generated from the updated layout 270 of example plan 400. Without being defined in a specific set of terminal information 220 and layer information 225, example plan 425 represents the output of one or more iterations of example process 200 using example plan 400 as input to physical simulation module 143.

[0207] Example plan 425 corresponds to an embodiment of example process 200, wherein terminal information 220 includes input frequency, driver impedance, and load capacitance. For simplicity, descriptions of specific values ​​to focus on the relative effects of the constituent parameters of terminal information 220 are omitted. In practice, it should be understood that terminal information may include values ​​of parameters corresponding to those used during integrated circuit operation. For example, driver impedance may be or include values ​​of approximately zero ohms or greater, approximately 10 ohms or greater, approximately 100 ohms or greater, approximately 1000 ohms or greater, approximately 5000 ohms or greater, approximately 10,000 ohms or greater, approximately 100,000 ohms or greater, approximately 1,000,000 ohms or greater, or approximately 10,000,000 ohms or greater, including its fractions and interpolations. Similarly, input frequency may be or include frequencies in the kHz, MHz, or GHz range, including their fractions and interpolations. Similarly, the load capacitance can be or include values ​​of about 0.0001 fF or greater, about 0.001 fF or greater, about 0.01 fF or greater, about 0.1 fF or greater, about 1.0 fF or greater, about 10 fF or greater, or about 100 fF or greater, including their fractions and interpolations. In the illustrative example, example configuration 425 may correspond to terminal information specifying a driver impedance of about 1 M ohms, a load capacitance of about 1 fF, and an input frequency of about 100 GHz.

[0208] like Figure 4B As shown, the shape of interconnect 310 in example design 425 is significantly different from the straight shape of interconnect 310 in example design 400. Specifically, interconnect 310 is wider, where the non-uniform widening of interconnect 310 is applied as a function of its lateral position relative to terminal 305. (See reference...) Figure 2-3B The location-dependent width (“X”) of interconnect 310 is determined by using the contribution of monomer 405 to the capacitance and conductance terms based on the RC time constant of interconnect 310. W (Y)”). Without being defined in relation to a particular physical phenomenon, the shape of the interconnect 310 of the updated layout 270 shown in example layout 425 is understood to indicate the contribution of capacitance, which is greater than the contribution of conductance to the RC value of interconnect 310.

[0209] Advantageously, the techniques described herein allow the example system 100 to generate an updated layout 270 corresponding to the example plan 425 through one or more iterations of the example process 200, using physically meaningful information rather than physically naive heuristics. For example, it might appear that the example plan 425 could be generated by a rule-based model designed to widen the interconnects 310 while maintaining a minimum distance between the interconnects 310 and the conductive elements 415. However, such a physically naive model would not produce an updated layout 270 that results in optimized RC values ​​for the terminal information 220 and the layer information 225.

[0210] However, as referenced Figure 1 In more detail, the physical simulation module 143 can be enhanced with one or more machine learning models 144 trained to reshape at least a portion of the interconnect 310. For example, a convolutional neural network can be trained to accept a layout file 170 or a 3D representation 235 as input, having terminal information 220 and / or layer information 225, and output the reshaped interconnect 310. The output of the machine learning model 144 may be or include material identifiers of one or more monomers 401, a portion of interface 311, etc. Unlike models based on physically naive rules, the machine learning model 144 can be trained, for example, using a labeled training set of the linear layout file 170 and the updated layout 270 (e.g., as a method of supervised training) against a specific set of terminal information 220 and / or layer information 125. In this way, the machine learning model 144 can approximately reference... Figures 3A-3B The physical simulation described.

[0211] Figure 4C The second set of terminal information 220 used according to embodiments of this disclosure is from Figure 4A Example layout 400 generates updated layout 270. Another example layout 440 is also shown. Figure 4BSimilar to example plan 425, example plan 440 is... Figure 2 Example procedure 200 operation generation, as shown in the reference Figures 3A-3B More detailed description. Compared to example layout 425, example layout 440 includes a relatively narrow interconnect with a wider spacing between the interconnect surface 311 and the conductive element 415. Example layout 440 illustrates the effect of different terminal information 220 on the shape modification of interconnect 310, at least in part, based on operating parameters of terminals 305 and interconnect 310, such as driver impedance, load capacitance, or frequency. Figure 4C In the example, the driver impedance is a relatively higher figure than the corresponding driver impedance used to generate example layout 425. Thus, it can be seen that as the impedance increases, the conductance contribution of interconnect unit 401 decreases relative to the capacitance contribution of adjacent units 401 in boundary region 313, resulting in a relatively narrow interconnect 310. However, it should be noted that the interconnect 310 of example layout 440 is wider than the interconnect 310 of example layout 400, indicating that the typical straight-line "shortest path" route of the conventional routing algorithm is not optimized for the RC time constant. This further indicates that imposing a straight-line routing convention may lead to performance degradation of the integrated circuit proportional to the number of interconnects.

[0212] Figure 4D According to an embodiment of this disclosure, a third set of terminal information 220 is obtained from... Figure 4A Example layout 400 generates updated layout 270, and example layout 460.

[0213] and Figure 4B Example planning 425 and Figure 4C Similar to example plan 440, example plan 460 is... Figure 2 Example procedure 200 operation generation, as shown in the reference Figures 3A-3B Described in more detail. Compared to example layout 425, example layout 460 includes a relatively narrow interconnect with a wider spacing between the interconnect surface 311 and the conductive element 415. Example layout 460 illustrates the effect of different terminal information 220 on the shape modification of interconnect 310, at least in part, based on operating parameters of terminals 305 and interconnect 310, such as driver impedance, load capacitance, or frequency. Figure 4C In the example, the driver impedance is a relatively higher number than the corresponding driver impedance used to generate example plan 425. Thus, it can be seen that as the impedance increases, the conductance contribution of interconnect cell 401 decreases relative to the capacitance contribution of adjacent cells 401 in boundary region 313, resulting in a relatively narrow interconnect 310.

[0214] Note that the interconnect 310 of example layout 460 has a substantially the same width as the interconnect 310 of example layout 400, except that the position of the interconnect 310 unit 401 and therefore the position of the interface 311 are repositioned relative to the position of the terminal 305. This demonstrates that, as part of example process 200, reshaping the interconnect 310 may include translating, shifting, and / or redirecting the interconnect 310 relative to one or more conductive elements 415 in layout file 170, as well as widening or narrowing the interconnect width 310.

[0215] Figures 5A-5B These are schematic diagrams illustrating example 3D representations 535 of layout file 170 and the updated layout 270, respectively. As shown, the 3D representation 235, including example 3D representation 535, includes 3D information discretized into monomers 401, with material properties assigned using layer information 225. Elements in layout file 170 can be located at different 3D positions, using... Figures 5A-5B The Cartesian axes “x”, “y”, and “z” are marked in the diagram. In some embodiments, optimization of interconnect 310 may be limited to interconnect 310 or may also include terminals 305. Similarly, one or more interfaces 311 may be constrained as part of the operation of example process 200. In this way, shape modifications to interconnect 310 can be guided away from non-physical solutions.

[0216] Figure 5A This is a schematic diagram illustrating an example three-dimensional representation 235 of a layout document 170 according to an embodiment of the present disclosure. The layout document 170 includes interconnects 310, terminals 305, conductive elements 415 at substantially the same "z" position as the interconnects 310, and additional conductive elements 515 at "z" positions different from the interconnects 310. In some embodiments, the conductive element 515 may be or include the terminal 305. The layout document 170 represents an exemplary input to an example process 200. Thus, the interconnects 310, conductive elements 515, and conductive elements 415 conform to a straight-line wiring convention. It should be understood that the three-dimensional representation 235 is discretized into monomers 501, wherein... Figure 5B Compared to the quantized curve interface 311 shown, straight-line routing allows each interface 311 of the interconnect 310 to be represented as a smooth single surface.

[0217] Figure 5B This is a schematic diagram illustrating an example 3D representation 575 of an updated layout file 270 according to an embodiment of the present disclosure. Example 3D representation 575 represents an optimized interconnect 310 reshaped according to example process 200, as referenced... Figure 2 More detailed description. As previously described, one or more interfaces 311 of the interconnect 310 can be constrained such that the interconnect 310 is reshaped while maintaining at least some electrical contact with the conductive element 515, while improving RC, as referenced. Figures 3A-3BA more detailed description. In Figures 3A-3B In the context, Figure 5B The diagram illustrates that physically based shape modifications to interconnect 310 can produce curved interconnect 310, which is at least partially based on an electromagnetic field simulation describing the interaction between interconnect 310 and conductive element 415 or conductive element 515, and is widened, narrowed, redirected, translated, shifted, or otherwise transformed at one or more locations. (See reference...) Figures 4A-4D In more detail, the final shape of the interconnect 310 is based at least in part on the terminal information 220 and the material information 225, such that Figure 5B The shapes of the interconnects shown are intended as examples and not as limiting embodiments. In some embodiments, differences in terminal information 220 and / or layer information 225 may result in different shape modifications in the example three-dimensional representation 575.

[0218] Figures 6A-6C These are schematic diagrams illustrating example layouts for layout file 170 and updated layout 270 used in intermediate and final iterations of example process 200, respectively. Provided Figures 6A-6C To illustrate the progressive shape modification of interconnect 310 over multiple iterations of example process 200, see reference. Figure 2 More detailed description.

[0219] Figure 6A This is a schematic diagram illustrating an exemplary layout 600 of layout file 170 according to an embodiment of the present disclosure. The example layout 600 corresponds to... Figure 5A Example 3D representation 535, which has been projected onto the "xy" plane at the "z" position of interconnect 310 for visual interpretation. Example layout 600 shows that, according to receiving layout file 170 after routing but before the initial iteration of example process 200, interconnect 315, conductive element 415, and conductive element 515 conform to a straight-line routing convention. However, in some embodiments, layout file 170 is received after at least one iteration of example process 200. For example, updated layout 270 may be encoded as layout file 170 and stored in a third database 165. Examples of such a process may include situations where a first set of one or more iterations of example process 200 is completed, after which updated layout 270 is stored as layout file 170 for access for additional iterations of example process 200 (if indicated).

[0220] Figure 6BThis is a schematic diagram illustrating an example layout 630 of an updated layout 270 in an intermediate state according to an embodiment of the present disclosure. Example layout 630 represents the "xy" projection of a three-dimensional representation 235 after one or more iterations of example process 200 have applied one or more shape modifications relative to example layout 600 to interconnects 310. As shown, interconnects 310 no longer conform to straight wiring conventions but instead include one or more curved surfaces. Although the three-dimensional representation 235 is discretized into monomers 401, for ease of visual interpretation, Figure 6B Including a smoothed interface 311, although in some embodiments, the three-dimensional representation 235 may be smoothed as part of generating an updated layout 270 (e.g., a smoothed updated layout 270 may be used to generate masks that are sent to the manufacturing system 115). Depending on the shape of the interconnect 310, one or more shape constraints are visible because the interconnect 310 is constrained to maintain contact with the conductive element 515 at one or more locations corresponding to the contact points of the terminal 305. Although the interconnect 310 is shown as having three contact points, it should be understood that the interconnect 310 may be represented in... Figures 3A-3B The “two-port” configuration described in the context.

[0221] Figure 6C This is a schematic diagram illustrating an example layout 650 of an updated layout 270 in an advanced state according to an embodiment of the present disclosure. Example layout 650 represents one or more additional iterations of example process 200 that have been performed relative to... Figure 6B Example plan 630 applies one or more shape modifications to the “xy” projection of the three-dimensional representation 235 following the interconnect 310. Example plan 650 illustrates multiple shape modifications to the interconnect 310 to (i) increase the distance between the interconnect 310 and the conductive element 415, (ii) constrain the interconnect 310 to maintain contact with the terminal 305, and (iii) incorporate, at least in part, a local width “W” as a function of the lateral position on the interconnect 310, based on the local contribution of the monomer 401 to the RC time constant, according to the terminal information 220 and the layer information 225. X (Y)" change. In some embodiments, example plan 650 is the result of iteration applied to the updated layout 270. In some embodiments, example plan 650 is generated from operations applied to the 3D representation 235 before the updated layout 270 is generated. In this way, referencing Figures 3A-3B The described heuristic can be applied to three-dimensional representations 235, for example, by reassigning material property information of one or more monomers 401.

[0222] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 2The example process 700 is a block diagram of an example flow 700, which is a part of the example process 200 and applies to operations in a three-dimensional representation. Like the constituent operations of example process 200, example flow 700 represents operations that can be implemented locally and / or in a distributed manner by a computer system (e.g., server 105, client computing device 110, etc.). Thus, the constituent blocks of example flow 700 can be understood as representing operations implemented in software (e.g., Figure 1 The software 155 encodes machine-readable instructions that allow the computer system to modify the shape of interconnects 310, terminals 305, etc., as part of a physically-based optimization of layout file 170, which can introduce curved features into the wiring elements of layout file 170. While the components of example process 700 are represented sequentially, it should be understood that one or more blocks may be omitted, repeated, reordered, or subdivided as part of an iteration of example process 200 and / or as part of an implementation on a particular computer system. For example, in a distributed system context, blocks may be subdivided into multiple component processes to facilitate parallelization. In this way, two or more blocks can be executed in parallel rather than sequentially.

[0223] At block 705, example flow 700 includes generating a 3D representation 235, which corresponds to operation 207 of example flow 200. Operations 201-205 of example flow 200 are omitted from example flow 700 to focus the description on the constituent elements of operations 207-211. (See reference...) Figure 2 In more detail, block 705 may include a discretized layout file 170 or a modified layout 270 to generate a three-dimensional representation 235.

[0224] In blocks 710-715, example process 700 includes generating at least a subset of the three-dimensional representation 235 of the monomer 401 to contribute to the conductance of the RC time constant of the interconnect 310. (See reference...) Figures 3A-3B To describe in more detail, in some cases, the contribution of at least a portion of monomer 401 in the three-dimensional representation 235 can be ignored, for example, where this portion of monomer 401 is relatively far from interface 311, making it unlikely that material information will be reassigned. (See above reference) Figures 3A-3B The method for determining individual contributions was discussed. and Detailed physical simulation information.

[0225] At block 720, one or more smoothing operations are applied on a per-unit basis to the contributions generated in blocks 710-715. The smoothing operations can be or include three-dimensional smoothing functions, such as Gaussian smoothing functions with a standard deviation parameter σ. (See reference...) Figure 3BIn more detail, smoothing allows the relative contributions of adjacent monomers 401 to be extrapolated, thereby facilitating the heuristics described in reference blocks 721-730 for determining material reassignment, which can be implemented on a monomer-by-monomer basis.

[0226] In decision block 721, for a given monomer 401, the position of the given monomer 401 in the three-dimensional representation 235 and / or the material property metadata of the given monomer 401 are used to determine whether the given monomer 401 is part of forming the interconnect 310 or part of the surrounding oxide. In some embodiments, the monomers 401 corresponding to the terminals 305 and / or conductive elements 415 and 515 are omitted from the operation of example flow 700. In some embodiments, at least a subset of the monomers 401 corresponding to the interconnect 310 are similarly omitted, for example as a method of imposing one or more shape constraints on the interconnect 310.

[0227] At decision blocks 723 and 724, appropriate comparisons are applied to the individual contributions generated at blocks 710 and 715 to determine whether the material information for a given monomer 401 should be reassigned at block 725 or retained at block 730, as referenced. Figures 3A-3B More detailed description. Block 730 is shown as two blocks, but the instructions are understood to be equivalent regardless of whether the given monomer 401 forms part of the interconnect 310 or the surrounding oxide.

[0228] At block 735, the modifications indicated by blocks 721-730 for the subset of individual 501 are encoded into the updated layout 270. (See reference...) Figure 2 In more detail, an updated three-dimensional representation 235 can be generated by reassigning one or more materials to the three-dimensional representation 235 (e.g., Figure 5B An example 3D representation 575 is used to generate an updated layout 270. The updated representation can then be converted into a layout file 170 (e.g., OASIS or GDSII format) for use in manufacturing integrated circuits.

[0229] In some embodiments, example process 700 includes manufacturability determination and subsequent modifications of the updated layout 270 at blocks 740 and 745, respectively. (See reference...) Figure 2 and Figures 3A-3BIn more detail, manufacturability verification of the updated layout 270 may include performing process simulations using process data describing a semiconductor manufacturing system 115 that allows one or more manufacturability criteria to be evaluated. For example, while a conventional Boolean design rule checker may return an inaccurate value for the updated layout 270, at least in part, due to curved routing, physical-based process simulations may allow functionality to be retained to guide manufacturability verification. In this way, manufacturability verification may include determining whether the updated layout 270 represents a non-physical solution, whether the updated layout 270 will function according to the design once manufactured, and / or whether the updated layout 270 violates any Boolean design rules applied to the straight portions of the updated layout 270.

[0230] In some cases, the updated layout 270 may include portions conforming to straight-line routing standards. For example, interconnect 310 may include curved interfaces 311 in the "xz" and "yz" planes, and may include flat or substantially flat interfaces 311 in the "xy" plane. Similarly, interconnect 310 may be constrained by a minimum thickness on the "z" axis, allowing Boolean design rule checks—which are computationally less demanding than physics-based process simulations—to verify whether the updated layout 270 is manufacturable. For this purpose, such a minimum thickness constraint may be encoded as part of the operation of example process 200. For example, modifying the three-dimensional representation 235 as part of operation 211 of example process 200 may include the constraint that a minimum number of monomers 401 (e.g., assigned conductive material properties) at all locations within interconnect 310 remain in the "z" direction (e.g., as defined by interface 311).

[0231] Advantageously, the operation of example process 200 and example process 700 can be implemented for a variety of combinations of input and output terminals 305, as described in terminal information 220. The so-called "fan-out", "fan-in", and "fan-in-out" layout 170 includes at least one input terminal and at least one output terminal, but may include one or a multiple of both.

[0232] Figure 8 This is a schematic diagram illustrating an example three-dimensional representation 835 of an updated layout file 270 including a fan-out configuration according to an embodiment of the present invention. Example three-dimensional representation 835 represents interconnects 310 with shape modifications based on example process 200, as referenced... Figure 2 For a more detailed description, as shown in the figure, the first terminal 305-1 of terminal 305 represents a single input terminal, while the second terminal 305-2, the third terminal 305-3, and the fourth terminal 305-4 represent output terminals, as shown in the reference. Figures 3A-3BA more detailed description, particularly the detailed discussion of the fan-out optimization above, includes equations (39)-(42). With output terminals 305-2 to 305-3 located in different quadrants of the three-dimensional representation 835, the interconnect 310 exhibits a T-shape, characterized by discrete curve features and non-uniform width as a function of position (r). In this respect, the interconnect 310 of the three-dimensional representation 835 narrows into multiple branches at the dividing point, each branch coupling the input terminal 305-1 to a different output terminal 305-2, 305-3, or 305-4. It is also shown that the interconnect 310 has a substantially uniform thickness in the "z" direction, while each branch has a different width in the "x" or "y" direction. In this way, the effect of the different terminal information 220 describing each terminal 305 is shown as a result of different operating parameters for the different terminals 305.

[0233] Figure 9 This is a schematic diagram illustrating an example three-dimensional representation 935 of an updated layout file 270 including a fan-in / out configuration according to an embodiment of the present disclosure. Example three-dimensional representation 935 represents an interconnect 310 with a shape modified according to example process 200, as referenced... Figure 2 More detailed description. Example 3D representation 935 can be understood as a modification of example 3D representation 835, in which a fifth terminal 305-5 representing the second input terminal is added. Like the first terminal 305-1, the fifth terminal 305-5 is electrically coupled to output terminals 305-2, 305-3, and 305-4 via interconnect 310. Figure 8 As shown, interconnect 310 branches near a partition point substantially aligned with output terminals 305-3 and 305-4. The 3D representation of interconnect 310 also shows a wider region between the partition point and input terminals 305-1 and 305-5, where the conductive path becomes relatively narrower after partitioning. In contrast to the operation described as part of fan-out optimization, fan-in optimization can be performed via dividing the layout file into multiple partial layouts to be modified by the operations of example process 200. After the shape of the partial layouts is modified, an updated layout is generated by merging the partial layouts. In this way, fan-in / out modification can include parallel instances of example process 200, as well as one or more preliminary operations applied to the layout file, for example, as part of a discretization operation.

[0234] Figure 10This is a block diagram illustrating an example flow 1000 for shape modification of a fan-in or fan-out layout file 170 according to embodiments of the present disclosure. Like example flow 200 and example flow 800, example flow 1000 represents operations that can be implemented locally and / or distributed by a computer system (e.g., server 105, client computing device 110, etc.). Thus, the constituent blocks of example flow 1000 can be understood as representing code encoded in software (e.g., Figure 1 The machine-readable instructions in the software 155 allow the computer system to modify the shape of interconnects 310, terminals 305, etc., as part of a physically-based optimization of layout file 170, which can introduce curved features into the wiring elements of layout file 170. Although the components of example process 1000 are represented sequentially, it should be understood that one or more blocks may be omitted, repeated, reordered, or subdivided as part of an iteration of example process 200 and / or as part of an implementation on a particular computer system. For example, in a distributed system context, blocks may be subdivided into multiple component processes to facilitate parallelization. In this way, two or more blocks can be executed in parallel rather than sequentially.

[0235] At block 1005, example process 1000 includes receiving layout data 215, including terminals 305 and interconnects 310. Similar to example process 200, layout data 215 includes terminal information 220 and layer information 225. Terminal information 220 encodes whether terminal 305 is an input terminal or an output terminal. Thus, block 1010 includes generating different conductive paths for each input terminal. For example, in Figure 9 In the example 3D layout 1035, interconnect 310 couples two input terminals to three output terminals. Therefore, block 1010 includes defining a first conductive path between the first input terminal 305-1 and output terminals 305-2, 305-3, and 305-5, and defining a second conductive path between the second input terminal 305-5 and the output terminals. In this way, the operation of example process 200 can modify the fan-in / out configuration by defining the number of different conductive paths equal to the number of input terminals. Advantageously, implementing example process 1000 allows complex layout file 170 to be segmented into relatively simple configurations for parallel processing. In this way, physical shape modifications can be applied to layout file 170 that would otherwise fail manufacturability verification based on design rules. Furthermore, integrated circuit layouts typically incorporate many repeating instances of basic layout elements, such as those associated with circuit components (e.g., fin-FETs). Thus, segmentation allows layout data 215 to be used to populate a database of partial layouts indexed to layer information 225 and terminal information 220, which can further improve the performance of example system 100.

[0236] At block 1015, at least a subset of the operations of example procedure 200 are used to iterate over the first conductive path defined by layout data 215. (See reference...) Figure 3A-8 As described, one or more iterations of example process 200 can generate an updated layout 270. However, in the context of example process 1000, iteration of the first path provides a partial update to layout file 170. Simultaneously, block 1020 includes iterating a second conductive path using at least a subset of operations of example process 200, either in parallel, serially, or otherwise. As previously mentioned, example process 1000 is described for layout file 170 including two input terminals 305. Therefore, blocks 1000 and 1015 may be accompanied by additional instances of example process 200 for additional conductive paths corresponding to third input terminals 305, fourth input terminals 305, etc.

[0237] At block 1025, example flow 1000 includes fusing shape modification paths to generate an updated 3D representation 235 for a fan-in or fan-in-out configuration. In some embodiments, fusing includes applying a Boolean function on a per-monomer basis to determine whether a given monomer 401 is assigned to a conductive material, a dielectric material, or an insulating material. Examples of Boolean functions include AND, OR, INCLUSIVE OR, EXCLUSIVE OR, etc. In the illustrative example, to avoid eliminating the two portions of interconnect 310 coupled only to one terminal of input terminal 305, the INCLUSIVE OR function can be defined such that if monomer 401 is assigned to a metal in a first conductive path or a second conductive path, then monomer 401 is assigned to a conductive material (e.g., a metal).

[0238] Figure 11 This is a schematic diagram illustrating an example three-dimensional representation 1175 of a multi-layer layout file 170 including a plurality of interconnects 310 coupled with a plurality of terminals according to an embodiment of the present disclosure. Example three-dimensional representation 1175 represents an optimized layout file 170, which includes a first interconnect 310-1 and a second interconnect 310-2 reshaped according to example process 200, as referenced... Figure 2 A more detailed description. In Figure 11 In the example, both the first interconnect 310-1 and the second interconnect 310-2 are fan-in and out, configured to couple multiple input terminals to multiple output terminals on two different "z" layers of the integrated circuit layout. For such a multi-layer layout 170, the example process 200 may include multiple parallel optimization processes incorporated into the operations of example process 800 and example process 1100 to subdivide the optimization operations and subsequently merge the constituent elements of the example 3D representation 1175 into an updated layout 270.

[0239] In the illustrative example shown in example 3D representation 1175, it can be seen as referenced Figure 8-11Modify the first interconnect 310-1 as described in more detail. During the optimization of the first interconnect 310-1, the second interconnect 310-2 can remain static. The subsequent convergence of the first interconnect 310-1 and the second interconnect 310-2 can be optimized, as described in the reference... Figure 8-11 In a more detailed description, the first interconnect 310-1 remains static. By iterating this process, both the first interconnect 310-1 and the second interconnect 310-2 can be modified to optimize the corresponding RC value or other optimization metrics, as shown in the reference. Figure 2 More detailed description. Additionally or alternatively, the first interconnect 310-1 and the second interconnect 310-2 can be optimized in parallel, such that multiple interconnects 310 are modified together in each iteration of example process 200. Advantageously, such an approach allows for fewer iterations of example process 200.

[0240] The above-described process is described in light of computer software and hardware. The described techniques can be embodied in machine-executable instructions within a tangible or non-transitory machine-readable storage medium, which, when executed by a machine, will cause the machine to perform the described operations. Additionally, the process can be embodied in hardware such as an application-specific integrated circuit (“ASIC”) or otherwise.

[0241] Tangible machine-readable storage media include any mechanism that provides (i.e., stores) information in a non-transitory form accessible to a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device having a collection of one or more processors, etc.). For example, machine-readable storage media include recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.).

[0242] The above description of the embodiments illustrated in this invention, including the content described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments and examples of the invention have been described herein for illustrative purposes, various modifications can be made within the scope of the invention, as will be recognized by those skilled in the art.

[0243] Based on the above detailed description, these modifications can be made to the present invention. The terminology used in the appended claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention will be fully defined by the appended claims, which will be interpreted according to the established principles of claim interpretation.

Claims

1. A computer-implemented method for optimizing conductive interconnects, the method comprising: The receiver includes an integrated circuit layout comprising multiple terminals and interconnections, wherein the interconnections represent conductive coupling between the multiple terminals; Receive terminal information describing the operating parameters of the plurality of terminals; Receive layer information describing the material composition and material properties of the plurality of terminals and the interconnection; A three-dimensional representation of the integrated circuit is generated using the integrated circuit layout and the layer information, wherein the three-dimensional representation includes a single unit corresponding to a discrete volume element of the three-dimensional representation, the single unit representing at least a portion of the interconnect or at least a portion of non-conductive material outside the interconnect; The three-dimensional representation and the terminal information are used to determine the individual contribution of each cell to the resistance-capacitance (RC) value of the interconnect; and An updated integrated circuit layout is generated, at least in part, based on the individual contributions.

2. The computer-implemented method according to claim 1, wherein, The individual contribution of the component to the RC value includes: The generator admittance and load admittance of the individual are determined at least in part based on the layer information and the terminal information; The generator admittance and the load admittance are used to determine the input admittance; The input admittance is used to determine the admittance density of the monomer, wherein the admittance density describes the local contribution of the monomer to the admittance of the interconnect; and The differential RC value of the monomer is generated at least in part based on the admittance density.

3. The computer-implemented method according to claim 1, wherein, The single entity is a first single entity, wherein the three-dimensional representation further includes a second single entity, and wherein generating the updated integrated circuit layout includes: Determine the conductance contributions of the first monomer and the second monomer to the conductance of the interconnect; Determine the capacitive contributions of the first and second monomers to the capacitance of the interconnect; The smoothed conductance contribution and smoothed capacitance contribution of the first monomer are generated using the corresponding contributions of the first monomer and the second monomer; and The material composition of the first monomer is determined at least in part based on the smooth conductance contribution and the smooth capacitance contribution of the first monomer.

4. The computer-implemented method according to claim 3, wherein, Determining the material composition includes: When the monomer represents a portion of the interconnect, if the smooth capacitance contribution of the first monomer exceeds the smooth conductivity contribution of the first monomer, the monomer is reassigned to represent the non-conductive material; or When the monomer represents a portion of the non-conductive material, if the smooth conductivity contribution of the first monomer exceeds the smooth capacitance contribution of the first monomer, the monomer is reassigned to represent the interconnect.

5. The computer-implemented method according to claim 4, wherein, The smoothed conductance contribution and smoothed capacitance contribution of the first monomer include a three-dimensional smoothing of the corresponding contributions of the first monomer and the second monomer.

6. The computer-implemented method according to claim 4, wherein, The smoothed conductance contribution and smoothed capacitance contribution of the first monomer are generated by Gaussian smoothing using a standard deviation parameter σ, which is smaller than the width of the interconnect in the integrated circuit layout.

7. The computer-implemented method according to claim 1, further comprising: The updated integrated circuit layout is input into a process model, which is configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout. The simulated manufacturing integrated circuit is generated as the output of the process model; as well as The output of the process model is used to determine the manufacturability of the updated integrated circuit layout of the semiconductor manufacturing system.

8. The computer-implemented method according to claim 7, wherein, The manufacturability indicates that the updated integrated circuit layout cannot be manufactured by the semiconductor manufacturing system, and the method further includes: A revised layout is generated using the updated integrated circuit layout and the process model, and the revised layout can be manufactured by the semiconductor manufacturing system.

9. The computer-implemented method according to claim 1, wherein, The plurality of terminals includes an input terminal and two output terminals.

10. The computer-implemented method according to claim 1, wherein, The plurality of terminals includes a plurality of input terminals and at least one output terminal, wherein the three-dimensional representation is a first representation, and wherein the method further includes: Generate the first representation corresponding to when the first input terminal included in the input terminals is active and the other input terminals are inactive; A second representation is generated using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and the remaining input terminals are inactive, and wherein both the first representation and the second representation include the single unit; The first part of the update is generated using the first representation; The second representation is used to generate a second part of the update; and The updated integrated circuit layout is generated using the first part of the update and the second part of the update.

11. The computer-implemented method according to claim 10, wherein, Generating the updated integrated circuit layout involves merging the first part of the update and the second part of the update using the inclusion OR operator.

12. The computer-implemented method of claim 1, further comprising outputting the updated integrated circuit layout, the output including: The updated integrated circuit layout is used to generate an updated integrated circuit layout file; as well as The updated integrated circuit layout file is stored in the data repository.

13. A non-transitory computer-readable storage device for storing machine-executable instructions, said machine-executable instructions causing the machine to perform operations when executed by a machine, said operations including: The receiver includes an integrated circuit layout comprising multiple terminals and interconnections, wherein the interconnections represent conductive coupling between the multiple terminals; Receive terminal information describing the operating parameters of the plurality of terminals; Receive layer information describing the material composition and material properties of the plurality of terminals and the interconnection; A three-dimensional representation of the integrated circuit is generated using the integrated circuit layout and the layer information, wherein the three-dimensional representation includes a single unit corresponding to a discrete volume element of the three-dimensional representation, the single unit representing at least a portion of the interconnect or at least a portion of non-conductive material outside the interconnect; The three-dimensional representation and the terminal information are used to determine the individual contribution of each cell to the resistance-capacitance (RC) value of the interconnect; and An updated integrated circuit layout is generated, at least in part, based on the individual contributions.

14. The non-transitory computer-readable storage device according to claim 13, wherein, The individual contribution of the component to the RC value includes: The generator admittance and load admittance of the individual are determined at least in part based on the layer information and the terminal information; The generator admittance and the load admittance are used to determine the input admittance; The input admittance is used to determine the admittance density of the monomer, wherein the admittance density describes the local contribution of the monomer to the admittance of the interconnect; and The differential RC value of the monomer is generated at least in part based on the admittance density.

15. The non-transitory computer-readable storage device according to claim 13, wherein, The single entity is a first single entity and the three-dimensional representation further includes a second single entity, wherein generating the updated integrated circuit layout includes: Determine the conductance contributions of the first monomer and the second monomer to the conductance of the interconnect; Determine the capacitive contributions of the first and second monomers to the capacitance of the interconnect; The smoothed conductance contribution and smoothed capacitance contribution of the first monomer are generated using the corresponding contributions of the first monomer and the second monomer; and The material composition of the first monomer is determined at least in part based on the smooth conductance contribution and the smooth capacitance contribution of the first monomer.

16. The non-transitory computer-readable storage device according to claim 15, wherein, Determining the material composition includes: When the monomer represents a portion of the interconnect, if the smooth capacitance contribution of the first monomer exceeds the smooth conductivity contribution of the first monomer, the monomer is reassigned to represent the non-conductive material; or When the monomer represents a portion of the non-conductive material, if the smooth conductivity contribution of the first monomer exceeds the smooth capacitance contribution of the first monomer, the monomer is reassigned to represent the interconnect.

17. The non-transitory computer-readable storage device according to claim 16, wherein, The smoothed conductance contribution and smoothed capacitance contribution of the first monomer are generated by Gaussian smoothing using a standard deviation parameter σ, which is less than the initial width of the interconnect in the integrated circuit layout.

18. The non-transitory computer-readable storage device according to claim 13, wherein, When executed by the machine, the instruction causes the machine to perform further operations, including: The updated integrated circuit layout is input into a process model, which is configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout. Generate the simulated manufacturing integrated circuit as the output of the process model; and The manufacturability of the updated integrated circuit layout of the semiconductor manufacturing system is determined at least in part based on the output of the process model.

19. The non-transitory computer-readable storage device according to claim 18, wherein, The manufacturability indication states that the updated integrated circuit layout cannot be manufactured by the semiconductor manufacturing system, and wherein the instructions, when executed by the machine, cause the machine to perform further operations, including: A revised layout is generated, at least in part, based on the updated integrated circuit layout and the process model, and the revised layout can be manufactured by the semiconductor manufacturing system.

20. The non-transitory computer-readable storage device according to claim 13, wherein, The plurality of terminals includes a plurality of input terminals and at least one output terminal, wherein the three-dimensional representation is a first representation, and wherein the instruction, when executed by the machine, causes the machine to perform further operations, the operations including: Generate the first representation corresponding to when the first input terminal included in the input terminals is active and the other input terminals are inactive; A second representation is generated using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and the remaining input terminals are inactive, and wherein both the first representation and the second representation include the single unit; The first part of the update is generated using the first representation; The second representation is used to generate a second part of the update; and The updated integrated circuit layout is generated using the first part of the update and the second part of the update.

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