A power module package structure and a packaging method with low stray inductance

Abstract

The application discloses a low-stray inductance power module packaging structure and a packaging method, and relates to the technical field of semiconductor packaging. The packaging structure comprises a DBC substrate and a chip set arranged on the DBC substrate, and the chip set comprises at least one chip. A target chip in the chip set is electrically connected with the DBC substrate through an interconnecting conductive sheet. A plurality of stress release holes are arranged on the interconnecting conductive sheet and penetrate through the interconnecting conductive sheet. The packaging structure effectively reduces the stray inductance of the power module and improves the reliability of the power module packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a power module packaging structure and packaging method with low stray inductance. Background Technology

[0002] A power module is a module formed by combining power electronic devices according to certain functions and then encapsulating them. Most commercially available power modules still use traditional packaging methods. This involves first soldering the back of the chip onto a DBC (Direct Bonding Copper) substrate, then establishing electrical connections via metal bonding wires (aluminum wires), and finally encapsulating or potting with adhesive. While traditional packaging technology is mature and low-cost, it suffers from large stray inductance, which can easily lead to severe voltage overshoot during rapid switching, increasing losses and causing electromagnetic interference. The size of the stray inductance is related to the area of ​​the switching commutation circuit, and the connection method of the metal bonding wires is a key factor contributing to the large commutation circuit area in traditional packaging.

[0003] Furthermore, due to the limited stress that metal bonding wires can withstand and the height difference between the chip and the DBC surface, the metal bonding wires connecting the chips and the chip surface to the DBC are prone to breakage and failure during power module operation, reducing the reliability of the power module package. Simultaneously, when the power module contains silicon carbide chips, these chips generate significant heat during operation in high-power scenarios, placing high demands on the package's heat dissipation capabilities. Traditional metal bonding wire connection methods cannot meet the heat dissipation requirements of silicon carbide chips, easily causing the power module to overheat and fail, affecting its operational stability. Summary of the Invention

[0004] To address the aforementioned problems and technical requirements, the inventors have proposed a power module packaging structure and method with low stray inductance. The technical solution of this invention is as follows:

[0005] A power module packaging structure with low stray inductance includes a DBC substrate and a chipset disposed on the DBC substrate, wherein the chipset includes at least one chip.

[0006] The target chip in the chipset is electrically connected to the DBC substrate via interconnecting conductive sheets.

[0007] The interconnecting conductive sheet is provided with a plurality of stress relief holes, which penetrate the interconnecting conductive sheet.

[0008] A further technical solution is that the interconnecting conductive sheet includes a first flat portion, which is disposed on the target chip. When the chip group includes more than one target chip, the target chips in the chip group are electrically connected to each other through the first flat portion.

[0009] A further technical solution is that the interconnecting conductive sheet further includes a U-shaped connection group connected to the first straight portion, the U-shaped connection group including a plurality of U-shaped connection portions, and the target chip in the chip group is electrically connected to the DBC substrate through the U-shaped connection portions;

[0010] When the U-shaped connection group includes one or more U-shaped connection parts, the U-shaped connection group also includes several second straight parts, and adjacent U-shaped connection parts are connected through the second straight parts.

[0011] A further technical solution is that the chip includes a front side and a back side corresponding to the front side;

[0012] The back of the chip is soldered to the DBC substrate via a first solder layer;

[0013] The U-shaped connection portion of the interconnect conductive sheet is soldered to the DBC substrate through a first solder layer, and the first straight portion of the interconnect conductive sheet is soldered to the front side of the chip through a second solder layer.

[0014] A further technical solution is that the DBC substrate includes an upper connection layer, a lower connection layer and an insulating layer, wherein the insulating layer is located between the upper connection layer and the lower connection layer and is in contact with the upper connection layer and the lower connection layer;

[0015] In the chipset, the back of the chip is soldered to the upper connection layer via a first solder layer, and the lower connection layer is soldered to the support plate via a third solder layer.

[0016] A further technical solution is that a housing is also fixed on the support plate, and after the housing is fixed to the support plate, a receiving cavity is formed between the support plate and the housing;

[0017] The DBC substrate, chipset, and interconnect conductive sheet are located in the receiving cavity, which is filled with encapsulating adhesive, and the encapsulating adhesive covers the DBC substrate, chipset, and interconnect conductive sheet.

[0018] Its further technical solution includes several lead-out terminals;

[0019] The housing is provided with a plurality of mounting holes, each corresponding to a lead-out terminal. One end of the lead-out terminal is connected to the DBC substrate, and the other end of the lead-out terminal extends out of the housing through the corresponding mounting hole on the housing.

[0020] A further technical solution is that the material of the interconnecting conductive sheet includes Cu.

[0021] A further technical solution is that the stress relief hole has an elliptical shape, and a plurality of stress relief holes are evenly distributed in the first straight portion of the interconnecting conductive sheet.

[0022] A method for packaging a power module with low stray inductance, used to form the aforementioned power module packaging structure, the packaging method comprising:

[0023] A DBC substrate is provided and a chipset is packaged on the DBC substrate, wherein the chipset includes at least one chip;

[0024] The target chip in the chipset is electrically connected to the DBC substrate through an interconnect conductive sheet. The interconnect conductive sheet is provided with a plurality of stress relief holes, which penetrate the interconnect conductive sheet.

[0025] The beneficial technical effects of this invention are:

[0026] This invention achieves electrical connections within a power module through interconnecting conductive sheets, each with several stress-relief holes. These conductive sheets effectively reduce the area of ​​the commutation loop in the package structure, thereby reducing stray inductance in the power module. Furthermore, compared to traditional metal bonding wires, the conductive sheets offer superior current conductivity and stress resistance, enhancing both the temperature cycling characteristics and reliability of the power module.

[0027] In addition, a U-shaped connection group is provided on the interconnect conductive sheet. The U-shaped connection group includes several U-shaped connection parts. The chip in the chipset is electrically connected to the DBC substrate through the bottom end of the U-shaped connection part. The height of the U-shaped connection part compensates for the height difference between the chip and the DBC surface, which improves the stability of the electrical connection between the chip and the DBC and further enhances the reliability of the power module. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a power module packaging structure with low stray inductance in one embodiment of the present invention.

[0029] Figure 2 This is a front view of the interconnecting conductive sheet in one embodiment of the present invention.

[0030] Figures 3-5 This is a schematic diagram of the process steps of an embodiment of the power module packaging method with low stray inductance provided by the present invention, wherein,

[0031] Figure 3 This is a schematic diagram of the power module packaging structure after the chips are mounted on the first base island and the second base island in one embodiment of the present invention.

[0032] Figure 4This is a schematic diagram of the power module packaging structure after reflow soldering in one embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the power module encapsulation structure after injecting encapsulating adhesive into the receiving cavity in one embodiment of the present invention.

[0034] Reference numerals: 10-Support plate, 11-First welding layer, 12-Second welding layer, 13-Third welding layer, 14-Chip, 15-Housing, 16-Lead terminal, 17-Encapsulating adhesive, 18-Mounting hole, 20-DBC substrate, 21-Upper connection layer, 211-First base island, 212-Second base island, 213-Third base island, 22-Insulating layer, 23-Lower connection layer, 31-First straight portion, 32-U-shaped connection portion, 33-Second straight portion, 34-Stress relief hole. Detailed Implementation

[0035] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0036] The present invention proposes a power module packaging structure with low stray inductance, including a DBC substrate 20 and a chipset disposed on the DBC substrate 20, wherein the chipset includes at least one chip 14.

[0037] The target chip 14 in the chipset is electrically connected to the DBC substrate 20 via interconnecting conductive sheets;

[0038] The interconnecting conductive sheet is provided with a plurality of stress relief holes 34, which penetrate the interconnecting conductive sheet.

[0039] Specifically, the DBC substrate 20 provided by the present invention includes a front side and a back side corresponding to the front side, and the chip 14 generally also includes a front side and a back side corresponding to the front side. The back side of the chip 14 is packaged on the front side of the DBC substrate 20. The specific packaging method of the chip 14 can be referred to the following description. The chipset includes several chips. In specific implementation, the chip 14 in the chipset is electrically connected to the DBC substrate 20 through bonding wires and / or interconnect conductive sheets. The chip 14 that is connected to the DBC substrate 20 through interconnect conductive sheets is the target chip 14. The target chip 14 in the chipset and the front side of the DBC substrate 20 are provided with the same interconnect conductive sheet. The interconnect conductive sheet is provided with stress relief holes 34 for stress relief. Optionally, the material of the interconnect conductive sheet can be Cu. In specific implementation, the thickness of the interconnect conductive sheet and the material used can be set according to actual needs. Preferably, all chips 14 in the chipset are electrically connected to the DBC substrate 20 through interconnect conductive sheets.

[0040] Compared to traditional metal bonding wires, interconnect conductive sheets effectively reduce the area of ​​the commutation loop in the package structure, thereby reducing stray inductance. Simultaneously, interconnect conductive sheets also possess higher current conductivity, reducing thermal resistance in the power module and resulting in excellent temperature cycling characteristics and improved heat dissipation performance. The stress relief holes 34 in the interconnect conductive sheets alter the load transfer path on the interconnect film, thereby improving local stress distribution and releasing stress, further enhancing module reliability and extending service life. Simultaneously, the stress relief holes 34 also contribute to improving the heat dissipation performance of the power module.

[0041] Furthermore, the interconnecting conductive sheet includes a first flat portion 31, which is disposed on the chip 14. When the chip group includes one or more target chips 14, the target chips 14 in the chip group are electrically connected to each other through the first flat portion 31.

[0042] Specifically, in the cross-section of the package structure, the first flat portion 31 is disposed parallel to the front side of the chip 14 and electrically connected to the target chip 14, parallel to the DBC substrate 20. When the chip group includes more than one target chip 14, all target chips 14 in the chip group are electrically connected to the first flat portion 31, so as to realize the mutual electrical connection of all target chips 14 in the chip group through the first flat portion 31. The model and quantity of the chip 14 can be set according to the circuit topology of the power module formed by the package.

[0043] Preferably, a plurality of stress relief holes 34 are evenly distributed in the first straight portion 31 of the interconnecting conductive sheet.

[0044] Figure 2 A front view diagram of an embodiment of an interconnect conductive sheet when the chipset includes only one chip 14 is shown. As shown, in this embodiment, the front of the first straight portion 31 of the interconnect conductive sheet is generally rectangular, and the front of the U-shaped connection group is also rectangular. Furthermore, the width of the first straight portion 31 in the front direction is greater than the width of the U-shaped connection group. Along the long side of the rectangular first straight portion 31... Figure 2 Two stress relief hole groups are arranged side by side along the x-axis direction. Each stress relief hole group includes two stress relief holes 34 arranged along the y-axis direction. In the first straight section 31, the four stress relief holes 34 in the two stress relief hole groups are evenly distributed at the four corners of the rectangular first straight section 31. The y-axis direction is perpendicular to the x-axis direction.

[0045] Specifically, the stress relief holes 34 can be elliptical. In this embodiment, the major axis of each elliptical stress relief hole 34 is parallel to the aforementioned x-axis direction. The size of the elliptical stress relief hole 34 is 1mm × 0.5mm, and the spacing between adjacent stress relief holes 34 in the stress relief hole group is 2mm. The stress relief holes 34 penetrate the interconnecting conductive sheet. In specific implementations, the shape, size, and distribution of the stress relief holes 34 can be selected according to actual needs.

[0046] The chip 14 includes an IGBT chip and / or a MOSFET chip. For both the IGBT and MOSFET chips, the front side of the chip 14 includes a control electrode connection area and a target electrode connection area. Generally, the control electrode connection area is small and the control electrode potential needs to be connected separately. Therefore, when the front side of the chip 14 includes a control electrode connection area, the first flat portion of the interconnect conductive sheet is connected to the target electrode connection area, and the corresponding area of ​​the control electrode connection area is removed from the first flat portion 31 of the interconnect conductive sheet to avoid the interconnect conductive sheet covering the control electrode connection area and affecting the extraction of the control electrode potential. The method of extracting the control electrode potential is consistent with the prior art. Figure 2 As shown, in this embodiment, a rectangular area is cut away from the long side of one side of the first straight portion 31 to form a U-shaped first straight portion 31 to avoid the interconnect conductive sheet covering the connection area of ​​the control electrode of the chip 14. When the chip 14 is an IGBT chip, the control electrode is the gate and the target electrode is the emitter; when the chip 14 is a MOSFET chip, the control electrode is the gate and the target electrode is the source.

[0047] Furthermore, the interconnecting conductive sheet also includes a U-shaped connection group connected to the first straight portion 31. The U-shaped connection group includes a plurality of U-shaped connection portions 32. The chip 14 in the chip group is electrically connected to the DBC substrate 20 through the bottom end of the U-shaped connection portion 32.

[0048] Specifically, the back side of the chip 14 is soldered to the front side of the DBC substrate 20 via a first solder layer 11. The first flat portion 31 of the interconnect conductive sheet is soldered to the front side of the chip 14 via a second solder layer 12. The U-shaped connection portion 32 of the interconnect conductive sheet is soldered to the front side of the DBC substrate 20 via the first solder layer 11. Since the first flat portion 31 and the U-shaped connection portion 32 in the U-shaped connection group are connected as one unit, the chip 14 can be electrically connected to the DBC substrate 20 via the U-shaped connection portion 32. The U-shaped connection portion 32 is recessed into a U-shape in the cross-section of the package structure from the plane where the first flat portion 31 is located. The arc-shaped bottom end of the U-shaped connection portion 32 is soldered to the front side of the DBC substrate 20 via the first solder layer 11. The top end of the U-shaped connecting portion 32, which is adjacent to the first straight portion 31, is connected to the first straight portion 31. To ensure that the bottom end of the U-shaped connecting portion 32 is soldered to the first solder layer 11 on the front side of the DBC substrate 20, the height of the U-shaped connecting portion 32 must be equal to the height difference between the surface of the first solder layer 11 and the surface of the second solder layer 12. This invention utilizes the height of the U-shaped connecting portion 32 to compensate for the height difference between the chip 14 and the front side of the DBC substrate 20, thereby improving the stability of the electrical connection between the chip 14 and the DBC substrate 20.

[0049] Preferably, the U-shaped connection group includes one or more U-shaped connection portions 32, so as to evenly distribute the stress borne by the interconnecting conductive sheets at the U-shaped connection group by multiple U-shaped connection portions 32 in the U-shaped connection group, thereby improving the overall support force of the U-shaped connection group and further improving the reliability of the module. When the U-shaped connection group includes one or more U-shaped connection portions 32, the U-shaped connection group also includes several second straight portions 33. Adjacent U-shaped connection portions 32 are connected by second straight portions 33. All U-shaped connection portions 32 in the U-shaped connection group can adopt the same shape. The second straight portions 33 are supported between adjacent U-shaped connection portions 32 and suspended above the DBC substrate 20. At this time, the U-shaped connection group is generally wavy in the cross-section of the packaging structure.

[0050] Furthermore, the DBC substrate 20 includes an upper connection layer 21, a lower connection layer 23, and an insulating layer 22. The insulating layer 22 is located between the upper connection layer 21 and the lower connection layer 23 and is in contact with both the upper connection layer 21 and the lower connection layer 23. The back side of the chip 14 in the chipset is soldered to the upper connection layer 21 through a first solder layer 11, and the lower connection layer 23 is soldered to the support plate 10 through a third solder layer 13.

[0051] Optionally, the upper connecting layer 21 can be used as the front side of the DBC substrate 20, and the lower connecting layer 23 can be used as the back side of the DBC substrate 20, with the upper connecting layer 21 corresponding to the lower connecting layer 23. The insulating layer 22 can be made of materials such as Al2O3, AlN, and Si3N4, while the upper connecting layer 21 and the lower connecting layer 23 can be made of Cu. In specific implementations, the materials of the upper connecting layer 21, the insulating layer 22, and the lower connecting layer 23 can be selected according to actual needs.

[0052] Generally, the upper interconnect layer 21 used for bonding chip 14 needs to be patterned to form multiple base islands, and the first bonding layer 11 located on the upper interconnect layer 21 needs to correspond to the distribution of the base islands. In this embodiment, the upper interconnect layer 21 is divided into three base islands after patterning, namely Figure 1 The first base island 211, second base island 212, and third base island 213 are shown. A first solder layer 11 is formed on each of these three base islands. A chip 14 is placed on each of the first and second base islands 211 and 212. The back side of the chip 14 on the first base island 211 is soldered to the first base island 211 via the first solder layer 11. Similarly, the back side of the chip 14 on the second base island 212 is soldered to the second base island 212 via the first solder layer 11. In this embodiment, the U-shaped connection group has two U-shaped connection portions 32, both of which are soldered to the third base island 213 via the first solder layer 11 on the second base island 212. The first solder layer 11, second solder layer 12, and third solder layer 13 can be formed by printing solder or by placing solder pads on the front side of the DBC substrate 20 and the support plate 10. When the front side of the chip 14 includes a control electrode connection area, the second solder layer 12 formed on the front side of the chip 14 for soldering interconnect conductive sheets should also avoid covering the control electrode connection area.

[0053] Furthermore, a housing 15 is also fixed to the support plate 10. After the housing 15 is fixed to the support plate 10, a receiving cavity is formed between the support plate 10 and the housing 15.

[0054] The DBC substrate 20, chipset, and interconnect conductive sheet are located in the receiving cavity, which is filled with encapsulating adhesive 17, and the encapsulating adhesive 17 covers the DBC substrate 20, chipset, and interconnect conductive sheet.

[0055] Optionally, the encapsulating adhesive 17 can be made of epoxy resin, the support plate 10 can be made of Cu, and the housing 15 can be made of insulating material. The encapsulation structure also includes several lead-out terminals 16. The housing 15 has several mounting holes 18, each corresponding to a lead-out terminal 16. One end of each lead-out terminal 16 is connected to the DBC substrate 20, and the other end extends out of the housing 15 through the corresponding mounting hole 18. The portion of the lead-out terminal 16 located within the receiving cavity is covered by the encapsulating adhesive 17. In this embodiment, two lead-out terminals 16 are provided. One lead-out terminal 16 is connected to the first base island 211 in the upper connection layer 21 of the DBC substrate 20, and the other lead-out terminal 16 is connected to the third base island 213 in the upper connection layer 21. Corresponding to the number of lead-out terminals 16, this embodiment has two mounting holes 18 on the housing 15, which penetrate the housing 15 and communicate with the receiving cavity.

[0056] For the aforementioned power module packaging structure with low stray inductance, the present invention provides a corresponding packaging method for the packaging structure, the packaging method comprising:

[0057] A DBC substrate 20 is provided and a chipset is mounted on the DBC substrate 20, wherein the chipset includes at least one chip 14;

[0058] The target chip 14 in the chipset is electrically connected to the DBC substrate 20 through an interconnect conductive sheet. The interconnect conductive sheet is provided with a plurality of stress relief holes 34, which penetrate the interconnect conductive sheet.

[0059] Specifically, the packaging method is compatible with existing packaging processes. Figures 3-5 This is a schematic diagram of the process steps of an embodiment of the power module packaging method with low stray inductance provided by the present invention. The following is a detailed explanation of the process steps. Figures 3-5 This encapsulation method will be described in detail:

[0060] like Figure 3 As shown, a copper support plate 10 is provided. Solder pads are mounted on the support plate 10 to form a third solder layer 13. A DBC substrate 20 is mounted on the first solder layer 13. The upper interconnect layer 21 of the DBC substrate 20 includes a first base island 211, a second base island 212, and a third base island 213. A solder pad is mounted on each of the first base island 211, the second base island 212, and the third base island 213 to form a first solder layer 11. A chip 14 is mounted on the first solder layer 11 located on the first base island 211 and the second base island 212, respectively.

[0061] like Figure 4As shown, solder pads are mounted on two chips 14 to form a second solder layer 12. Interconnect conductive sheets are placed on the second solder layer 12 and the first solder layer 11 located on the third base island 213. The specific structure of the interconnect conductive sheets is consistent with that described above and will not be repeated here. Two leads 16 are provided, one end of which is coated with solder (not shown in the figure) and mounted on the first base island 211 and the third base island 213 respectively.

[0062] The lower interconnect layer of the DBC substrate 20 is soldered to the support plate 10 via the third solder layer 13 using a reflow soldering process. Two chips 14 are soldered to the first base island 211 and the second base island 212 via the first solder layer 11, respectively. The first straight portion 31 of the interconnect conductive sheet is soldered to the two chips via the second solder layer 12. The arc-shaped bottom end of the U-shaped connection portion 32 of the interconnect conductive sheet is soldered to the third base island 213 via the first solder layer 11. Two lead terminals 16 are soldered to the first base island 211 and the third base island 213 via solder.

[0063] like Figure 5 As shown, a housing 15 is assembled and fixed on the support plate 10. The housing 15 and the support plate 10 form a receiving cavity. The DBC substrate 20, the chipset and the interconnect conductive sheet are all located in the receiving cavity. The housing 15 is provided with two mounting holes 18 for extending lead terminals 16. The mounting holes 18 penetrate the housing 15, and the two lead terminals 16 extend out of the housing 15 through the corresponding mounting holes 18.

[0064] Molten epoxy resin is injected into the receiving cavity formed by the housing 15 and the support plate 10 through an injection hole (not shown in the figure) to form an encapsulating adhesive. The encapsulating adhesive covers the portions of the DBC substrate 20, chipset, interconnect conductive sheet, and lead terminal 16 located in the receiving cavity. Compared with conventional wire bonding processes, the encapsulation method using interconnect conductive sheets in this invention can effectively improve encapsulation efficiency and has lower manufacturing costs.

[0065] It should be noted that the terms "front," "rear," "left," "right," "up," and "down" used in the above description refer to the directions in the accompanying drawings of this application, and the terms "front" and "back," "inner" and "outer" refer to facing or away from a specific component, respectively. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0066] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A power module packaging structure with low stray inductance, characterized in that, The invention includes a DBC substrate and a chipset disposed on the DBC substrate, wherein the chipset includes at least one chip. The target chip in the chipset is electrically connected to the DBC substrate via interconnecting conductive sheets. The interconnecting conductive sheet is provided with a plurality of stress relief holes, which penetrate the interconnecting conductive sheet; The interconnecting conductive sheet includes a first flat portion, which is disposed on the target chip. When the chip group includes more than one target chip, the target chips in the chip group are electrically connected to each other through the first flat portion. The stress relief holes are elliptical in shape, and a plurality of stress relief holes are evenly distributed in the first straight portion of the interconnecting conductive sheet; The interconnecting conductive sheet also includes a U-shaped connection group connected to the first straight portion; The U-shaped connection group includes one or more U-shaped connection parts, and the target chip in the chipset is electrically connected to the DBC substrate through the U-shaped connection parts; The U-shaped connection group also includes several second straight sections, and adjacent U-shaped connection sections are connected through the second straight sections. The U-shaped connection group is generally wavy in the cross-section of the packaging structure. The height difference between the target chip and the front side of the DBC substrate is compensated by the height of the U-shaped connector to improve the stability of the electrical connection between the target chip and the DBC substrate.

2. The power module packaging structure with low stray inductance according to claim 1, characterized in that, The chip includes a front side and a back side corresponding to the front side; The back of the chip is soldered to the DBC substrate via a first solder layer; The U-shaped connection portion of the interconnect conductive sheet is soldered to the DBC substrate through a first solder layer, and the first straight portion of the interconnect conductive sheet is soldered to the front side of the chip through a second solder layer.

3. The power module packaging structure with low stray inductance according to claim 2, characterized in that, The DBC substrate includes an upper connection layer, a lower connection layer, and an insulating layer. The insulating layer is located between the upper connection layer and the lower connection layer and is in contact with both the upper connection layer and the lower connection layer. In the chipset, the back of the chip is soldered to the upper connection layer via a first solder layer, and the lower connection layer is soldered to the support plate via a third solder layer.

4. The power module packaging structure with low stray inductance according to claim 3, characterized in that, A housing is also fixed to the support plate, and after the housing is fixed to the support plate, a receiving cavity is formed between the support plate and the housing; The DBC substrate, chipset, and interconnect conductive sheet are located in the receiving cavity, which is filled with encapsulating adhesive, and the encapsulating adhesive covers the DBC substrate, chipset, and interconnect conductive sheet.

5. The power module packaging structure with low stray inductance according to claim 4, characterized in that, It also includes several lead-out terminals; The housing is provided with a plurality of mounting holes, each corresponding to a lead-out terminal. One end of the lead-out terminal is connected to the DBC substrate, and the other end of the lead-out terminal extends out of the housing through the corresponding mounting hole on the housing.

6. The power module packaging structure with low stray inductance according to claim 1, characterized in that, The material of the interconnecting conductive sheet includes Cu.

7. A method for packaging a power module with low stray inductance, characterized in that, The packaging method for forming the power module packaging structure according to any one of claims 1-6 includes: A DBC substrate is provided and a chipset is mounted on the DBC substrate, wherein the chipset includes at least one chip; The target chip in the chipset is electrically connected to the DBC substrate through an interconnect conductive sheet. The interconnect conductive sheet is provided with a plurality of stress relief holes, which penetrate the interconnect conductive sheet.

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