Sinc filter and ADC data high-speed acquisition system

Abstract

The present application discloses a Sinc filter and an ADC data high-speed acquisition system, and relates to the field of filter technology. The Sinc filter includes a controller, an integrator, a differentiator, and a multiplexing controller. Among them, the controller is connected to the ADC, the integrator is connected to the controller, the differentiator is connected to the controller, and the multiplexing controller is connected to the connector. The multiplexing controller is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode. In the filtering mode, the Sinc filter is configured to filter the output signal of the ADC. In the data acquisition mode, the Sinc filter is configured to collect the data output by the ADC by the controller, and output it through at least one first memory and / or at least one second memory. The Sinc filter can be used as a filter and can also be used as a data collector for ADC debugging, which saves circuit resources to a large extent and reduces costs.

Description

Technical Field

[0001] The present application relates to the technical field of filters, and more specifically, to a Sinc filter and an ADC data high-speed acquisition system. Background Art

[0002] On the one hand, ADC (analog-to-digital converter) debugging is a crucial part of designing and verifying digital systems. Dumping the ADC's raw data stream is a common debugging method that can help engineers analyze and verify the ADC's performance. The implementation of this function often requires the introduction of new circuit resources, such as memory, controllers, etc., which will undoubtedly increase resources and costs.

[0003] On the other hand, SAR (Successive Approximation Register) ADC is a commonly used analog-to-digital converter that performs digital conversion by gradually approximating the analog value of the input data. However, due to the existence of certain nonlinearity and noise in SAR ADC, in order to improve its accuracy, CIC (Integral Comb) filter is usually used to filter its output. The frequency response of CIC filter is presented in the form of Sinc function, so it is also called Sinc filter. The combination of SAR ADC and Sinc filter is widely used in many applications, such as precision measurement, instrumentation, communication systems and other fields. Summary of the invention

[0004] The embodiments of the present application provide a Sinc filter and an ADC data high-speed acquisition system.

[0005] The Sinc filter provided in the embodiment of the present application may include a controller, an integrator, a differentiator, and a multiplexing controller. Among them, the controller can be connected to the ADC, the integrator can be connected to the controller, the differentiator can be connected to the controller, and the multiplexing controller can be connected to the connector. The multiplexing controller is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode. In the filtering mode, the Sinc filter is configured to filter the output signal of the ADC. In the data acquisition mode, the Sinc filter is configured to collect the data output by the ADC by the controller and output it through at least one first memory and / or at least one second memory.

[0006] The multiplexing control circuit can control the Sinc filter to work in filtering mode or data acquisition mode. In data acquisition mode, the controller can collect data output by the ADC, and the first memory of the integrator and the second memory of the differentiator can store the data output by the ADC, and the controller, the first memory and the second memory are multiplexed. The Sinc filter provided in the embodiment of the present application can be used as a filter and a data collector for ADC debugging at the same time, which saves circuit resources to a large extent and reduces costs.

[0007] In some embodiments, the filter further comprises a selector connected to the multiplexing controller, and the multiplexing controller is configured to control the selector to write the data output by the ADC into the at least one first memory and / or the at least one second memory in a predetermined writing manner.

[0008] In this way, the multiplexing controller can control the second end of the selector to select the first memory or the second memory to be connected, so that the data output by the ADC can be written into the corresponding first memory or the corresponding second memory according to a predetermined writing method.

[0009] In some implementations, the predetermined writing mode includes a ping-pong operation or a multi-level ping-pong operation writing mode.

[0010] In this way, the writing method of ping-pong operation or multi-level ping-pong operation can achieve concurrent access and update of data while avoiding direct conflicts.

[0011] In some embodiments, the multiplexing controller is configured to control the selector to read data from at least one level of first memory and / or at least one level of second memory in a predetermined reading manner.

[0012] In this way, the multiplexing controller can control the second end of the selector to select the connected first memory or the second memory, so that the controller can read the data of the corresponding first memory or the corresponding second memory according to a predetermined reading method.

[0013] In some embodiments, the predetermined reading mode includes a ping-pong operation or a multi-level ping-pong operation reading mode.

[0014] In this way, the reading method of ping-pong operation or multi-level ping-pong operation can achieve concurrent access and update of data while avoiding direct conflicts.

[0015] In some embodiments, the integrator includes a first processor, and the differentiator includes a second processor. In the filtering mode, the controller is configured to control the first processor and the second processor to operate so as to filter the output signal of the ADC.

[0016] In some embodiments, the filter includes a downsampler connected between the integrator and the differentiator, and the downsampler is configured to downsample the signal processed by the integrator and provide the signal to the differentiator.

[0017] The ADC data high-speed acquisition system provided in the embodiment of the present application includes an ADC, a Sinc filter and a storage module. The ADC can be configured to convert an analog signal connected to a digital signal. The Sinc filter can be connected to the ADC and configured to filter the output signal of the ADC and output it, or store the output data of the ADC and output it. The storage module can be connected to the filter and configured to store the output data of the filter.

[0018] In certain embodiments, the ADC is a successive approximation ADC.

[0019] In some embodiments, the ADC data high-speed acquisition system is configured to communicate with an external device, the external device is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode, and the external device is also configured to read data from a storage module.

[0020] The Sinc filter provided in the embodiment of the present application may include a controller, an integrator, a differentiator, and a multiplexing controller. Among them, the controller can be connected to the ADC, the integrator can be connected to the controller, the differentiator can be connected to the controller, and the multiplexing controller can be connected to the connector. The multiplexing controller is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode. In the filtering mode, the Sinc filter is configured to filter the output signal of the ADC. In the data acquisition mode, the Sinc filter is configured to collect the data output by the ADC by the controller and output it through at least one first memory and / or at least one second memory.

[0021] The multiplexing control circuit can control the Sinc filter to work in filtering mode or data acquisition mode. In data acquisition mode, the controller can collect data output by the ADC, and the first memory of the integrator and the second memory of the differentiator can store the data output by the ADC, and the controller, the first memory and the second memory are multiplexed. The Sinc filter provided in the embodiment of the present application can be used as a filter and a data collector for ADC debugging at the same time, which saves circuit resources to a large extent and reduces costs.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a schematic diagram of a Sinc filter according to an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a Sinc filter according to some embodiments of the present application;

[0026] Figure 3 is a schematic diagram of reading data of a ping-pong operation according to an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of an ADC data high-speed acquisition system according to an embodiment of the present application;

[0028] Figure 5 It is a schematic diagram of the working process of the Sinc filter in the implementation mode of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] On the one hand, ADC (analog-to-digital converter) debugging is a crucial part of designing and verifying digital systems. Dumping the ADC's raw data stream is a common debugging method that can help engineers analyze and verify the ADC's performance. The implementation of this function often requires the introduction of new circuit resources, such as memory, controllers, etc., which will undoubtedly increase resources and costs.

[0031] On the other hand, SAR (Successive Approximation Register) ADC is a commonly used analog-to-digital converter that performs digital conversion by gradually approximating the analog value of the input data. However, due to the existence of certain nonlinearity and noise in SAR ADC, in order to improve its accuracy, CIC (Integral Comb) filter is usually used to filter its output. The frequency response of CIC filter is presented in the form of Sinc function, so it is also called Sinc filter. The combination of SAR ADC and Sinc filter is widely used in many applications, such as precision measurement, instrumentation, communication systems and other fields.

[0032] The present application embodiment provides a Sinc filter 100 (such as Figure 1 as well as Figure 2 As shown in FIG. 1 ), the Sinc filter 100 can realize the multiplexing of data acquisition and filtering functions, thereby saving circuit resources to a large extent and reducing costs.

[0033] Reference Figure 1The Sinc filter 100 provided in the embodiment of the present application may include a controller 10, an integrator 20, a differentiator 30, and a multiplexing controller 40. The controller 10 may be connected to the ADC 200, the integrator 20 may be connected to the controller 10, the differentiator 30 may be connected to the controller 10, and the multiplexing controller 40 may be connected to the connector. The multiplexing controller 40 is configured to control the Sinc filter 100 to operate in a filtering mode or a data acquisition mode. In the filtering mode, the Sinc filter 100 is configured to filter the output signal of the ADC 200. In the data acquisition mode, the Sinc filter 100 is configured so that the controller 10 collects the data output by the ADC 200 and outputs it through at least one first memory 21 and / or at least one second memory 31.

[0034] Specifically, the Sinc filter 100 (sine coagulant filter) is a low-pass filter. The Sinc filter 100 can filter the signal based on the Sinc function (sine coagulant function). The Sinc function can be defined as: when x is not equal to 0, Sinc(x) is equivalent to sin(x) / x, and when x is equal to 0, Sinc(0) is defined as 1 to ensure that the function is continuous at x=0.

[0035] The Sinc filter 100 can eliminate frequency components above the cutoff frequency while keeping all frequency components below the cutoff frequency unaffected. The Sinc filter 100 is widely used in many fields. For example, in the field of image processing, the use of the Sinc filter 100 in image reconstruction and interpolation can help restore or enhance image quality. In audio signal processing, the Sinc filter 100 can be used for sound quality improvement, noise reduction or accurate replication of signals. In the field of communications, the Sinc filter 100 can be used for signal pre-processing and post-processing, such as pre-emphasis before analog signal transmission, or de-emphasis at the receiving end to compensate for the impact of the channel on the signal. In digital signal processing, the Sinc filter 100 can be used as a low-pass filter for signal filtering and signal recovery after sampling.

[0036] The integrator 20 may include an integration circuit composed of a capacitor and a resistor, and the integrator 20 may perform an integration operation on the input data. In the Sinc filter 100, for analog signals, the integrator 20 may provide a smooth signal and reduce high-frequency noise. In digital signal processing, the integrator 20 is used to calculate the accumulated value of the signal, which plays an important role in realizing the low-pass filtering of the Sinc filter 100.

[0037] The integrator 20 may further include a first memory 21 of one level, or may include a multi-level first memory 21. The first memory 21 may be a memory resource of the integrator 20 itself. During the process of the integrator 20 performing the integration operation, the first memory 21 may be used to accumulate the amount of electricity or energy received from the input data. Each time the input data changes, the first memory 21 will increase or decrease the energy inside it accordingly, and the memory may realize the integration function during the accumulation process. The capacity of the first memory 21 also affects the response time of the integrator 20, and the response time of the integrator 20 may be set by setting the capacity of the first memory 21. The first memory 21 may also be used as a buffer for the signal in the integrator 20 to reduce the delay or distortion during the signal transmission process.

[0038] The differentiator 30 may include a differential circuit composed of a capacitor element and a resistor element, and the integrator 20 may perform a differential operation on the input data. In the Sinc filter 100, the differentiator 30 may generate a filter with a steep transition band, i.e., a sharp drop at the pass frequency and a complete cutoff at the stop frequency. This may be achieved by differentiating the input data, thereby generating a greater attenuation on the high frequency components while retaining the low frequency components.

[0039] The differentiator 30 may also include a first-level second memory 31, or may include multiple levels of second memory 31. The second memory 31 may be a memory resource of the differentiator 30 itself. The differentiator 30 may be designed to cache changes in input data at one or more time points. The second memory 31 may be used to calculate continuous differences of signals, or as part of an intermediate step in a differential operation. In the differential operation of the differentiator 30, when comparing the difference between two signals at the same time point, the second memory 31 may store the instantaneous value of the signal for comparison.

[0040] The number of levels of the Sinc filter 100 provided in the embodiment of the present application can be set according to actual needs, including but not limited to Sinc filters 100 such as Sinc1, Sinc3, and Sinc5. The number of levels of the corresponding first memory 21 and the second memory 31 can be set according to actual needs. The types of the first memory 21 and the second memory 31 are not limited, including but not limited to register groups, RAM (random access memory), FIFO (first-in-first-out data buffer) and other data buffer modules for storage.

[0041] The controller 10 can be set as the main controller 10 of the filter, and the working mode of the controller 10 is consistent with the working mode of the filter. The controller 10 and the filter can work in the filtering mode, and the controller 10 can control the integrator 20 and the differentiator 30 to work in combination. The output data of ADC200 can be used as input data of the integration circuit in the integrator 20, or as input data of the differential circuit in the differentiator 30. The integrator 20 and the differentiator 30 work in combination to filter the output signal of ADC200.

[0042] The controller 10 and the filter can also work in the data acquisition mode, and the first memory 21 and the second memory 31 can both be used as storage resources for the output data of ADC200. In the data acquisition mode, the first memory 21 and the second memory 31 can both be used as intermediate links for the output data of ADC200, and can temporarily store these data to ensure that the data will not be lost before being processed by the data processing system. The output data of ADC200 can be output after passing through the first memory 21, can be output after passing through the second memory 31, or can be output after passing through the first memory 21 and the second memory 31. The number of levels of the first memory 21 and the second memory 31 can be set according to actual needs.

[0043] In the data acquisition mode, the first memory 21 and the second memory 31 can be cascaded. When the data acquisition rate does not match the data processing or transmission rate, the cascaded first memory 21 and the second memory 31 can act as a buffer to prevent data loss or system overload. For example, a large amount of data generated by a high-speed sensor can be temporarily stored in the first memory 21 or the second memory 31, waiting for system processing or transmission to the next stage.

[0044] In the data acquisition mode, the first memory 21 and the second memory 31 can also ensure the integrity and consistency of the data. During data transmission or processing, data may be lost or damaged due to network delays, hardware failures, etc. The first memory 21 and the second memory 31 can be used as backup storage resources to provide the possibility of data recovery and ensure the integrity of the data.

[0045] It should be noted that, in the data acquisition mode, the first memory 21 and the second memory 31 can realize the raw data stream acquisition of the data output by the ADC 200. The raw data stream acquisition is the process of collecting data directly from the source without any processing or conversion. The first memory 21 and the second memory 31 may not perform any processing or conversion on the data output by the ADC 200.

[0046] The multiplexing control circuit can control the Sinc filter 100 to operate in filtering mode or data acquisition mode. In the data acquisition mode, the controller 10 can collect data output by the ADC 200, and the first memory 21 of the integrator 20 and the second memory 31 of the differentiator 30 can store the data output by the ADC 200, thereby multiplexing the controller 10, the first memory 21 and the second memory 31.

[0047] It can be understood that the Sinc filter 100 provided in the embodiment of the present application can be used as a filter and also as a data collector for debugging the ADC 200, which saves circuit resources to a great extent and reduces costs.

[0048] Reference Figure 2 In some embodiments, the filter further includes a selector 50 connected to the multiplexing controller 40. The multiplexing controller 40 is configured to control the selector 50 to write the data output by the ADC 200 into the at least one first memory 21 and / or the at least one second memory 31 in a predetermined writing manner.

[0049] Specifically, in the data acquisition mode, the selector 50 can be set as a write selector of the memory. The first end of the selector 50 can access the data output by the ADC 200, and the multiplexing controller 40 can control the second end of the selector 50 to select access to the first memory 21 or the second memory 31. The multiplexing controller 40 can control the output data of the ADC 200 as the input data of the first memory 21, or as the input data of the second memory 31.

[0050] When the output data of ADC200 is used as the input data of the first memory 21, the output data of ADC200 is written into the first memory 21. When the output data of ADC200 is used as the input data of the second memory 31, the output data of ADC200 is written into the second memory 31. The multiplexing controller 40 can control the second end of the selector 50 to select the first memory 21 or the second memory 31 to be connected, so that the data output by ADC200 can be written into the corresponding first memory 21 or the corresponding second memory 31 according to a predetermined writing method.

[0051] Reference Figure 2 In some embodiments, the multiplexing controller 40 is configured to control the selector 50 to read data from at least one level of the first memory 21 and / or at least one level of the second memory 31 in a predetermined reading manner.

[0052] Specifically, in the data acquisition mode, the selector 50 can be set as a read selector of the memory. The first end of the selector 50 can be connected to the output end of the Sinc filter 100, and the multiplexing controller 40 can control the second end of the selector 50 to select the first memory 21 or the second memory 31. The multiplexing controller 40 can control the data of the first memory 21 as the output data of the Sinc filter 100, or control the data of the second memory 31 as the output data of the Sinc filter 100. The multiplexing controller 40 can control the second end of the selector 50 to select the first memory 21 or the second memory 31 to be connected, and the data of the first memory 21 or the second memory 31 can be output from the output end of the Sinc filter 100.

[0053] The first end of the selector 50 can also be connected to the controller 10, and the multiplexing controller 40 can control the data of the first memory 21 as the data read by the controller 10, or control the data of the second memory 31 as the data read by the controller 10. The multiplexing controller 40 can control the second end of the selector 50 to select the connected first memory 21 or the second memory 31, so that the controller 10 can read the corresponding data of the first memory 21 or the corresponding data of the second memory 31 according to a predetermined reading method.

[0054] In some implementations, the predetermined writing mode includes a ping-pong operation or a multi-level ping-pong operation writing mode.

[0055] Specifically, the core idea of ​​ping-pong operation is to use two "buffers" to store and access data in turn. When one processor is reading or writing one buffer, the other buffer can be accessed by another processor, thus achieving concurrent access and update of data while avoiding direct conflicts.

[0056] by Figure 3 For example, the multiplexing controller 40 can realize the writing mode of ping-pong operation by alternately writing data between the memory 1 and the memory 2 through the selector 50. Among them, the memory 1 can be set to the first memory 21 of any level or the second memory 31 of any level, and the memory 2 can be set to the first memory 21 of any level or the second memory 31 of any level, and the memory 1 is different from the memory 2.

[0057] The output data stream of ADC200 can be divided into data 1, data 2, data 3 and data 4. At time t1, the multiplexing controller 40 can control data 1 to be written into memory 1 through the selector 50. At time t2 after time t1, the multiplexing controller 40 can control data 2 to be written into memory 2 through the selector 50. At time t3 after time t2, the multiplexing controller 40 can control data 3 to be written into memory 1 through the selector 50. At time t4 after time t3, the multiplexing controller 40 can control data 4 to be written into memory 2 through the selector 50.

[0058] Multi-level ping-pong operation adds layers and complexity based on ping-pong operation, and supports more complex concurrency control and data processing requirements by introducing multiple buffers and corresponding management strategies.

[0059] In multi-level ping-pong operation, multiple levels of buffers can be used. For example, the first level buffer is used to process the most recent request, the second level buffer is used to process slightly more distant requests, and so on. Each level of buffer is responsible for different tasks or data processing stages, which can achieve hierarchical processing and optimization of tasks. In multi-level ping-pong operation, queue structures can be used to manage multiple buffers. Queues can allocate buffers to different requests or tasks based on first-in-first-out (FIFO), priority, or other strategies. This approach helps ensure fairness, priority processing, or fast response for specific tasks.

[0060] For example, the multiplexing controller 40 can store data alternately among the memory 1 , the memory 2 , the memory 3 , and the memory 4 through the selector 50 , thereby realizing a writing method of a multi-level ping-pong operation.

[0061] The output data stream of ADC200 can be divided into data 1, data 2, data 3 and data 4. At time t1, the multiplexing controller 40 can control data 1 to be written into memory 1 through the selector 50. At time t2 after time t1, the multiplexing controller 40 can control data 2 to be written into memory 2 through the selector 50. At time t3 after time t2, the multiplexing controller 40 can control data 3 to be written into memory 3 through the selector 50. At time t4 after time t3, the multiplexing controller 40 can control data 4 to be written into memory 4 through the selector 50.

[0062] In some embodiments, the predetermined reading mode includes a ping-pong operation or a multi-level ping-pong operation reading mode.

[0063] by Figure 3For example, the multiplexing controller 40 can realize the ping-pong operation reading mode by alternately reading data between the memory 1 and the memory 2 through the selector 50. Among them, the memory 1 can be set to the first memory 21 of any level or the second memory 31 of any level, and the memory 2 can be set to the first memory 21 of any level or the second memory 31 of any level, and the memory 1 is different from the memory 2.

[0064] The output data stream of ADC200 can be divided into data 1, data 2, data 3 and data 4. At time t1, the multiplexing controller 40 can read data 1 from the memory 1 through the selector 50. At time t2 after time t1, the multiplexing controller 40 can control the reading of data 2 from the memory 2 through the selector 50. At time t3 after time t2, the multiplexing controller 40 can read data 3 from the memory 1 through the selector 50. At time t4 after time t3, the multiplexing controller 40 can read data 4 from the memory 2 through the selector 50.

[0065] The multiplexing controller 40 can also perform data reading alternately among the memory 1 , the memory 2 , the memory 3 and the memory 4 through the selector 50 , so as to implement a multi-level ping-pong operation reading method.

[0066] The output data stream of ADC200 can be divided into data 1, data 2, data 3 and data 4. At time t1, the multiplexing controller 40 can read data 1 from memory 1 through the selector 50. At time t2 after time t1, the multiplexing controller 40 can control the reading of data 2 from memory 2 through the selector 50. At time t3 after time t2, the multiplexing controller 40 can read data 3 from memory 3 through the selector 50. At time t4 after time t3, the multiplexing controller 40 can read data 4 from memory 4 through the selector 50.

[0067] based on Figure 3 By comparing the common read and write mode with the ping-pong operation or multi-level ping-pong operation, it can be clearly seen that the ping-pong operation has the advantage in time, which can realize the parallelization of data processing and improve the efficiency of data processing. In addition, the ping-pong operation can effectively reduce the processing delay, so that data can be processed and transmitted faster, and optimize the data processing process.

[0068] Reference Figure 2 In some embodiments, the integrator 20 includes a first processor 22, and the differentiator 30 includes a second processor 32. In the filtering mode, the controller 10 is configured to control the first processor 22 and the second processor 32 to filter the output signal of the ADC 200.

[0069] Specifically, the integrator 20 may include a first processor 22. When the first processor 22 is working, the integrator 20 may perform an integration operation on the input data. The differentiator 30 may include a second processor 32. When the second processor 32 is working, the differentiator 30 may perform an integration operation on the input data.

[0070] In the filtering mode, the controller 10 can control the first processor 22 and the second processor 32 to work, so that the integrator 20 and the differentiator 30 work in combination to filter the output signal of the ADC 200 .

[0071] Reference Figure 2 In some embodiments, the filter includes a downsampler 60 , which is connected between the integrator 20 and the differentiator 30 , and the downsampler 60 is configured to downsample the signal processed by the integrator 20 and provide it to the differentiator 30 .

[0072] The downsampler 60 can reduce the sampling rate of the signal. The downsampler 60 can reduce the sampling rate of the signal by reducing the number of sampling points. For example, every N sampling points are merged into a new sampling point, where N is an integer greater than 1. In the filtering mode, the downsampler 60 can remove the frequency components that may be introduced by the sampling rate reduction to avoid aliasing effects.

[0073] The downsampler 60 can downsample the signal processed by the integrator 20 , and the cutoff frequency of the integrator 20 can be set below half of the sampling rate of the downsampler 60 to ensure that all frequency components higher than half of the new sampling rate are filtered out.

[0074] In the Sic filter, the downsampler 60 plays an important role in processing large amounts of data, saving storage space, optimizing transmission efficiency and increasing processing speed. By combining sampling rate reduction with appropriate filtering, the frequency content of the signal can be effectively managed to ensure that the quality of the signal remains good after the sampling rate is reduced.

[0075] Reference Figure 4 , the embodiment of the present application also provides an ADC data high-speed acquisition system 1000. The ADC data high-speed acquisition system 1000 provided in the embodiment of the present application includes ADC200, Sinc filter 100 and storage module 300. ADC200 can be configured to convert the analog signal connected to the digital signal. Sinc filter 100 can be connected to ADC200, and configured to filter the output signal of ADC200 and output it, or store the output data of ADC200 and output it. The storage module 300 can be connected to the filter, and configured to store the output data of the filter.

[0076] The ADC data high-speed acquisition system 1000 based on resource reuse provided in the embodiment of the present application saves circuit resources to a large extent and reduces costs while taking into account normal filtering functions and debugging functions. Among them, the data storage solution of the ping-pong structure not only reduces additional resources by reusing the memory, but also improves the efficiency of data processing.

[0077] In some implementations, ADC 200 is a successive approximation ADC.

[0078] Specifically, the successive approximation ADC can perform conversion by gradually approximating the difference between a reference voltage and an input analog voltage.

[0079] The successive approximation ADC can first set a reference voltage, usually half of the full-scale voltage, and then determine whether the reference voltage needs to be increased or decreased based on the size of the input analog signal. After each comparison, the comparator inside the successive approximation ADC compares the reference voltage with the input analog signal. If the voltage of the analog signal is higher, it means that the target voltage is above the reference voltage, otherwise it is below the reference voltage. Based on the result of the comparison, the successive approximation ADC changes the set value of the reference voltage. This process is performed bit by bit, starting with the highest bit and ending with the lowest bit. Each comparison selects a possible bit value until the desired accuracy is achieved.

[0080] The Sinc filter 100 can filter the output signal of the successive approximation ADC 200, suppress the noise generated by the successive approximation ADC, and improve the accuracy of the output signal of the successive approximation ADC.

[0081] In some embodiments, the ADC data high-speed acquisition system 1000 is configured to communicate with an external device, the external device is configured to control the Sinc filter 100 to operate in a filtering mode or a data acquisition mode, and the external device is also configured to read data from the storage module 300.

[0082] Specifically, the external device can be set as a debugging host of the ADC data high-speed acquisition system 1000, and the external device can control the Sinc filter 100 to work in a filtering mode or a data acquisition mode.

[0083] The workflow of the Sinc filter 100 of the embodiment of the present application can be referred to Figure 5 When the ADC data high-speed acquisition system 1000 starts to work, the ADC 200 can convert the analog signal received into a data signal and provide it to the Sinc filter 100. The debugging host can control the Sinc filter 100 to perform the filtering function or the debugging function.

[0084] In filtering mode, the Sinc filter 100 can filter the output signal of the ADC 200 and provide the output data to the storage module 300. In debugging mode, the Sinc filter 100 can collect the original data stream output by the ADC 200 based on the data storage of the ping-pong result and provide the collected data to the storage module 300.

[0085] The debugging host can be connected to the storage module 300 based on a communication protocol such as I2C, I3C, UART, SPI, USB, etc. to read the filtered data or collected data in the storage module 300 so that the debugging host can perform the debugging function.

[0086] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, deconstructions, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0087] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0088] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0089] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0090] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A Sinc filter, characterized in that: The filter comprises: A controller configured to be connected to the ADC; an integrator connected to the controller, the integrator comprising at least one level of first memory; A differentiator connected to the controller, the differentiator comprising at least one level of second memory; A multiplexing controller connected to the controller, the multiplexing controller is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode. In the filtering mode, the Sinc filter is configured to filter the output signal of the ADC. In the data acquisition mode, the Sinc filter is configured to allow the controller to collect the original data stream output by the ADC and output it through at least one level of the first memory and / or at least one level of the second memory. The first memory and the second memory are configured to store the original data stream output by the ADC.

2. The Sinc filter according to claim 1, characterized in that: The filter further includes a selector connected to the multiplexing controller, and the multiplexing controller is configured to control the selector to write the data output by the ADC into the at least one first memory and / or the at least one second memory in a predetermined writing manner.

3. The Sinc filter according to claim 2, characterized in that: The predetermined writing mode includes a writing mode of a ping-pong operation or a writing mode of a multi-level ping-pong operation.

4. The Sinc filter according to claim 1, characterized in that: The filter also includes a selector connected to the multiplexing controller, and the multiplexing controller is configured to control the selector to read data from the at least one level of first memory and / or the at least one level of second memory in a predetermined reading manner.

5. The Sinc filter according to claim 4, characterized in that: The predetermined reading mode includes a ping-pong operation or a multi-level ping-pong operation reading mode.

6. The Sinc filter according to claim 1, characterized in that: The integrator includes a first processor, the differentiator includes a second processor, and in the filtering mode, the controller is configured to control the first processor and the second processor to operate so as to filter the output signal of the ADC.

7. The Sinc filter according to claim 1, characterized in that: The filter includes a down sampler connected between the integrator and the differentiator, and the down sampler is configured to down sample the signal processed by the integrator and provide the signal to the differentiator.

8. An ADC data high-speed acquisition system, characterized in that: The system comprises: ADC, configured to convert the input analog signal into a digital signal; The Sinc filter according to any one of claims 1 to 7, connected to the ADC, and configured to filter the output signal of the ADC and then output it, or store the output data of the ADC and then output it; The storage module is connected to the filter and is configured to store output data of the filter.

9. The ADC data high-speed acquisition system according to claim 8, characterized in that: The ADC is a successive approximation ADC.

10. The ADC data high-speed acquisition system according to claim 8, characterized in that: The system is configured to be in communication connection with an external device, the external device is configured to control the Sinc filter to operate in a filtering mode or a data acquisition mode, and the external device is further configured to read data from the storage module.

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