Method, electronic device and medium for processing requests based on pipeline

Abstract

The embodiment of the present invention provides a method, electronic device and medium based on pipeline processing request, which relates to the field of communication technology. The method includes: in response to receiving a pending transaction, determining the type of pipeline operation to be performed on the pending transaction; in response to determining a pipeline read operation, performing a pipeline read operation on the pending transaction; determining whether to trigger a pipeline write operation according to the operation result of the pipeline read operation; in response to the trigger, matching the cache line to be updated corresponding to the pending transaction with the cache line of the uncompleted update recorded in the risk queue; if the match is successful, marking the pending transaction as a retry request to re-perform a pipeline read operation on the pending transaction and canceling the pipeline write operation; if the match is unsuccessful, performing a pipeline write operation. The method records the cache line that has not been updated in the risk queue, and prohibits the processing of the cache line when the cache line has not been updated to avoid cache inconsistency.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method, electronic equipment and medium for processing requests based on a pipeline. Background Art

[0002] Cache is a memory hierarchy used to store temporary data to improve the performance of computer programs. It is usually divided into three levels: L1 Cache (first-level cache), L2 Cache (second-level cache), and L3 Cache (third-level cache). Among them, L3 Cache is a shared cache located between processor cores. Multiple processor cores can share the same L3 Cache. L3 Cache significantly improves the overall performance of the system by increasing data access speed, reducing memory bandwidth pressure, and improving data sharing efficiency of multi-core processors. Data interaction optimization for L3 Cache has always been an important part of computer architecture. At present, dual-port L3 Cache or single-port L3 Cache is usually used in computer systems. Dual-port L3 Cache can read and write at the same time and has high data parallel processing capabilities, but it does not have a good PPA (PPA is an important indicator in the field of chip design, representing performance (Performance), power consumption (Power) and area (Area)) because of its large power consumption area and high critical path latency in specific pipeline implementation. Therefore, dual-port L3 Cache is gradually replaced by single-port L3 Cache.

[0003] However, the current cache consistency processing method for single-port L3 Cache has at least the following technical problems: the pipeline design is too redundant, the critical path timing performance is not good, the overall cache consistency performance is poor, and the maximum supported clock frequency is reduced; the single-port design causes the L3 Cache to be unable to support simultaneous reading and writing, and the Cache Victim consistency problem (victim cache, referring to the consistency problem caused by the cache being replaced by different transactions) and cache line (way) update conflict problems that may be caused by different transactions cannot be solved. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, an embodiment of the present invention provides a method, an electronic device and a medium for processing requests based on a pipeline.

[0005] In a first aspect, an embodiment of the present application provides a method for processing a request based on a pipeline, the method comprising:

[0006] In response to the receiving end of the pipeline receiving a pending transaction, arbitrating the pending transaction and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes a pipeline read operation and a pipeline write operation;

[0007] In response to determining to perform a pipeline read operation on the pending transaction, performing a pipeline read operation on the pending transaction;

[0008] Determine whether to trigger a pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes updating the cache line to be updated corresponding to the pending transaction;

[0009] In response to determining that a pipeline write operation is triggered, matching the cache line to be updated corresponding to the pending transaction with a risk queue, the risk queue being used to record the cache line for which the update is not completed;

[0010] In response to the cache line to be updated matching the cache line of incomplete update recorded by the risk queue, the pending transaction is identified as a retry request, and the pipeline write operation on the pending transaction is canceled; the retry request indicates re-performing a pipeline read operation on the pending transaction; or, in response to the cache line to be updated not matching the cache line of incomplete update recorded by the risk queue, a pipeline write operation is performed on the pending transaction.

[0011] Optionally, the method further includes: the pipeline read operation and the pipeline write operation are read and written in the same beat.

[0012] Optionally, the pipeline includes five beats; the method includes:

[0013] In response to receiving a pending transaction at a receiving end of the pipeline, the pending transaction is arbitrated in a first beat of the pipeline to determine a type of pipeline operation to be performed on the pending transaction.

[0014] Optionally, arbitrating the pending transaction to determine a type of pipeline operation to be performed on the pending transaction includes:

[0015] If the pending transaction is a request for missing state holding register output, and there is no pipeline write operation to be processed currently, determining to perform a pipeline read operation on the pending transaction;

[0016] If the transaction to be processed is a pipeline write operation to be processed, determine to perform a pipeline write operation on the transaction to be processed.

[0017] Optionally, the pipeline read operation includes one or more of reading Tag SRAM, reading SF SRAM, reading LRU SRAM, and reading Data SRAM; the pipeline write operation includes one or more of writing Tag SRAM, writing SF SRAM, writing LRU SRAM, and writing Data SRAM;

[0018] The beats of writing Tag SRAM, writing SF SRAM, and writing LRU SRAM are the same as the beats of reading Tag SRAM, reading SF SRAM, and reading LRU SRAM; the beats of writing Data SRAM are the same as the beats of reading Data SRAM.

[0019] Optionally, the method further includes: reading Tag SRAM, reading SFSRAM, and reading LRU SRAM in the second beat of the pipeline, and reading Data SRAM in the fifth beat of the pipeline; and writing Tag SRAM, writing SF SRAM, and writing LRU SRAM in the second beat of the pipeline, and writing Data SRAM in the fifth beat of the pipeline.

[0020] Optionally, in the second beat of the pipeline, the method includes:

[0021] If a pipeline read operation is performed, a target cache group is determined according to the address information of the transaction to be processed;

[0022] Reading first tag information of all valid cache lines of the target cache group from the Tag SRAM, wherein the Tag SRAM is used to record tag information corresponding to data stored in the L3 Cache;

[0023] Reading snoop filter information of all valid cache lines of the target cache group from the SF SRAM, the SF SRAM being used to record the snoop filter information acquired by the snoop filter, the snoop filter information including second tag information, the second tag information being tag information of cache lines shared by multiple processor cores;

[0024] Reading an entry in the LRU SRAM, the entry including re-reference prediction values ​​of all cache lines of the target cache group;

[0025] Outputting the first tag information, the second tag information and the entry in the LRU SRAM as output information of the second beat to the third beat of the pipeline;

[0026] If a pipeline write operation is performed, the tag information of the cache line to be updated in the Tag SRAM and the SF SRAM is updated, and the re-reference prediction value of the cache line to be updated in the LRU SRAM is updated.

[0027] Optionally, in the third beat of the pipeline, the method includes:

[0028] If a pipeline read operation is performed, determining whether the transaction to be processed hits the cache line in the Tag SRAM and the cache line in the SF SRAM according to the output information of the second beat and the tag information in the address information of the transaction to be processed;

[0029] In response to the pending transaction not hitting a cache line in the Tag SRAM, determining a free cache line of a target cache group in the Tag SRAM;

[0030] In response to the pending transaction missing a cache line in the SF SRAM, determining a free cache line of a target cache group in the SF SRAM;

[0031] Determine the cache line to be replaced according to the entry in the LRU SRAM outputted in the second beat;

[0032] The cache line hit by the pending transaction in the Tag SRAM is used as the first hit cache line, the cache line hit by the pending transaction in the SF SRAM is used as the second hit cache line, the free cache line of the target cache group in the Tag SRAM is used as the first free cache line, and the free cache line of the target cache group in the SF SRAM is used as the second free cache line; the tag information and re-reference prediction value of the first hit cache line, the tag information and re-reference prediction value of the second hit cache line, the tag information and re-reference prediction value of the first free cache line, the tag information and re-reference prediction value of the second free cache line, and the tag information and re-reference prediction value of the cache line to be replaced are used as output information of the third beat, and output to the fourth beat of the pipeline;

[0033] If a pipeline write operation is performed, in the third beat of the pipeline, the output information of the second beat is transferred to the fourth beat.

[0034] Optionally, determining, according to the output information of the second beat and the tag information in the address information of the transaction to be processed, a cache line hit by the transaction to be processed in the Tag SRAM and a cache line hit by the transaction to be processed in the SF SRAM, comprises:

[0035] Matching the first tag information with the tag information in the address information of the pending transaction to determine whether the pending transaction hits the first tag information; if so, determining the cache line hit by the pending transaction in the Tag SRAM;

[0036] The second tag information is matched with the tag information in the address information of the pending transaction to determine whether the pending transaction hits the second tag information; if so, a cache line hit by the pending transaction in the SF SRAM is determined.

[0037] Optionally, the method of using the free cache line of the target cache group in the Tag SRAM as the first free cache line and the free cache line of the target cache group in the SFSRAM as the second free cache line includes:

[0038] Determine whether there is a free cache line in the target cache group in the Tag SRAM; in response to the existence of a free cache line, use the free cache line as a first free cache line; in response to the existence of multiple free cache lines, use the free cache line with the smallest Way Number as the first free cache line;

[0039] Determine whether there is a free cache line in the target cache group in the SF SRAM; in response to the existence of one free cache line, use the one free cache line as a second free cache line; in response to the existence of multiple free cache lines, use the free cache line with the smallest Way Number as the second free cache line;

[0040] Optionally, in the fourth beat of the pipeline, the method includes:

[0041] If a pipeline read operation is performed, the cache line to be updated is determined and an internal state machine judgment is performed according to the result outputted in the third beat and the address information of the transaction to be processed; the cache line to be updated and the judgment result of the internal state machine are outputted to the fifth beat of the pipeline; the internal state machine judgment is used to determine whether to read Data SRAM, whether to write Data SRAM, and whether to trigger one or more of the pipeline write operations;

[0042] If a pipeline write operation is performed, in the fourth beat of the pipeline, the output information of the third beat is transferred to the fifth beat.

[0043] Optionally, in the fifth beat of the pipeline, the method includes:

[0044] If a pipeline read operation is performed, the cache line to be updated corresponding to the pending transaction is matched with the risk queue; in response to the cache line to be updated corresponding to the pending transaction matching the cache line of incomplete update recorded by the risk queue, the pending transaction is marked as a retry request, and it is determined not to perform a pipeline write operation on the pending transaction; or, in response to the cache line to be updated corresponding to the pending transaction not matching the cache line of incomplete update recorded by the risk queue, the pipeline write operation is passed as a pending transaction to the receiving end of the pipeline, and the tag information of the cache line to be updated is written into the risk queue;

[0045] and, in response to the cache line to be updated being a cache line to be replaced and a replacement queue being full, marking the pending transaction as a retry request and determining not to perform a pipeline write operation on the pending transaction, the replacement queue being used to store tag information of the replaced cache line;

[0046] If the pipeline write operation is performed, in the fifth beat of the pipeline, in response to determining to write to the Data SRAM, the writing to the Data SRAM is performed.

[0047] Optionally, determining the cache line to be updated and performing internal state machine judgment according to the result of the third beat output and the address information of the transaction to be processed includes:

[0048] In response to receiving the tag information of the first hit cache line, taking the first hit cache line as a first cache line to be updated; or,

[0049] In response to not receiving the tag information of the first hit cache line and receiving the tag information of the first free cache line, using the first free cache line as the first cache line to be updated; or,

[0050] In response to not receiving the tag information of the first hit cache line and the tag information of the first free cache line, taking the cache line to be replaced as a first cache line to be updated;

[0051] In response to receiving the tag information of the second hit cache line, taking the second hit cache line as a second cache line to be updated; or,

[0052] In response to not receiving the tag information of the second hit cache line and receiving the tag information of the second free cache line, using the second free cache line as a second cache line to be updated;

[0053] Determine whether to update the re-reference prediction value of the first cache line to be updated and the re-reference prediction value of the second cache line to be updated;

[0054] If so, determining an update value of the re-reference prediction value of the first cache line to be updated and an update value of the re-reference prediction value of the second cache line to be updated;

[0055] An internal state machine judgment is performed according to the transaction to be processed, the tag information of the first cache line to be updated, and the tag information of the second cache line to be updated.

[0056] Optionally, matching the cache line to be updated corresponding to the transaction to be processed with a risk queue includes:

[0057] In response to the fourth beat outputting the first cache line to be updated, matching the first cache line to be updated with the cache line whose update has not been completed and recorded in the first risk queue; or,

[0058] In response to the fourth beat, a second cache line to be updated is output, and the second cache line to be updated is matched with the cache line whose update is not completed and recorded in the second risk queue.

[0059] Optionally, in the fourth beat of the pipeline, the method further includes: if a pipeline read operation is performed, in response to the pending transaction missing the cache line in the Tag SRAM and the pending transaction missing the cache line in the SFSRAM, initiating an Addr Buffer query.

[0060] Optionally, in the fifth beat of the pipeline, the method further includes: if a pipeline read operation is performed, determining, based on the result of the Addr Buffer query, to mark the pending transaction as a retry request, and determining not to perform a pipeline write operation on the pending transaction.

[0061] Optionally, in the fifth beat of the pipeline, the method further includes:

[0062] If a pipeline read operation is performed, a second cache line to be updated is output in response to the fourth beat, the second cache line to be updated is not the second hit cache line, and the tag information in the address information of the transaction to be processed exists in the replacement queue, transaction feedback information is output, and it is determined not to perform a pipeline write operation on the transaction to be processed, the transaction feedback information includes broadcast information of the transaction to be processed, and the broadcast information is used to indicate that data corresponding to the address information of the transaction to be processed is obtained from the processor core.

[0063] In a second aspect, an embodiment of the present application provides an electronic device, characterized in that it includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement the method based on pipeline processing requests provided in any embodiment of the present application when executing the program stored in the memory.

[0064] In a third aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, characterized in that when the program is executed by a processor, the method for pipeline processing requests based on any embodiment of the present application is implemented.

[0065] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0066] The method based on pipeline processing request provided by the embodiment of the present application, in response to the receiving end of the pipeline receiving the pending transaction, arbitrating the pending transaction, and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes pipeline read operation and pipeline write operation; in response to determining to perform a pipeline read operation on the pending transaction, executing the pipeline read operation on the pending transaction; determining whether to trigger the pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes the cache line to be updated corresponding to the pending transaction The pipeline write operation is performed by updating the cache line to be updated corresponding to the pending transaction; in response to determining that the pipeline write operation is triggered, the cache line to be updated corresponding to the pending transaction is matched with the risk queue, and the risk queue is used to record the cache line that has not been updated; in response to the cache line to be updated matching the cache line that has not been updated recorded by the risk queue, the pending transaction is marked as a retry request, and the pipeline write operation of the pending transaction is canceled; the retry request indicates that the pipeline read operation is performed again on the pending transaction; or, in response to the cache line to be updated not matching the cache line that has not been updated recorded by the risk queue, the pipeline write operation is performed on the pending transaction. The method stores the cache line that has not been updated in the risk queue. If the cache line to be updated corresponding to the pending transaction is in the risk queue, the pending transaction is marked as a retry request to prohibit the pending transaction from processing the cache line to be updated, and the pipeline read operation is performed again on the pending transaction to avoid overwriting data and reading out erroneous data, thereby ensuring cache consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0068] Figure 1A schematic diagram of a process flow of a method for pipeline-based request processing provided by an embodiment of the present application is shown;

[0069] Figure 2 A block diagram of a pipeline provided by an embodiment of the present application is shown;

[0070] Figure 3 A schematic diagram of a sub-process of a pipeline read operation provided by an embodiment of the present application is shown;

[0071] Figure 4 A schematic diagram showing another sub-process of a pipeline read operation provided by an embodiment of the present application is shown;

[0072] Figure 5 A schematic structural diagram of an electronic device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0073] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0074] To facilitate understanding, the technical terms and technical nouns involved in the embodiments of the present application are first explained.

[0075] In the organizational structure of cache, a set-associative cache is a cache structure in which the cache is divided into several sets, each set contains several cache lines, and these cache lines are called ways.

[0076] Tag is an important field in cache memory, which is used to identify the address in the main memory from which the data in the cache line comes. When the processor requests data, the cache controller uses the tag part of the address to determine whether the requested data is in the cache.

[0077] Snoop Filter is a hardware mechanism that records which data in each cache is shared by multiple processors. It is used in cache consistency protocols in multi-processor systems to reduce unnecessary snooping operations and improve system efficiency.

[0078] RRPV (Re-Reference Prediction Value) is an indicator used for cache replacement strategy, mainly used in cache management in computer architecture. RRPV determines which cache block should be replaced by predicting the possibility of the cache block being accessed again to optimize cache performance.

[0079] LRU (Least Recently Used) is a cache replacement strategy that determines the data blocks to be replaced when the cache is full. The LRU strategy selects the least recently used data blocks for replacement based on recent usage.

[0080] SRAM (Static Random Access Memory): is a type of semiconductor memory used to store data. In the embodiments of the present application, Tag SRAM, SF SRAM, LRU SRAM, and Data SRAM are involved. Tag SRAM, SF SRAM, LRU SRAM, and Data SRAM (L3 Cache) can be regarded as part of the storage space in SRAM. Data SRAM is used to store data, such as system data or user data. Tag SRAM is used to record tag information corresponding to the data stored in Data SRAM. SF SRAM is used to record the snoop filter information obtained by the snoop filter, and the snoop filter information includes the tag information of the cache line shared by multiple processor cores and the status of the data cached in each processor core. LRU SRAM is used to record the weight information of all groups in the group-connected cache structure, and the weight information is used to determine the data block to be replaced.

[0081] Figure 1 FIG. 1 is a flow chart of a method for processing requests based on pipeline provided in an embodiment of the present application. Figure 1 As shown, the method for pipeline-based request processing provided by the embodiment of the present application includes:

[0082] Step S101: in response to the receiving end of the pipeline receiving a pending transaction, arbitrating the pending transaction and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes a pipeline read operation and a pipeline write operation.

[0083] In an embodiment of the present application, the transactions received by the receiving end of the pipeline include two types: external requests and pipeline write operations. The external request is, for example, a request output by the Miss Status Handling Register (MSHR) (hereinafter referred to as an MSHR request), and the MSHR request may be a read request, a write request, or a cache maintenance operation request. The MSHR request includes address information to be accessed, and the address information to be accessed includes tag information, index information, and offset information.

[0084] The embodiment of the present application distributes the processing process of pending transactions to each beat of the pipeline. The pipeline includes two operations: pipeline read operation and pipeline write operation. Different pending transactions trigger different operations. For example, when the pending transaction is a request for the output of the missing state holding register, and there is currently no pending pipeline write operation, the pipeline read operation is triggered, and according to the operation result of the pipeline read operation and the relevant information of the pending transaction, it is determined whether to trigger the pipeline write operation. If the pending transaction is a pending pipeline write operation, the pipeline write operation is triggered.

[0085] Figure 2 FIG. 1 shows a block diagram of a pipeline provided by an embodiment of the present application. Figure 2 As shown in FIG. 1 , the pipeline includes 5 beats: Sx1, Sx2, Sx3, Sx4, and Sx5. Each beat represents a clock cycle. Figure 2 In the figure, MSHR represents the request output by the Miss Status Handling Register (MSHR), the black arrow represents the path of the pipeline read operation, and the red arrow represents the path of the pipeline write operation. If the pipeline read operation in the Sx5 stage determines that the pipeline write operation is triggered, the pipeline write operation is passed to the Sx1 stage; "empty beat" represents a pipeline bubble, which means that the input data is not processed in this beat and is directly passed to the next beat.

[0086] like Figure 2As shown, in the Sx1 stage, the transactions input to the pipeline include MSHR requests and / or pipeline write operations. If there are both MSHR requests and pipeline write operations, the pipeline write operation is executed first, and the MSHR request is saved by the MSHR register. If only an MSHR request exists, the pipeline read operation is triggered, and whether to trigger the pipeline write operation is determined based on the operation result of the pipeline read operation and the relevant information of the transaction to be processed. If only a pipeline write operation exists, the pipeline write operation is executed. In an optional embodiment, the logical operation executed in the Sx1 stage is implemented by a 2-to-1 arbiter, the MSHR request arbitration is successful, triggering the pipeline read operation, and the pipeline write operation arbitration is successful, and the pipeline write operation is executed.

[0087] Step S102: In response to determining to perform a pipeline read operation on the pending transaction, a pipeline read operation is performed on the pending transaction.

[0088] If the pending transaction is an MSHR request, a pipeline read operation is triggered to determine whether to trigger a pipeline write operation. The pipeline read operation reads information from one or more of the Tag SRAM, SF SRAM, LRU SRAM, and Data SRAM according to the relevant information of the pending transaction (such as address information, opcode (operation code) and input status). The operation process of the pipeline read operation refers to the processing logic of each beat of the pipeline below.

[0089] Step S103: Determine whether to trigger a pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes updating the cache line to be updated corresponding to the pending transaction.

[0090] Step S104: In response to determining that the pipeline write operation is triggered, the cache line to be updated corresponding to the pending transaction is matched with a risk queue, and the risk queue is used to record the cache line that has not been updated.

[0091] Step S105: in response to the cache line to be updated matching the cache line of the risk queue record that has not been updated, marking the pending transaction as a retry request, and canceling the pipeline write operation of the pending transaction; the retry request indicates re-performing the pipeline read operation on the pending transaction;

[0092] Step S106: In response to the cache line to be updated not matching the cache line of incomplete update recorded in the risk queue, a pipeline write operation is performed on the transaction to be processed.

[0093] Among them, if the cache line to be updated way corresponding to the pending transaction matches the unupdated way recorded in the risk queue, that is, the cache line to be updated corresponding to the pending transaction is the recorded unupdated cache line. In order to ensure cache consistency, in this case, the cache line to be updated corresponding to the pending transaction cannot be read or written, so the pending transaction is marked as a retry request, and the pipeline write operation of the pending transaction is canceled. Marking the pending transaction as a retry request indicates that the pending transaction needs to re-enter the pipeline and re-execute the pipeline read operation.

[0094] The method based on pipeline processing request provided by the embodiment of the present application, in response to the receiving end of the pipeline receiving the pending transaction, arbitrating the pending transaction, and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes pipeline read operation and pipeline write operation; in response to determining to perform a pipeline read operation on the pending transaction, executing the pipeline read operation on the pending transaction; determining whether to trigger the pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes the cache line to be updated corresponding to the pending transaction The pipeline write operation is performed by updating the cache line to be updated corresponding to the pending transaction; in response to determining that the pipeline write operation is triggered, the cache line to be updated corresponding to the pending transaction is matched with the risk queue, and the risk queue is used to record the cache line that has not been updated; in response to the cache line to be updated matching the cache line that has not been updated recorded by the risk queue, the pending transaction is marked as a retry request, and the pipeline write operation of the pending transaction is canceled; the retry request indicates that the pipeline read operation is performed again on the pending transaction; or, in response to the cache line to be updated not matching the cache line that has not been updated recorded by the risk queue, the pipeline write operation is performed on the pending transaction. The method stores the cache line that has not been updated in the risk queue. If the cache line to be updated corresponding to the pending transaction is in the risk queue, the pending transaction is marked as a retry request to prohibit the pending transaction from processing the cache line to be updated, and the pipeline read operation is performed again on the pending transaction to avoid overwriting data and reading out erroneous data, thereby ensuring cache consistency.

[0095] In an optional embodiment, the pipeline read operation and the pipeline write operation are read and written in the same beat. For example, the pipeline read operation includes one or more of reading Tag SRAM, reading SF SRAM, reading LRU SRAM, and reading Data SRAM. The pipeline write operation includes one or more of writing Tag SRAM, writing SF SRAM, writing LRU SRAM, and writing Data SRAM. The beat of executing write Tag SRAM, writing SF SRAM, and writing LRU SRAM is the same as the beat of executing read Tag SRAM, reading SF SRAM, and reading LRU SRAM; the beat of executing write Data SRAM is the same as the beat of executing read Data SRAM. Reference Figure 2 , read Tag SRAM, read SF SRAM, read LRU SRAM in the second beat (Sx2) of the pipeline, and read Data SRAM in the fifth beat (Sx5) of the pipeline. Also, write Tag SRAM, write SF SRAM, write LRU SRAM in the second beat (Sx2) of the pipeline, and write Data SRAM in the fifth beat (Sx5) of the pipeline.

[0096] refer to Figure 2 The pipeline shown explains the processing logic of each beat.

[0097] In the Sx1 stage (the first beat of the pipeline), transactions input to the pipeline include MSHR requests and / or pipeline write operations. If there are both MSHR requests and pipeline write operations, the pipeline write operation is executed first, and the MSHR request is saved by the MSHR register. If only an MSHR request exists, the pipeline read operation is triggered, and based on the operation result of the pipeline read operation and the relevant information of the transaction to be processed, it is determined whether to trigger the pipeline write operation. If only a pipeline write operation exists, the pipeline write operation is executed. In an optional embodiment, the logical operation performed in the Sx1 stage is implemented by a 2-to-1 arbiter. If the MSHR request arbitrates successfully, the pipeline read operation is triggered. If the pipeline write operation arbitrates successfully, the pipeline write operation is executed.

[0098] In the Sx2 stage (the second beat of the pipeline), the processing logic of the pipeline read operation is as follows Figure 3 As shown, including:

[0099] Step S301: Determine a target cache group according to the address information of the transaction to be processed. The address information of the transaction to be processed includes tag information (tag), index information (index), and offset information (offset). Determine the target cache group according to the index information (index).

[0100] Step S302: Read the first tag information of all valid cache lines of the target cache group from the Tag SRAM, where the Tag SRAM is used to record the tag information corresponding to the data stored in the L3 Cache. Optionally, all cache lines (ways) of the target cache group to be read in the Tag SRAM may be determined first, and valid cache lines (valid ways) may be screened out according to the status of each cache line (the status of a cache line includes valid and invalid), and then the tag information of all valid cache lines (valid ways) may be read, and the tag information of the valid cache lines (valid ways) read from the Tag SRAM may be used as the first tag information.

[0101] Step S303: Read the snoop filter information of all valid cache lines of the target cache group from the SF SRAM, the SF SRAM is used to record the snoop filter information obtained by the snoop filter, the snoop filter information includes second tag information, and the second tag information is the tag information of the cache line shared by multiple processor cores. Optionally, all cache lines (ways) of the target cache group to be read in the SF SRAM can be determined first, and valid cache lines (valid ways) can be screened out according to the status of each cache line (way), and then the tag information of all valid cache lines (valid ways) can be read, and the tag information of the valid cache lines (valid ways) read from the SF SRAM can be used as the second tag information.

[0102] Step S304: reading entries in the LRU SRAM, the entries including re-reference prediction values ​​of all cache lines of the target cache group.

[0103] Step S305: The first tag information, the second tag information and the entry in the LRU SRAM are used as the output information of the second beat, and output to the third beat of the pipeline.

[0104] In the Sx3 stage (the third beat of the pipeline), the processing logic of the pipeline read operation is as follows Figure 4 As shown, including:

[0105] Step S401: Determine whether the pending transaction hits the cache line in the Tag SRAM and the cache line in the SF SRAM according to the output information of the second beat and the tag information in the address information of the pending transaction. If so, the cache line hit by the pending transaction in the Tag SRAM is used as the first hit cache line, and the cache line hit by the pending transaction in the SF SRAM is used as the second hit cache line.

[0106] The output information of the second beat includes the first tag information, the second tag information and the entry in the LRU SRAM. The first tag information is matched with the tag information carried by the pending transaction to determine whether the pending transaction hits the first tag information. If so, it is determined that the pending transaction hits the cache line in the Tag SRAM (that is, it is determined that the pending transaction hits the cache line of the L3 Cache). If not, the pending transaction does not hit the cache line in the L3 Cache.

[0107] The second tag information is matched with the tag information carried by the pending transaction to determine whether the pending transaction hits the second tag information. If so, it is determined that the pending transaction hits the cache line in the SF SRAM; if not, it is determined that the pending transaction does not hit the cache line in the SF SRAM.

[0108] Step S402: in response to a pending transaction not hitting a cache line in the Tag SRAM, determining a free cache line in a target cache group in the Tag SRAM, and using the free cache line as a first free cache line.

[0109] For example, it can be determined whether there is a free cache line in the target cache group in the Tag SRAM; in response to the existence of a free cache line, the free cache line is used as the first free cache line; in response to the existence of multiple free cache lines, the free cache line with the smallest Way Number is used as the first free cache line;

[0110] Step S403: in response to the pending transaction not hitting a cache line in the SF SRAM, determining a free cache line in the target cache group in the SF SRAM, and using the free cache line as a first free cache line.

[0111] For example, it can be determined whether there is a free cache line in the target cache group in the SF SRAM; in response to the existence of a free cache line, a free cache line is used as the second free cache line; in response to the existence of multiple free cache lines, the free cache line with the smallest Way Number is used as the second free cache line.

[0112] Step S404: Determine the cache line to be replaced according to the entry in the LRU SRAM output by the second beat. The entry in the LRU SRAM output by the second beat includes a re-reference prediction value, and the cache line to be replaced is determined according to the cache replacement strategy and the re-reference prediction value. The cache replacement strategy may be, for example, LRU (Least Recently Used).

[0113] Step S405: The tag information and re-reference prediction value of the first hit cache line, the tag information and re-reference prediction value of the second hit cache line, the tag information and re-reference prediction value of the first free cache line, the tag information and re-reference prediction value of the second free cache line, and the tag information and re-reference prediction value of the cache line to be replaced are output as the output information of the third beat to the fourth beat of the pipeline.

[0114] In the Sx4 stage (the fourth beat of the pipeline), the processing logic of the pipeline read operation includes: determining the cache line to be updated and performing internal state machine judgment based on the result output of the third beat and the address information of the transaction to be processed; outputting the cache line to be updated and the judgment result of the internal state machine to the fifth beat of the pipeline.

[0115] Optionally, the rule for determining the cache line to be updated may be: if there is a hit way, then the hit way is selected; if there is no hit way but there is an idle way, then the idle way is selected; if there is no hit way and no idle way, then the replacement way is selected. Specifically, the cache line to be updated may be determined according to the following process:

[0116] In response to receiving the tag information of the first hit cache line, taking the first hit cache line as the first cache line to be updated; or,

[0117] In response to not receiving tag information of the first hit cache line and receiving tag information of the first free cache line, using the first free cache line as the first cache line to be updated; or,

[0118] In response to not receiving the tag information of the first hit cache line and the tag information of the first free cache line, taking the cache line to be replaced as the first cache line to be updated;

[0119] In response to receiving the tag information of the second hit cache line, taking the second hit cache line as the second cache line to be updated; or,

[0120] In response to not receiving the tag information of the second hit cache line and receiving the tag information of the second free cache line, the second free cache line is used as the second cache line to be updated.

[0121] After determining the first cache line to be updated and the second cache line to be updated, determine whether to update the re-reference prediction value of the first cache line to be updated and the re-reference prediction value of the second cache line to be updated. If so, determine the update value of the re-reference prediction value of the first cache line to be updated and the update value of the re-reference prediction value of the second cache line to be updated.

[0122] Among them, 1) if the first cache line to be updated is the first hit cache line (ie, L3 Cache hit), it is determined to update the re-reference prediction value of the first hit cache line, and the update value of the re-reference prediction value of the first hit cache line is 0, and other values ​​remain unchanged.

[0123] 2) If the first cache line to be updated is the first free cache line, and it is determined that L3 needs to be written according to the operation code (opcode) and input status (mshr_l3_fill_sx1_q) of the transaction to be processed (that is, L3Cache misses, there is a free way, and L3 Cache needs to be written), then it is determined to update the re-reference prediction value of the first free cache line, and the update value of the re-reference prediction value of the first hit cache line is 2, and other values ​​remain unchanged.

[0124] 3) If the first cache line to be updated is the cache line to be replaced, and it is determined that the L3 Cache needs to be written according to the operation code (opcode) and input status (mshr_l3_fill_sx1_q) of the transaction to be processed (that is, the L3 Cache misses and there is no free way and the L3 Cache needs to be written), then the re-reference prediction value of the cache line to be replaced is updated, and the update value of the re-reference prediction value is 2.

[0125] Except for the above three cases, the re-reference prediction value of the cache line to be updated will not be updated.

[0126] After determining the update values ​​of the first cache line to be updated, the second cache line to be updated, and the re-reference prediction value, an internal state machine judgment is performed based on the tag information of the first cache line to be updated, the tag information of the second cache line to be updated, and relevant information of the transaction to be processed, such as the operation code (opcode), input status (mshr_l3_fill_sx1_q), etc.

[0127] Optionally, the internal state machine can be used to determine and output the following: whether to read Data SRAM, whether to write Data SRAM, whether to trigger a pipeline write operation, whether the data in Tag SRAM, SF SRAM or LRU SRAM needs to be updated, output data used to update Tag SRAM, SF SRAM or LRU SRAM, relevant feedback information of pending transactions, etc.

[0128] As an optional example, the internal state machine can make judgments and output relevant content according to the following process:

[0129] Whether pipeline write operation is required: When the pending transaction belongs to a cache maintenance operation request and both L3 Cache and SF SRAM miss, pipeline write operation is not required; otherwise, write operation is required.

[0130] Whether to read Data SRAM: If the pending transaction is a read request and the pending transaction hits the cache line of L3Cache (that is, the pending transaction hits the cache line in Tag SRAM), then the Data SRAM needs to be read.

[0131] Whether Data SRAM needs to be written: If the pending transaction is a write request, Data SRAM needs to be written.

[0132] The data written into the Data SRAM is input by an external module, and the pipeline only gives a write signal.

[0133] Whether Tag SRAM needs to be written: If the pending transaction is a write request, Tag SRAM needs to be written.

[0134] Data written to Tag SRAM: The tag information carried by the address information of the transaction to be processed is written into the first cache line to be updated selected in the Sx4 stage, and updated into the Tag SRAM.

[0135] Whether to write to SF SRAM: If the pending transaction is a read request, it needs to be written to SF SRAM.

[0136] Data written into SF SRAM: The tag information carried by the address information of the transaction to be processed is written into the second cache line to be updated selected in the Sx4 stage, and updated into the SF SRAM.

[0137] Whether to write to LRU SRAM: If the pending transaction is a write request or an L3 Cache hit, it needs to be written to LRUSRAM.

[0138] Data written to the LRU SRAM: the updated value of the re-reference prediction value obtained by the pipeline read operation in the fourth beat.

[0139] In the Sx5 stage (the fifth beat of the pipeline), the processing logic of the pipeline read operation includes:

[0140] Matching the cache line to be updated corresponding to the pending transaction with the risk queue; in response to the cache line to be updated corresponding to the pending transaction matching the cache line of incomplete update recorded by the risk queue, marking the pending transaction as a retry request, and determining not to perform a pipeline write operation on the pending transaction; or, in response to the cache line to be updated corresponding to the pending transaction not matching the cache line of incomplete update recorded by the risk queue, passing the pipeline write operation as a pending transaction to the receiving end of the pipeline, and writing the tag information of the cache line to be updated into the risk queue;

[0141] And, in response to the cache line to be updated being a cache line to be replaced and a replacement queue being full, marking the pending transaction as a retry request and determining not to perform a pipeline write operation on the pending transaction, the replacement queue being used to store tag information of the replaced cache line.

[0142] In the Sx5 stage, it is determined again whether the pipeline write operation needs to be triggered and whether the pending transaction needs to be marked as a retry request. The retry request indicates that the pending transaction has failed and needs to be retried again.

[0143] Optionally, whether to mark a pending transaction as a retry request may be determined according to the following process:

[0144] (1) Match the cache line to be updated corresponding to the pending transaction with the risk queue;

[0145] If the match is successful, the pending transaction is marked as a retry request, and it is determined not to perform a pipeline write operation on the pending transaction, and the pending transaction is transferred to the receiving end of the pipeline for reprocessing;

[0146] If the match is unsuccessful, the pipeline write operation is passed to the receiving end of the pipeline as a pending transaction, and the tag information of the cache line to be updated is written into the risk queue.

[0147] The cache line to be updated outputted in the fourth beat includes the first cache line to be updated and / or the second cache line to be updated. In the fifth beat, the first cache line to be updated is outputted in response to the fourth beat, and the first cache line to be updated is matched with the cache line of incomplete update recorded in the first risk queue; the second cache line to be updated is outputted in response to the fourth beat, and the second cache line to be updated is matched with the cache line of incomplete update recorded in the second risk queue.

[0148] (2) In response to the cache line to be updated being the cache line to be replaced and the replacement queue BIQ being full, the pending transaction is marked as a retry request, and it is determined not to perform a pipeline write operation on the pending transaction. The replacement queue (Back Invalid Queue, BIQ for short) is used to store tag information of the replaced cache line.

[0149] In an optional embodiment, if a pipeline read operation is performed, in the fourth beat of the pipeline, in response to the pending transaction not hitting the cache line in the Tag SRAM, and the pending transaction not hitting the cache line in the SF SRAM (in the third beat, it is determined whether the pending transaction hits the cache line in the Tag SRAM and the cache line in the SF SRAM), an AddrBuffer query is initiated. In the fifth beat of the pipeline, the result of the Addr Buffer query is received, and it is determined whether to mark the pending transaction as a retry request based on the result of the Addr Buffer query. For example, the result of the Addr Buffer query is that mshr_l3_hazard_valid_sx3_q shows a high level, indicating that an address conflict occurs in the current pending transaction, and the pending transaction needs to be marked as a retry request, and a pipeline write operation is not initiated for the pending transaction.

[0150] In an optional embodiment, if a pipeline read operation is performed, the following process is also performed in the fifth beat of the pipeline:

[0151] In response to the fourth beat output that the second cache line to be updated is not the second hit cache line, and the tag information in the address information of the transaction to be processed exists in the replacement queue, the transaction feedback information is output, and it is determined not to perform a pipeline write operation on the transaction to be processed. The transaction feedback information includes broadcast information of the transaction to be processed, and the broadcast information is used to indicate that data corresponding to the address information of the transaction to be processed is obtained from the processor core.

[0152] If it is determined in the fifth beat that a pipeline write operation needs to be initiated, the pipeline write operation is passed to the receiving end of the pipeline as a pending transaction, and the relevant write data, such as data written to the Tag SRAM, SF SRAM, LRU SRAM or Data SRAM, is passed to the receiving end of the pipeline as the data carried by the pending transaction.

[0153] In the Sx2 stage (the second beat of the pipeline), according to the data carried by the pipeline write operation, it is determined that the Tag SRAM, SF SRAM or LRU SRAM needs to be written, then the tag information of the cache line to be updated in the Tag SRAM and SF SRAM is updated, and the re-reference prediction value of the cache line to be updated in the LRU SRAM is updated. In this stage, the operation of writing to the Data SRAM is not performed, and the operation of writing to the Data SRAM is performed in the Sx5 stage.

[0154] In the Sx3 stage (the third beat of the pipeline), the output information of the Sx3 stage is transmitted to the Sx4 stage.

[0155] In the Sx4 stage (the fourth beat of the pipeline), the output information of the Sx4 stage is transmitted to the Sx5 stage.

[0156] In the Sx5 stage (the fifth beat of the pipeline), based on the data carried by the pipeline write operation, it is determined that the Data SRAM needs to be written, and the Data SRAM is written.

[0157] Since the single-port design makes it impossible to read and write the L3 Cache at the same time, in order to operate on a certain SRAM, a pipeline bubble is added in the pipeline write operation to avoid competitive operations on the SRAM, so that there is only one pending transaction that has been successfully arbitrated from the Sx1 stage per clock cycle, and the initiation time of the read and write operations on the SRAM is the same relative to Sx1, so different pending transactions will not have competitive operations on the SRAM. Among them, the pipeline means that all operations on the cache are divided into one beat and completed in a beat. The pipeline provided in the embodiment of the present application is divided into 5 beats, but in the pipeline write operation, not every beat has to do something, it may just beat a beat but do nothing (such as the 2nd and 3rd beats), this behavior is called a pipeline bubble.

[0158] The method based on pipeline processing request provided by the embodiment of the present application stores the cache lines that have not been updated in the risk queue. If the cache line to be updated corresponding to the pending transaction is in the risk queue, the pending transaction is marked as a retry request to prohibit the pending transaction from processing the cache line to be updated, and the pipeline read operation is re-performed on the pending transaction to avoid overwriting data and reading erroneous data, thereby ensuring cache consistency. The method adopts a five-level pipeline to ensure that no blocking behavior occurs in the operation of the entire L3 Cache. At the same time, the processing process of the pending transaction, such as transaction arbitration behavior, address translation behavior, tag comparison behavior, data reading and writing behavior, and response behavior, is reasonably divided into 5 beats of the entire pipeline, and the performance of the critical path is perfectly optimized.

[0159] In a single-port L3 cache, the L3 cache cannot be read and written at the same time due to the single-port design. Figure 2 The pipeline shown in the figure has a state update delay (in Figure 2 In the embodiment shown, the delay is 5 beats), different transactions, such as different requests for the same cache line (way), may cause cache line update conflicts and cache consistency issues. For example, request 1 and request 2 access the same cache line (way), and request 1 enters the pipeline before request 2, which may cause the following two conflicts:

[0160] (1) The evict mechanism makes the replaced way unreliable: The evict mechanism of the L3 Cache makes a cache line correspond to different physical addresses and data before and after the update. Conflicts caused by operations on the same cache line may cause data loss or unreliable data.

[0161] For example, request 1 needs to write data in cache line 1. In the read phase corresponding to request 1, the L3 Cache is not hit, and there is no free cache line (way) in the L3 Cache. Therefore, the data cached in the L3 Cache needs to be replaced, for example, the designated cache line (way) to be replaced is determined according to the cache replacement policy. In the write phase of request 1, the data corresponding to request 1 is written to the designated cache line (way). Assuming that request 2 needs to use the designated cache line (way), if request 2 is a read request, the data of the designated cache line (way) needs to be read. If request 2 is a write request, the data needs to be written to the designated cache line (way). However, when processing request 1, the data of the designated cache line (way) is replaced. If request 2 is a read request, the data read by request 2 is the data written by request 1, not the original data. If request 2 is a write request, the data written by request 2 will overwrite the data written by request 1, resulting in the loss of the data written by request 1.

[0162] (2) Repeated writing to the same cache line (way) causes data loss.

[0163] For example, request 1 and request 2 need to write data to L3 Cache. In the read phase corresponding to request 1, L3 Cache is not hit, and there is a free cache line (way) in L3 Cache, and the free cache line with the smallest way number is selected as the cache line to be written. In the read phase corresponding to request 2, L3 Cache is not hit, and there is a free cache line (way) in L3 Cache, and the free cache line with the smallest way number is selected as the cache line to be written. However, when request 2 selects the free cache line with the smallest waynumber, request 1 has not yet completed the update of the free cache line, resulting in the cache line to be written selected by request 2 being the same as the cache line to be written selected by request 1. In the write phase of request 1, request 1 writes data to the cache line to be written, and in the write phase of request 2, request 2 also writes data to the cache line to be written. The data corresponding to request 2 overwrites the data corresponding to request 1, resulting in data loss of request 1.

[0164] To resolve the above-mentioned conflict, an embodiment of the present application provides a risk queue, and writes the cache lines that have not been updated into the risk queue. When operating the cache line to be updated, the cache line to be updated is matched with the cache lines that have not been updated in the risk queue. If the match is successful, the operation on the cache line to be updated is prohibited, the pending transaction is marked as a retry request, and the pending transaction is re-entered into the pipeline for processing, thereby avoiding cache inconsistency problems.

[0165] The embodiment of the present application avoids the above two conflicts through risk queues:

[0166] (1) Request 1 needs to write data in cache line 1. In the read phase corresponding to request 1, the L3 Cache is not hit, and there is no free cache line (way) in the L3 Cache. Therefore, the data cached in the L3 Cache needs to be replaced, for example, the designated cache line (way) to be replaced is determined according to the cache replacement policy. When request 1 comes to the sx5 stage to perform the pipeline read operation, because it needs to update the Tag SRAM, the tag information in the address information of request 1 is written into the first risk queue, and the pipeline write operation begins. Request 2 needs to use the designated cache line to be replaced. The result of the read phase sx3 is that the L3 Cache is hit and the designated cache line is hit. When request 2 reaches the Sx5 stage and determines that the designated cache line is successfully matched with the first risk queue, request 2 is marked as a retry request, and the read or write of request 2 to the designated cache line is cancelled, thus avoiding the problem of data loss or data unreliability.

[0167] (2) Repeated writing to the same cache line (way) causes data loss.

[0168] For example, request 1 and request 2 need to write data to L3 Cache. In the read phase corresponding to request 1, L3 Cache is not hit, and there is an idle cache line (way) in L3 Cache. The idle cache line with the smallest way number is selected as the cache line to be written. When request 1 comes to the sx5 stage to perform a pipeline read operation, because it needs to update the Tag SRAM, the tag information in the address information of request 1 is written to the first risk queue, and the pipeline write operation begins. In the read phase corresponding to request 2, L3 Cache is not hit, and there is an idle cache line (way) in L3 Cache. The idle cache line with the smallest way number is selected as the cache line to be updated. When request 2 reaches the Sx5 stage and determines that the specified cache line is successfully matched with the first risk queue, request 2 is marked as a retry request, and the reading or writing of the specified cache line by request 2 is cancelled, thus avoiding the problem of data loss or unreliable data.

[0169] Figure 5FIG. 1 is a schematic diagram showing the structure of an electronic device according to an embodiment of the present invention. Figure 5 As shown, the electronic device includes:

[0170] Processor 501, communication interface 502, memory 503 and communication bus 504, wherein the processor 501, communication interface 502, memory 503 communicate with each other via the communication bus 504.

[0171] Memory 503, used for storing computer programs;

[0172] The processor 501 is used to execute the program stored in the memory 503, and implements the following steps:

[0173] In response to the receiving end of the pipeline receiving a pending transaction, arbitrating the pending transaction and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes a pipeline read operation and a pipeline write operation;

[0174] In response to determining to perform a pipeline read operation on the pending transaction, performing a pipeline read operation on the pending transaction;

[0175] Determine whether to trigger a pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes updating the cache line to be updated corresponding to the pending transaction;

[0176] In response to determining that a pipeline write operation is triggered, matching the cache line to be updated corresponding to the pending transaction with a risk queue, the risk queue being used to record the cache line for which the update is not completed;

[0177] In response to the cache line to be updated matching the cache line of incomplete update recorded by the risk queue, the pending transaction is identified as a retry request, and the pipeline write operation on the pending transaction is canceled; the retry request indicates re-performing a pipeline read operation on the pending transaction; or, in response to the cache line to be updated not matching the cache line of incomplete update recorded by the risk queue, a pipeline write operation is performed on the pending transaction.

[0178] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0179] The communication interface is used for communication between the above terminal and other devices.

[0180] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0181] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0182] In another embodiment of the present invention, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is executed on a computer, the computer executes the method based on pipeline processing request described in any of the above embodiments.

[0183] In another embodiment provided by the present invention, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the method for processing requests based on a pipeline as described in any one of the above embodiments.

[0184] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0185] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0186] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0187] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for processing requests based on pipeline, characterized in that: The method comprises: In response to the receiving end of the pipeline receiving a pending transaction, arbitrating the pending transaction and determining the type of pipeline operation to be performed on the pending transaction; wherein the type of pipeline operation includes a pipeline read operation and a pipeline write operation; In response to determining to perform a pipeline read operation on the pending transaction, performing a pipeline read operation on the pending transaction; Determine whether to trigger a pipeline write operation according to the operation result of the pipeline read operation; the operation result of the pipeline read operation at least includes the cache line to be updated corresponding to the pending transaction, and the pipeline write operation at least includes updating the cache line to be updated corresponding to the pending transaction; In response to determining that a pipeline write operation is triggered, matching the cache line to be updated corresponding to the pending transaction with a risk queue, the risk queue being used to record the cache line for which the update is not completed; In response to the cache line to be updated matching the cache line of the unfinished update recorded by the risk queue, marking the pending transaction as a retry request and canceling the pipeline write operation on the pending transaction; the retry request indicates re-performing a pipeline read operation on the pending transaction; or, in response to the cache line to be updated not matching the cache line of the unfinished update recorded by the risk queue, performing a pipeline write operation on the pending transaction; The pipeline includes five beats; in response to receiving a pending transaction at a receiving end of the pipeline, arbitrating the pending transaction in the first beat of the pipeline to determine the type of pipeline operation to be performed on the pending transaction; The pipeline read operation includes one or more of reading Tag SRAM, reading SF SRAM, reading LRU SRAM, and reading Data SRAM; the pipeline write operation includes one or more of writing Tag SRAM, writing SF SRAM, writing LRU SRAM, and writing Data SRAM; The beats of writing Tag SRAM, writing SF SRAM, and writing LRU SRAM are the same as the beats of reading Tag SRAM, reading SF SRAM, and reading LRUSRAM; The beat for writing to Data SRAM is the same as the beat for reading from Data SRAM.

2. The method according to claim 1, characterized in that The method further comprises: The pipeline read operation and the pipeline write operation are read and written in the same beat.

3. The method according to claim 1, characterized in that Arbitrating the pending transaction and determining the type of pipeline operation to be performed on the pending transaction includes: If the pending transaction is a request for missing state holding register output, and there is no pipeline write operation to be processed currently, determining to perform a pipeline read operation on the pending transaction; If the transaction to be processed is a pipeline write operation to be processed, determine to perform a pipeline write operation on the transaction to be processed.

4. The method according to claim 1, characterized in that The method further comprises: Reading Tag SRAM, SF SRAM and LRU SRAM is performed in the second beat of the pipeline, and reading Data SRAM is performed in the fifth beat of the pipeline; Furthermore, writing to Tag SRAM, writing to SF SRAM, and writing to LRU SRAM are performed in the second beat of the pipeline, and writing to Data SRAM is performed in the fifth beat of the pipeline.

5. The method according to claim 4, characterized in that In the second beat of the pipeline, the method includes: If a pipeline read operation is performed, a target cache group is determined according to the address information of the transaction to be processed; Reading first tag information of all valid cache lines of the target cache group from the Tag SRAM, wherein the Tag SRAM is used to record tag information corresponding to data stored in the L3 Cache; Reading snoop filter information of all valid cache lines of the target cache group from the SF SRAM, wherein the SF SRAM is used to record the snoop filter information acquired by the snoop filter, wherein the snoop filter information includes second tag information, and the second tag information is tag information of cache lines shared by multiple processor cores; Reading an entry in the LRU SRAM, the entry including re-reference prediction values ​​of all cache lines of the target cache group; Outputting the first tag information, the second tag information and the entry in the LRU SRAM as output information of the second beat to the third beat of the pipeline; If a pipeline write operation is performed, the tag information of the cache line to be updated in the Tag SRAM and the SF SRAM is updated, and the re-reference prediction value of the cache line to be updated in the LRU SRAM is updated.

6. The method according to claim 5, characterized in that In the third beat of the pipeline, the method includes: If a pipeline read operation is performed, determining whether the transaction to be processed hits the cache line in the Tag SRAM and the cache line in the SF SRAM according to the output information of the second beat and the tag information in the address information of the transaction to be processed; In response to the pending transaction not hitting a cache line in the Tag SRAM, determining a free cache line of a target cache group in the Tag SRAM; In response to the pending transaction missing a cache line in the SF SRAM, determining a free cache line of a target cache group in the SF SRAM; Determine the cache line to be replaced according to the entry in the LRU SRAM outputted in the second beat; The cache line hit by the pending transaction in the Tag SRAM is used as the first hit cache line, the cache line hit by the pending transaction in the SF SRAM is used as the second hit cache line, the free cache line of the target cache group in the Tag SRAM is used as the first free cache line, and the free cache line of the target cache group in the SF SRAM is used as the second free cache line; the tag information and re-reference prediction value of the first hit cache line, the tag information and re-reference prediction value of the second hit cache line, the tag information and re-reference prediction value of the first free cache line, the tag information and re-reference prediction value of the second free cache line, and the tag information and re-reference prediction value of the cache line to be replaced are used as output information of the third beat, and output to the fourth beat of the pipeline; If a pipeline write operation is performed, in the third beat of the pipeline, the output information of the second beat is transferred to the fourth beat.

7. The method according to claim 6, characterized in that Determining, according to the output information of the second beat and the tag information in the address information of the transaction to be processed, a cache line hit by the transaction to be processed in the Tag SRAM and a cache line hit by the transaction to be processed in the SF SRAM, including: Matching the first tag information with the tag information in the address information of the pending transaction to determine whether the pending transaction hits the first tag information; if so, determining the cache line hit by the pending transaction in the Tag SRAM; The second tag information is matched with the tag information in the address information of the pending transaction to determine whether the pending transaction hits the second tag information; if so, a cache line hit by the pending transaction in the SF SRAM is determined.

8. The method according to claim 7, characterized in that The method of using the free cache line of the target cache group in the Tag SRAM as the first free cache line and the free cache line of the target cache group in the SF SRAM as the second free cache line includes: Determine whether there is a free cache line in the target cache group in the Tag SRAM; in response to the existence of a free cache line, use the free cache line as a first free cache line; in response to the existence of multiple free cache lines, use the free cache line with the smallest Way Number as the first free cache line; Determine whether there is a free cache line in the target cache group in the SF SRAM; in response to the existence of one free cache line, use the one free cache line as the second free cache line; in response to the existence of multiple free cache lines, use the free cache line with the smallest Way Number as the second free cache line.

9. The method according to claim 4, characterized in that In the fourth beat of the pipeline, the method includes: If a pipeline read operation is performed, the cache line to be updated is determined and an internal state machine judgment is performed according to the result outputted in the third beat and the address information of the transaction to be processed; the cache line to be updated and the judgment result of the internal state machine are outputted to the fifth beat of the pipeline; the internal state machine judgment is used to determine whether to read Data SRAM, whether to write Data SRAM, and whether to trigger one or more of the pipeline write operations; If a pipeline write operation is performed, in the fourth beat of the pipeline, the output information of the third beat is transferred to the fifth beat.

10. The method according to claim 9, characterized in that In the fifth beat of the pipeline, the method includes: If a pipeline read operation is performed, the cache line to be updated corresponding to the pending transaction is matched with the risk queue; in response to the cache line to be updated corresponding to the pending transaction matching the cache line of incomplete update recorded by the risk queue, the pending transaction is marked as a retry request, and it is determined not to perform a pipeline write operation on the pending transaction; or, in response to the cache line to be updated corresponding to the pending transaction not matching the cache line of incomplete update recorded by the risk queue, the pipeline write operation is passed as a pending transaction to the receiving end of the pipeline, and the tag information of the cache line to be updated is written into the risk queue; and, in response to the cache line to be updated being a cache line to be replaced and a replacement queue being full, marking the pending transaction as a retry request and determining not to perform a pipeline write operation on the pending transaction, the replacement queue being used to store tag information of the replaced cache line; If the pipeline write operation is performed, in the fifth beat of the pipeline, in response to determining to write to the Data SRAM, the writing to the Data SRAM is performed.

11. The method according to claim 6, characterized in that According to the result of the third beat output and the address information of the transaction to be processed, the cache line to be updated is determined and the internal state machine is judged, including: In response to receiving the tag information of the first hit cache line, taking the first hit cache line as a first cache line to be updated; or, In response to not receiving the tag information of the first hit cache line and receiving the tag information of the first free cache line, using the first free cache line as the first cache line to be updated; or, In response to not receiving the tag information of the first hit cache line and the tag information of the first free cache line, taking the cache line to be replaced as a first cache line to be updated; In response to receiving the tag information of the second hit cache line, taking the second hit cache line as a second cache line to be updated; or, In response to not receiving the tag information of the second hit cache line and receiving the tag information of the second free cache line, using the second free cache line as a second cache line to be updated; Determine whether to update the re-reference prediction value of the first cache line to be updated and the re-reference prediction value of the second cache line to be updated; If so, determining an update value of the re-reference prediction value of the first cache line to be updated and an update value of the re-reference prediction value of the second cache line to be updated; An internal state machine judgment is performed according to the transaction to be processed, the tag information of the first cache line to be updated, and the tag information of the second cache line to be updated.

12. The method according to claim 11, characterized in that Matching the cache line to be updated corresponding to the pending transaction with the risk queue includes: In response to the fourth beat outputting the first cache line to be updated, matching the first cache line to be updated with the cache line whose update has not been completed recorded in the first risk queue; or, In response to the fourth beat, a second cache line to be updated is output, and the second cache line to be updated is matched with the cache line whose update is not completed and recorded in the second risk queue.

13. The method according to claim 11 or 12, characterized in that: In the fourth beat of the pipeline, the method further includes: if a pipeline read operation is performed, in response to the pending transaction not hitting the cache line in the Tag SRAM and the pending transaction not hitting the cache line in the SF SRAM, initiating an Addr Buffer query.

14. The method according to claim 13, characterized in that In the fifth beat of the pipeline, the method further includes: if a pipeline read operation is performed, determining to mark the pending transaction as a retry request based on the result of the Addr Buffer query, and determining not to perform a pipeline write operation on the pending transaction.

15. The method according to claim 10, characterized in that In the fifth beat of the pipeline, the method further includes: If a pipeline read operation is performed, a second cache line to be updated is output in response to the fourth beat, the second cache line to be updated is not the second hit cache line, and the tag information in the address information of the transaction to be processed exists in the replacement queue, transaction feedback information is output, and it is determined not to perform a pipeline write operation on the transaction to be processed, the transaction feedback information includes broadcast information of the transaction to be processed, and the broadcast information is used to indicate that data corresponding to the address information of the transaction to be processed is obtained from the processor core.

16. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, configured to implement the method according to any one of claims 1 to 15 when executing a program stored in a memory.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 15 is implemented.

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