Method, apparatus, storage medium, and program product for video encoding

Abstract

Methods, apparatuses, storage media, and program products for video encoding are provided. In one method, a decoder determines a codec bit depth of at least one sample in a bitstream; the decoder determines a value of a first sequence parameter set (SPS) flag for the at least one sample; and the decoder further determines a second SPS flag for the at least one sample based on the value of the first SPS flag and the codec bit depth of the at least one sample.

Description

[0001] This application is a divisional application of the invention patent application with application number 202280048756.6, priority date July 9, 2021, application date July 8, 2022, and invention name “Residual and coefficient encoding and decoding for video encoding and decoding”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application is based upon and claims priority from provisional application No. 63 / 220,380, filed on July 9, 2021, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0004] The present disclosure relates to video coding and compression. More particularly, the present disclosure relates to improvements and simplifications of residual and coefficient coding for video coding. Background Art

[0005] Various video coding and decoding technologies can be used to compress video data. Video coding and decoding is performed according to one or more video coding and decoding standards. For example, video coding and decoding standards include Versatile Video Codec (VVC), Joint Exploration Test Model (JEM), High Efficiency Video Codec (H.265 / HEVC), Advanced Video Codec (H.264 / AVC), Moving Picture Experts Group (MPEG) codec, etc. Video coding and decoding are usually performed using prediction methods (e.g., inter-frame prediction, intra-frame prediction, etc.) that utilize the redundancy present in video images or sequences. An important goal of video coding and decoding technology is to compress video data into a form that uses a lower bit rate while avoiding or minimizing video quality degradation. Summary of the Invention

[0006] Examples of the present disclosure provide methods and apparatus for video encoding and decoding.

[0007] According to the present disclosure, a method for video decoding is provided. The method may include: determining, by a decoder, a codec bit depth of at least one sample in a bitstream; determining, by the decoder, a value of a first SPS flag of the at least one sample; and determining, by the decoder, a second SPS flag of the at least one sample based on the value of the first SPS flag and the codec bit depth of the at least one sample.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate examples consistent with the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] Figure 1 is a block diagram of an encoder according to an example of the present disclosure.

[0011] Figure 2 is a block diagram of a decoder according to an example of the present disclosure.

[0012] Figure 3A is a diagram illustrating block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0013] Figure 3B is a diagram illustrating block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0014] Figure 3C is a diagram illustrating block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0015] Figure 3D is a diagram illustrating block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0016] Figure 3E is a diagram illustrating block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0017] Figure 4 is a diagram of a residual coding structure for a transform block according to an example of the present disclosure.

[0018] Figure 5 is a diagram of a residual codec structure for transforming skip blocks according to an example of the present disclosure.

[0019] Figure 6 A method for encoding a video signal according to an example of the present disclosure is provided.

[0020] Figure 7 A method for encoding a video signal according to an example of the present disclosure is provided.

[0021] Figure 8 is a diagram illustrating a computing environment coupled with a user interface according to examples of the present disclosure.

[0022] Figure 9 A method for video encoding and decoding according to an example of the present disclosure is illustrated.

[0023] Figure 10 A method for video encoding and decoding according to an example of the present disclosure is illustrated.

[0024] Figure 11A method for video encoding and decoding according to an example of the present disclosure is illustrated.

[0025] Figure 12 A method for video encoding and decoding according to an example of the present disclosure is illustrated.

[0026] Figure 13 is a block diagram illustrating an exemplary system for encoding and decoding video blocks according to examples of the present disclosure.

[0027] Figure 14 is a block diagram illustrating an exemplary video encoder according to examples of the present disclosure.

[0028] Figure 15 is a block diagram illustrating an exemplary video decoder according to examples of the present disclosure.

[0029] Figure 16 A low-latency transform skip residual coding (TSRC) method according to examples of the present disclosure is illustrated.

[0030] Figure 17 A method for video decoding according to an example of the present disclosure is illustrated.

[0031] Figure 18 A method for video decoding according to an example of the present disclosure is illustrated.

[0032] Figure 19 A method for video decoding according to an example of the present disclosure is illustrated.

[0033] Figure 20 A method for video decoding according to an example of the present disclosure is illustrated.

[0034] Figure 21 A method for video decoding according to an example of the present disclosure is illustrated.

[0035] Figure 22 A method for video decoding according to an example of the present disclosure is illustrated. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like reference numerals in different figures represent like or similar elements unless otherwise specified. The embodiments set forth in the following description of exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects related to the present disclosure recited in the appended claims.

[0037] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein is intended to mean and include any and all possible combinations of one or more of the associated listed items.

[0038] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, such information should not be limited by these terms. These terms are merely used to distinguish one type of information from another type of information. For example, without departing from the scope of this disclosure, first information may be referred to as second information; and similarly, second information may be referred to as first information. As used herein, the term "if" may be understood to mean "when," "at," or "in response to a determination," depending on the context.

[0039] Figure 1 An overall diagram of a block-based video encoder for VVC is shown. Specifically, Figure 1 A typical encoder 100 is shown. The encoder 100 has a video input 110, motion compensation 112, motion estimation 114, intra / inter mode decision 116, block prediction value 140, adder 128, transform 130, quantization 132, prediction related information 142, intra prediction 118, picture buffer 120, inverse quantization 134, inverse transform 136, adder 126, memory 124, loop filter 122, entropy coding 138, and a bitstream 144.

[0040] In encoder 100, a video frame is partitioned into multiple video blocks for processing. For each given video block, a prediction is formed based on either an inter-frame prediction method or an intra-frame prediction method.

[0041] The prediction residual representing the difference between the current video block (part of the video input 110) and its prediction value (part of the block prediction value 140) is sent from the adder 128 to the transform 130. The transform coefficients are then sent from the transform 130 to the quantization 132 for entropy reduction. The quantized coefficients are then fed to the entropy coding 138 to generate the compressed video bitstream. Figure 1 As shown, prediction related information 142 from the intra / inter mode decision 116 (such as video block partition information, motion vectors (MVs), reference picture indices, and intra prediction modes) is also fed through entropy coding 138 and saved into a compressed bitstream 144. The compressed bitstream 144 comprises a video bitstream.

[0042] In the encoder 100, decoder-related circuitry is also required to reconstruct pixels for prediction purposes. First, a prediction residual is reconstructed through inverse quantization 134 and inverse transformation 136. The reconstructed prediction residual is combined with the block prediction value 140 to generate the unfiltered reconstructed pixels of the current video block.

[0043] Spatial prediction (or "intra-frame prediction") uses pixels from samples of already coded neighboring blocks (called reference samples) in the same video frame as the current video block to predict the current video block.

[0044] Temporal prediction (also known as "inter prediction") uses reconstructed pixels from already coded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in video signals. The temporal prediction signal for a given coding unit (CU) or coding block is typically signaled as one or more MVs that indicate the amount and direction of motion between the current CU and its temporal reference. Furthermore, if multiple reference pictures are supported, a reference picture index is additionally sent, which identifies which reference picture in the reference picture store the temporal prediction signal comes from.

[0045] Motion estimation 114 takes the video input 110 and the signal from the picture buffer 120 and outputs a motion estimation signal to motion compensation 112. Motion compensation 112 takes the video input 110, the signal from the picture buffer 120, and the motion estimation signal from motion estimation 114 and outputs a motion compensation signal to intra / inter mode decision 116.

[0046] After performing spatial prediction and / or temporal prediction, the intra / inter mode decision 116 in the encoder 100 selects the best prediction mode, for example, based on a rate-distortion optimization approach. The block prediction value 140 is then subtracted from the current video block, and the resulting prediction residual is decorrelated using a transform 130 and a quantization 132. The resulting quantized residual coefficients are inversely quantized by inverse quantization 134 and inversely transformed by an inverse transform 136 to form a reconstructed residual, which is then added back to the predicted block to form a reconstructed signal for the CU. Further loop filtering 122, such as a deblocking filter, sample adaptive offset (SAO), and / or an adaptive loop filter (ALF), may be applied to the reconstructed CU before it is placed in the reference picture storage of the picture buffer 120 and used for encoding and decoding future video blocks. To form the output video bitstream 144, the codec mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are sent to the entropy coding unit 138 for further compression and packing to form a bitstream.

[0047] Figure 1A block diagram of a general block-based hybrid video coding system is presented. The input video signal is processed block by block, called coding units (CUs). In VTM-1.0, a CU can be up to 128×128 pixels. However, unlike HEVC, which partitions blocks based solely on a quadtree, in VVC, a coding tree unit (CTU) is split into multiple CUs to accommodate different local characteristics based on quad, binary, or ternary trees. By definition, a coding tree block (CTB) is an N×N sample block for some value of N, so that the division of components into CTBs is partitioning. A CTU consists of one luma sample CTB and two corresponding chroma sample CTBs for a picture with three sample arrays, or one sample CTB for a monochrome picture or a picture encoded or decoded using three separate color planes and syntax structures for encoding and decoding the samples. In addition, the concept of multiple partition unit types in HEVC has been removed. That is, the split into CU, prediction unit (PU), and transform unit (TU) no longer exists in VVC; instead, each CU is always used as the basic unit for both prediction and transform without further partitioning. In the multi-type tree structure, a CTU is first partitioned by a quadtree structure. Then, each quadtree leaf node can be further partitioned by a binary tree structure and a ternary tree structure. Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E As shown, there are five types of splits: quadruple partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, and vertical ternary partitioning.

[0048] Figure 3A Shown is a diagram illustrating block quad partitioning in a multi-type tree structure according to the present disclosure.

[0049] Figure 3B Shown is a diagram illustrating vertical binary partitioning of blocks in a multi-type tree structure according to the present disclosure.

[0050] Figure 3C Shown is a diagram illustrating block-level binary partitioning in a multi-type tree structure according to the present disclosure.

[0051] Figure 3D Shown is a diagram illustrating vertical ternary partitioning of blocks in a multi-type tree structure according to the present disclosure.

[0052] Figure 3E Shown is a diagram illustrating block-level ternary partitioning in a multi-type tree structure according to the present disclosure.

[0053] exist Figure 1In

[15] , spatial prediction and / or temporal prediction can be performed. Spatial prediction (or "intra-frame prediction") uses pixels from samples of already coded neighboring blocks in the same video picture / slice (called reference samples) to predict the current video block. Spatial prediction reduces the spatial redundancy inherent in the video signal. Temporal prediction (also known as "inter-frame prediction" or "motion compensated prediction") uses reconstructed pixels from already coded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in the video signal. The temporal prediction signal for a given CU is typically signaled as one or more motion vectors (MVs) indicating the amount and direction of motion between the current CU and its temporal reference. Similarly, if multiple reference pictures are supported, a reference picture index is additionally sent, which is used to identify which reference picture in the reference picture store the temporal prediction signal comes from. After performing spatial and / or temporal prediction, the mode decision block in the encoder selects the best prediction mode, for example based on a rate-distortion optimization method. The prediction block is then subtracted from the current video block; and the prediction residual is decorrelated and quantized using a transform. The quantized residual coefficients are inverse quantized and inverse transformed to form a reconstructed residual, which is then added back to the prediction block to form the reconstructed signal of the CU. Furthermore, loop filtering such as deblocking filter, sample adaptive offset (SAO), and adaptive loop filter (ALF) can be applied to the reconstructed CU before it is placed in the reference picture store and used for encoding and decoding future video blocks. In order to form the output video bitstream, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are sent to the entropy coding unit for further compression and packaging to form the bitstream.

[0054] Figure 2 FIG. 1 shows a general block diagram of a video decoder for VVC. Specifically, Figure 2 A block diagram of a typical decoder 200 is shown. The decoder 200 has a bitstream 210, entropy decoding 212, inverse quantization 214, inverse transform 216, adder 218, intra / inter mode selection 220, intra prediction 222, memory 230, loop filter 228, motion compensation 224, picture buffer 226, prediction related information 234, and video output 232.

[0055] The decoder 200 is located at Figure 1The reconstruction-related parts in the encoder 100 are similar. In the decoder 200, the incoming video bitstream 210 is first decoded by entropy decoding 212 to obtain quantization coefficient levels and prediction-related information. The quantization coefficient levels are then processed by inverse quantization 214 and inverse transform 216 to obtain reconstructed prediction residuals. The block predictor mechanism implemented in the intra / inter mode selector 220 is configured to perform intra prediction 222 or motion compensation 224 based on the decoded prediction information. A set of unfiltered reconstructed pixels is obtained by summing the reconstructed prediction residuals from the inverse transform 216 with the prediction output generated by the block predictor mechanism using a summer 218.

[0056] The reconstructed block can further pass through a loop filter 228 and then be stored in a picture buffer 226 used as a reference picture storage. The reconstructed video in the picture buffer 226 can be sent to drive a display device and used to predict future video blocks. When the loop filter 228 is turned on, a filtering operation is performed on these reconstructed pixels, resulting in a final reconstructed video output 232.

[0057] Figure 2 A general block diagram of a block-based video decoder is given. The video bitstream is first entropy decoded at the entropy decoding unit. The codec mode and prediction information are sent to the spatial prediction unit (in the case of intra-frame codecs) or the temporal prediction unit (in the case of inter-frame codecs) to form a prediction block. The residual transform coefficients are sent to the inverse quantization unit and the inverse transform unit to reconstruct the residual block. The prediction block and the residual block are then added together. The reconstructed block can be further loop filtered and then stored in the reference picture store. The reconstructed video in the reference picture store is then sent to drive the display device and is used to predict future video blocks.

[0058] Transform coefficient encoding and decoding in VVC

[0059] In transform coefficient encoding and decoding in VVC, the variable remBinsPass1 is initially set to the maximum number of allowed context coding bits (MCCB). During the encoding and decoding process, this variable is decremented by one each time a context coding bit is signaled. When remBinsPass1 is greater than or equal to four, the coefficient is first signaled via syntax elements such as sig_coeff_flag, abs_level_gt1_flag, par_level_flag, and abs_level_gt3_flag. In the first pass, all of these syntax elements use context coding bits. The remainder of the coefficient's level information is encoded and decoded in the second pass using Golomb-Rice coding and bypass coded bits via the syntax element abs_remainder. If remBinsPass1 becomes less than four during the first encoding and decoding pass, the current coefficient is not encoded and decoded in the first pass, but is instead directly encoded and decoded in the second pass using Golomb-Rice coding and bypass coded bits via the syntax element dec_abs_level. The Rice parameter derivation process of dec_abs_level[] is obtained as specified in Table 1A. After encoding and decoding of all the above levels, the sign (sign_flag) of all scan positions with sig_coeff_flag equal to 1 is finally encoded and decoded as a bypass binary bit. Figure 4 . remBinsPass1 is reset for each TB. The transition from using context coding for sig_coeff_flag, abs_level_gt1_flag, par_level_flag, and abs_level_gt3_flag to bypass coding for the remaining coefficients occurs at most once per TB. For a coefficient subblock, if remBinsPass1 is less than 4 before the first coefficient of the subblock is coded, the entire coefficient subblock is coded using bypass coding.

[0060] Figure 4 A diagram showing the residual codec structure for a transform block is shown.

[0061] Table 1A. Rice parameter derivation process of abs_remainder[] and dec_abs_level[]

[0062]

[0063]

[0064] Table 1B. Specification of cRiceParam based on locSumAbs

[0065] locSumAbs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cRiceParam 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 locSumAbs 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cRiceParam 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3

[0066] Residual Coding and Decoding of Transform Skip Mode in VVC

[0067] In transform skip mode, the statistical properties of the residual signal are different from those of the transform coefficients and no energy compression around low frequency components is observed.The residual codec is modified to take into account the different signal properties of the (spatial) transform skip residual.

[0068] Figure 5 A diagram showing the residual codec structure for transform skip blocks.

[0069] General constraint information (GCI)

[0070] The GCI structure contains several types of constraint syntax elements, including: flags for general bitstream constraints, such as indicating that only intra codecs are used, all layers are coded independently, or the bitstream contains only one AU; fields that constrain the bit depth and chroma format of coded pictures; flags that indicate that certain NAL unit types are not allowed to appear in the bitstream; flags that constrain the way in which pictures can be divided into slices, tiles, and sub-pictures in the bitstream; flags that constrain the CTU size and the size and type of partition trees; flags that constrain the use of specific intra codec tools; flags that constrain the use of specific inter codec tools; flags that constrain the transform, quantization, and residual codec tools; and flags that constrain aspects of the loop filter.

[0071] The purpose of the GCI syntax structure is to enable simple discovery of configuration information about features required to decode a bitstream, and to allow interoperability points to be signaled at a finer granularity than allowed by previous video codec standards, which impose restrictions beyond those specified by profiles, tiers, and levels (PTLs). Similar to sub-profiles, the GCI syntax structure is used to define interoperability for decoder implementations that do not support all features of the VVC profile but meet specific application requirements. Decoder implementations can inspect GCI syntax elements to check whether a bitstream avoids the use of specific features to determine how to configure the decoding process and identify whether the bitstream is decodable by the decoder. Decoder implementations that support all features of the VVC profile can ignore the GCI syntax element values, as such decoders will be able to decode any bitstream that conforms to the indicated PTL.

[0072] Transform-skipped residual codec

[0073] According to one or more examples of the present disclosure, a variable set of binary codewords is proposed to encode and decode certain syntax elements (such as abs_remainder) in transform skip residual encoding and decoding, and a selection is determined according to certain encoded information of the current block (such as quantization parameters or encoding and decoding bit depths associated with TB / CB and / or strip / profile) and / or according to a new flag (such as extended_precision_processing_flag) associated with the TB / CB / strip / picture / sequence level. Different methods can be used to obtain the variable set of binary codewords, and some exemplary methods are listed below.

[0074] First, use the same procedure for determining the codewords of abs_remainder as that used in the current VVC, but always adopt fixed Rice parameters (such as 2, 3, 4, 5, 6, 7, or 8). According to certain encoded information of the current block, such as quantization parameters, frame type (such as I, P, or B), component ID (such as luminance or chrominance), color format (such as 420, 422, or 444), or encoding and decoding bit depths associated with TB / CB and / or strip / profile, and / or according to syntax elements associated with the TB / CB / strip / picture / sequence level, such as rice_parameter_value, the fixed value may be different under different conditions. A specific example is where TH1 to TH4 are predefined thresholds satisfying (TH1 < TH2 < TH3 < TH4), and K0 to K4 are predefined Rice parameters. It should be noted that the same logic can have different implementations in practice. For example, certain equations or look-up tables can also be used to obtain the same Rice parameters from the bit depth values of the current CU / Sequence.

[0075] Second, fixed-length binarization.

[0076] Third, truncated Rice binarization.

[0077] Fourth, truncated binary (TB) binarization process. [[ID=D13]]

[0078] Fifth, k-th order exponential Golomb binarization process (EGk). <0OO0300>Sixth, finite k-th order exponential Golomb binarization.

[0080] An example of the corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are illustrated in Table 1 in bold and italic fonts, and the deleted content is shown in italic fonts. It should be noted that the same logic can have different implementations in practice. For example, certain equations or look-up tables can also be used to obtain the same Rice parameters.

[0081] Table 1. Rice parameter derivation process

[0082]

[0083]

[0084] In another example, it is proposed that when a new flag (e.g., extended_precision_processing_flag) is equal to 1, only a fixed value for the Rice parameter is used when encoding and decoding the syntax element of abs_remainder. The corresponding decoding process based on the VVC draft is shown below, with the changes shown in bold and italic fonts, and the deleted content shown in italic fonts. Changes to the VVC draft are shown in bold and italic fonts in Table 2.

[0085] Table 2. Rice parameter derivation process

[0086]

[0087] In yet another example, when the new flag (e.g., extended_precision_processing_flag) is equal to 1, the Rice parameter cRiceParam is fixed to n, where n is a positive number (e.g., 2, 3, 4, 5, 6, 7, or 8). The fixed value may be different under different conditions. An example of the corresponding decoding process based on the VVC draft is shown below, with the changes shown in bold and italic fonts, and the deleted content shown in italic fonts. Changes to the VVC draft are shown in bold and italic fonts in Table 3.

[0088] Table 3. Rice parameter derivation process In yet another example, when the bit depth is greater than or equal to a predefined threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), the Rice parameter cRiceParam is fixed to n, where n is a positive number, e.g., 4, 5, 6, 7, or 8. The fixed value may be different under different conditions. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), the changed parts are shown in bold and italic fonts, and the deleted content is shown in italic fonts. Changes to the VVC draft are shown in bold and italic fonts in Table 4.

[0089] Table 4. Rice parameter derivation process

[0090]

[0091]

[0092] In yet another example, a control flag is signaled in the slice header to indicate whether the signaling of the Rice parameters of the transform skip block is enabled or disabled. When the control flag is signaled as enabled, a syntax element is further signaled for each transform skip stripe to indicate the Rice parameters of the stripe. When the control flag is signaled as disabled (e.g., set to equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the transform skip stripe, but default Rice parameters (e.g., 1) are used for all transform skip stripes. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2), the changed portion is shown in bold and italic fonts, and the deleted content is shown in italic fonts. Changes to the VVC draft are shown in bold and italic fonts in Table 5. It is worth noting that sh_ts_residual_coding_rice_index can be encoded and decoded in different ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0093] Strip header syntax

[0094] Table 5. Syntax of residual codec

[0095]

[0096] sh_ts_residual_coding_rice_flag equal to 1 specifies that sh_ts_residual_coding_rice_index may exist in the current slice. sh_ts_residual_coding_rice_flag equal to 0 specifies that sh_ts_residual_coding_rice_index may not exist in the current slice. When sh_ts_residual_coding_rice_flag is not present, the value of sh_ts_residual_coding_rice_flag is inferred to be equal to 0.

[0097] sh_ts_residual_coding_rice_index specifies the Rice parameter used for the residual_ts_coding() syntax structure.

[0098] Table 6. Rice parameter derivation process

[0099]

[0100] In yet another example, a control flag is signaled in the sequence parameter set (or in the sequence parameter set range extension syntax) to indicate whether the signaling of the Rice parameters of the transform skip block is enabled or disabled. When the control flag is signaled as enabled, a syntax element is further signaled for each transform skip strip to indicate the Rice parameters of the strip. When the control flag is signaled as disabled (e.g., set to equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the transform skip strip, but default Rice parameters (e.g., 1) are used for all transform skip strips. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic fonts in Table 7, and deleted content is shown in italic fonts. It is worth noting that sh_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0101] Sequence Parameter Set RBSP Syntax

[0102] Table 7. Syntax of residual codec

[0103]

[0104] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx is not present in the SH syntax structure referencing the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be 0.

[0105] Strip header syntax

[0106] Table 8. Syntax of residual codec

[0107]

[0108] sh_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure.

[0109] Table 9. Rice parameter derivation process

[0110]

[0111]

[0112] In one or more examples of the present disclosure, it is proposed to disable the presence of Rice parameters for transform skip residual coding if transform skip is disabled. In a specific example, in order to achieve such a design purpose, it is proposed to use sps_transform_skip_enabled_flag to limit the presence of sps_ts_residual_coding_rice_present_in_sh_flag. For example, when the flag sps_transform_skip_enabled_flag is equal to zero (i.e., transform skip is disabled in the current picture), sps_ts_residual_coding_rice_present_in_sh_flag is not signaled but is inferred to be 0. When the flag sps_transform_skip_enabled_flag is equal to one, sps_ts_residual_coding_rice_present_in_sh_flag is further signaled. The changes to the current VVC working draft are shown in italic font as follows.

[0113] if(sps_transform_skip_enabled_flag) sps_ts_residual_coding_rice_present_in_sh_flag u(1)

[0114] In another specific example, to achieve such a design goal, it is proposed to add a bitstream consistency requirement related to sps_transform_skip_enabled_flag to sps_ts_residual_coding_rice_present_in_sh_flag. For example, the bitstream consistency requirement is that when sps_transform_skip_enabled_flag is equal to 0, the value of sps_ts_residual_coding_rice_present_in_sh_flag should be equal to 0. The changes to the current VVC working draft are shown in italics below.

[0115] Sequence parameter set range extension semantics

[0116] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx_minus1 may be present in the slice_header() syntax structure referencing the SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx_minus1 is not present in the slice_header() syntax structure referencing the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0117] A bitstream conformance requirement is that when sps_transform_skip_enabled_flag is equal to 0, the value of sps_ts_residual_coding_rice_present_in_sh_flag shall be equal to 0.

[0118] In yet another example, when the transform skip flag (sps_transform_skip_enabled_flag) is signaled as enabled, a control flag is further signaled in the sequence parameter set (or in the sequence parameter set range extension syntax) to indicate whether the signaling of the Rice parameters of the transform skip block is enabled or disabled. When the control flag is signaled as enabled, a syntax element is further signaled for each transform skip slice to indicate the Rice parameters for the slice. When the control flag is signaled as disabled (e.g., set to equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the transform skip slice, but default Rice parameters (e.g., 1) are used for all transform skip slices. An example of a corresponding decoding process based on the VVC draft is illustrated below. Changes to the VVC draft are shown in italic font.

[0119] Sequence Parameter Set RBSP Syntax

[0120]

[0121] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_present_in_sh_flag is not present in the SH syntax structure referencing the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0122] Strip header syntax

[0123]

[0124]

[0125] sh_ts_residual_coding_rice_idx_minus1 plus 1 specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_idx_minus1 does not exist, the value of sh_ts_residual_coding_rice_idx_minus1 is inferred to be equal to 0.

[0126] 9.3.3.11 Binarization of abs_remainder[]

[0127] The inputs to this process are a request for binarization of the syntax element abs_remainder[n], the color component cIdx, the current sub-block index i, the luma position (x0, y0) specifying the top-left sample of the current luma transform block relative to the top-left luma sample of the picture, the current coefficient scan position (xC, yC), the binary logarithm of the transform block width log2TbWidth, and the binary logarithm of the transform block height log2TbHeight.

[0128] The output of this process is the binarization of the syntax elements.

[0129] The variables lastAbsRemainder and lastRiceParam are obtained as follows:

[0130] If this procedure is called for the first time for the current sub-block index i, both lastAbsRemainder and lastRiceParam are set equal to 0.

[0131] Otherwise (this is not the first call of the process for the current sub-block index i), lastAbsRemainder and lastRiceParam are set equal to the values ​​of abs_remainder[n] and cRiceParam, respectively, obtained in the last call of the binarization process for the syntax element abs_remainder[n] as specified in this clause.

[0132] The Rice parameter cRiceParam is obtained as follows:

[0133] -If transform_skip_flag[x0][y0][cIdx] is equal to 1 and sh_ts_residual_coding_disabled_flag is equal to 0, the Rice parameter cRiceParam is set equal to sh_ts_residual_coding_rice_idx_minus1+1.

[0134] Otherwise, the Rice parameter cRiceParam is obtained by calling the Rice parameter derivation procedure of abs_remainder[] as specified in clause 9.3.3.2, with as input the variable baseLevel set equal to 4, the color component index cIdx, the luma position (x0, y0), the current coefficient scan position (xC, yC), the binary logarithm of the transform block width log2TbWidth, and the binary logarithm of the transform block height log2TbHeight.

[0135] In yet another example, a syntax element is signaled for each transform skipped slice to indicate the Rice parameters for that slice. An example of a corresponding decoding process based on the VVC draft is illustrated below. Changes to the VVC draft are shown in bold and italic font in Table 10. It is worth noting that sh_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have a maximum value. For example, u(n), using an n-bit unsigned integer, or f(n), using a fixed pattern bit string of n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0136] Strip header syntax

[0137] Table 10. Syntax of residual codec

[0138]

[0139] sh_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_idx does not exist, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

[0140] Table 11. Rice parameter derivation process

[0141]

[0142] In yet another example, a control flag is signaled in the picture parameter set range extension syntax to indicate whether the signaling of the Rice parameters for the transform skip block is enabled or disabled. When the control flag is signaled as enabled, a syntax element is further signaled to indicate the Rice parameters for the picture. When the control flag is signaled as disabled (e.g., set to equal "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters for the transform skip slice, but default Rice parameters (e.g., 1) are used for all transform skip slices. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 12. It is worth noting that pps_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0143] Picture Parameter Set Range Extension Syntax

[0144] Table 12. Syntax of residual codec

[0145]

[0146] pps_ts_residual_coding_rice_flag equal to 1 specifies that pps_ts_residual_coding_rice_index may be present in the current picture. pps_ts_residual_coding_rice_flag equal to 0 specifies that pps_ts_residual_coding_rice_idx is not present in the current picture. When pps_ts_residual_coding_rice_flag is not present, the value of pps_ts_residual_coding_rice_flag is inferred to be 0.

[0147] pps_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure.

[0148] Table 13. Rice parameter derivation process

[0149]

[0150]

[0151] In yet another example, it is proposed to encode and decode the syntax element abs_remainder using only variable Rice parameters. The value of the applied Rice parameter can be determined based on certain encoded information of the current block, such as block size, quantization parameter, bit depth, transform type, etc. In a specific embodiment, it is proposed to adjust the Rice parameter based on the codec bit depth and quantization parameter applicable to a CU. The corresponding decoding process based on the VVC draft is shown below, and the changes to the VVC draft are shown in bold and italic fonts in Table 14, and the deleted content is shown in italic fonts. It is worth noting that the same logic can be implemented in different ways in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0152] Table 14. Rice parameter derivation process

[0153]

[0154]

[0155] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 33 or 34). Changes to the VVC draft are shown in bold and italic fonts in Table 15, and deleted content is shown in italic fonts. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0156] Table 15. Rice parameter derivation process

[0157]

[0158]

[0159] In yet another example, the corresponding decoding process based on the VVC draft is as follows, where TH A and TH B is a predefined threshold (e.g., TH A =8,TH B =33 or 34). Changes to the VVC draft are shown in bold and italics in Table 16, and deletions are shown in italics. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0160] Table 16. Rice parameter derivation process

[0161]

[0162] In yet another example, it is proposed that when a new flag (e.g., extended_precision_processing_flag) is equal to 1, only variable Rice parameters are used to encode and decode the syntax elements of abs_remainder. The variable value can be determined based on certain encoded information of the current block, such as block size, quantization parameter, bit depth, transform type, etc. In a specific embodiment, it is proposed to adjust the Rice parameters based on the codec bit depth and quantization parameters applicable to a CU. The corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are shown in bold and italic fonts in Table 17. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0163] Table 17. Rice parameter derivation process

[0164]

[0165]

[0166] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 18, 19). The changes to the VVC draft are shown in bold and italic fonts in Table 18. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0167] Table 18. Rice parameter derivation process

[0168]

[0169]

[0170] In yet another example, the corresponding decoding process based on the VVC draft is as follows, where TH A and TH B is a predefined threshold (e.g., TH A =8,TH B = 18 or 19). The changes to the VVC draft are shown in bold and italic font in Table 19. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Ricean parameters.

[0171] Table 19. Rice parameter derivation process

[0172]

[0173] Figure 6 A method for video encoding is shown. For example, the method can be applied to an encoder. In step 1610, the encoder can receive a video input. For example, the video input can be a real-time stream. In step 1612, the encoder can obtain a quantization parameter based on the video input. For example, the quantization parameter can be calculated by a quantization unit in the encoder. In step 1614, the encoder can obtain Rice parameters based on at least one predefined threshold, the codec bit depth, and the quantization parameter. For example, the Rice parameters are used to signal the syntax of abs_remainder and dec_abs_level. In step 1616, the encoder can entropy encode the video bitstream based on the Rice parameters. For example, the video bitstream can be entropy encoded to produce a compressed video bitstream.

[0174] In yet another example, it is proposed that when the bit depth is greater than 10, only fixed values ​​(e.g., 2, 3, 4, 5, 6, 7, or 8) are used for the Rice parameters when encoding and decoding the syntax elements of abs_remainder. Depending on certain encoded information of the current block (e.g., quantization parameters), the fixed values ​​may be different under different conditions. The corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 18, 19). The changes to the VVC draft are shown in bold and italic fonts in Table 20. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0175] Table 20. Rice parameter derivation process

[0176]

[0177] In yet another example, the corresponding decoding process based on the VVC draft is as follows, where TH A and TH B is a predefined threshold (e.g., TH A =8,TH B = 18 or 19). The changes to the VVC draft are shown in bold and italic font in Table 21. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Ricean parameters.

[0178] Table 21. Rice parameter derivation process

[0179]

[0180]

[0181] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 33 or 34). The changes to the VVC draft are shown in bold and italic fonts in Table 22. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0182] Table 22. Rice parameter derivation process

[0183]

[0184] In yet another example, the corresponding decoding process based on the VVC draft is as follows, where TH A and TH B is a predefined threshold (e.g., TH A =8,THB =33 or 34). The changes to the VVC draft are shown in bold and italic font in Table 23. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Ricean parameters.

[0185] Table 23. Rice parameter derivation process

[0186]

[0187]

[0188] It is worth mentioning that in the above figure, the equations used to calculate specific Rice parameters are only used as examples to illustrate the proposed ideas. For those who are proficient in modern video coding and decoding technology, other mapping functions (or equivalent mapping equations) are already applicable to the proposed ideas (i.e., determining the Rice parameters of the transform skip mode based on the codec bits and the applied quantization parameters). At the same time, it should also be mentioned that in the current VVC design, the value of the applied quantization parameter is allowed to change at the coding block group level. Therefore, the proposed Rice parameter adjustment scheme can flexibly adjust the Rice parameters of the transform skip mode at the coding block group level.

[0189] Signaling information for conventional residual codec and transform-skipped residual codec

[0190] According to one or more examples of the present disclosure, it is proposed to use signals to represent Rice parameters of binary codewords for encoding and decoding certain syntax elements (such as abs_remainder in transform skip residual coding, shift parameters and offset parameters for obtaining Rice parameters for abs_remainder / dec_abs_level in conventional residual coding), and determine whether to use signals based on certain coded information of the current block (such as quantization parameters or coding bit depth associated with TB / CB and / or slice / profile) and / or based on a new flag associated with TB / CB / slice / picture / sequence level (such as sps_residual_coding_info_present_in_sh_flag).

[0191] In one example, a control flag is signaled in a slice header to indicate whether the signaling of Rice parameters for a transform skip block and the signaling of shift parameters and / or offset parameters for obtaining Rice parameters in the transform block are enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled for each transform skip slice to indicate the Rice parameters of the slice, and two syntax elements are further signaled for each transform slice to indicate the shift parameters and / or offset parameters for obtaining Rice parameters of the slice. When the control flag is signaled as disabled (e.g., set to equal "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the transform skip slice, and instead, default Rice parameters (e.g., 1) are used for all transform skip slices, and no further syntax elements are signaled at a lower level to indicate the shift parameters and offset parameters for obtaining Rice parameters of the transform slice, and instead, default shift parameters and / or offset parameters (e.g., 0) are used for all transform slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 24. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_index can be encoded and decoded in different ways and / or may have maximum values. For example, u(n), using an n-bit unsigned integer, or f(n), using a fixed pattern bit string of n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0192] Figure 7 A method for video decoding is shown. For example, the method can be applied to an encoder. In step 1710, the encoder can receive a video input. In step 1712, the encoder can signal Rice parameters of binary codewords for codec syntax elements. The codec syntax elements can include abs_remainder in a transform skip residual codec. In step 1714, the encoder can entropy encode the video bitstream based on the Rice parameters and the video input.

[0193] Strip header syntax

[0194] Table 24. Syntax of residual codec

[0195]

[0196] sh_residual_coding_rice_flag equal to 1 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index may exist in the current slice. sh_residual_coding_rice_flag equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index do not exist in the current slice.

[0197] sh_residual_coding_rice_shift specifies the shift parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_shift does not exist, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0198] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0199] sh_ts_residual_coding_rice_index specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_index does not exist, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0200] Table 25. Rice parameter derivation process

[0201]

[0202] Table 26. Rice parameter derivation process

[0203]

[0204]

[0205] In another example, a control flag is signaled in a sequence parameter set (or in a sequence parameter set range extension syntax) to indicate whether the signaling of Rice parameters for a transform skip block and the signaling of shift parameters and / or offset parameters for obtaining Rice parameters in the transform block are enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled for each transform skip slice to indicate the Rice parameters for the slice, and two syntax elements are further signaled for each transform slice to indicate the shift parameters and / or offset parameters for obtaining Rice parameters for the slice. When the control flag is signaled as disabled (e.g., set to equal "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters for the transform skip slice, and instead, default Rice parameters (e.g., 1) are used for all transform skip slices, and no further syntax elements are signaled at a lower level to indicate the shift parameters and / or offset parameters for obtaining Rice parameters for the transform slice, and instead, default shift parameters and / or offset parameters (e.g., 0) are used for all transform slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 27. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have maximum values. For example, u(n), using an n-bit unsigned integer, or f(n), using a fixed pattern bit string of n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0206] Sequence Parameter Set RBSP Syntax

[0207] Table 27. Syntax of residual codec

[0208]

[0209] sps_residual_coding_info_present_in_sh_flag equal to 1 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. sps_residual_coding_info_present_in_sh_flag equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx are not present in the SH syntax structure referencing the SPS. When sps_residual_coding_info_present_in_sh_flag is not present, the value of sps_residual_coding_info_present_in_sh_flag is inferred to be 0.

[0210] Strip header syntax

[0211] Table 28. Syntax of residual codec

[0212]

[0213]

[0214] sh_residual_coding_rice_shift specifies the shift parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_shift does not exist, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0215] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0216] sh_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_index does not exist, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0217] Table 29. Rice parameter derivation process

[0218]

[0219] Table 30. Rice parameter derivation process

[0220]

[0221] In yet another example, one syntax element is signaled for each transform skipped slice to indicate the Rice parameters for that slice, and two syntax elements are signaled for each transform slice to indicate the shift parameters and / or offset parameters for obtaining the Rice parameters for that slice. An example of a corresponding decoding process based on the VVC draft is illustrated below. Changes to the VVC draft are shown in bold and italic font in Table 31. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have a maximum value. For example, u(n), using an n-bit unsigned integer, or f(n), using a fixed pattern bit string of n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0222] Strip header syntax

[0223] Table 31. Syntax of residual codec

[0224]

[0225] sh_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_idx does not exist, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

[0226] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0227] sh_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_index does not exist, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0228] Table 32. Rice parameter derivation process

[0229]

[0230]

[0231] Table 33. Rice parameter derivation process

[0232]

[0233]

[0234] In yet another example, a control flag is signaled in the picture parameter set range extension syntax to indicate whether the signaling of Rice parameters for transform skip blocks and the signaling of shift parameters and / or offset parameters for deriving Rice parameters in the transform blocks are enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled to indicate Rice parameters for transform skip residual codec for the picture, and two syntax elements are further signaled for normal residual codec to indicate shift parameters and / or offset parameters for deriving Rice parameters for the picture. When the control flag is signaled as disabled (e.g., set to equal "0"), no further syntax elements are signaled at a lower level to indicate Rice parameters for transform skip residual codec, and instead default Rice parameters (e.g., 1) are used for all transform skip residual codecs, and no further syntax elements are signaled at a lower level to indicate shift parameters and / or offset parameters for deriving Rice parameters for normal residual codecs, and instead default shift parameters and / or offset parameters (e.g., 0) are used for all normal residual codecs. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 34. It is worth noting that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx can be encoded and decoded in different ways and / or may have maximum values. For example, u(n), using an n-bit unsigned integer, or f(n), using a fixed pattern bit string of n bits (from left to right) written with the left bit first, can also be used to encode / decode the same syntax element.

[0235] Picture Parameter Set Range Extension Syntax

[0236] Table 34. Syntax of residual codec

[0237]

[0238]

[0239] pps_residual_coding_info_flag equal to 1 specifies that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_index may be present in the current picture. pps_residual_coding_info_flag equal to 0 specifies that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx are not present in the current picture. When pps_residual_coding_info_flag is not present, the value of pps_residual_coding_info_flag is inferred to be 0.

[0240] pps_residual_coding_rice_shift specifies the shift parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When pps_residual_coding_rice_shift does not exist, the inferred value of pps_residual_coding_rice_shift is equal to 0.

[0241] pps_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When pps_residual_coding_rice_offset does not exist, the value of pps_residual_coding_rice_offset is inferred to be equal to 0.

[0242] pps_ts_residual_coding_rice_idx specifies the Rice parameter used for the residual_ts_coding() syntax structure. When pps_ts_residual_coding_rice_index does not exist, the value of pps_ts_residual_coding_rice_index is inferred to be equal to 0.

[0243] Table 35. Rice parameter derivation process

[0244]

[0245]

[0246] Table 36. Rice parameter derivation process

[0247]

[0248] According to one or more examples of the present disclosure, it is proposed to use different Rice parameters to encode and decode certain syntax elements (such as abs_remainder in transform skip residual coding, shift parameters and offset parameters for obtaining Rice parameters for abs_remainder / dec_abs_level in conventional residual coding), and determine which one to use based on certain encoded information of the current block (such as quantization parameters or coding bit depth associated with TB / CB and / or slice / profile) and / or based on a new flag associated with TB / CB / slice / picture / sequence level (such as sps_residual_coding_info_present_in_sh_flag).

[0249] In one example, a control flag is signaled in a slice header to indicate whether the derivation process of Rice parameters for transform skip blocks and the derivation process of shift parameters and / or offset parameters for Rice parameters in transform blocks are enabled or disabled. When the control flag is signaled as enabled, the Rice parameters may be different under different conditions based on certain encoded information of the current block (e.g., quantization parameter and bit depth). And the shift parameters and / or offset parameters used to obtain Rice parameters in conventional residual coding may be different under different conditions based on certain encoded information of the current block (e.g., quantization parameter and bit depth). When the control flag is signaled as disabled (e.g., set to equal "0"), default Rice parameters (e.g., 1) are used for all transform skip slices, and default shift parameters and / or offset parameters (e.g., 0) are used for all transform slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH A and TH B is a predefined threshold (e.g., TH A =8, TH B =18 or 19). The changes to the VVC draft are shown in bold and italic font in Table 37. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Ricean parameters.

[0250] Strip header syntax

[0251] Table 37. Syntax of residual codec

[0252]

[0253] sh_residual_coding_rice_flag equal to 1 specifies that the bit-depth-dependent Rice parameter derivation process is used in the current slice. sh_residual_coding_rice_flag equal to 0 specifies that the bit-depth-dependent Rice parameter derivation process is not used in the current slice.

[0254] Table 38. Rice parameter derivation process

[0255] Table 39. Rice parameter derivation process

[0256]

[0257]

[0258] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predefined threshold (e.g., 18, 19). The changes to the VVC draft are shown in bold and italic fonts in Table 40. It is worth noting that the same logic can be implemented differently in practice. For example, certain equations or lookup tables can also be used to obtain the same Rice parameters.

[0259] Table 40. Rice parameter derivation process

[0260]

[0261]

[0262]

[0263] According to another aspect of the present disclosure, it is proposed to add constraints marked by the values ​​of the above-mentioned codec tools to provide the same general constraint control as other constraints in the general constraint information.

[0264] For example, sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx is not present in the SH syntax structure referencing the SPS. According to the present disclosure, it is proposed to add a syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted.

[0265] Additions are highlighted in italic font.

[0266]

[0267] In another example, pps_ts_residual_coding_rice_flag equal to 1 specifies that pps_ts_residual_coding_rice_index may be present in the current picture. pps_ts_residual_coding_rice_flag equal to 0 specifies that pps_ts_residual_coding_rice_idx is not present in the current picture. According to the present disclosure, it is proposed to add a syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted. Added parts are highlighted in italic font.

[0268]

[0269]

[0270] In yet another example, sps_rice_adaptation_enabled_flag equal to 1 indicates that the binarized Rice parameters for abs_remainder[] and dec_abs_level can be obtained by the formula.

[0271] The formula may include: RiceParam=RiceParam+shiftVal and shiftVal=(localSumAbs <Tx[0])?Rx[0]:((localSumAbs<Tx[1])?Rx[1]:((localSumAbs<Tx[2])?Rx[2]:((localSumAbs<Tx[3])?Rx[3]:Rx[4]))),

[0272] Wherein, the lists Tx[] and Rx[] are specified as follows: Tx[] = {32, 128, 512, 2048} >> (1523) Rx[] = {0, 2, 4, 6, 8}

[0273] According to the present disclosure, it is proposed to add a syntax element gci_no_rice_adaptation_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. The changes to the VVC draft are highlighted. The added parts are highlighted in italic font.

[0274]

[0275] Since the proposed Rice parameter adaptation scheme is only used for transform skip residual coding (TSRC), the proposed method can only take effect when TSRC is enabled. Accordingly, in one or more embodiments of the present disclosure, it is proposed to add a bitstream constraint requiring that when the transform skip mode is disabled from the general constraint information level, for example, when the value of gci_no_transform_skip_constraint_flag is set to one, the value of gci_no_rice_adaptation_constraint_flag is one.

[0276] In yet another example, sps_range_extension_flag equal to 1 specifies that the sps_range_extension() syntax structure is present in the SPS RBSP syntax structure. sps_range_extension_flag equal to 0 specifies that the syntax structure is not present. According to the present disclosure, it is proposed to add a syntax element gci_no_range_extension_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted. Added parts are highlighted in italic font.

[0277]

[0278] Figure 9 A method for video encoding and decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 1902, the decoder can receive a sequence parameter set (SPS) range extension flag, wherein the SPS range extension flag indicates whether a syntax structure sps_range_extension is present in a slice header (SH) raw byte sequence payload (RBSP) syntax structure based on a value of the SPS range extension flag.

[0279] In step 1904 , in response to determining that the value of the SPS range extension flag is equal to 1, the decoder may determine that sps_range_extension is present in the SH RBSP syntax structure.

[0280] In step 1906 , in response to determining that the value of the range extension flag is equal to 0, the decoder may determine that sps_range_extension is not present in the SH RBSP syntax structure.

[0281] In yet another example, sps_cabac_bypass_alignment_enabled_flag equal to 1 specifies that the value of ivlCurrRange can be aligned before bypass decoding of the syntax elements sb_coded_flag[][], abs_remainder[], dec_abs_level[n], and coeff_sign_flag[]. sps_cabac_bypass_alignment_enabled_flag equal to 0 specifies that the value of ivlCurrRange is not aligned before bypass decoding. According to the present disclosure, it is proposed to add a syntax element gci_no_cabac_bypass_alignment_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted. The added parts are highlighted in italic font.

[0282]

[0283]

[0284] Figure 10A method for video coding and decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2002, the decoder can receive a sequence parameter set (SPS) alignment enable flag, which indicates whether the index ivlCurrRange is aligned before bypass decoding of syntax elements sb_coded_flag, abs_remainder, dec_abs_level, and coeff_sign_flagn based on the value of the SPS alignment enable.

[0285] In step 2004 , in response to determining that the value of the SPS alignment enable flag is equal to 1, the decoder may determine that ivlCurrRange is aligned prior to bypass decoding.

[0286] In step 2006 , in response to determining that the value of the SPS alignment enable flag is equal to 0, the decoder may determine that ivlCurrRange is not aligned prior to bypass decoding.

[0287] In yet another example, extended_precision_processing_flag equal to 1 specifies that extended dynamic range can be used for transform coefficients and transform processing. extended_precision_processing_flag equal to 0 specifies that extended dynamic range is not used. According to the present disclosure, it is proposed to add a syntax element gci_no_extended_precision_processing_constraint_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted.

[0288] Additions are highlighted in italic font.

[0289]

[0290]

[0291] Figure 11 A method for video encoding and decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2102, the decoder can receive an extended precision processing flag, which indicates whether to use an extended dynamic range during transform processing for transform coefficients based on the value of the extended precision processing flag.

[0292] In step 2104 , in response to determining that the value of the extended precision processing flag is equal to 1, the decoder may determine to employ an extended dynamic range for the transform coefficients and during the transform process.

[0293] In step 2106 , in response to determining that the value of the extended precision processing flag is equal to 0, the decoder may determine not to employ extended dynamic range for transform coefficients or during transform processing.

[0294] In yet another example, persistent_rice_adaptation_enabled_flag equal to 1 specifies that the mode-related statistics accumulated from the previous sub-blocks can be used at the beginning of each sub-block to initialize the Rice parameter derivation for the binarization of abs_remainder[] and dec_abs_level. persistent_rice_adaptation_enabled_flag equal to 0 specifies that the previous sub-block state is not used in the Rice parameter derivation. According to the present disclosure, it is proposed to add a syntax element gci_no_persistent_rice_adaptation_constraint_flag in the general constraint information syntax to provide the same general constraint control as other flags. The following diagram illustrates an example of the decoding process for the VVC draft. The changes to the VVC draft are highlighted. The added parts are highlighted in italic font.

[0295]

[0296] Figure 12 A method for video encoding and decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2202, the decoder can receive a persistent Rice adaptive enable flag, which indicates whether the mode-related statistics accumulated from the previous sub-blocks are used to initialize the Rice parameter derivation for binarization of abs_remainder and dec_abs_level at the beginning of each sub-block based on the value of the persistent Rice adaptive enable flag.

[0297] In step 2204, in response to determining that the value of the persistent Rice adaptation enable flag is equal to 1, the decoder can determine that pattern-related statistics accumulated from previous sub-blocks are used at the beginning of each sub-block to initialize the Rice parameter derivation for binarization.

[0298] In step 2206, in response to determining that the value of the persistent Rice adaptation enable flag is equal to 0, the decoder can determine that the previous sub-block state is not adopted in the Rice parameter derivation.

[0299] In yet another example, sps_rrc_rice_extension_flag equal to 1 specifies that the extension of Rice parameter derivation for binarization of abs_remainder[] and dec_abs_level[] is enabled. sps_rrc_rice_extension_flag equal to 0 specifies that the extension of Rice parameter derivation for binarization of abs_remainder[] and dec_abs_level[] is disabled. According to the present disclosure, it is proposed to add a syntax element gci_no_rrc_rice_extension_flag to the general constraint information syntax to provide the same general constraint control as other flags. The following diagram illustrates an example of the decoding process for the VVC draft. The changes to the VVC draft are highlighted. The added parts are described in italics below.

[0300]

[0301] Figure 17 A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2702, the decoder can receive an SPS Rice extension flag indicating whether an extension for Rice parameter derivation of binarization of abs_remainder and dec_abs_level is enabled.

[0302] In step 2704, in response to determining that the value of the SPS Rice extension flag is equal to 1, the decoder can determine that the extension for the derivation of Rice parameters for binarization is enabled.

[0303] In step 2706, in response to determining that the value of the SPS Rice extension flag is equal to 0, the decoder can determine that the extension for the derivation of Rice parameters for binarization is disabled.

[0304] In yet another example, sps_persistent_rice_adaptation_enabled_flag equal to 1 specifies that the statistics accumulated from the previous TU can be used at the beginning of each TU to initialize the Rice parameter derivation for the binarization of abs_remainder[] and dec_abs_level[]. sps_persistent_rice_adaptation_enabled_flag equal to 0 specifies that the previous TU state is not used in the Rice parameter derivation. According to the present disclosure, it is proposed to add a syntax element gci_no_persistent_rice_adaptation_enabled_flag in the general constraint information syntax to provide the same general constraint control as other flags. The following diagram illustrates an example of the decoding process for the VVC draft. The changes to the VVC draft are highlighted. The added parts are described in italics below.

[0305]

[0306] Figure 18 A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2802, the decoder can receive an SPS Rice adaptation enable flag, which indicates whether to initialize the Rice parameter derivation for binarization of abs_remainder and dec_abs_level with statistical data accumulated from previous TUs at the beginning of each transform unit.

[0307] In step 2804, in response to determining that the value of the SPS Rice adaptation enable flag is equal to 1, the decoder may determine to initialize Rice parameter derivation for binarization at the beginning of each TU using statistics accumulated from previous TUs.

[0308] In step 2806, in response to determining that the value of the SPS Rice adaptation enable flag is equal to 0, the decoder can determine that the previous TU state is not used in Rice parameter derivation.

[0309] In yet another example, sps_reverse_last_sig_coeff_enabled_flag equal to 1 specifies that sh_reverse_last_sig_coeff_flag is present in the slice_header() syntax structure referencing the SPS. sps_reverse_last_sig_coeff_enabled_flag equal to 0 specifies that sh_reverse_last_sig_coeff_flag is not present in the slice_header() syntax structure referencing the SPS. According to the present disclosure, it is proposed to add a syntax element gci_no_reverse_last_sig_coeff_enabled_flag to the general constraint information syntax to provide general constraint control similar to other flags. The following illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted.

[0310] Additions are highlighted in italic font.

[0311]

[0312] sh_reverse_last_sig_coeff_flag equal to 1 specifies that the coordinates of the last significant coefficient of each transform block in the current slice are encoded relative to ((Log2ZoTbWidth<<1)-1, (Log2ZoTbHeight<<1)-1). sh_reverse_last_sig_coeff_flag equal to 0 specifies that the coordinates of the last significant coefficient of each transform block in the current slice are encoded relative to (0,0). When not present, the value of sh_reverse_last_sig_coeff_flag is inferred to be 0.

[0313] Figure 19 A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 2902, the decoder can receive an SPS inversion coordinate enable flag for the last significant coefficient, which indicates whether an SH inversion coordinate enable flag for the last significant coefficient is present in a slice header syntax structure that references an SPS.

[0314] In step 2904 , in response to determining that the value of the SPS inversion coordinate enable flag for the last significant coefficient is equal to 1, the decoder may determine that the SH inversion coordinate enable flag for the last significant coefficient exists in the slice header syntax structure referencing the SPS.

[0315] In step 2906 , in response to determining that the value of the SPS invert coordinate enable flag for the last significant coefficient is equal to 0, the decoder may determine that the SH invert coordinate enable flag for the last significant coefficient is not present in the slice header syntax structure referencing the SPS.

[0316] In yet another example, sps_transform_precision_adaptation_enabled_flag equal to 1 specifies that the downshifting during scaling of transform coefficients and during transformation of scaled transform coefficients is adaptively allocated by examining the coefficient values ​​of dequantization and inverse transformation. According to the present disclosure, it is proposed to add a syntax element gci_no_transform_precision_adaptation_enabled_flag to the general constraint information syntax to provide the same general constraint control as other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted. Added parts are highlighted in italic font.

[0317]

[0318] Figure 20 A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 3002, the decoder can receive an SPS transform precision adaptation enable flag, which indicates whether a downshift in the scaling process of transform coefficients and in the transformation process of scaled transform coefficients is adaptively allocated by examining the coefficient values ​​of dequantization and inverse transformation.

[0319] In step 3004, in response to determining that the value of the SPS transform precision adaptation enable flag is equal to 1, the decoder can determine that the downshift in the scaling process of the transform coefficients and in the transformation process of the scaled transform coefficients is adaptively allocated by examining the coefficient values ​​of the dequantized and inverse transformed coefficients.

[0320] In yet another example, sps_high_throughput_flag equal to 1 specifies that all syntax elements in the residual codec except the last significant coefficient position in the RRC are coded in bypass mode and only need to be aligned once after the last significant coefficient position in the RRC and at the very beginning of the TB in the TSRC. According to the present disclosure, it is proposed to add a syntax element gci_no_high_throughput_flag to the general constraint information syntax to provide the same general constraint control as other flags. The following diagram illustrates an example of the decoding process for the VVC draft. Changes to the VVC draft are highlighted. Added parts are highlighted in italic font.

[0321]

[0322]

[0323] Figure 21 A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 3102, the decoder can receive an SPS high-throughput flag, which indicates whether syntax elements in residual codecs are encoded or decoded using bypass mode.

[0324] In step 3104, in response to determining that the value of the SPS high-throughput flag is equal to 1, the decoder can determine that all syntax elements in the residual codec except the last significant coefficient position in the regular residual codec (RRC) are coded by the bypass mode, and alignment is performed after the last significant coefficient position in the RRC and at the beginning of the transform block (TB) in the transform skip residual codec (TSRC).

[0325] The above method can be implemented using an apparatus including one or more circuits, including an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. The apparatus can use these circuits in combination with other hardware or software components for performing the methods described above. Each module, submodule, unit, or subunit disclosed above can be at least partially implemented using the one or more circuits.

[0326] Rice parameter decision

[0327] On the encoder side, TSRC encoding may require multiple encoding passes to obtain the optimal Rice parameters. This multi-pass encoding may not be suitable for actual hardware encoder design. In order to solve this problem, a low-latency TSRC encoding method is also proposed. According to one or more examples of the present disclosure, it is proposed to obtain Rice parameters based on certain encoded information of the current strip (for example, quantization parameters and / or codec bit depth associated with the strip / picture / sequence) and / or based on the hash rate associated with the strip / picture / sequence level. Different methods can be used to obtain Rice parameters, and some exemplary methods are listed below. Note that the following methods can be used alone or in combination.

[0328] 1. The Rice parameters mentioned in the above embodiments may additionally depend on the video resolution, including the temporal resolution (e.g., frame rate) and spatial resolution (e.g., picture width and height) of the video.

[0329] 2. Rice parameters can vary at the sequence level, picture level, slice level and / or any predefined area. In a specific example, different Rice values ​​are used for pictures with different temporal layer IDs (this is related to nuh_temporal_id_plus1 specified in the VVC specification). Alternatively, the Rice parameter may include a value determined based on the QP value used at the sequence level, picture level, slice level and / or any predefined area. For example, Rice parameter = Clip3 (1, 8, (TH–QP) / 6), where TH is a predefined threshold (e.g., 18, 19).

[0330] 3. Depending on the change in coded information between the current slice and the previous slice, the Rice parameter can be set to a default value, such as 1. In a specific example, when the temporal layer ID of a picture changes compared to the previous picture, a default Rice value is used for the picture. Alternatively, when ΔQ is greater than TH, a default Rice value is used for the picture, where ΔQ is calculated as abs(QPcurrent-QPprevious) and TH is a predefined threshold. Rice parameter (e.g., 0, 5). For example, when the hash rate of the intra-block copy mode in the current slice is greater than TH, the Rice parameter = 1, where TH is a predefined threshold, for example, a maximum value (41*(number of CTUs), 4200).

[0331] 4. The Rice parameters of each stripe based on the value of abs_remainder are encoded and decoded in its previous stripe according to the encoding and decoding order. In a specific example, after encoding and decoding a stripe, the number of binary digits for binarizing abs_remainder using different Rice parameters is calculated, and then the number of binary digits is used to determine the Rice parameters of the subsequent stripe. For example, the Rice parameter that reaches the minimum number of binary digits in the previous stripe will be selected for the current stripe. For another example, if the current stripe and its previous stripe use the same QP, the Rice parameter that reaches the minimum number of binary digits in the previous stripe will be selected for the current stripe; otherwise, before comparing with other Rice parameters, the number of binary digits generated using the default Rice parameter (i.e., 1) in the previous stripe will be scaled by TH, and the Rice parameter that results in the minimum number of binary digits will be selected for the current stripe, where TH is a predefined threshold, such as 0.9.

[0332] 5. The Rice parameter of each stripe is based on the value of abs_remainer encoded and decoded in its previous stripe according to the encoding and decoding order, and the Rice parameter can be adjusted according to the change of the coded information between the current stripe and the previous stripe. In a specific example, the Rice parameter that reaches the minimum number of binary digits in the previous stripe will be selected for the current stripe. And when ΔQ is greater than TH, the Rice value can be adjusted, where ΔQ is calculated as abs(QPcurrent-QPprevious) and TH is a predefined threshold. Rice parameter (e.g., 0, 5). The adjustment can be to increase a predefined offset (e.g., +1, -1) or to scale by a predefined value.

[0333] Bitstream constraints

[0334] In one or more examples of the present disclosure, it is proposed to disable the presence of Rice parameters for transform skip residual codecs and high bit depth tools for low bit depth codecs. In a specific example, to achieve such a goal, it is proposed to add a requirement for bit stream consistency, which indicates that in a profile definition such as HEVC or its semantics, such tools should be disabled for bit depths less than or equal to 10.

[0335] For example, sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. The changes to the current VVC working draft are as follows.

[0336] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_ts_residual_coding_rice_present_in_sh_flag shall be equal to 0.

[0337] In another example, sps_rrc_rice_extension_flag equal to 1 specifies that the extension of Rice parameter derivation for binarization of abs_remaining[] and dec_abs_level[] is enabled. sps_rrc_rice_extension_flag equal to 0 specifies that the extension of Rice parameter derivation for binarization of abs_remaining[] and dec_abs_level[] is disabled. In accordance with the present disclosure, the changes to the current VVC working draft are as follows.

[0338] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_rrc_rice_extension_flag shall be equal to 0.

[0339] In yet another example, sps_persistent_rice_adaptation_enabled_flag equal to 1 specifies that the Rice parameter derivation for binarization of abs_remainder[] and dec_abs_level[] can be initialized at the beginning of each TU using statistics accumulated from previous TUs. sps_persistent_rice_adaptation_enabled_flag equal to 0 specifies that previous TU states are not used in Rice parameter derivation. In accordance with the present disclosure, the changes to the current VVC working draft are as follows.

[0340] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_persistent_rice_adaptation_enabled_flag shall be equal to 0.

[0341] In yet another example, sps_reverse_last_sig_coeff_enabled_flag equal to 1 specifies that sh_reverse_last_sig_coeff_flag is present in the slice_header() syntax structure referencing the SPS. sps_reverse_last_sig_coeff_enabled_flag equal to 0 specifies that sh_reverse_last_sig_coeff_flag is not present in the slice_header() syntax structure referencing the SPS. In accordance with the present disclosure, changes to the current VVC working draft are as follows.

[0342] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_reverse_last_sig_coeff_enabled_flag shall be equal to 0.

[0343] In yet another example, sps_high_throughput_flag equal to 1 specifies that syntax elements in residual coding are coded in bypass mode. According to the present disclosure, changes to the current VVC working draft are as follows.

[0344] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_high_throughput_flag shall be equal to 0.

[0345] In addition, it is worth mentioning that the proposed bitstream conformance constraint sps_ts_residual_coding_rice_present_in_sh_flag on the codec bit depth is orthogonal to the conditional signal of the slice level flag on the transform skip flag (i.e., sps_transform_skip_enabled_flag). In an embodiment, in such a combination, the flag sps_transform_skip_enabled_flag is used to restrict the presence of sps_ts_residual_coding_rice_present_in_sh_flag. At the same time, the conforming bitstream is also applied to require that sps_ts_residual_coding_rice_present_in_sh_flag can be equal to 1 only when the value of the codec bit depth is greater than 10. The SPS syntax table and semantic changes when applying this approach are described below:

[0346]

[0347] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referencing the SPS. The changes to the current VVC working draft are as follows.

[0348] A bitstream conformance requirement is that when the bit depth is less than or equal to 10, the value of sps_ts_residual_coding_rice_present_in_sh_flag shall be equal to 0.

[0349] Figure 22A method for video decoding according to an example of the present disclosure is shown. For example, the method can be applied to a decoder. In step 3202, the decoder can determine the codec bit depth of at least one sample in the bitstream. In step 3204, the decoder can determine the value of the first SPS flag of the at least one sample. In step 3206, the decoder can determine the second SPS flag of the at least one sample based on the value of the first SPS flag and the codec bit depth of the at least one sample. In some examples, the decoder can determine the presence of the second SPS flag based on the first SPS flag, or determine the value of the second SPS flag based on the codec bit depth. In some examples, the decoder can determine the presence of the second SPS flag based on the first SPS flag and the codec bit depth. In some examples, the decoder can determine the value of the second SPS flag based on the first SPS flag and the codec bit depth. In some other examples, the decoder can determine the value of the second SPS flag based on the codec bit depth, regardless of the value of the first SPS flag.

[0350] In another embodiment, instead of applying bitstream consistency, it is proposed to directly use the bit depth and the flag sps_transform_skip_enabled_flag to limit the signal transmission of the flag sps_ts_residual_coding_rice_present_in_sh_flag. Specifically, in this way, the value of the flag sps_ts_residual_coding_rice_present_in_sh_flag is signaled only when sps_transform_skip_enabled_flag is equal to 1 and the codec bit depth is greater than 10, as shown below

[0351]

[0352]

[0353] Figure 16 A flow chart of a low-latency transform skip residual coding (TSRC) method according to an example of the present disclosure is shown. For example, the method can be applied to an encoder. In step 2602, the encoder can obtain Rice parameters based on encoded information of the current slice of the video. The encoded information may include one or more of the following parameters: a quantization parameter or a codec bit depth associated with a slice, picture, or sequence of the video; or a hash rate associated with a slice, picture, or sequence of the video.

[0354] It should be noted that the above encoder method can be applied to the decoder side. In a specific example, the Rice parameters do not need to be transmitted to the decoder with a signal, and the encoder / decoder uses the same method to obtain the Rice parameters.

[0355] Figure 8 The computing environment 1810 is shown coupled to a user interface 1860. The computing environment 1810 may be part of a data processing server. The computing environment 1810 includes a processor 1820, a memory 1840, and an I / O interface 1850.

[0356] The processor 1820 generally controls the overall operation of the computing environment 1810, such as operations associated with display, data acquisition, data communication, and image processing. The processor 1820 may include one or more processors for executing instructions to perform all or some of the steps in the method described above. Furthermore, the processor 1820 may include one or more modules that facilitate interaction between the processor 1820 and other components. The processor may be a central processing unit (CPU), a microprocessor, a single-chip microcomputer, a GPU, etc.

[0357] The memory 1840 is configured to store various types of data to support the operation of the computing environment 1810. The memory 1840 may include predetermined software 1842. Examples of such data include instructions for any application or method operating on the computing environment 1810, video data sets, image data, etc. The memory 1840 may be implemented using any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0358] I / O interface 1850 provides an interface between processor 1820 and peripheral interface modules (such as a keyboard, click wheel, buttons, etc.). Buttons may include, but are not limited to, a home button, a start scan button, and a stop scan button. I / O interface 1850 may be coupled to an encoder and a decoder.

[0359] In some embodiments, a non-transitory computer-readable storage medium is further provided, the non-transitory computer-readable storage medium including a plurality of programs, such as those included in the memory 1840 and executable by the processor 1820 in the computing environment 1810 for performing the methods described above. For example, the non-transitory computer-readable storage medium may be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0360] The non-transitory computer-readable storage medium stores a plurality of programs for execution by a computing device having one or more processors, wherein the plurality of programs, when executed by the one or more processors, causes the computing device to perform the method for motion prediction described above.

[0361] In some embodiments, the computing environment 1810 may be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), graphics processing units (GPUs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0362] Figure 13 is a block diagram illustrating an exemplary system 10 for encoding and decoding video blocks in parallel according to some embodiments of the present disclosure. Figure 13 As shown, system 10 includes a source device 12 that generates and encodes video data to be decoded at a later time by a destination device 14. Source device 12 and destination device 14 may include any of a variety of electronic devices, including a desktop or laptop computer, a tablet computer, a smartphone, a set-top box, a digital television, a camera, a display device, a digital media player, a video game console, a video streaming device, etc. In some implementations, source device 12 and destination device 14 are equipped with wireless communication capabilities.

[0363] In some embodiments, the destination device 14 may receive the encoded video data to be decoded via a link 16. The link 16 may include any type of communication medium or device capable of moving the encoded video data from the source device 12 to the destination device 14. In one example, the link 16 may include a communication medium for enabling the source device 12 to transmit the encoded video data directly to the destination device 14 in real time. The encoded video data may be modulated and transmitted to the destination device 14 according to a communication standard such as a wireless communication protocol. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include a router, a switch, a base station, or any other device that may be used to facilitate communication from the source device 12 to the destination device 14.

[0364] In some other embodiments, the encoded video data can be transferred from the output interface 22 to a storage device 32. The encoded video data in the storage device 32 can then be accessed by the destination device 14 via the input interface 28. The storage device 32 can include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a digital versatile disc (DVD), a compact disc read-only memory (CD-ROM), flash memory, volatile memory or non-volatile memory, or any other suitable digital storage medium for storing encoded video data. In a further example, the storage device 32 can correspond to a file server or another intermediate storage device that can hold the encoded video data generated by the source device 12. The destination device 14 can access the stored video data from the storage device 32 via streaming or downloading. The file server can be any type of computer capable of storing and transferring the encoded video data to the destination device 14. Exemplary file servers include a web server (e.g., for a website), a file transfer protocol (FTP) server, a network attached storage (NAS) device, or a local disk drive. Destination device 14 may access the encoded video data through any standard data connection, including a wireless channel suitable for accessing encoded video data stored on a file server (e.g., a Wireless Fidelity (Wi-Fi) connection), a wired connection (e.g., a Digital Subscriber Line (DSL), a cable modem, etc.), or a combination of both. The transmission of the encoded video data from storage device 32 may be a streaming transmission, a download transmission, or a combination of both.

[0365] like Figure 13 As shown in FIG, source device 12 includes a video source 18, a video encoder 20, and an output interface 22. Video source 18 may include a source such as a video capture device, for example, a camera, a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and / or a computer graphics system for generating computer graphics data as source video, or a combination of these sources. As an example, if video source 18 is a camera of a security monitoring system, source device 12 and destination device 14 may form a camera phone or a video phone. However, the embodiments described in this application may be generally applicable to video encoding and decoding and may be applied to wireless and / or wired applications.

[0366] Captured, pre-captured, or computer-generated video may be encoded by video encoder 20. The encoded video data may be transmitted directly to destination device 14 via output interface 22 of source device 12. The encoded video data may also (or alternatively) be stored on storage device 32 for later access by destination device 14 or other devices for decoding and / or playback. Output interface 22 may further include a modem and / or a transmitter.

[0367] Destination device 14 includes an input interface 28, a video decoder 30, and a display device 34. Input interface 28 may include a receiver and / or a modem and receives encoded video data via link 16. The encoded video data transmitted via link 16 or provided on storage device 32 may include various syntax elements generated by video encoder 20 for use in decoding the video data by video decoder 30. Such syntax elements may be included within the encoded video data transmitted over a communication medium, stored on a storage medium, or stored on a file server.

[0368] In some implementations, destination device 14 may include a display device 34, which may be an integrated display device or an external display device configured to communicate with destination device 14. Display device 34 displays the decoded video data to a user and may include any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0369] The video encoder 20 and the video decoder 30 may operate in accordance with proprietary or industry standards such as VVC, HEVC, MPEG-4 Part 10, AVC, or extensions of such standards. It will be appreciated that the present application is not limited to a particular video encoding / decoding standard and may be applicable to other video encoding / decoding standards. It is generally contemplated that the video encoder 20 of the source device 12 may be configured to encode video data in accordance with any of these current or future standards. Similarly, it is also generally contemplated that the video decoder 30 of the destination device 14 may be configured to decode video data in accordance with any of these current or future standards.

[0370] The video encoder 20 and the video decoder 30 can each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When implemented partially in software, the electronic device can store instructions for the software in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the video encoding / decoding operations disclosed in the present disclosure. Each of the video encoder 20 and the video decoder 30 can be included in one or more encoders or decoders, any of which can be integrated as part of a combined encoder / decoder (CODEC) in the corresponding device.

[0371] Figure 14is a block diagram illustrating an exemplary video encoder 20 according to some embodiments described herein. Video encoder 20 can perform intra-frame prediction and inter-frame prediction encoding of video blocks within a video frame. Intra-frame prediction codecs rely on spatial prediction to reduce or remove spatial redundancy in video data within a given video frame or picture. Inter-frame prediction codecs rely on temporal prediction to reduce or remove temporal redundancy in video data within adjacent video frames or pictures of a video sequence. It should be noted that in the field of video coding, the term "frame" can be used as a synonym for the term "image" or "picture."

[0372] like Figure 14 As shown in FIG, video encoder 20 includes video data memory 40, prediction processing unit 41, decoded picture buffer (DPB) 64, adder 50, transform processing unit 52, quantization unit 54, and entropy coding unit 56. Prediction processing unit 41 further includes motion estimation unit 42, motion compensation unit 44, partitioning unit 45, intra prediction processing unit 46, and intra block copy (BC) unit 48. In some embodiments, video encoder 20 also includes inverse quantization unit 58 for video block reconstruction, inverse transform processing unit 60, and adder 62. A loop filter 63, such as a deblocking filter, can be located between adder 62 and DPB 64 to filter block boundaries to remove blocking artifacts from the reconstructed video. In addition to the deblocking filter, another loop filter, such as a sample adaptive offset (SAO) filter and / or an adaptive loop filter (ALF), can also be used to filter the output of adder 62. In some examples, the loop filter may be omitted and the decoded video blocks may be provided directly by summer 62 to DPB 64. Video encoder 20 may take the form of fixed or programmable hardware units, or may be partitioned among one or more of the illustrated fixed or programmable hardware units.

[0373] Video data memory 40 may store video data to be encoded by components of video encoder 20. For example, video data may be stored in memory such as Figure 13 The video source 18 shown obtains video data in the video data memory 40. The DPB 64 is a buffer that stores reference video data (e.g., reference frames or pictures) for encoding the video data by the video encoder 20 (e.g., in intra-frame prediction codec mode or inter-frame prediction codec mode). The video data memory 40 and the DPB 64 can be formed by any of a variety of memory devices. In various examples, the video data memory 40 can be on-chip with other components of the video encoder 20, or off-chip relative to those components.

[0374] like Figure 14As shown in , after receiving the video data, the partitioning unit 45 within the prediction processing unit 41 partitions the video data into video blocks. The partitioning may also include partitioning the video frame into slices, tiles (e.g., sets of video blocks), or other larger coding units (CUs) according to a predefined partitioning structure (e.g., a quadtree (QT) structure associated with the video data). A video frame is or can be viewed as a two-dimensional array or matrix of sample values. The samples in the array may also be referred to as pixels (pixels or pels). The number of samples in the horizontal and vertical directions (or axes) of the array or picture defines the size and / or resolution of the video frame. For example, a video frame can be divided into multiple video blocks by using QT partitioning. A video block is again or can be viewed as a two-dimensional array or matrix of sample values, but its dimensions are smaller than a video frame. The number of samples in the horizontal and vertical directions (or axes) of a video block defines the size of the video block. The video block can be further divided into one or more block partitions or sub-blocks (which can again form blocks) by, for example, iteratively using QT partitioning, binary tree (BT) partitioning or ternary tree (TT) partitioning or any combination thereof. It should be noted that the terms "block" or "video block" used herein can be a part of a frame or picture, in particular a rectangular (square or non-square) part. For example, with reference to HEVC and VVC, a block or video block can be or correspond to a coding tree unit (CTU), a CU, a prediction unit (PU) or a transform unit (TU), and / or can be or correspond to a corresponding block (e.g., a coding tree block (CTB), a coding block (CB), a prediction block (PB) or a transform block (TB)) and / or correspond to a sub-block.

[0375] Prediction processing unit 41 may select one of a plurality of possible prediction codec modes for the current video block based on the error results (e.g., coding rate and distortion level), such as one of a plurality of intra-frame prediction codec modes or one of a plurality of inter-frame prediction codec modes. Prediction processing unit 41 may provide the resulting intra-frame prediction coded block or inter-frame prediction coded block to adder 50 to generate a residual block and to adder 62 to reconstruct the coded block for subsequent use as part of a reference frame. Prediction processing unit 41 also provides syntax elements such as motion vectors, intra-frame mode indicators, partition information, and other such syntax information to entropy coding unit 56.

[0376] To select an appropriate intra-prediction codec mode for the current video block, intra-prediction processing unit 46 within prediction processing unit 41 may perform intra-prediction coding of the current video block relative to one or more neighboring blocks in the same frame as the current block to be encoded to provide spatial prediction. Motion estimation unit 42 and motion compensation unit 44 within prediction processing unit 41 may perform inter-prediction coding of the current video block relative to one or more prediction blocks in one or more reference frames to provide temporal prediction. Video encoder 20 may perform multiple coding passes, for example, to select an appropriate coding mode for each block of video data.

[0377] In some embodiments, motion estimation unit 42 determines the inter-prediction mode for the current video frame according to a predetermined pattern within the sequence of video frames by generating motion vectors that indicate the displacement of a video block within the current video frame relative to a prediction block within a reference video frame. Motion estimation performed by motion estimation unit 42 is the process of generating motion vectors that estimate the motion of video blocks. A motion vector may, for example, indicate the displacement of a video block within the current video frame or picture relative to a prediction block within a reference frame, the prediction block being relative to the current block encoded within the current frame. The predetermined pattern may designate video frames in the sequence as P-frames or B-frames. Intra BC unit 48 may determine vectors (e.g., block vectors) for intra BC coding in a manner similar to the manner in which motion estimation unit 42 determines motion vectors for inter-prediction, or may utilize motion estimation unit 42 to determine block vectors.

[0378] The prediction block for a video block may be or may correspond to a block or reference block of a reference frame that is considered to closely match the video block to be encoded in terms of pixel difference, which may be determined by sum of absolute difference (SAD), sum of squared difference (SSD), or other difference metrics. In some embodiments, video encoder 20 may calculate values ​​for sub-integer pixel positions of the reference frame stored in DPB 64. For example, video encoder 20 may interpolate values ​​for quarter-pixel positions, eighth-pixel positions, or other fractional pixel positions of the reference frame. Thus, motion estimation unit 42 may perform motion searches relative to full pixel positions and fractional pixel positions and output motion vectors with fractional pixel accuracy.

[0379] Motion estimation unit 42 calculates a motion vector for a video block in an inter-prediction coded frame by comparing the position of the video block to the position of a prediction block of a reference frame selected from either the first reference frame list (List 0) or the second reference frame list (List 1), each of which identifies one or more reference frames stored in DPB 64. Motion estimation unit 42 sends the calculated motion vector to motion compensation unit 44 and then to entropy encoding unit 56.

[0380] Motion compensation performed by motion compensation unit 44 may involve obtaining or generating a prediction block based on the motion vector determined by motion estimation unit 42. Upon receiving the motion vector for the current video block, motion compensation unit 44 may locate the prediction block pointed to by the motion vector in one of the reference frame lists, retrieve the prediction block from DPB 64, and forward the prediction block to adder 50. Adder 50 then forms a residual video block having pixel difference values ​​by subtracting the pixel values ​​of the prediction block provided by motion compensation unit 44 from the pixel values ​​of the current video block being encoded. The pixel difference values ​​forming the residual video block may include luma difference components, chroma difference components, or both. Motion compensation unit 44 may also generate syntax elements associated with the video block of the video frame for use by video decoder 30 when decoding the video block of the video frame. The syntax elements may include, for example, syntax elements defining a motion vector for identifying the prediction block, any flags indicating a prediction mode, or any other syntax information described herein. Note that motion estimation unit 42 and motion compensation unit 44 may be highly integrated but are illustrated separately for conceptual purposes.

[0381] In some embodiments, the intra BC unit 48 may generate a vector and obtain a prediction block in a manner similar to that described above in conjunction with the motion estimation unit 42 and the motion compensation unit 44, but wherein the prediction block is in the same frame as the current block being encoded, and wherein the vector is referred to as a block vector relative to the motion vector. Specifically, the intra BC unit 48 may determine an intra prediction mode to use for encoding the current block. In some examples, the intra BC unit 48 may encode the current block using various intra prediction modes, for example during separate encoding passes, and test their performance using rate-distortion analysis. Next, the intra BC unit 48 may select an appropriate intra prediction mode to use from among the various tested intra prediction modes and generate an intra mode indicator accordingly. For example, the intra BC unit 48 may calculate rate-distortion values ​​using rate-distortion analysis for the various tested intra prediction modes and select the intra prediction mode with the best rate-distortion characteristics among the tested modes as the appropriate intra prediction mode to use. Rate-distortion analysis typically determines the amount of distortion (or error) between a coded block and the original, uncoded block (coded to produce the coded block) and the bit rate (i.e., the number of bits) used to produce the coded block. Intra BC unit 48 may calculate a ratio based on the distortion and rate for each coded block to determine which intra prediction mode exhibits the best rate-distortion value for the block.

[0382] In other examples, intra BC unit 48 may utilize, in whole or in part, motion estimation unit 42 and motion compensation unit 44 to perform such functions for intra BC prediction in accordance with embodiments described herein. In either case, for intra block copying, the prediction block may be a block that is considered to closely match the block to be encoded in terms of pixel differences, which may be determined by SAD, SSD, or other difference metrics, and identification of the prediction block may include calculating values ​​for sub-integer pixel positions.

[0383] Regardless of whether the prediction block is from the same frame according to intra-frame prediction or from different frames according to inter-frame prediction, video encoder 20 can form a residual video block by subtracting the pixel values ​​of the prediction block from the pixel values ​​of the current video block being encoded and decoded to form pixel difference values. The pixel difference values ​​forming the residual video block may include luma component difference values ​​and chroma component difference values.

[0384] As described above, intra-prediction processing unit 46 may perform intra-prediction on the current video block as an alternative to inter-prediction performed by motion estimation unit 42 and motion compensation unit 44, or intra-block copy prediction performed by intra BC unit 48. Specifically, intra-prediction processing unit 46 may determine an intra-prediction mode to use for encoding the current block. To this end, intra-prediction processing unit 46 may encode the current block using various intra-prediction modes, for example, during separate encoding passes, and intra-prediction processing unit 46 (or mode selection unit in some examples) may select an appropriate intra-prediction mode to use from the tested intra-prediction modes. Intra-prediction processing unit 46 may provide information indicating the selected intra-prediction mode for the block to entropy encoding unit 56. Entropy encoding unit 56 may encode the information indicating the selected intra-prediction mode in the bitstream.

[0385] After prediction processing unit 41 determines a prediction block for the current video block via inter-frame prediction or intra-frame prediction, adder 50 forms a residual video block by subtracting the prediction block from the current video block. The residual video data in the residual block may be included in one or more TUs and provided to transform processing unit 52. Transform processing unit 52 transforms the residual video data into residual transform coefficients using a transform such as a discrete cosine transform (DCT) or a conceptually similar transform.

[0386] Transform processing unit 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may also reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan of the matrix comprising the quantized transform coefficients. Alternatively, entropy coding unit 56 may perform the scan.

[0387] After quantization, entropy coding unit 56 entropy encodes the quantized transform coefficients into a video bitstream using, for example, context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), probability interval partitioned entropy (PIPE) coding, or other entropy coding methods or techniques. The encoded bitstream may then be transmitted to a video bitstream such as Figure 13 The video decoder 30 shown, or archive it to Figure 13 The data is stored in the storage device 32 as shown for later transmission to or retrieval by the video decoder 30. The entropy coding unit 56 may also entropy encode the motion vectors and other syntax elements of the current video frame being encoded.

[0388] Inverse quantization unit 58 and inverse transform processing unit 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual video block in the pixel domain to generate a reference block used to predict other video blocks. As described above, motion compensation unit 44 may generate a motion compensated prediction block from one or more reference blocks of a frame stored in DPB 64. Motion compensation unit 44 may also apply one or more interpolation filters to the prediction block to calculate sub-integer pixel values ​​for use in motion estimation.

[0389] Adder 62 adds the reconstructed residual block to the motion compensated prediction block produced by motion compensation unit 44 to produce a reference block for storage in DPB 64. The reference block may then be used as a prediction block by intra BC unit 48, motion estimation unit 42, and motion compensation unit 44 to inter-predict another video block in a subsequent video frame.

[0390] Figure 15 3 is a block diagram illustrating an exemplary video decoder 30 according to some embodiments of the present application. The video decoder 30 includes a video data memory 79, an entropy decoding unit 80, a prediction processing unit 81, an inverse quantization unit 86, an inverse transform processing unit 88, an adder 90, and a DPB 92. The prediction processing unit 81 further includes a motion compensation unit 82, an intra-frame prediction unit 84, and an intra-frame BC unit 85. The video decoder 30 may perform the above-mentioned operations in combination with the above-mentioned operations. Figure 14 The decoding process is the reverse of the encoding process described with respect to video encoder 20. For example, motion compensation unit 82 may generate prediction data based on motion vectors received from entropy decoding unit 80, and intra-prediction unit 84 may generate prediction data based on intra-prediction mode indicators received from entropy decoding unit 80.

[0391] In some examples, units of the video decoder 30 may be assigned to perform embodiments of the present application. Likewise, in some examples, embodiments of the present disclosure may be divided between one or more units of the video decoder 30. For example, the intra BC unit 85 may perform embodiments of the present application alone or in combination with other units of the video decoder 30, such as the motion compensation unit 82, the intra prediction unit 84, and the entropy decoding unit 80. In some examples, the video decoder 30 may not include the intra BC unit 85, and the functions of the intra BC unit 85 may be performed by other components of the prediction processing unit 81, such as the motion compensation unit 82.

[0392] The video data memory 79 can store video data to be decoded by other components of the video decoder 30, such as an encoded video bitstream. For example, the video data stored in the video data memory 79 can be obtained from the storage device 32, a local video source (such as a camera) via a wired or wireless network transmission of the video data or by accessing a physical data storage medium (such as a flash drive or hard disk). The video data memory 79 may include a coded picture buffer (CPB) that stores encoded video data from the encoded and decoded video bitstream. The DPB 92 of the video decoder 30 stores reference video data for use in decoding the video data by the video decoder 30 (for example, in an intra-frame prediction codec mode or an inter-frame prediction codec mode). The video data memory 79 and the DPB 92 can be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. For illustrative purposes, the video data memory 79 is a coded picture buffer (CPB) that stores encoded video data from the encoded and decoded video bitstream. The DPB 92 of the video decoder 30 stores reference video data for use in decoding the video data by the video decoder 30 (for example, in an intra-frame prediction codec mode or an inter-frame prediction codec mode). The video data memory 79 and the DPB 92 can be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. For illustrative purposes, Figure 15 9 depicts video data memory 79 and DPB 92 as two distinct components of video decoder 30. However, it will be apparent to those skilled in the art that video data memory 79 and DPB 92 may be provided by the same memory device or separate memory devices. In some examples, video data memory 79 may be on-chip with other components of video decoder 30, or off-chip relative to those components.

[0393] During the decoding process, the video decoder 30 receives an encoded video bitstream representing video blocks of an encoded video frame and associated syntax elements. The video decoder 30 may receive syntax elements at the video frame level and / or the video block level. The entropy decoding unit 80 of the video decoder 30 entropy decodes the bitstream to generate quantized coefficients, motion vectors or intra-frame prediction mode indicators, and other syntax elements. The entropy decoding unit 80 then forwards the motion vectors or intra-frame prediction mode indicators and other syntax elements to the prediction processing unit 81.

[0394] When a video frame is encoded as an intra-frame prediction (I) frame or as an intra-frame prediction block in other types of frames, the intra-frame prediction unit 84 of the prediction processing unit 81 can generate prediction data for the video block of the current video frame based on the signaled intra-frame prediction mode and reference data from a previously decoded block of the current frame.

[0395] When the video frame is encoded as an inter-frame prediction codec (i.e., B or P) frame, the motion compensation unit 82 of the prediction processing unit 81 generates one or more prediction blocks for the video block of the current video frame based on the motion vectors and other syntax elements received from the entropy decoding unit 80. Each prediction block can be generated from a reference frame in one of the reference frame lists. The video decoder 30 can construct the reference frame lists: List 0 and List 1 using a default construction technique based on the reference frames stored in the DPB 92.

[0396] In some examples, when a video block is encoded or decoded according to the intra BC mode described herein, intra BC unit 85 of prediction processing unit 81 generates a prediction block for the current video block based on the block vector and other syntax elements received from entropy decoding unit 80. The prediction block may be within a reconstruction region of the same picture as the current video block defined by video encoder 20.

[0397] The motion compensation unit 82 and / or the intra BC unit 85 determine prediction information for a video block of the current video frame by parsing the motion vector and other syntax elements, and then use the prediction information to generate a prediction block for the current video block being decoded. For example, the motion compensation unit 82 uses some of the received syntax elements to determine the prediction mode (e.g., intra prediction or inter prediction) used to encode the video block of the video frame, the inter prediction frame type (e.g., B or P), construction information for one or more reference frame lists in the reference frame list of the frame, the motion vector of each inter-frame prediction coded video block of the frame, the inter prediction state of each inter-frame prediction coded video block of the frame, and other information used to decode the video block in the current video frame.

[0398] Similarly, the intra BC unit 85 may use some of the received syntax elements (e.g., flags) to determine whether the current video block is predicted using the intra BC mode, construction information that video blocks of the frame are within the reconstructed region and should be stored in the DPB 92, block vectors for each intra BC-predicted video block of the frame, intra BC prediction status for each intra BC-predicted video block of the frame, and other information used to decode the video blocks in the current video frame.

[0399] Motion compensation unit 82 may also perform interpolation using interpolation filters to calculate interpolated values ​​for sub-integer pixels of a reference block, as used by video encoder 20 during encoding of the video block. In this case, motion compensation unit 82 may determine the interpolation filters used by video encoder 20 from received syntax elements and use the interpolation filters to produce the prediction block.

[0400] Inverse quantization unit 86 inverse quantizes the quantized transform coefficients provided in the bitstream and entropy decoded by entropy decoding unit 80, using the same quantization parameters that determine the degree of quantization calculated by video encoder 20 for each video block in the video frame. Inverse transform processing unit 88 applies an inverse transform (e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients to reconstruct the residual block in the pixel domain.

[0401] After the motion compensation unit 82 or the intra BC unit 85 generates a prediction block for the current video block based on the vector and other syntax elements, the adder 90 reconstructs the decoded video block of the current video block by summing the residual block from the inverse transform processing unit 88 and the corresponding prediction block generated by the motion compensation unit 82 and the intra BC unit 85. A loop filter 91 (such as a deblocking filter, an SAO filter and / or an ALF) can be positioned between the adder 90 and the DPB 92 to further process the decoded video block. In some examples, the loop filter 91 can be omitted and the decoded video block can be provided directly to the DPB 92 by the adder 90. The decoded video block in a given frame is then stored in the DPB 92, which stores reference frames for subsequent motion compensation of the next video block. The DPB 92 or a memory device separate from the DPB 92 can also store the decoded video for later presentation on a video device such as a MPEG-4 video frame. Figure 13 On display devices such as display device 34.

[0402] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limited to the present disclosure. Many modifications, variations, and alternative embodiments will be apparent to one of ordinary skill in the art having the benefit of the teachings presented in the foregoing description and the associated drawings.

[0403] The examples are chosen and described in order to explain the principles of the present disclosure and to enable others skilled in the art to understand the various embodiments of the present disclosure and to best utilize the basic principles as well as the various embodiments with various modifications as are suited to the particular use contemplated. Therefore, it should be understood that the scope of the present disclosure should not be limited to the specific examples of the embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the present disclosure.

Claims

1. A method for video encoding, the method comprising: signaling a parameter for determining a value of a codec bit depth; signaling a first sequence parameter set (SPS) flag, wherein the first SPS flag is a transform skip enable flag; and A second SPS flag is set based on the value of the first SPS flag and the value of the codec bit depth, wherein the second SPS flag is a transform skip residual codec Rice presence flag.

2. The method for video encoding according to claim 1, wherein: Setting the second SPS flag based on the value of the first SPS flag and the value of the codec bit depth includes: The second SPS flag is signaled based on a value of the first SPS flag and a value of the codec bit depth.

3. The method for video encoding according to claim 1, wherein: Setting the second SPS flag based on the value of the first SPS flag and the value of the codec bit depth includes: The value of the second SPS flag is set based on the value of the first SPS flag and the value of the codec bit depth.

4. The method for video encoding according to claim 3, wherein: When the value of the first SPS flag is equal to 0 and the value of the codec bit depth is greater than 10, the value of the second SPS flag is set to be equal to 0.

5. The method for video encoding according to claim 1 , further comprising: The value of the second SPS flag is set to 1 to indicate that there may be information about the SH transform skip residual codec Rice index in the slice header SH syntax structure that references the SPS.

6. The method for video encoding according to claim 2, wherein: Signaling the second SPS flag based on the value of the first SPS flag and the value of the codec bit depth includes: When the value of the first SPS flag is equal to 1 and the value of the codec bit depth is greater than 10, the second SPS flag is signaled.

7. A device for video encoding, the device comprising: one or more processors; as well as A memory configured to store instructions executable by the one or more processors; wherein, when executing the instructions, the one or more processors are configured to perform the method according to any one of claims 1 to 6 to generate a bitstream and store the bitstream in the memory.

8. A non-transitory computer-readable storage medium for video encoding, the non-transitory computer-readable storage medium storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to perform the method according to any one of claims 1 to 6 and store a bitstream generated by the method according to any one of claims 1 to 6 in the non-transitory computer-readable storage medium.

9. A computer program product comprising instructions for execution by a computing device having one or more processors, wherein when the instructions are executed by the one or more processors, the computing device performs the method according to any one of claims 1 to 6 to generate a bitstream.

10. A method for storing a bitstream, wherein: The bit stream is generated by the method according to any one of claims 1 to 6.

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