A method and device for implementing a Retimer low power consumption mode

Abstract

The present invention discloses a method and device for realizing a Retimer low power consumption mode, comprising: in a forwarding non-training sequence state, when an electrical idle ordered set is received on any differential signal pair channel of pseudo ports on both sides, the opposite end transmitting end is placed in an electrical idle state, and the power-off working mode of the local end is switched to a specified low power consumption state, and after the electrical idle state and the power-off working mode of the pseudo ports on both sides are adjusted, the low power consumption mode of L1 is entered; in the low power consumption mode of L1, when an electrical idle exit is detected on any differential signal pair channel of pseudo ports on both sides, the opposite end transmitting end is exited from the electrical idle state, and the power-off working mode of the local end is switched to the P0 state, and after the electrical idle state and the power-off working mode of the pseudo ports on both sides are adjusted, the low power consumption mode of L1 is exited. The present invention can solve the shortcomings of the current Retimer low power consumption scheme that is complex to realize and supports fewer low power consumption modes, and the logic implementation is simple and the robustness is good.

Description

Technical Field

[0001] The present invention belongs to the technical field of relay chips, and more specifically, relates to a method and device for implementing a Retimer low power consumption mode. Background Art

[0002] As the transmission rate of Peripheral Component Interconnect Express (PCIE) continues to increase, the signal attenuation problem becomes particularly serious, and the unit signal time (UnitInterval, abbreviated as: UI) becomes smaller and smaller, resulting in worsening eye diagram quality at the receiving end, which directly causes the bit error rate to deteriorate. In order to solve the above problems, it is necessary to place a relay chip in the middle of the signal transmission path or at the interface card slot to restore the signal quality. Common relay chips include redriver and retimer. Redriver is a non-protocol-aware device that simply amplifies the signal and does not have the ability to perform individual equalization and testing on each sub-link. Retimer is improved on the basis of redriver and has protocol perception capabilities, can perceive the link training process, and can adjust the equalization of each sub-link individually, but the transmission delay is greater.

[0003] The low power consumption function is essential for every PCIE device. It is used to turn off the interface function when the device or link is idle to save power. According to the Advanced Configuration and Power Interface (ACPI) protocol, low power consumption can be divided into device level, processor level, device level, link level, etc. The device level and link level power consumption management are directly related to PCIE. Devices are divided into several levels according to their usage scenarios, such as D0, D1, D2, D3Hot and D3Cold. Links are divided into several levels according to their usage scenarios, such as L0, L0s, L1, L2 and L3. Since Retimer is a physical layer device, it is only related to link-level low power consumption.

[0004] According to the characteristics of Retimer, it is only responsible for forwarding Data Link Layer Packet (DLLP) and Transaction Layer Packet (TLP), and does not have the ability to directly identify packet headers and payloads. If this function needs to be implemented additionally, it will not only be more complicated to implement, but also occupy a large amount of logic resources. As far as the existing technology is concerned, the current Retimer low-power solution is complex to implement and supports fewer low-power modes.

[0005] In view of this, how to overcome the technical problems existing in the above-mentioned prior art is a difficult problem to be solved urgently in this technical field. Summary of the invention

[0006] One of the purposes of the present invention is to overcome the technical problems existing in the above-mentioned prior art, and propose a method and device for realizing a Retimer low power consumption mode, aiming to improve the architecture and process of Retimer entering and exiting low power consumption, and does not adopt any packet recognition logic, so as to solve the shortcomings of the current Retimer low power consumption scheme that is complex to implement and supports fewer low power consumption modes, and has the characteristics of simple logic implementation and good robustness.

[0007] To achieve the above object, according to a first aspect of the present invention, a method for implementing a Retimer low power consumption mode is provided, including a low power consumption mode of L1:

[0008] In the state of forwarding non-training sequences, when an electrical idle ordered set is received on any differential signal pair channel of the pseudo ports on both sides, the transmitting end of the opposite end is placed in an electrical idle state, and the power-down working mode of the local end is switched to a specified low-power state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low-power mode of L1 is entered;

[0009] In the low power consumption mode of L1, when an electrical idle exit is detected on any differential signal pair channel of the pseudo ports on both sides, the transmitting end of the other end exits the electrical idle state, and the power-down working mode of the local end is switched to the P0 state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low power consumption mode of L1 is exited.

[0010] Furthermore, it also includes L1.1 low power mode:

[0011] Based on the low power consumption mode of L1, after the pseudo ports on both sides switch the local power-down working mode to the specified low power consumption state, the reference clock request signal is pulled high and the reference clock is turned off to enter the low power consumption mode of L1.1;

[0012] In the low power consumption mode of L1.1, when it is detected that the reference clock request signal is pulled low, the reference clock is restored, the low power consumption mode of L1.1 is exited, and the low power consumption mode of L1 is entered.

[0013] Furthermore, it also includes a low power consumption mode of L2, the entry conditions of the low power consumption mode of L2 are consistent with those of the low power consumption mode of L1, the low power consumption mode of L1 does not slow down after exiting, and the low power consumption mode of L2 slows down to 2.5GT / s during the exit process.

[0014] Furthermore, the exit of the L2 low power consumption mode includes:

[0015] When both pseudo ports on both sides exit the electrical idle state and the power-down working mode is switched to P0, if no training sequence is received within the specified time, the rate is switched to 2.5GT / s; when the electrical idle indication signals of the transmitting ends of the two ports are pulled low, the low power consumption mode of L2 is exited.

[0016] Furthermore, the exit of the L2 low power consumption mode includes:

[0017] When the pseudo port on one side exits the electrical idle state and the power-down working mode is switched to P0, the pseudo port on the other side does not receive Ordered Sets, triggering the forwarding electrical idle exit mode; if the Retimer does not actively reduce the speed, it will be forced to reduce the speed to 2.5GT / s; when the transmitting end electrical idle indication signals of the two ports are pulled low, the L2 low power mode is exited.

[0018] Furthermore, the entry into the L1 low power consumption mode specifically includes:

[0019] When any differential signal pair channel of the upstream pseudo port and the downstream pseudo port receives the electrical idle ordered set in sequence, the electrical idle indication signal of the transmitting end of the opposite transmitting module is set high, and the power-down working mode of the local end is switched in the order of P0, P1, POWER_STATE_4, and POWER_STATE_5. In the POWER_STATE_5 state, the Retimer pulls the reference clock request signal high; when the transmitting end electrical idle indication signals of the two ports are both pulled high and the power-down working modes are switched to POWER_STATE_5, the Retimer enters the low power consumption mode of L1.

[0020] Furthermore, the exit of the L1 low power consumption mode specifically includes:

[0021] When the pseudo port on either side of the Retimer detects the electrical idle exit, the power-down working mode is switched in the order of POWER_STATE_5, P1, and P0, and the sending end electrical idle indication signal of the pseudo port that exits the electrical idle state is pulled low; when the sending end electrical idle indication signals of the two pseudo ports are pulled low and the power-down working modes are switched to P0, the Retimer exits the low power consumption mode of L1.

[0022] Furthermore, the exit of the L2 low power consumption mode specifically includes:

[0023] The power-down working modes of the pseudo ports on both sides are switched in the order of POWER_STATE_5, P1, and P0. In the POWER_STATE_5 state, the electrical idle indication signal of the transmitting end is pulled low and then pulled high to wake up the link peer device; when the power-down working modes of the two pseudo ports are switched to P0, the timeout counter is started. When the timeout counter times out, the speed is switched to 2.5GT / s; when the electrical idle indication signals of the transmitting end of the two pseudo ports are pulled low, the Retimer exits the low power consumption mode of L2.

[0024] Furthermore, the exit of the L2 low power consumption mode specifically includes:

[0025] The power-down working mode of the pseudo port on the side that exits the electrical idle state is switched in the order of POWER_STATE_5, P1, and P0. If the pseudo port on the other side does not receive the Ordered Sets sequence within the preset time, the forwarding electrical idle exit mode scenario in the electrical idle exit mode is triggered. After the forwarding electrical idle exit mode, the link peer device is awakened. When the electrical idle is inferred or after a timeout, the rate is cut to 2.5GT / s. When the transmitting end electrical idle indication signals of the two ports are both pulled low, the Retimer exits the low power consumption mode of L2.

[0026] In a second aspect, the present invention provides a device for implementing a Retimer low power consumption mode, applying the Retimer low power consumption mode implementation method described in the first aspect, the device includes at least one processor and a memory, the at least one processor and the memory are connected via a data bus, the memory stores instructions that can be executed by the at least one processor, and the instructions are used to complete the Retimer low power consumption mode implementation method described in the first aspect after being executed by the processor.

[0027] In general, the above technical solution conceived by the present invention has the following beneficial effects compared with the prior art: the present invention proposes a method and device for implementing a Retimer low power consumption mode, which can improve the architecture and process of Retimer entering and exiting low power consumption, and does not adopt any packet recognition logic, thereby solving the shortcomings of the current Retimer low power consumption solution, such as complex implementation and fewer supported low power consumption modes, and has the characteristics of simple logic implementation and good robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the process of entering and exiting the low power consumption mode of L1 in a method for implementing the Retimer low power consumption mode provided by an embodiment of the present invention;

[0029] Figure 2A schematic diagram of the process of entering and exiting the low power consumption mode of L1.1 in a method for implementing the low power consumption mode of Retimer provided in an embodiment of the present invention;

[0030] Figure 3 A detailed example flow chart of entering and exiting the low power consumption mode of L1 provided in an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a power-off working mode switching process provided by an embodiment of the present invention;

[0032] Figure 5 A detailed example flow chart of entering and exiting the low power consumption mode of L1.1 provided in an embodiment of the present invention;

[0033] Figure 6 A first detailed example flow chart of entering and exiting the low power consumption mode of L2 provided in an embodiment of the present invention;

[0034] Figure 7 A second detailed example flow chart of entering and exiting the low power consumption mode of L2 provided in an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of the structure of a device for implementing a Retimer low power consumption mode provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] The present invention is an architecture of a specific functional device, so the specific embodiments mainly illustrate the functional logical relationship between the various structural modules, and do not limit the specific software and hardware implementation methods.

[0038] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other, and the order of each step can be changed if it is logical and does not conflict. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0039] According to the characteristics of Retimer, it is only responsible for the forwarding of DLLP and TLP, and does not have the ability to directly identify the packet header and payload. If this function needs to be implemented additionally, it is not only more complicated to implement, but also requires a lot of logical resources; therefore, when RC (root complex), EP (endpoint), and Switch (switch) enter and exit low power consumption, Retimer is better to make a series of actions according to the interaction process of low power consumption at the physical layer, cooperate with RC / EP / Switch, instead of directly identifying packets related to low power consumption. In addition, the PCIE specification (spec) states that Retimer does not need to support L0s, L2 is optional, L1.1 needs to be supported, L1.2 is not supported, but it should not interfere with RC, EP, and Switch entering and exiting L1.2.

[0040] Since the interaction process of L1, L1.1, and L2 in the physical layer is similar, some entry and exit processes can be reused, and a method that does not require packet identification is adopted. Therefore, a low-power implementation scheme of Retimer is proposed, which adopts the above implementation ideas and has the characteristics of supporting all scenarios (the embodiment of the present invention supports L1, L1.1 and L2, and does not interfere with the entry and exit of L1.2), simple logic implementation, and good robustness.

[0041] The present invention provides a method for implementing a Retimer low power consumption mode, including a low power consumption mode of L1, a low power consumption mode of L1.1, and a low power consumption mode of L2.

[0042] In some embodiments, Figure 1 As shown, entering and exiting the low power consumption mode of L1 includes the following steps.

[0043] Step 101: In the forwarding non-training sequence state, when an Electrical Idle Ordered Set (EIOS) is received on any differential signal pair (Lane) channel of the pseudo ports on both sides, the transmitting end of the opposite end is placed in an electrical idle state, and the power state of the power-down working mode (powerdown) of the local end is switched to a specified low power state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low power mode of L1 is entered. In this step, Lane refers to a group of differential signal pairs, one pair is used for sending, and the other pair is used for receiving. A PCIe link contains at least one Lane.

[0044] Step 102: In the low power mode of L1, when an electrical idle exit is detected on any differential signal pair channel of the pseudo ports on both sides, the transmitting end of the opposite end exits the electrical idle state, and the power-down working mode of the local end is switched to the P0 state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low power mode of L1 is exited. It can be understood that in some embodiments, P0 represents a normal working power state; P1 represents a low power power state that requires a long recovery time.

[0045] The description of entering and exiting the low power consumption mode of L1 is as follows: Since the PCIE spec does not specifically describe the implementation method of Retimer entering and exiting L1, it is usually implemented by identifying the packet and the electrical idle ordered set. However, the handshake process of the packet is cumbersome, and there may still be a situation where L1 cannot be successfully entered, so this method is cumbersome and the logic area is large. In view of this problem, the embodiment of the present invention only adopts the electrical idle ordered set identification method, that is, in the scenario of forwarding non-training sequences, if the upstream and downstream pseudo ports successively identify that the electrical idle ordered set is received on any differential signal pair channel, the opposite end sending end is placed in the electrical idle state respectively, and the power-down working mode is switched to the specified low power consumption state, and L1 is entered at this time; when the electrical idle exit is detected on any differential signal pair channel of the two pseudo ports, the power-down working mode is switched to the P0 state, and the opposite end sending end is respectively exited from the electrical idle state, and L1 is exited at this time; if for some reason, RC and EP fail to enter L1, then it is definitely not in line with the situation that both pseudo ports on both sides receive the electrical idle ordered set when forwarding non-training sequences, and the Retimer will not enter L1. Therefore, this implementation supports both the normal entry into L1 scenario and the abnormal scenario where L1 cannot be entered, and can reuse the electrical idle entry logic, which can not only achieve stable entry and exit of L1, but also make the logic area very small.

[0046] In some embodiments, Figure 2 As shown, entering and exiting the low power consumption mode of L1.1 includes the following steps.

[0047] Step 201: Based on the low power mode of L1, after the pseudo ports on both sides switch the local power-down working mode to the specified low power state, the reference clock request signal (CLK_REQN) is pulled high, and the reference clock is turned off to enter the low power mode of L1.1. Among them, CLK_REQN is the reference clock request signal, which is valid at a low level; when in the L1 state, after it is set to a high level, the reference clock will be removed.

[0048] Step 202: In the low power mode of L1.1, when it is detected that the reference clock request signal is pulled low, the reference clock is restored, the low power mode of L1.1 is exited, and the low power mode of L1 is entered. Then, the exit is performed according to the exit logic of the low power mode of L1.

[0049] The description of entering and exiting the low power mode of L1.1 mentioned above is as follows: According to PCIE spec, entering and exiting L1.1 is implemented on the basis of L1. The difference is that when RC and EP enter L1.1, the reference clock request signal pin will be pulled high during L1 to turn off the reference clock; when exiting L1.1, the reference clock request signal pin will be pulled low to turn on the reference clock; the usual practice is that during L1, when the reference clock request signal is detected to change from low to high, the power-down working mode is switched in the manner specified by L1.1; at this time, there is such a problem that when the reference clock request signal becomes high, the reference clock will disappear after several cycles, which is related to the internal implementation of PHY (physical layer transceiver) and may cause the power-down working mode switching to fail. To address this problem, the embodiment of the present invention adopts the same power-off working mode switching method as L1, that is, the power-off working mode switching no longer depends on the rising edge of the reference clock request signal, but after receiving the electrical idle ordered set, the power-off working mode is switched to the specified state in the manner of L1, and then the reference clock request signal is pulled high. If RC and EP both intend to enter L1.1 at this time, the reference clock can be successfully turned off. If RC and EP do not intend to enter L1.1, the reference clock cannot be turned off; when the falling edge of the reference clock request signal is detected, exit L1.1 to L1, restore the reference clock, and if the electrical idle is also exited at this time, exit L1. This method has strong stability and no longer depends on the internal implementation of PHY. It should be noted that the reference clock request signal is a bidirectional port. 1. After entering L1 (as an output port at this time), that is, after the power-off working mode is switched to POWER_STATE_5, the reference clock request signal is actively pulled high. The purpose of this operation is to avoid affecting RC and EP entering L1.1 (the premise for RC, EP, and Retimer to enter L1.1 is that their respective reference clock request signals are pulled high, and the reference clock can be turned off only after the line and operation); if RC and EP want to enter L1.1, they need to pull up the reference clock request signal. If they do not want to enter L1.1, they do not need to pull up the reference clock request signal. Therefore, if any of RC or EP does not pull up the reference clock request signal, the Retimer will still stay in L1; 2. After entering L1.1, the reference clock request signal is now used as an input port. When the falling edge of the reference clock request signal is detected in L1.1, the reference clock will be restored, and according to the protocol description, it will enter the L1 state.

[0050] In some embodiments, the entry conditions of the L2 low power mode are consistent with those of the L1 low power mode, the difference is that the L1 low power mode does not slow down after exiting, and the L2 low power mode slows down to 2.5GT / s during the exit process. Specifically, there are two ways to exit the L2 low power mode. It should be noted that since the Retimer is a PCIe physical layer sensing device, it cannot directly perceive the high-level protocol packet interaction process. Therefore, for the Retimer, the entry conditions of L1 and L2 are both to determine whether both pseudo-ports receive the electrical idle ordered set, and the Retimer does not know whether the link enters L1 or L2; similarly, when "exiting low power state stage 1", the Retimer does not know whether to exit L1 or exit L2, and only needs to exit electrical idle; when exiting electrical idle, it enters "exit low power stage 2", that is, it determines whether the TS1 sequence is received within the specified time range. If so, it is determined to exit L1 without slowing down; otherwise, it is determined to exit L2 and slow down to 2.5GT / s.

[0051] The first type: When both pseudo ports on both sides exit the electrical idle state and the power-down working mode is switched to P0, if no training sequence is received within the specified time, the rate is switched to 2.5GT / s; TS1: training sequence 1, TS2: training sequence 2. When the electrical idle indication signals of the transmitting end of both ports are pulled low, the low power consumption mode of L2 is exited. It should be noted that when the rate is switched to 2.5GT / s, the Retimer is able to receive the TS1 sequence sent by the root complex or endpoint; when one pseudo port receives the TS1 sequence, the other pseudo port can pull down the transmitting end electrical idle indication signal.

[0052] The second type: when the pseudo port on one side exits the electrical idle state and the power-down working mode is switched to P0, the pseudo port on the other side does not receive Ordered Sets (sequence, a data packet unique to the PCIe physical layer, used for information exchange during the link establishment process), triggering the forwarding electrical idle exit mode; if the Retimer does not actively reduce the speed, it will be forced to reduce the speed to 2.5GT / s; when the electrical idle indication signals of the sender of both ports are pulled low, the low power consumption mode of L2 is exited. Among them, the electrical idle exit mode: when the Retimer detects the electrical idle exit, in order to ensure that the root complex or endpoint can also exit the electrical idle normally, the Retimer sends a data combination with certain characteristics on a pseudo port on one side. This data combination can make it easier for the electrical idle exit detection circuit of the root complex or endpoint PHY to detect the electrical idle exit behavior. It should be noted that both exit methods require a port to exit the electrical idle state. The core point is: if it is to exit L2, method one requires a timeout and then a speed reduction, and method two requires the use of the "electrical idle exit module" to exit.

[0053] The description of entering and exiting the low power consumption mode of L2 is as follows: For the Retimer, the entry method of L2 is exactly the same as that of L1, but L1 does not slow down after exiting, and L2 slows down to 2.5GT / s after exiting. The usual practice is to determine whether to enter L1 or L2 through packet recognition, but there are problems such as cumbersome implementation and large logic area. In response to this problem, the embodiment of the present invention adopts two implementation methods, both of which can achieve correct exit from L2. Method 1: The entry method of L2 is the same as L1, and any differential signal pair channel of the two pseudo ports receives the electrical idle ordered set. The exit method is that after exiting the electrical idle and switching the power-off working mode to P0, if the TS1 and TS2 sequences are not received within the specified time, it is determined that the previous entry state is L2, and the rate is cut to 2.5GT / s. This specified time is usually 24ms, corresponding to the timeout time of recovery.lock, and can be adjusted. This method has the characteristics of simple implementation ideas. Mode 2: The L2 entry mode is the same as the L1 entry mode. Any differential signal pair channel of the two pseudo ports can receive the electrical idle ordered set. When exiting, the electrical idle exit mode 3 of the Retimer is used: that is, when exiting the electrical idle and switching the power-down working mode to P0, since the RC and EP are at 2.5GT / s rate, the Retimer is at a non-2.5GT / s rate, and the pseudo port on one side of the Retimer has exited the electrical idle, and the port on the other side has not received Ordered Sets, it meets the trigger condition of mode 3 and will forward the electrical idle exit mode. If the Retimer does not actively reduce the speed, it will be forced to reduce the speed to 2.5GT / s. This method has the characteristic of occupying almost no additional logic, but the logical relationship of the rate switching module needs to be designed so that after inferring the electrical idle in mode 3, it can reduce the speed to 2.5GT / s.

[0054] Based on the above settings, the embodiment of the present invention improves the architecture and process of Retimer entering and exiting low power consumption, and does not adopt any packet recognition logic, thereby solving the shortcomings of the current Retimer low power consumption solution that is complex to implement and supports fewer low power consumption modes, and has the characteristics of simple logic implementation and good robustness.

[0055] Based on the above embodiments, the entry and exit of the low power consumption modes of L1, L1.1 and L2 are described below by means of more detailed examples.

[0056] In an alternative embodiment, reference Figure 3As shown, the entry of the low power consumption mode of L1 specifically includes: when any differential signal pair channel of the upstream pseudo port and the downstream pseudo port receives the electrical idle ordered set in sequence, the transmitting end electrical idle indication signal (txelecidle) of the opposite end transmitting module is set high (txelecidle is the transmitting end electrical idle indication signal, and this signal is set high when the link enters the electrical idle state), and the power-down working mode of the local end is switched in the order of P0, P1, POWER_STATE_4, and POWER_STATE_5. In the POWER_STATE_5 state, the Retimer pulls up the reference clock request signal; when the transmitting end electrical idle indication signals of the two ports are both pulled high and the power-down working modes are both switched to POWER_STATE_5, the Retimer enters the low power consumption mode of L1. The exit from the low power consumption mode of L1 specifically includes: when the pseudo port on either side of the Retimer detects the electrical idle exit, the power-down working mode is switched in the order of POWER_STATE_5, P1, and P0, and the sending end electrical idle indication signal of the pseudo port that exits the electrical idle state is pulled low (when the electrical idle exit is detected, the rxelecidle signal of the PHY receiving port will be pulled low. After the Retimer detects that the rxelecidle is pulled low and the forwarding conditions are met, the sending end electrical idle indication signal of the pseudo port on the other side will be pulled low to meet the forwarding conditions); when the sending end electrical idle indication signals of the two pseudo ports are both pulled low and the power-down working modes are switched to P0, the Retimer exits the low power consumption mode of L1.

[0057] Specifically, the Retimer link is trained to the forwarding non-training sequence mode. When any differential signal pair channel of the upstream pseudo port and the downstream pseudo port receives the electrical idle ordered set in sequence, on the one hand, the transmitting end electrical idle indication signal of the opposite transmitting module is set high, and on the other hand, the power-down working mode is switched in the manner of P0->P1->POWER_STATE_4->POWER_STATE_5. POWER_STATE_4 and POWER_STATE_5 are PHY custom states. Here, POWER_STATE_4 is the transition state to enter L1PM, and POWER_STATE_5 is the L1PM state. In this state, the Retimer pulls the reference clock request signal high. Since RC and EP do not intend to enter the L1.1 state at this time, the reference clock will not be turned off. When the electrical idle indication signals of the two ports are pulled high and the power-down working mode is switched to POWER_STATE_5, the Retimer enters the L1 low power state; when the pseudo-port on either side of the Retimer detects the electrical idle exit, on the one hand, the power-down working mode is switched in the manner of POWER_STATE_5->P1->P0, and on the other hand, the electrical idle indication signals of the pseudo-ports exiting the electrical idle are pulled low in turn. When the electrical idle indication signals of the two ports are pulled low and the power-down working mode is switched to P0, the Retimer exits the L1 low power state. Reference Figure 4 As shown, the switching of the power-down working mode specifically includes: when forwarding a non-training sequence, any differential signal pair channel of the pseudo ports on both sides receives an electrical idle ordered set and switches from P0 to P1; when Phystatus (PHY status response signal, when PHY completes switching rate, switching power-down working mode, Tx Detect Rx and other operations, PHY will reply with a Phystatus response signal to notify the controller that the corresponding operation has been completed) is detected to return, and the links on both sides enter electrical idle, switching from P1 to POWER_STATE_4; when Phystatus return is detected, switching from POWER_STATE_4 to POWER_STATE_5; when Phystatus return is detected, and any differential signal pair channel of any pseudo port detects electrical idle exit, switching from POWER_STATE_5 to P1; when Phystatus return is detected, and both pseudo ports on both sides exit electrical idle, switching from P1 to P0.

[0058] In an optional implementation, the steps for implementing L1.1 entry and exit are as follows: Figure 5As shown; the entry process is exactly the same as the entry process of L1, but at this time the reference clock request signals of RC and EP are both pulled high, the reference clock is turned off, and the Retimer enters the L1.1 low power state; when the Retimer detects that the reference clock request signal is pulled low, the reference clock will be restored. After the reference clock is restored, the electrical idle exit detection circuit inside the PHY starts to work, and then exits to L1. The subsequent exit process is exactly the same as the exit process of L1, and the Retimer exits the L1.1 low power state.

[0059] In an alternative embodiment, reference Figure 6 In the first method shown, the exit from the low power consumption mode of L2 specifically includes: switching the power-down working modes of the pseudo ports on both sides in the order of POWER_STATE_5, P1, and P0, and in the POWER_STATE_5 state, pulling the electrical idle indication signal of the transmitting end low and then high to wake up the link peer device; when the power-down working modes of the two pseudo ports are switched to P0, starting the timeout counter, and when the timeout counter times out, cutting the speed to 2.5GT / s; when the electrical idle indication signals of the transmitting ends of the two pseudo ports are pulled low, the Retimer exits the low power consumption mode of L2.

[0060] In an alternative embodiment, reference Figure 7 In the second method shown, the exit from the low power consumption mode of L2 specifically includes: switching the power-down working mode of the pseudo port on the side that exits the electrical idle state in the order of POWER_STATE_5, P1, and P0; if the pseudo port on the other side does not receive the Ordered Sets sequence within the preset time, the forwarding electrical idle exit mode scenario in the electrical idle exit mode is triggered; after the forwarding electrical idle exit mode, the link peer device is awakened, and when the electrical idle is inferred or after a timeout, the rate is cut to 2.5GT / s; when the transmitting end electrical idle indication signals of the two ports are both pulled low, the Retimer exits the low power consumption mode of L2.

[0061] For more details, please refer to the implementation steps of L2 entry and exit. Figure 6 , Figure 7As shown, the entry process of L2 is exactly the same as that of L1, and the Retimer enters the L2 low power state at this time; when the pseudo port on either side of the Retimer detects an electrical idle exit, there are two L2 exit implementation methods. The first one: on the one hand, the power-down working mode is switched in the manner of POWER_STATE_5->P1->P0, and on the other hand, a "beacon-like pulse" is sent to the opposite port of the port where the electrical idle exit is detected, that is, in the POWER_STATE_5 state, the electrical idle indication signal of the transmitting end is pulled low for 1ms, and then pulled high again to wake up the link opposite end device; when the power-down working modes of both ports are switched to P0, the timeout counter is started, which is 24ms by default and can be adjusted through the configuration register; at this time, the counter is counting, and when the training sequence is received, the counter is cleared, which indicates that it is in a non-L2 state; when the counter times out, it indicates that it is in the L2 state (this is the working mode of L2 exit mode 1, exiting L1 will not cause the counter timeout behavior, but exiting L2 will), and the speed is cut to 2.5GT / s; when the electrical idle indication signals of the transmitting end of both ports are pulled low, the Retimer exits the L2 low power state. The second type: On the one hand, the power-down working mode is switched in the manner of POWER_STATE_5->P1->P0. On the other hand, since the pseudo port on the other side cannot receive the Ordered Sets sequence within 3ms, the forwarding electrical idle exit mode scenario in the electrical idle exit mode will be triggered. After the forwarding electrical idle exit mode, the link peer device will be awakened. When the electrical idle is inferred or after a 48ms timeout, the rate will be cut to 2.5GT / s. When the transmitting end electrical idle indication signals of the two ports are both pulled low, the Retimer exits the L2 low power state.

[0062] Based on the above implementation, this embodiment has the following improvements:

[0063] (1) The L1 entry implementation method has the following characteristics: L1 can be entered only by receiving the electrical idle ordered set on the two pseudo ports in the forwarding non-training sequence state; it has a power-down working mode switching method similar to L1.1, and when the power-down working mode is switched to the target state, the reference clock request signal is pulled high.

[0064] (2) The L1.1 entry implementation method has the following characteristics: P0->P1->POWER_STATE_4->POWER_STATE_5->P0->P1 and similar power-down working mode switching methods; when the power-down working mode is POWER_STATE_5, the reference clock request signal is pulled high.

[0065] (3) The entry and exit implementation method of L2 has the following characteristics: it has the same entry method as L1; it has two exit methods, exit method 1: in non-P0 states such as POWER_STATE_5, by pulling down the transmitter's electrical idle indication signal for a certain period of time, in short, sending a "beacon-like pulse" to wake up the link peer device, including a timeout timer. The counter threshold can be configured through a register, usually 24ms. The enable signal of the counter is the flag signal that the ports on both sides switch to P0. The clear signal of the timer is the reception of a training sequence flag signal such as TS1 and TS2. After the counter times out, the Retimer working rate will be cut to 2.5GT / s; exit method 2: use the scenario of forwarding the electrical idle exit mode in the electrical idle exit function to assist in exiting L2.

[0066] In summary, the present invention proposes a method for implementing a Retimer low power mode, which can improve the architecture and process of Retimer entering and exiting low power consumption, and does not adopt any packet recognition logic, thereby solving the shortcomings of the current Retimer low power solution, such as complex implementation and fewer supported low power modes, and has the characteristics of supporting full scenarios, simple logic implementation, and good robustness.

[0067] Based on the Retimer low power mode implementation method provided in the above embodiment, the present invention also provides a Retimer low power mode implementation device that can be used to implement the above method, such as Figure 8 , which is a schematic diagram of the device architecture of an embodiment of the present invention. The Retimer low power mode implementation device of this embodiment includes one or more processors 21 and a memory 22. Figure 8 A processor 21 is taken as an example.

[0068] The processor 21 and the memory 22 may be connected via a bus or other means. Figure 8 The example of connecting through bus is taken in the following.

[0069] The memory 22 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the Retimer low power mode implementation method in the above-mentioned embodiment. The processor 21 executes various functional applications and data processing of the Retimer low power mode implementation device by running the non-volatile software programs, instructions and modules stored in the memory 22, that is, the Retimer low power mode implementation method of the embodiment of the present invention is implemented.

[0070] The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 may optionally include a memory remotely arranged relative to the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0071] The program instructions / modules are stored in the memory 22. When executed by one or more processors 21, the Retimer low power mode implementation method in the above embodiment is executed. For example, the above described Figures 1 to 7 The steps shown.

[0072] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for implementing a Retimer low power consumption mode, characterized in that: Including low power mode for L1: In the state of forwarding non-training sequences, when an electrical idle ordered set is received on any differential signal pair channel of the pseudo ports on both sides, the transmitting end of the opposite end is placed in an electrical idle state, and the power-down working mode of the local end is switched to a specified low-power state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low-power mode of L1 is entered; The entry of the L1 low power consumption mode includes: when any differential signal pair channel of the upstream pseudo port and the downstream pseudo port receives the electrical idle ordered set in sequence, the sending end electrical idle indication signal of the opposite end sending module is set high, and the power-down working mode of the local end is switched in the order of P0, P1, POWER_STATE_4, and POWER_STATE_5. In the POWER_STATE_5 state, the Retimer pulls up the reference clock request signal; when the sending end electrical idle indication signals of the two ports are both pulled high and the power-down working mode is switched to POWER_STATE_5, the Retimer enters the L1 low power consumption mode; In the low power consumption mode of L1, when an electrical idle exit is detected on any differential signal pair channel of the pseudo ports on both sides, the transmitting end of the opposite end is caused to exit the electrical idle state, and the power-down working mode of the local end is switched to the P0 state. After the electrical idle state and the power-down working mode of the pseudo ports on both sides are adjusted, the low power consumption mode of L1 is exited; the exit of the low power consumption mode of L1 includes: when the pseudo port on either side of the Retimer detects an electrical idle exit, the power-down working mode is switched in the order of POWER_STATE_5, P1, and P0, and the electrical idle indication signal of the transmitting end of the pseudo port exiting the electrical idle state is pulled low; when the electrical idle indication signals of the transmitting ends of the two pseudo ports are both pulled low and the power-down working modes are both switched to P0, the Retimer exits the low power consumption mode of L1.

2. The method for implementing the Retimer low power consumption mode according to claim 1, characterized in that: Also includes L1.1 low power mode: Based on the low power consumption mode of L1, after the pseudo ports on both sides switch the local power-down working mode to the specified low power consumption state, the reference clock request signal is pulled high and the reference clock is turned off to enter the low power consumption mode of L1.1; In the low power consumption mode of L1.1, when it is detected that the reference clock request signal is pulled low, the reference clock is restored, the low power consumption mode of L1.1 is exited, and the low power consumption mode of L1 is entered.

3. The method for implementing the Retimer low power consumption mode according to claim 1, characterized in that: It also includes a low power consumption mode of L2, the entry conditions of the low power consumption mode of L2 are consistent with those of the low power consumption mode of L1, the low power consumption mode of L1 does not slow down after exiting, and the low power consumption mode of L2 slows down to 2.5GT / s during the exit process.

4. The method for implementing the Retimer low power consumption mode according to claim 3, characterized in that: The exit of the L2 low power mode includes: When both pseudo ports on both sides exit the electrical idle state and the power-down working mode is switched to P0, if no training sequence is received within the specified time, the rate will be switched to 2.5GT / s; when the electrical idle indication signals of the transmitting ends of the two ports are pulled low, the low power consumption mode of L2 is exited.

5. The method for implementing the Retimer low power consumption mode according to claim 3, characterized in that: The exit of the L2 low power mode includes: When the pseudo port on one side exits the electrical idle state and the power-down working mode is switched to P0, the pseudo port on the other side does not receive Ordered Sets, triggering the forwarding electrical idle exit mode; if the Retimer does not actively reduce the speed, it will be forced to reduce the speed to 2.5GT / s; when the transmitting end electrical idle indication signals of the two ports are pulled low, the L2 low power mode is exited.

6. The method for implementing the Retimer low power consumption mode according to claim 4, characterized in that: The exit of the L2 low power mode also includes: The power-down working modes of the pseudo ports on both sides are switched in the order of POWER_STATE_5, P1, and P0. In the POWER_STATE_5 state, the electrical idle indication signal of the transmitting end is pulled low and then pulled high to wake up the link peer device; when the power-down working modes of the two pseudo ports are switched to P0, the timeout counter is started. When the timeout counter times out, the speed is switched to 2.5GT / s; when the electrical idle indication signals of the transmitting end of the two pseudo ports are pulled low, the Retimer exits the low power consumption mode of L2.

7. The method for implementing the Retimer low power consumption mode according to claim 5, characterized in that: The exit of the L2 low power mode also includes: The power-down working mode of the pseudo port on the side that exits the electrical idle state is switched in the order of POWER_STATE_5, P1, and P0. If the pseudo port on the other side does not receive the Ordered Sets sequence within the preset time, the forwarding electrical idle exit mode scenario in the electrical idle exit mode is triggered. After the forwarding electrical idle exit mode, the link peer device is awakened. When the electrical idle is inferred or after a timeout, the rate is cut to 2.5GT / s. When the transmitting end electrical idle indication signals of the two ports are both pulled low, the Retimer exits the low power consumption mode of L2.

8. A device for implementing a Retimer low power consumption mode, characterized in that: The method comprises at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, and the memory stores instructions that can be executed by the at least one processor, and after being executed by the processor, the instructions are used to complete the Retimer low power consumption mode implementation method according to any one of claims 1 to 7.

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